A GaN-based monolithic integrated CMOS circuit

Abstract

The present invention belongs to the field of power semiconductor technology, and in particular relates to a GaN-based monolithic integrated CMOS circuit. The circuit of the present invention replaces the traditional AlGaN barrier layer with a fixed Al component with a linearly gradient Al component, specifically a linearly gradient AlGaN barrier layer that decreases linearly from bottom to top. The 3DHG induced by the polarization difference of the linearly gradient AlGaN barrier layer plus the 2DHG formed at the heterojunction interface between the GaN channel and the linearly gradient AlGaN barrier increase the overall concentration of the hole gas, thereby improving the on-current density of p-FETs. The structure of the present invention helps to improve the on-current density of p-FETs, increase the P / N channel compatibility, reduce the on-current mismatch of p- / n-FETs in monolithic integration, and promote the development of CMOS-based all-GaN monolithic power integrated ICs.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a GaN-based monolithic integrated CMOS circuit. Background Art

[0002] Compared with traditional Si-based devices, GaN power devices have significant advantages in electron saturation velocity, bandgap width, and critical breakdown electric field. For example, the high concentration and high mobility 2DEG at the AlGaN / GaN heterojunction has become a unique feature of GaN power devices. Monolithic integration based on on-chip GaN CMOS not only simplifies circuit design, but also reduces the influence of parasitic inductance, realizing the most energy-efficient and efficient integrated topology with low static power consumption and strong noise resistance for the entire power switching system. GaN-based P-channel field-effect transistors (FETs) provide the possibility of on-chip CMOS. However, due to factors such as the low hole mobility of GaN at room temperature and the difficulty of significantly improving it, and the high ohmic contact resistivity of the device's drain and source, the on-current density of GaN p-FETs is much lower than that of the corresponding n-FETs, which is the main obstacle to the current realization of CMOS monolithic integration.

[0003] Therefore, to solve this problem, the most effective approach is to increase the on-current density of p-FETs by increasing the hole concentration. Currently, GaN-based P / N dual-channel stacked heterojunction epitaxial structures, which increase the hole concentration by increasing the heterojunction polarization strength, can lead to degradation of the n-FET device threshold voltage, reduced on-current density, increased leakage current, poor P / N channel performance compatibility, and excessive P / N channel synergistic regulation coupling. Summary of the Invention

[0004] To address the above problems, in order to realize enhancement-mode GaN p-FETs with high on-current density and monolithically integrate CMOS devices with enhancement-mode n-FETs on the same epitaxial structure, while avoiding the degradation of the n-FETs threshold voltage and improving the P / N channel compatibility, the present invention proposes a GaN-based epitaxial structure and a monolithically integrated CMOS circuit.

[0005] The technical solution adopted in the present invention is:

[0006] A GaN-based monolithic integrated CMOS circuit includes p-FETs and n-FETs. The p-FETs and n-FETs share a common structure comprising a substrate 01, a group III nitride buffer layer 02, a GaN channel layer 03, and an AlGaN barrier layer 04 stacked in sequence along a vertical direction. The Al content in the AlGaN barrier layer 04 is linearly graded, decreasing from bottom to top. The AlGaN barrier layer of the p-FETs is isolated from the AlGaN barrier layer of the n-FETs.

[0007] The AlGaN barrier layer of the p-FETs is cross-distributed with a polarization-induced 3DHG due to a gradual change in polarization intensity. A GaN channel layer 05 is provided on the upper surface of the AlGaN barrier layer. A 2DEG is formed at the interface between the AlGaN barrier layer of the p-FETs and the GaN channel layer 05. A P-type heavily doped GaN layer 06 is provided on the upper surface of the GaN channel layer 05. The upper surfaces of the P-type heavily doped GaN layer 06 are provided with a p-FETs source ohmic metal 07 and a p-FETs drain ohmic metal 07 at both ends. 8, wherein the p-FETs drain ohmic metal 08 is located on the side close to the n-FETs; a trench gate structure is provided between the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08, the trench gate structure including a gate dielectric 13 and a first gate metal 09, the gate dielectric 13 being located in a groove formed on the upper surface of the P-type heavily doped GaN layer 06, wrapping the lower portion of the first gate metal 09 and contacting the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 on both sides respectively;

[0008] The AlGaN barrier layer structure of the n-FETs also has a GaN channel layer 05 on its upper surface, and a P-type heavily doped GaN layer 06 on its upper surface. Unlike p-FETs, part of the upper layer of the AlGaN barrier layer, the GaN channel layer 05, and both sides of the P-type heavily doped GaN layer 06 of the n-FETs are etched away, leaving only a portion of the middle gate region. A 2DEG is formed at the interface between the AlGaN barrier layer and the GaN channel layer 03 of the n-FETs. The n-FETs drain ohmic metal 10 and the n-FETs source ohmic metal 1 are respectively provided on both sides of the upper surface of the AlGaN barrier layer of the n-FETs, wherein the n-FETs drain ohmic metal 10 is located on the side close to the p-FETs. A second gate metal 12 is provided on the upper surface of the P-type heavily doped GaN layer 06 of the n-FETs to form a planar gate.

[0009] The p-FETs source ohmic metal 07 is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal 1 is a low-level signal port of the CMOS circuit, the first gate metal 09 and the second gate metal 12 are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (8) and the n-FETs drain ohmic metal 10 are connected to form an output-level signal port of the CMOS circuit.

[0010] Furthermore, the material used for the substrate 01 is one of Si, sapphire and SiC.

[0011] Furthermore, the material used for the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 is any one of Pd / Au / Ni, Ni / Au, and Pd / Ni.

[0012] Furthermore, the material of the first gate metal 09 is any one of Ti / Au, W / Au, Ni / Au, Mo / Au, and Ru.

[0013] Furthermore, the gate dielectric 13 is any one of an oxide layer and an insulating layer.

[0014] Furthermore, the material used for the n-FETs drain ohmic metal 10 and the n-FETs source ohmic metal 1 is any one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al.

[0015] Furthermore, the contact between the second gate metal 12 and the P-type heavily doped GaN layer 06 is an ohmic contact, and the material used for the second gate metal 12 is Ni / Au.

[0016] The beneficial effects of the present invention are that, based on the epitaxial structure of commercial enhancement-mode p-GaN-gate HEMTs, the traditional AlGaN barrier layer with a fixed Al composition is replaced with a linearly graded AlGaN barrier layer with a linearly decreasing Al composition from bottom to top. The 3DHG induced by the polarization difference of the linearly graded AlGaN barrier layer, combined with the 2DHG formed at the heterojunction interface between the GaN channel and the linearly graded AlGaN barrier, increases the overall hole gas concentration, thereby improving the on-current density of p-FETs. At the same time, the 3DHG widens the spatial distribution of the P channel and improves the conductivity of the barrier layer. The graded AlGaN barrier layer also helps the P-type heavily doped GaN deplete the 2DEG concentration at the AlGaN / GaN heterojunction interface, thereby increasing the threshold voltage of n-FETs. During the fabrication of the p-GaN gate for n-FETs, etching away the entire heavily P-type doped GaN layer, GaN channel layer, and portion of the linearly graded AlGaN barrier layer in the gate-drain / source regions helps restore the 2DEG depleted by the heavily P-type doping, 2DHG, and 3DHG. Different depths of the linearly graded AlGaN barrier layer etch different 2DEG concentrations in the gate-drain / source regions of the n-FETs, enabling a tunable N-channel. This tunability of the N-channel conduction characteristics helps improve P / N channel compatibility, reduce the on-current mismatch between p- and n-FETs in monolithic integration, and promote the development of all-GaN monolithic power integrated circuits based on CMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the epitaxial structure of the device proposed in the present invention.

[0018] Figure 2 This is the variation trend of the Al component in the linearly graded AlGaN barrier layer of the present invention.

[0019] Figure 3This is a schematic diagram of the structure of the device proposed in the present invention after etching out the p-FETs gate groove in the p-FETs region, etching out the P-type heavily doped GaN layer, GaN channel layer and part of the linearly graded AlGaN barrier layer in the n-FETs gate-drain / gate-source regions, and etching out the p-FETs and n-FETs device isolation regions.

[0020] Figure 4 This is a schematic diagram of the complete structure of the GaN-based CMOS device based on the graded AlGaN barrier layer and the adjustable N-channel monolithic integrated epitaxial structure proposed by the present invention.

[0021] Figure 5 This is a schematic diagram of the CMOS circuit topology structure of the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is described in detail below with reference to the appended drawings.

[0023] The present invention proposes a GaN-based monolithic integrated CMOS circuit, the preparation method of which is to first prepare Figure 1 The epitaxial structure shown, along Figure 1 The epitaxial structure obtained from the bottom to top in the

[0001] growth direction includes a substrate 01, a III-nitride buffer layer 02 located above the substrate 01, a GaN channel layer 03 located above the III-nitride buffer layer 02, a linearly graded AlGaN barrier layer 04 located above the GaN channel layer, a GaN channel layer 05 located above the linearly graded AlGaN barrier layer 04, and a P-type heavily doped GaN layer 06 located above the GaN channel layer 05.

[0024] The GaN channel layer 05, the linearly graded AlGaN barrier layer 04, and the GaN channel layer 03 form a multi-dimensional heterojunction. A 2DHG is formed at the heterojunction interface between the GaN channel layer 05 and the linearly graded AlGaN barrier layer 04, a 3DHG is formed in the linearly graded AlGaN barrier layer 04, and a 2DEG is formed at the heterojunction interface between the linearly graded AlGaN barrier layer 04 and the GaN channel layer 03. The variation trend of the Al component size in the linearly graded AlGaN barrier layer is as follows: Figure 2 shown.

[0025] From left to right along the lateral direction, the surface of the CMOS device is divided into the p-FETs device area, the isolation area formed by etching or ion implantation between the p-FETs and n-FETs, and the n-FETs device area. Among them, the P-type heavily doped GaN layer 06, the GaN channel layer 05 and part of the linearly graded AlGaN barrier layer 04 in the drain / gate source region of the n-FETs region are etched away. Figure 3 shown.

[0026] From left to right along the lateral direction of the p-FET device surface, there are: a source structure consisting of a heavily P-type doped GaN layer 06 and a source metal 07 in the source region of the p-FET. The source ohmic metal 07 contacts the top of the heavily P-type doped GaN layer 06. A drain structure consisting of a heavily P-type doped GaN layer 06 and a drain metal 08 in the drain region of the p-FET. The drain ohmic metal 08 contacts the top of the heavily P-type doped GaN layer 06 at the other end of the p-FET device top surface away from the source structure. The p-FETs gate structure etches away part or all of the P-type heavily doped GaN layer 06 outside the drain and source regions, or etches away part or all of the P-type heavily doped GaN layer 06 in the gate region, and is located on the P-type heavily doped GaN layer 06 or GaN channel layer 05 between the source structure and the drain structure. The gate structure includes a gate metal 09 deposited on the gate groove and a gate dielectric 13 deposited on the gate groove and on the surface of the P-type heavily doped GaN layer 06 or GaN channel layer 05 between the drain and source.

[0027] From left to right along the lateral direction, the surface of the n-FETs device includes: a drain structure consisting of a partially linearly graded AlGaN barrier layer 04 in the n-FETs drain region and a drain metal 10. The drain ohmic metal 10 contacts the top of the portion of the linearly graded AlGaN barrier layer 04 remaining after etching. A source structure consisting of a partially linearly graded AlGaN barrier layer 04 in the n-FETs source region and a source metal 11. The other end of the source ohmic metal 11 on the n-FETs device top surface away from the drain structure contacts the top of the portion of the linearly graded AlGaN barrier layer 04 remaining after etching. The n-FETs p-GaN gate structure is located between the n-FETs source and drain structures. The n-FETs gate structure includes a gate metal 12 deposited on the p-type heavily doped GaN layer 06.

[0028] In the CMOS device, the p-FETs source metal 07 is used as the high-level signal VDD terminal of the CMOS circuit, the n-FETs source metal 11 is used as the ground or low-level signal GND terminal of the CMOS circuit, the p-FETs drain metal 08 and the n-FETs drain metal 10 are connected together as the output level signal terminal of the CMOS circuit, and the p-FETs gate metal 09 and the n-FETs gate metal 12 are connected together as the input level signal terminal of the CMOS circuit. Figure 5 shown.

[0029] The working principle of a GaN-based epitaxial structure and monolithic integrated CMOS circuit proposed in the present invention is as follows:

[0030] The current commercial enhancement-mode p-GaN gate HEMTs epitaxial structure has problems such as poor p-FET conduction characteristics, high p- / n-FET current mismatch, large device area differences, and poor P / N channel coordinated control capabilities and compatibility. Figure 4 This is a schematic diagram of the device structure of the present invention. The 3DHG brought by the linearly graded AlGaN barrier layer causes the distribution of the P channel not only at the 2DHG at the heterojunction interface between the GaN channel layer and the linearly graded AlGaN barrier layer, but also across the linearly graded AlGaN barrier layer in the 3DHG. Starting from improving the overall hole carrier concentration and the width of the P channel, an enhancement mode p-FET device with high on-current density is realized. In n-FETs based on the p-GaN gate structure, the linearly graded AlGaN helps to deplete the 2DEG concentration of the N channel below the p-GaN gate, thereby increasing the gate control capability and threshold voltage of n-FETs. Part of the linearly graded AlGaN barrier layer in the gate-drain / gate-source region of the n-FET is etched away. Since the Al component of the linearly graded AlGaN barrier layer decreases linearly from bottom to top, the retained high Al component helps to restore the 2DEG concentration, thereby achieving adjustable N-channel transport capability. This allows for a CMOS inverter with small p- / n-FET current mismatch and high P / N channel compatibility to be monolithically integrated on the same epitaxial structure.

Claims

1. A GaN-based monolithic integrated CMOS circuit, characterized in that: The invention comprises p-FETs and n-FETs, wherein the common structure of the p-FETs and n-FETs is a substrate (01), a group III nitride buffer layer (02), a GaN channel layer (03) and an AlGaN barrier layer (04) stacked in sequence in a vertical direction, wherein the Al component in the AlGaN barrier layer (04) is linearly gradient, and the gradient is gradually reduced from bottom to top, and the AlGaN barrier layer of the p-FETs and the AlGaN barrier layer of the n-FETs are isolated from each other; A 3DHG induced by polarization intensity gradient is distributed across the AlGaN barrier layer of the p-FETs, a GaN channel layer (05) is provided on the upper surface of the AlGaN barrier layer, a 2DEG is formed at the interface between the AlGaN barrier layer of the p-FETs and the GaN channel layer (05), and a P-type heavily doped GaN layer (06) is provided on the upper surface of the GaN channel layer (05); and a p-FETs source ohmic metal (07) and a p-FETs drain ohmic metal (08) are provided at both ends of the upper surface of the P-type heavily doped GaN layer (06), wherein The p-FETs drain ohmic metal (08) is located on a side close to the n-FETs; a groove gate structure is provided between the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08), the groove gate structure comprising a gate dielectric (13) and a first gate metal (09); the gate dielectric (13) is located in a groove formed on the upper surface of the P-type heavily doped GaN layer (06), wraps the lower part of the first gate metal (09), and contacts the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) on both sides respectively; The upper surface of the AlGaN barrier layer structure of the n-FETs also has a GaN channel layer (05), and the upper surface of the GaN channel layer (05) has a P-type heavily doped GaN layer (06); different from the p-FETs, part of the upper layer of the AlGaN barrier layer of the n-FETs, the GaN channel layer (05) and both sides of the P-type heavily doped GaN layer (06) are etched away, leaving only a portion of the middle gate area; a 2DEG is formed at the interface between the AlGaN barrier layer and the GaN channel layer (03) of the n-FETs, and both sides of the upper surface of the AlGaN barrier layer of the n-FETs have an n-FETs drain ohmic metal (10) and an n-FETs source ohmic metal (11), wherein the n-FETs drain ohmic metal (10) is located on the side close to the p-FETs; a second gate metal (12) is provided on the upper surface of the P-type heavily doped GaN layer (06) of the n-FETs to form a planar gate; The p-FETs source ohmic metal (07) is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal (11) is a low-level signal port of the CMOS circuit, the first gate metal (09) and the second gate metal (12) are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (08) and the n-FETs drain ohmic metal (10) are connected to form an output-level signal port of the CMOS circuit.

2. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the substrate (01) is one of Si, sapphire and SiC.

3. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) is any one of Pd / Au / Ni, Ni / Au and Pd / Ni.

4. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the first gate metal (09) is any one of Ti / Au, W / Au, Ni / Au, Mo / Au and Ru.

5. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The gate dielectric (13) is any one of an oxide layer and an insulating layer.

6. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The material used for the n-FETs drain ohmic metal (10) and the n-FETs source ohmic metal (11) is any one of Ti / Au, Ti / Al / Ni / Au and Ti / Al.

7. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that: The contact between the second gate metal (12) and the P-type heavily doped GaN layer (06) is an ohmic contact, and the material used for the second gate metal (12) is Ni / Au.

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