A monolithically integrated CMOS circuit based on GaN-based epitaxial structure

Abstract

The present invention belongs to the field of power semiconductor technology, and in particular relates to a monolithic integrated CMOS circuit based on a GaN-based epitaxial structure. The circuit of the present invention replaces the traditional AlGaN barrier layer with a fixed Al component with an AlGaN barrier layer having a high Al component and 2n-1 layers of AlGaN with different Al components stacked regularly. The Al component of the middle n-th layer of AlGaN is the highest value. By regulating the Al component size of the 1st to n-1th layers of AlGaN based on the Al component difference, it is possible to suppress the overall 2DEG concentration between the n-th to 2n-1th layers of AlGaN barrier layers and the GaN channel layer, thereby realizing an enhancement-mode n-FET with a high threshold voltage. For p-FETs under the same epitaxial structure, the overall increase in the Al component of the multiple AlGaN barrier layers helps to increase the concentration of 2DHG at the heterojunction interface between the overall multiple AlGaN barrier layers and the upper GaN channel layer, thereby realizing an enhancement-mode p-FET with a high on-current density, and promoting the development of CMOS-based all-GaN monolithic power integrated ICs.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a monolithic integrated CMOS circuit based on a GaN-based epitaxial structure. Background Art

[0002] Compared with traditional Si-based devices, GaN power devices have significant advantages in electron saturation velocity, bandgap width, and critical breakdown electric field. For example, the high concentration and high mobility 2DEG at the AlGaN / GaN heterojunction has become a unique feature of GaN power devices. Monolithic integration based on on-chip GaN CMOS not only simplifies circuit design, but also reduces the influence of parasitic inductance, realizing the most energy-efficient and efficient integrated topology with low static power consumption and strong noise resistance for the entire power switching system. GaN-based P-channel field-effect transistors (FETs) provide the possibility of on-chip CMOS. However, due to factors such as the low hole mobility of GaN at room temperature and the difficulty of significantly improving it, and the high ohmic contact resistivity of the device's drain and source, the on-current density of GaN p-FETs is much lower than that of the corresponding n-FETs, which is the main obstacle to the current realization of CMOS monolithic integration. Currently, in the commonly used commercial enhancement-mode p-GaN-gate HEMT power integration epitaxial structure, although the high-Al content AlGaN barrier layer has advantages such as a larger bandgap, a larger critical electric field, better thermal conductivity, and polarization discontinuity that can induce higher 2DEG and 2DHG concentrations, the high Al content difference in the heterojunction and the severe thermal and lattice mismatch can cause a large number of defects at the heterojunction interface, worsening the interface roughness and thus reducing overall device performance and reliability. At the same time, the high-concentration 2DEG p-GaN is difficult to deplete, which leads to degradation of the HEMTs threshold voltage.

[0003] Therefore, how to realize the advantages of high-Al content AlGaN barrier layers and avoid the deterioration of device performance caused by high-Al content AlGaN barrier layers is one of the key issues facing the bottleneck of CMOS-based all-GaN monolithic power integrated epitaxial structure. Summary of the Invention

[0004] To address the above problems, in order to realize GaN monolithic integrated CMOS devices with a high Al content AlGaN barrier layer, avoid the degradation of the multi-channel heterojunction interface quality and the degradation of the n-FETs threshold voltage, and at the same time achieve the improvement of the p- / n-FETs conduction characteristics and the output power and breakdown characteristics of the power devices, the present invention proposes a GaN-based epitaxial structure and a monolithic integrated CMOS circuit.

[0005] The technical solution adopted in the present invention is:

[0006] A monolithic integrated CMOS circuit based on a GaN-based epitaxial structure, characterized in that it includes p-FETs and n-FETs, wherein the p-FETs and n-FETs share a common structure comprising a substrate 01, a group III nitride buffer layer 02, a GaN channel layer 03, and an AlGaN barrier layer stacked in sequence along a vertical direction, and the AlGaN barrier layer of the p-FETs is isolated from the AlGaN barrier layer of the n-FETs;

[0007] The AlGaN barrier layer of the p-FETs includes 2n-1 AlGaN layers, where n≥1, and the topmost layer is defined as the first AlGaN layer, the middle layer is the nth layer, and the bottom layer is the 2n-1 layer, i.e., the 2n-1 AlGaN layer is in contact with the GaN channel layer 03; a GaN channel layer 05 is provided on the upper surface of the first AlGaN layer, and a P-type heavily doped GaN layer 06 is provided on the upper surface of the GaN channel layer 05; and both ends of the upper surface of the P-type heavily doped GaN layer 06 respectively have a p-FETs source ohmic metal 07 and a p-FETs drain ohmic metal 08, wherein the p-FETs drain ohmic metal 08 is located on the side close to the n-FETs; a trench gate structure is provided between the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 8, the trench gate structure comprising a gate dielectric 13 and a first gate metal 09, the gate dielectric 13 being located in a groove formed on the upper surface of the P-type heavily doped GaN layer 06, wrapping the lower portion of the first gate metal 09 and contacting the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 on both sides, respectively;

[0008] The AlGaN barrier layer structure of the n-FETs is the same as that of the p-FETs, and the AlGaN barrier layer further has a GaN channel layer 05 and a P-type heavily doped GaN layer 06 in sequence. The difference is that both sides of the AlGaN layer above the n-th layer in the AlGaN barrier layer of the n-FETs are completely etched away, leaving only a portion of the middle gate area. Similarly, both sides of the corresponding GaN channel layer 05 and the P-type heavily doped GaN layer 06 are also etched away; the n-FETs drain ohmic metal 10 and the n-FETs source ohmic metal 11 are respectively provided on both sides of the upper surface of the n-th layer of the AlGaN layer, wherein the n-FETs drain ohmic metal 10 is located on the side close to the p-FETs; a second gate metal 12 is provided on the upper surface of the P-type heavily doped GaN layer 06 of the n-FETs to form a planar gate;

[0009] The Al composition in the AlGaN layer constituting the AlGaN barrier layer is gradual. The Al composition ratio increases gradually from the 1st layer to the nth layer. The Al composition in the nth AlGaN layer is the highest. The Al composition ratio decreases gradually from the nth layer to the 2n-1th layer.

[0010] The p-FETs source ohmic metal 07 is the high-level signal port of the CMOS circuit, the n-FETs source ohmic metal 11 is the low-level signal port of the CMOS circuit, the first gate metal 09 and the second gate metal 12 are connected as the input level signal port of the CMOS circuit, and the p-FETs drain ohmic metal 08 and the n-FETs drain ohmic metal 10 are connected as the output level signal port of the CMOS circuit.

[0011] Furthermore, the material used for the substrate 01 is one of Si, sapphire and SiC.

[0012] Furthermore, the difference in Al composition between adjacent AlGaN layers is ≤30%.

[0013] Furthermore, the material used for the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 is any one of Pd / Au / Ni, Ni / Au, and Pd / Ni.

[0014] Furthermore, the material of the first gate metal 09 is any one of Ti / Au, W / Au, Ni / Au, Mo / Au, and Ru.

[0015] Furthermore, the gate dielectric 13 is any one of an oxide layer and an insulating layer.

[0016] Furthermore, the material used for the n-FETs drain ohmic metal 10 and the n-FETs source ohmic metal 11 is any one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al.

[0017] Furthermore, the contact between the second gate metal 12 and the P-type heavily doped GaN layer 06 is an ohmic contact, and the material used for the second gate metal 12 is Ni / Au.

[0018] The beneficial effect of the present invention is that, based on the epitaxial structure of commercial enhancement-mode p-GaN-gate HEMTs, the traditional AlGaN barrier layer with a fixed Al composition is replaced with an AlGaN barrier layer with a high Al composition, consisting of 2n-1 layers of AlGaN with different Al compositions. The Al composition of the middle nth AlGaN layer is the highest, and the Al composition difference between each AlGaN layer and between the AlGaN barrier layer and the GaN channel layer is ≤30%. This achieves the advantages of a high Al composition while effectively avoiding a significant degradation of the heterojunction interface quality. At the same time, the Al composition shows a decreasing trend from the nth AlGaN barrier layer to the n-1th AlGaN barrier layer, that is, the Al composition of the first AlGaN barrier layer close to the GaN channel layer is the lowest and is greater than 0%. By regulating the Al composition size of the 1st to the n-1th AlGaN layer within the rule of Al composition difference ≤ 30%, the overall 2DEG concentration between the nth to 2n-1th AlGaN barrier layers and the GaN channel layer can be suppressed, thereby realizing enhancement-mode n-FETs with high threshold voltage. Furthermore, during the fabrication of the p-GaN gate structure for n-FETs, etching away the entire heavily doped P-type GaN layer, GaN channel layer, and AlGaN barrier layers from the gate-drain / source regions not only helps restore the overall 2DEG concentration between the n-th to 2n-1-th AlGaN barrier layers and the GaN channel layer, but also, while maintaining the threshold voltage, fully utilizes the advantage of the highest Al content in the n-th AlGaN barrier layer to enhance the critical electric field, increase thermal conductivity, and thus improve breakdown voltage and high-power output characteristics. In p-FETs, the multi-AlGaN barrier layer with an overall high Al content helps increase the 2DHG concentration at the heterojunction interface between the GaN channel layer 05 and the multi-AlGaN barrier layer, thereby improving the on-current density of the p-FETs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the epitaxial structure of the device proposed in the present invention.

[0020] Figure 2 This is a schematic diagram of the energy band distribution of a reference structure in the epitaxial structure of the device proposed in the present invention.

[0021] Figure 3 This is a schematic diagram of the structure of the device proposed in the present invention after etching out the p-FETs gate groove in the p-FETs region, etching out the P-type heavily doped GaN layer, GaN channel layer and the 1st to n-1th AlGaN barrier layers in the n-FETs gate-drain / gate-source regions, and etching out the p-FETs and n-FETs device isolation regions.

[0022] Figure 4Schematic diagram of the change of 2DHG concentration with structural parameters of one of the devices proposed in this invention

[0023] Figure 5 Schematic diagram of the 2DEG concentration distribution of the nth to 2n-1th AlGaN barrier layers after etching all the P-type heavily doped GaN layers, GaN channel layers, and the 1st to n-1th AlGaN barrier layers in the gate-drain / gate-source regions of one of the devices proposed in the present invention.

[0024] Figure 6 This is a schematic diagram of the complete structure of the GaN-based CMOS device circuit proposed by the present invention based on high Al composition, high interface quality and multiple AlGaN barrier layers.

[0025] Figure 7 This is a schematic diagram of the CMOS circuit topology structure of the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention is described in detail below with reference to the appended drawings.

[0027] The present invention proposes a GaN-based epitaxial structure and a monolithic integrated CMOS circuit, the preparation method of which is to first prepare Figure 1 The epitaxial structure shown, along Figure 1 The epitaxial structure obtained from the bottom to top in the

[0001] growth direction includes a substrate 01, a III-nitride buffer layer 02 located above the substrate 01, a GaN channel layer 03 located above the III-nitride buffer layer 02, a multi-AlGaN barrier layer 04 located above the GaN channel layer, a GaN channel layer 05 located above the multi-AlGaN barrier layer 04, and a P-type heavily doped GaN layer 06 located above the GaN channel layer 05.

[0028] The GaN channel layer 05, the multi-AlGaN barrier layer 04 and the GaN channel layer 03 form a multi-layer stacked heterojunction. A 2DHG is formed at the heterojunction interface between the GaN channel layer 05 and the multi-AlGaN barrier layer 04, and a 2DEG is formed at the heterojunction interface between the multi-AlGaN barrier layer 04 and the GaN channel layer 03. The energy band distribution diagram is shown in FIG. Figure 2 shown.

[0029] From left to right along the lateral direction, the surface of the CMOS device is divided into the p-FETs device area, the isolation area formed by etching or ion implantation between the p-FETs and n-FETs, and the n-FETs device area. Among them, the P-type heavily doped GaN layer 06, GaN channel layer 05, and AlGaN 1 barrier layer 04 to AlGaN n barrier layer 04 in the drain / gate source region of the n-FETs region are etched away, as shown in the figure. Figure 3 The changes in 2DHG concentration are shown in Figure 4 and Figure 5 shown.

[0030] From left to right along the lateral direction of the p-FET device surface, there are: a source structure consisting of a heavily P-type doped GaN layer 06 and a source metal 07 in the source region of the p-FET. The source ohmic metal 07 contacts the top of the heavily P-type doped GaN layer 06. A drain structure consisting of a heavily P-type doped GaN layer 06 and a drain metal 08 in the drain region of the p-FET. The drain ohmic metal 08 contacts the top of the heavily P-type doped GaN layer 06 at the other end of the p-FET device top surface away from the source structure. The p-FETs gate structure is formed by etching away part or all of the P-type heavily doped GaN layer 06 outside the drain and source regions, or etching away part or all of the P-type heavily doped GaN layer 06 in the gate region. The gate structure is located on the P-type heavily doped GaN layer 06 or the GaN channel layer 05 between the source structure and the drain structure. The gate structure includes a gate metal 09 deposited on the gate groove and a gate dielectric 13 deposited on the gate groove and on the surface of the P-type heavily doped GaN layer 06 or the GaN channel layer 05 between the drain and source. Figure 6 shown.

[0031] From left to right along the lateral direction of the n-FET device surface, the following are: the source structure consisting of the AlGaN n barrier layer 04 in the n-FET drain region, the AlGaN 2n-1 barrier layer 04, and the drain metal 10. The drain ohmic metal 10 contacts the top of the etched AlGaN n barrier layer 04. The drain structure consisting of the AlGaN n barrier layer 04 in the n-FET source region, the AlGaN 2n-1 barrier layer 04, and the source metal 11. The other end of the source ohmic metal 11, away from the drain structure, contacts the top of the AlGaN n barrier layer remaining after etching. The n-FET p-GaN gate structure is located between the n-FET source and drain structures. The n-FET gate structure includes gate metal 12 deposited on the p-type heavily doped GaN layer 06.

[0032] In the CMOS device, the p-FETs source metal 07 is used as a CMOS circuit to connect the high-level signal V DD The n-FETs source metal 11 is used as the CMOS circuit ground or low-level signal GND terminal, the p-FETs drain metal 08 and the n-FETs drain metal 10 are connected together as the output level signal terminal of the CMOS circuit, and the p-FETs gate metal 09 and the n-FETs gate metal 12 are connected together as the input level signal terminal of the CMOS circuit. Figure 7 shown.

[0033] The working principle of the GaN-based epitaxial structure and monolithic integrated CMOS circuit preparation technology proposed in the present invention is as follows:

[0034] The current commercial enhancement-mode p-GaN-gate HEMTs epitaxial structure has the problem that if an AlGaN barrier layer with too high an Al content is used, there will be severe thermal and lattice mismatch, which will cause a large number of defects at the heterojunction interface and worsen the interface roughness, thereby reducing the 2DEG and 2DHG mobility, overall device performance and reliability. At the same time, the high-concentration 2DEG p-GaN is difficult to deplete, which in turn leads to problems such as degradation of the n-FETs threshold voltage. Figure 6 This is a schematic diagram of the device structure of the present invention. In n-FETs based on a p-GaN gate structure, regulating the Al composition of the 1st to n-1st AlGaN layers can help the p-GaN gate deplete the overall 2DEG concentration between the nth to 2n-1st AlGaN barrier layers and the underlying GaN channel layer, thereby increasing the gate control capability and threshold voltage of the n-FETs. After etching away the 1st to n-1st AlGaN barrier layers in the gate-drain / gate-source regions of the n-FETs, the nth AlGaN layer with a high Al composition can dominate the overall 2DEG concentration, N-channel transport capability, and high-voltage power performance of the n-FETs, thereby improving the corresponding performance. For p-FETs with the same epitaxial structure, the overall increase in the Al composition of the multiple AlGaN barrier layers helps to increase the 2DHG concentration at the heterojunction interface between the multiple AlGaN barrier layers and the upper GaN channel layer, thereby realizing enhancement-mode p-FETs with high on-current density and promoting the development of CMOS-based all-GaN monolithic power integrated circuits.

Claims

1. A monolithic integrated CMOS circuit based on a GaN-based epitaxial structure, characterized in that: The invention comprises p-FETs and n-FETs, wherein the common structure of the p-FETs and the n-FETs is a substrate (01), a group III nitride buffer layer (02), a GaN channel layer (03) and an AlGaN barrier layer stacked in sequence in a vertical direction, and the AlGaN barrier layer of the p-FETs and the AlGaN barrier layer of the n-FETs are isolated from each other; The AlGaN barrier layer of the p-FETs includes 2n-1 AlGaN layers, where n≥1, and the topmost layer is defined as the first AlGaN layer, the middle layer is the nth layer, and the bottom layer is the 2n-1 layer, i.e., the 2n-1 AlGaN layer is in contact with the GaN channel layer (03); a GaN channel layer (05) is provided on the upper surface of the first AlGaN layer, and a P-type heavily doped GaN layer (06) is provided on the upper surface of the GaN channel layer (05); and p-FETs source ohmic metal (07) and p-FET are provided at both ends of the upper surface of the P-type heavily doped GaN layer (06). s drain ohmic metal (08), wherein the p-FETs drain ohmic metal (08) is located on the side close to the n-FETs; a groove gate structure is provided between the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08), the groove gate structure comprising a gate dielectric (13) and a first gate metal (09), the gate dielectric (13) being located in a groove formed on the upper surface of the P-type heavily doped GaN layer (06), wrapping the lower part of the first gate metal (09) and contacting the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) on both sides respectively; The AlGaN barrier layer structure of the n-FETs is the same as that of the p-FETs, and the AlGaN barrier layer is sequentially provided with a GaN channel layer (05) and a P-type heavily doped GaN layer (06). Unlike the p-FETs, both sides of the AlGaN layer above the n-th layer in the AlGaN barrier layer of the n-FETs are completely etched away, leaving only a portion of the middle gate region. Similarly, both sides of the corresponding GaN channel layer (05) and the P-type heavily doped GaN layer (06) are also etched away; an n-FETs drain ohmic metal (10) and an n-FETs source ohmic metal (11) are respectively provided on both sides of the upper surface of the n-th AlGaN layer, wherein the n-FETs drain ohmic metal (10) is located on the side close to the p-FETs; a second gate metal (12) is provided on the upper surface of the P-type heavily doped GaN layer (06) of the n-FETs to form a planar gate; The Al composition in the AlGaN layer constituting the AlGaN barrier layer is gradual. The Al composition ratio increases gradually from the 1st layer to the nth layer. The Al composition in the nth AlGaN layer is the highest. The Al composition ratio decreases gradually from the nth layer to the 2n-1th layer. The p-FETs source ohmic metal (07) is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal (11) is a low-level signal port of the CMOS circuit, the first gate metal (09) and the second gate metal (12) are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (08) and the n-FETs drain ohmic metal (10) are connected to form an output-level signal port of the CMOS circuit.

2. The monolithic integrated CMOS circuit based on a GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the substrate (01) is one of Si, sapphire and SiC.

3. The monolithic integrated CMOS circuit based on a GaN-based epitaxial structure according to claim 1, characterized in that: The Al composition difference between adjacent AlGaN layers is ≤30%.

4. The monolithic integrated CMOS circuit based on a GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) is any one of Pd / Au / Ni, Ni / Au and Pd / Ni.

5. The monolithic integrated CMOS circuit based on a GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the first gate metal (09) is any one of Ti / Au, W / Au, Ni / Au, Mo / Au and Ru.

6. The monolithic integrated CMOS circuit based on a GaN-based epitaxial structure according to claim 1, characterized in that: The gate dielectric (13) is any one of an oxide layer and an insulating layer.

7. The monolithic integrated CMOS circuit based on a GaN-based epitaxial structure according to claim 1, characterized in that: The material used for the n-FETs drain ohmic metal (10) and the n-FETs source ohmic metal (11) is any one of Ti / Au, Ti / Al / Ni / Au and Ti / Al.

8. The monolithic integrated CMOS circuit based on a GaN-based epitaxial structure according to claim 1, characterized in that: The contact between the second gate metal (12) and the P-type heavily doped GaN layer (06) is an ohmic contact, and the material used for the second gate metal (12) is Ni / Au.

Images