Array substrate and preparation method thereof, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device, and relates to the technical field of display.The manufacturing method of the array substrate comprises the steps that a substrate is provided; forming a grid electrode on the substrate; forming an active layer on the grid electrode; depositing a second metal layer on the active layer, and patterning the second metal layer to form a source electrode, a drain electrode and a pixel electrode; wherein the grid electrode comprises a first grid electrode part, a first line connecting part, a second grid electrode part and a second line connecting part; the active layer specifically comprises a first active layer region, a second active layer region, a third active layer region and a fourth active layer region, the first active layer region and the first gate part are correspondingly arranged and overlapped, and the second active layer region and the first line connecting part are correspondingly arranged and overlapped; the third active layer region and the second gate portion are correspondingly arranged and overlapped, and the fourth active layer region and the second line connection portion are correspondingly arranged and overlapped. The garment can improve the forehead wrinkles.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] As people's requirements for panel display performance are getting higher and higher, some problems that affect panel display need to be solved. In TFT-LCD panels, especially products with DRD (Double Rate Driving) long and short hand design, head shake wrinkles are prone to occur. Head shake wrinkles cannot be seen when the observer is not moving, but they will be seen when the observer shakes his head. This phenomenon will affect the display effect of the monitor. Since the product process will fluctuate, this phenomenon will be particularly obvious when the process shifts. Generally, Cgs compensation is used to improve this process fluctuation problem. However, for 5mask products, conventional compensation methods cannot compensate in place, resulting in more serious head shake wrinkles when the process shifts. Summary of the invention

[0003] The main purpose of the present invention is to provide an array substrate, a display panel and a display device, aiming to improve the shaking head wrinkle problem of 5mask products.

[0004] To achieve the above object, the present invention provides a method for manufacturing an array substrate, the method comprising:

[0005] providing a substrate;

[0006] Depositing a first metal layer on the substrate, and patterning the first metal layer using a photomask to form a gate;

[0007] Depositing a gate insulating layer and a semiconductor layer in sequence on the gate, and patterning the semiconductor layer using a photomask to form an active layer;

[0008] After depositing a second metal layer on the active layer, the second metal layer is patterned using a photomask to form a source electrode, a drain electrode and a pixel electrode; wherein,

[0009] The gate has:

[0010] a first gate portion and a first wire connection portion connected to each other, and a second gate portion and a second wire connection portion connected to each other;

[0011] The active layer specifically includes a first active layer region, a second active layer region, a third active layer region and a fourth active layer region: wherein,

[0012] The first active layer region is disposed correspondingly and overlapped with the first gate portion, and the second active layer region is disposed correspondingly and overlapped with the first wire connection portion;

[0013] The third active layer region is disposed correspondingly to and overlaps with the second gate portion, and the fourth active layer region is disposed correspondingly to and overlaps with the second wire connection portion.

[0014] In one embodiment, the sum of the overlapping area of ​​the first active layer region and the first gate portion and the overlapping area of ​​the second active layer region and the first wire connection portion is recorded as a first overlapping area value;

[0015] The sum of the overlapping area between the third active layer region and the second gate portion and the overlapping area between the fourth active layer region and the second wire connection portion is recorded as a second overlapping area value;

[0016] The first overlapping area value is equal to the second overlapping area value.

[0017] In one embodiment, in the step of patterning the first metal layer using a first photomask to form a first gate line:

[0018] The gate further comprises a first line portion and a second line portion;

[0019] The first gate portion, the first line portion and the first line connecting portion form a first gap;

[0020] The second gate portion, the second line portion, and the second line connecting portion form a second notch.

[0021] In one embodiment, the step of patterning the semiconductor layer using a photomask to form an active layer specifically includes:

[0022] The first active region and the second active region are arranged at intervals, the first active region overlaps with the first gate portion, and the second active region overlaps with the first wire connection portion;

[0023] The third active region and the fourth active region are arranged at intervals, the third active region overlaps with the second gate portion, and the fourth active region overlaps with the second wire connection portion.

[0024] In one embodiment, in the step of patterning the second metal layer using a photomask to form a source electrode, a drain electrode and a pixel electrode:

[0025] An end of the first drain electrode close to the data line overlaps with the first active area;

[0026] An end of the first source electrode close to the data line overlaps with the first active area;

[0027] An end of the first source electrode away from the data line overlaps with the second active area;

[0028] An end of the second drain electrode close to the data line overlaps with the third active area;

[0029] An end of the second source electrode close to the data line overlaps with the third active area;

[0030] One end of the second source electrode away from the data line overlaps with the fourth active area.

[0031] The present invention further provides an array substrate, which is prepared by the above-mentioned method for manufacturing an array substrate, comprising a substrate, on which a plurality of pixel units are arranged, each pixel unit comprising a data line, a first gate line, a second gate line, a first thin film transistor and a second thin film transistor, wherein the first gate line and the second gate line are arranged at intervals, and the data line is arranged to cross the first gate line and the second gate line;

[0032] The first thin film transistor and the second thin film transistor are respectively arranged at one side of the data line and connected to the data line;

[0033] The first thin film transistor includes a first source electrode, a first drain electrode and a first active layer, the first active layer overlaps with the first gate line, and the first source electrode and the first drain electrode at least partially overlap with the first active layer, respectively.

[0034] The second thin film transistor comprises a second source electrode, a second drain electrode and a second active layer, the second active layer overlaps with the second gate line, and the second source electrode and the second drain electrode at least partially overlap with the first active layer respectively;

[0035] The value of the area of ​​the overlapping portion of the first source electrode and the first drain electrode with the first active layer is equal to the value of the area of ​​the overlapping portion of the second source electrode and the second drain electrode with the second active layer.

[0036] In one embodiment, the first active layer includes a first active region and a second active region, wherein the first active region is spaced apart from the second active region, the first active region is correspondingly arranged and overlapped with the first gate portion, and the second active region is correspondingly arranged and overlapped with the first wire connection portion;

[0037] And / or, the second active layer includes a third active region and a fourth active region, wherein the third active region and the fourth active region are arranged at intervals, the third active region is arranged correspondingly to and overlaps with the second gate portion, and the fourth active region is arranged correspondingly to and overlaps with the second wire connection portion.

[0038] In one embodiment, it further includes a first gate portion, a first line portion, and a first line connection portion, and a second gate portion, a second line portion, and a second line connection portion;

[0039] The first gate portion, the first line portion and the first line connecting portion form a first gap;

[0040] The first active layer overlaps with the first gate portion, the first notch and the first line connection portion, and does not overlap with the data line;

[0041] The second gate portion, the second line portion and the second line connecting portion form a second gap;

[0042] The second active layer overlaps with the second gate portion, the second notch, and the second line connection portion, but does not overlap with the data line.

[0043] In one embodiment, an end of the first drain electrode close to the data line overlaps with the first active region;

[0044] An end of the first source electrode close to the data line overlaps with the first active area;

[0045] An end of the first source electrode away from the data line overlaps with the second active area;

[0046] An end of the second drain electrode close to the data line overlaps with the third active area;

[0047] An end of the second source electrode close to the data line overlaps with the third active area;

[0048] One end of the second source electrode away from the data line overlaps with the fourth active area.

[0049] The present invention further provides a display panel, comprising the array substrate as described above.

[0050] The manufacturing method of the array substrate of the present invention comprises the following steps: depositing a first metal layer on a provided substrate, patterning the first metal layer using a photomask to form a gate; depositing a gate insulating layer and a semiconductor layer on the gate in sequence, patterning the semiconductor layer using a photomask to form an active layer; depositing a second metal layer on the active layer, patterning the second metal layer using a photomask to form a source electrode, a drain electrode and a pixel electrode; wherein the source electrode and the drain electrode overlap at least partially with the active layer respectively. The active region overlaps with the source electrode and the drain electrode of the first thin film transistor and the second thin film transistor to form a compensating parasitic capacitor. When the process is offset, the parasitic capacitor of the first thin film transistor and the second thin film transistor is compensated, so that the pixel voltage jump amount ΔVp of the first pixel region and the second pixel region is the same, thereby improving forehead wrinkles and improving display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0052] Figure 1 A schematic structural diagram of an embodiment of an array substrate provided by the present invention;

[0053] Figure 2 for Figure 1 A cross-sectional view of a first thin film transistor;

[0054] Figure 3 for Figure 1 A cross-sectional view of a second thin film transistor;

[0055] Figure 4 A schematic structural diagram of another embodiment of an array substrate provided by the present invention;

[0056] Figure 5 for Figure 4 A cross-sectional view of a first thin film transistor;

[0057] Figure 6 for Figure 4 A cross-sectional view of a second thin film transistor;

[0058] Figure 7 It is a schematic diagram of the pixel voltage of a pixel of a pixel unit of a 5-mask array substrate when the source and drain metal layers are not offset and offset;

[0059] Figure 8 This is a schematic diagram of the grayscale image observed macroscopically;

[0060] Fig. 9 It is a structural schematic diagram of an existing 4-mask array substrate;

[0061] Fig.10 for Figure 8 A cross-sectional view of a thin film transistor;

[0062] Fig.11 It is a structural schematic diagram of an existing 5mask array substrate;

[0063] Fig.12 for Fig.10 Cross-sectional view of a thin film transistor.

[0064] Description of Figure Numbers:

[0065] 1. substrate; 2. gate; 3. active layer; 4. source; 5. drain; 6. pixel electrode; 7. passivation layer; 8. pixel unit; 81. data line; 82. first gate line; 821. first gate portion; 822. first line portion; 823. first line connection portion; 824. first notch; 83. second gate line; 831. second gate portion; 832. second line portion; 833. second line connection portion; 834. second notch; 84. first thin film transistor; 841. first gate; 842. first insulating layer; 8 43. First active layer; 8431. First active region; 8432. Second active region; 844. First source-drain layer; 8441. First source electrode; 8442. First drain electrode; 85. Second thin film transistor; 851. Second gate electrode; 852. Second insulating layer; 853. Second active layer; 8531. Third active region; 8532. Fourth active region; 854. Second source-drain layer; 8541. Second source electrode; 8542. Second drain electrode; 86. First pixel region; 87. Second pixel region; 100. Array substrate.

[0066] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0069] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0070] See also Figure 7 The brightness of TFT LCD is regulated by the liquid crystal deflection caused by the voltage difference between pixel and CF ITO. Cgs is the parasitic capacitance between the gate metal and the source metal. When the gate 2 voltage drops from a high level (Vgon) to a low level (Vgoff) instantly, there will be a jump amount Vgs. This change Vgs will be coupled to the pixel electrode 6 by the parasitic capacitance Cgs, causing the pixel voltage Vp to jump. This jump amount is ΔVp. At this time, the actual pixel electrode 6 voltage Vpixel will become Vp-ΔVp. Therefore, when the Cgs of the left and right pixels are different, the ΔVp of the left and right pixels will be different, resulting in different Vpixel (pixel) voltages, resulting in brightness differences between pixels on both sides of the data line. Macroscopically, when observing the grayscale shake, you will see the shake head line, that is, the alternating light and dark stripes that can be observed when the user shakes his head, affecting the display quality.

[0071] See also Figure 8 Head shake lines are alternating light and dark stripes that can be observed by users of a display panel when they shake their heads. Figure 8 The left picture is the image observed when the user of the display panel does not shake his head. Figure 8 The right figure is the image observed when the user of the display panel shakes his head (that is, the image with the bad head wrinkles).

[0072] The inventors of the present invention have discovered that in products adopting the DRD (Double Rate Driving) long-short hand design, when the parasitic capacitance Cgs of the long-connected pixel thin film transistor and the parasitic capacitance Cgs of the short-connected thin film transistor are closer, the pixel voltage jump amount ΔVp of the long-connected pixel is closer to the pixel voltage jump amount ΔVp of the short-connected pixel, thereby reducing the display unevenness phenomenon (for example, the shaking head phenomenon).

[0073] See also Figures 9 to 12 The existing TFT-LCD manufacturing process usually adopts 4-mask process and 5-mask process. Figures 9 and 10 , where the 4-mask process is M1 mask→M2+AS mask (HF mask)→PV mask→ITOmask. M1 mask forms the gate metal layer, and M2+AS mask (HF mask) forms the source and drain layers and the active layer 3. Since M2 and AS are made by the same mask, there is an active layer 3 under the data line 81 and the source and drain layer, and the area of ​​the active layer 3 is larger than the source and drain layer. When the process is offset, the source metal and the drain metal overlap with the active layer 3, the parasitic capacitance Cgs of the thin film transistors on the left and right sides are equal, and the pixel voltage jump amount ΔVp of the thin film transistors on the left and right sides is equal, so the shaking head phenomenon is weakened.

[0074] See also Fig.11 and Fig.12 The process of 5mask is M1 mask→AS mask→M2 mask→PV mask→ITOmask. In 5mask, the AS and M2 processes are made separately. In order to reduce leakage and lower loading, AS is generally only made at the corresponding position of the thin film transistor.

[0075] In the actual production process, due to the process offset, the source and drain metal layers of the array substrate 1 are offset relative to the gate metal layer, and the overlapping areas of the source metal and drain metal of the thin film transistors on the left and right sides with the active layer 3 are not equal, resulting in the parasitic capacitance Cgs of the long-connected pixel thin film crystal of the array substrate 1 not being equal to the parasitic capacitance Cgs of the short-connected pixel thin film crystal, causing the shaking head phenomenon. Therefore, the Cgs compensation scheme for the array substrate 1 produced by the 4-mask process is not suitable for the Cgs compensation of the array substrate 1 produced by the 5-mask process.

[0076] The present invention provides a method for manufacturing an array substrate 1 .

[0077] An array substrate 1 for making a display device, which can be a display device with a display panel such as a television, a mobile phone, a computer, etc. The array substrate 1 is generally provided with thin-film transistors (TFT), pixel electrodes 6, common electrodes, common signal lines, data lines 81, scanning lines (gate lines), etc., wherein the scanning line (gate line) is electrically connected to the gate 2 of the thin-film transistor, the data line 81 and the pixel electrode 6 are respectively electrically connected to one of the source 4 or the drain 5 of the thin-film transistor, the scanning line (gate line) provides a scanning signal to control the connection or disconnection state of the source 4 and the drain 5, when the source 4 is connected to the drain 5, the data line 81 transmits a data signal to control the voltage of the pixel electrode 6, the common signal line is electrically connected to the common electrode and controls the voltage of the common electrode, and the liquid crystal molecules are controlled to rotate by controlling the voltage difference between the pixel electrode 6 and the common electrode, so that the display panel displays the content of the image.

[0078] In one embodiment of the present invention, the manufacturing method of the array substrate 100 includes:

[0079] Step S100, providing a substrate 1;

[0080] In this embodiment, the substrate 1 is a transparent substrate 1 , and the transparent substrate 1 may be a rigid substrate 1 made of transparent materials such as glass or plastic.

[0081] Step S200, depositing a first metal layer on the substrate 1, and patterning the first metal layer using a first photomask to form a gate 2;

[0082] The first metal layer can be formed on the substrate 1 by a physical vapor deposition (PVD) method, or prepared on the substrate 1 by a sputtering deposition process, and the metal layer is annealed to activate the metal layer. Of course, it can also be achieved by other processes known to those skilled in the art, which is not limited here.

[0083] The first metal layer can be made of metal materials such as copper Cu, molybdenum Mo, titanium Ti, aluminum Al, chromium Cr, silver Ag, gold Au, etc. For example, it can be implemented by a single metal layer of the above metals, or by a composite metal layer composed of any two or more metals. In this embodiment, it can be made of a single copper metal layer. The conductive isolation layer 30 can be a laminated structure of one or more multi-metal oxide conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), etc.

[0084] The first photomask includes an exposure area corresponding to the pattern of the gate 2 to be formed and the gate insulating layer covering the gate 2. Ultraviolet light, yellow light or other light sources are irradiated from the side of the first photomask away from the substrate 1 toward the substrate 1, and after the first metal layer and the gate insulating layer are exposed through the exposure area, a gate 2 and a gate insulating layer of a specific pattern are formed by an etching process, wherein the etching process can be implemented by a dry etching process or a wet etching process. Specifically, under the protection of a photoresist mask, a wet etching process can be applied to etch the metal layer and the gate insulating layer to etch away the portions of the metal layer and the gate insulating layer that are not covered by the photoresist mask. The gate 2 formed by the patterned first metal layer is used to subsequently form a thin film transistor. The insulating layer formed by the patterned gate insulating layer wraps and covers the gate 2 layer. Since the line width loss of the gate 2 after etching is less than that of the insulating layer, the insulating layer can completely cover and wrap the gate 2.

[0085] The gate insulating layer is configured to isolate the gate 2 from the active layer 3 subsequently formed on the gate insulating layer. The insulating layer can prevent current from flowing directly between the gate 2 and the source / drain 5, thereby ensuring normal switching operation of the transistor.

[0086] In the present embodiment, the material of the gate insulating layer can be a laminated structure of one or more insulating dielectric materials such as SiOx, SiNx, HfO2, Al2O3, etc., and the gate insulating layer is formed by a chemical vapor deposition process or other processes, or other processes known to those skilled in the art. A photoresist is deposited on the gate insulating layer. Exposure is performed through a photomask, wherein the photomask divides the gate insulating layer into a non-exposure area and an exposure area, and the exposure area is located on the gate 2 layer. The exposed substrate 1 is developed to retain the photoresist in the non-exposure area. The gate insulating layer not covered by the photoresist is incompletely etched to form a gate insulating layer to isolate the gate 2 from the active layer 3 subsequently formed on the gate insulating layer.

[0087] Step S300 , after depositing a gate insulating layer on the gate 2 , depositing a semiconductor layer on the gate insulating layer, and patterning the semiconductor layer using a second photomask to form an active layer 3 .

[0088] The active layer 3 is formed by forming a semiconductor layer on the gate insulating layer, exposing and developing the photoresist layer using a mask to obtain a photoresist mask, and etching the semiconductor layer using a dry etching process under the protection of the photoresist mask to etch away the portion of the semiconductor layer not covered by the photoresist mask.

[0089] The semiconductor layer may be selected from amorphous silicon (a-Si, Amorphous Silicon), polycrystalline silicon (p-Si, Polycrystalline Silicon), low-temperature polycrystalline silicon (LTPS, Low-Temperature Polycrystalline Silicon), and an oxide film layer. The oxide film layer may be a laminated structure of one or more multi-metal oxide conductive materials such as indium gallium zinc oxide (IGZO), aluminum-doped zinc oxide (AZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGTO), zinc tin oxide (ZTO), and the like, and may be formed by a chemical vapor deposition process. Of course, other processes known to those skilled in the art may also be used. After forming the semiconductor layer, a photomask may be used to expose and develop the photoresist layer to obtain a photoresist mask. Under the protection of the photoresist mask, a dry etching process may be used to etch the semiconductor layer to remove the portion of the semiconductor layer not covered by the photoresist mask, thereby forming an active layer 3 of a thin film transistor.

[0090] Step S400 , after depositing a second metal layer on the active layer 3 , patterning the second metal layer using a third photomask to form a source electrode 4 and a drain electrode 5 , wherein the source electrode 4 and the drain electrode 5 are at least partially overlapped with the active layer 3 , respectively.

[0091] See also Figures 1 to 6 In this embodiment, a semiconductor layer is deposited on the gate insulating layer, and the semiconductor layer is patterned by a second photomask to form an active layer 3. After a second metal layer is deposited on the active layer 3, the second metal layer is patterned by a third photomask to form a source 4 and a drain 5, so that the source 4 and the drain 5 overlap at least partially with the active layer 3, respectively. When the array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), since the drain 5 of the long-connected pixel thin film transistor and the drain 5 of the short-connected pixel thin film transistor always overlap with the active layer 3, the overlapping areas of the two are equal. When the source 4 of the long-connected pixel thin film transistor and the source 4 of the short-connected pixel thin film transistor overlap with the active layer 3, and the overlapping areas of the two are equal, the parasitic capacitance Cgs of the long-connected pixel thin film transistor and the parasitic capacitance Cgs of the drain 5 overlapping with the active layer 3 are the same. The pixel voltage jump amount ΔVp of the long connection pixel is the same as the pixel voltage jump amount ΔVp of the short connection pixel, so the generation of the head shaking phenomenon can be suppressed.

[0092] The second metal layer can be made of metal materials such as copper Cu, molybdenum Mo, titanium Ti, aluminum Al, chromium Cr, silver Ag, gold Au, etc. For example, it can be realized by using a single metal layer of the above metals, or a composite metal layer composed of any two or more metals. The metal film is formed by a physical vapor deposition (PVD) method or a magnetron sputtering method.

[0093] After film formation, the second metal layer can be patterned by a third photomask to form the source 4 and the drain 5, and at the same time, the second metal layer can be patterned by a third photomask to form the data line 81, and the data line 81 is electrically connected to the source 4 or the drain 5. Specifically, the third photomask includes an exposure area pattern corresponding to the data line 81, so that when the source 4 and the drain 5 are exposed to form, the data line 81 is also formed synchronously. The data line 81 outputs a data voltage to the source 4 or the drain 5, thereby controlling the pixel voltage of the pixel electrode 6. The data line 81, the source 4 and the drain 5 are formed in the same photomask exposure, which can effectively reduce the manufacturing process of the array substrate 100 of the display panel, thereby reducing the manufacturing cost of the array substrate 100 and the liquid crystal display.

[0094] The source electrode 4 and the drain electrode 5 can be formed as a metal film on the active layer 3 by magnetron sputtering, that is, after the active layer 3 is formed, the second metal layer is patterned by a third photomask to form the source electrode 4 and the drain electrode 5. The second metal layer also includes a data line 81, and the data line 81 can be formed by patterning the second metal layer by a third photomask. The data line 81 is electrically connected to the source electrode 4 or the drain electrode 5, and the gate 2 outputs a gate 2 voltage to connect the source electrode 4 and the drain electrode 5, thereby controlling the data line 81 to output a data voltage to the source electrode 4 or the drain electrode 5, and further controlling the pixel voltage of the pixel electrode 6.

[0095] Optionally, after the step of forming the source electrode 4 and the drain electrode 5, the method for manufacturing the array substrate 1 further includes: depositing a passivation layer 7 on the surface of the source electrode 4 and the drain electrode 5, and patterning the passivation layer 7 using a fourth photomask. The passivation layer 7 is stacked on the second metal layer. The passivation layer 7 is used to protect the source electrode 4 and the drain electrode 5 to prevent oxidation of the source electrode 4 and the drain electrode 5 of the metal material.

[0096] Optionally, after the step of forming the passivation layer 7 , the method for manufacturing the array substrate 1 further includes: depositing metal oxide on the passivation layer 7 , and patterning the metal oxide using a fifth photomask to form a pixel electrode 6 .

[0097] In this embodiment, the material of the gate insulating layer can be a stacked structure of one or more insulating dielectric materials such as SiOx, SiNx, HfO2, Al2O3, etc., and the gate insulating layer is formed by chemical vapor deposition process or other processes, or it can be other processes known to technical personnel in this field.

[0098] The technical solution of the present invention adopts the method of depositing a first metal layer on a provided substrate 1, patterning the first metal layer by a photomask to form a gate 2; depositing a gate insulating layer and a semiconductor layer on the gate 2 in sequence, patterning the semiconductor layer by a photomask to form an active layer 3; depositing a second metal layer on the active layer 3, patterning the second metal layer by a photomask to form a source 4, a drain 5 and a pixel electrode 6; wherein the source 4 and the drain 5 overlap at least partially with the active layer 3 respectively. The active region overlaps with the source 4 and the drain 5 of the first thin film transistor 84 and the second thin film transistor 85 to form a compensating parasitic capacitor. When the array process is offset, the parasitic capacitor of the first thin film transistor 84 and the second thin film transistor 85 is compensated, so that the pixel voltage jump amount ΔVp of the first pixel area 86 and the second pixel area 87 is the same, thereby improving forehead wrinkles and improving display quality.

[0099] Reference Figures 1 to 6 In an optional embodiment, the gate 2 formed by depositing a first metal layer on the substrate 1 and patterning the first metal layer using a mask includes the first gate line 82 and the second gate line 83. The first gate line 82 has a first gate portion 822 and a first line connection portion 823 connected to each other, and the first gate portion 822 is set as a first gate 841. The second gate line 83 has a second gate portion 831 and a second line connection portion 833 connected to each other, and the second gate portion 831 is set as a second gate 852. The active layer 3 overlaps with the first gate portion 822, the first line connection portion 823, the second gate portion 831 and the second line connection portion 833.

[0100] In this embodiment, the first gate line 82 and the second gate line 83 have a rotationally symmetrical structure. When the Array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), the overlapping area between the active layer 3 on one side of the data line 81 and the first gate portion 822 is reduced, and at the same time, the overlapping area between the active layer 3 and the first line connecting portion 823 is increased. Since the left and right ends of the active layer 3 on one side of the data line 81 have the same structure, the reduction in the overlapping area between the active layer 3 and the first gate portion 822 is offset by the increase in the overlapping area between the active layer 3 and the first line connecting portion 823, and the overlapping area between the active layer 3 on one side of the data line 81 and the corresponding gate line remains unchanged. It can be understood that, according to the same principle, when the Array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), the overlapping area of ​​the active layer 3 located on the other side of the data line 81 and the second gate portion 831 and the second line connection portion 833 remains unchanged.

[0101] Reference Figures 1 to 6 In an optional embodiment, the gate insulating layer and the semiconductor layer are sequentially deposited on the gate 2 , and the active layer 3 is formed by patterning the semiconductor layer using a mask. Specifically, both ends of the source electrode 4 overlap with the active layer 3 .

[0102] In this embodiment, since the sizes of the drain electrode 5, the source electrode 4 and the active layer 3 remain unchanged, only the positions change, and the drain electrode 5 always overlaps with the active layer 3, the overlapping area of ​​the drain electrode 5 and the active layer 3 remains unchanged. When the array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), since both ends of the source electrode 4 overlap with the active layer 3, the total overlapping area of ​​the source electrode 4 and the active layer 3 remains unchanged, and thus the parasitic capacitance Cgs formed remains unchanged, which can improve the shaking head wrinkles.

[0103] Reference Figures 2 to 5 In an optional embodiment, the gate insulating layer and the semiconductor layer are sequentially deposited on the gate 2, and the active layer 3 is formed by patterning the semiconductor layer using a mask. Specifically, the active layer 3 is:

[0104] The source electrode 4 completely overlaps with the active layer 3 .

[0105] In this embodiment, since the sizes of the drain electrode 5, the source electrode 4 and the active layer 3 remain unchanged, when the process is shifted, only the position changes, and the drain electrode 5 always overlaps with the active layer 3, so the overlapping area of ​​the drain electrode 5 and the active layer 3 remains unchanged. When the source electrode 4 completely overlaps with the active layer 3, the overlapping area of ​​the drain electrode 5, the source electrode 4 and the active layer 3 remains unchanged, so the parasitic capacitance Cgs formed remains unchanged, which can improve the shaking head wrinkles.

[0106] Reference Figures 1 to 6 In an optional embodiment, a first metal layer is deposited on the substrate 1, and the gate 2 formed by patterning the first metal layer using a mask has:

[0107] A first gate portion 822 and a first line connection portion 823 connected to each other, a second gate portion 831 and a second line connection portion 833 connected to each other, the first gate portion 822 is configured as a first gate 841, and the second gate portion 831 is configured as a second gate 852;

[0108] The active layer 3 formed by sequentially depositing a gate insulating layer and a semiconductor layer on the gate 2 and patterning the semiconductor layer using a mask specifically includes a first active layer region 8431, a second active layer region 8432, a third active layer region 8531 and a fourth active layer region 8532: wherein,

[0109] The first active layer region 8431 is arranged correspondingly to and overlaps with the first gate portion 822 , the second active layer region 8432 is arranged correspondingly to and overlaps with the first line connection portion 823 , the third active layer region 8531 is arranged correspondingly to and overlaps with the second gate portion 831 , and the fourth active layer region 8532 is arranged correspondingly to and overlaps with the second line connection portion 833 .

[0110] In this embodiment, the first gate line 82 and the second gate line 83 have a rotationally symmetrical structure. When the array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), the overlapping area between the first active layer region 8431 and the first gate portion 822 is reduced, and at the same time, the overlapping area between the third active layer region 8531 and the second gate portion 831 is increased. Since the structures of the left and right ends of the active layer 3 located on one side of the data line 81 are the same, the reduction in the overlapping area between the first active layer region 8431 and the first gate portion 822 is offset by the increase in the overlapping area between the third active layer region 8531 and the second gate portion 831.

[0111] Similarly, since the overlapping area between the second active layer region 8432 and the first line connection portion 823 is reduced, the overlapping area between the fourth active layer region 8532 and the second line connection portion 833 is increased. Since the structures of the left and right ends of the active layer 3 located on one side of the data line 81 are the same, the reduced overlapping area between the second active layer region 8432 and the first line connection portion 823 and the increased overlapping area between the fourth active layer region 8532 and the second line connection portion 833 are offset.

[0112] The sum of the overlapping areas of the first active layer region 8431 and the first gate portion 822 and the second active layer region 8432 and the first line connection portion 823 is equal to the sum of the overlapping areas of the third active layer region 8531 and the second gate portion 831 and the fourth active layer region 8532 and the second line connection portion 833. That is, the overlapping area of ​​the active layer on the left side of the data line and the first gate line is equal to the overlapping area of ​​the active layer on the right side of the data line and the second gate line, so the parasitic capacitance Cgs formed does not change, which can improve the shaking head wrinkles.

[0113] According to the same principle, when the array process is shifted (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), the parasitic capacitance Cgs formed remains unchanged, which can improve the shaking head pattern.

[0114] Reference Figures 1 to 6 In an optional embodiment, in the step of patterning the first metal layer using a first photomask to form a first gate line:

[0115] The gate 2 formed by depositing a first metal layer on the substrate 1 and patterning the first metal layer using a mask has a first gate portion 822, a first line portion 822 and a first line connecting portion 823, and a second gate portion 831, a second line portion 832 and a second line connecting portion 833;

[0116] The first gate portion 822 , the first line portion 822 and the first line connection portion 823 form a first notch 824 ;

[0117] The second gate portion 831 , the second line portion 832 and the second line connection portion 833 form a second notch 834 ;

[0118] The active layer 3 formed by patterning the semiconductor layer using a mask overlaps the first gate portion 822 , the first notch 824 , the first line connection portion 823 , the second gate portion 831 , the second notch 834 and the second line connection portion 833 , but does not overlap the data line 81 .

[0119] In the present embodiment, in the product adopting the DRD (Double Rate Driving) long-short hand design, the first gate portion 822, the first line portion 822 and the first line connecting portion 823 form a first notch 824. The second gate portion 831, the second line portion 832 and the second line connecting portion 833 form a second notch 834. The area of ​​the first notch 824 is the same as that of the second notch 834. According to the same principle, that is, the area where the active layer on the left side of the data line overlaps with the first gate line is equal to the area where the active layer on the right side of the data line overlaps with the second gate line, so the parasitic capacitance Cgs formed remains unchanged, which can improve the shaking head wrinkles.

[0120] Reference Figures 1 to 6 In an optional embodiment, the step of patterning the semiconductor layer using a mask to form the active layer 3 specifically includes:

[0121] A first active region 8431 and a second active region 8432 are formed in the active layer 3, wherein the first active region 8431 and the second active region 8432 are arranged at intervals, the first active region 8431 overlaps with the first gate portion 822, and the second active region 8432 overlaps with the first wire connection portion 823;

[0122] See also Figures 4 to 6 A third active region 8531 and a fourth active region 8532 are formed in the active layer 3 , wherein the third active region 8531 and the fourth active region 8532 are spaced apart from each other, the third active region overlaps with the second gate portion 831 , and the fourth active region 8532 overlaps with the second wire connection portion 833 .

[0123] Specifically, one end of the first drain 8442 and the first source 8441 opposite to the data line 81 overlaps with the first active area 8431 , and one end of the first source 8441 opposite to the data line 81 overlaps with the second active area 8432 .

[0124] One end of the second drain electrode 8542 and the second source electrode 8541 opposite to the data line 81 overlaps with the third active area 8531 , and one end of the second source electrode 8541 opposite to the data line 81 overlaps with the fourth active area 8532 .

[0125] One end of the first source electrode 8441 close to the data line 81 overlaps with the first active area 8431;

[0126] One end of the first source electrode 8441 away from the data line 81 overlaps with the second active area 8432;

[0127] One end of the second drain electrode 8542 close to the data line 81 overlaps with the third active area 8531;

[0128] One end of the second source electrode 8541 close to the data line 81 overlaps with the third active area 8531;

[0129] One end of the second source electrode 8541 away from the data line 81 overlaps with the fourth active region 8532 .

[0130] In this embodiment, the first active region 8431 is provided corresponding to the first gate portion 822. The second active region 8432 is provided corresponding to the first wire connection portion 823. The third active region 8531 is provided corresponding to the second gate portion 831. The fourth active region 8532 is provided corresponding to the second wire connection portion 833. A first wire portion 822 is provided between the first gate portion 822 and the first wire connection portion 823, and the first active region 8431 and the second active region 8432 are separated by the first wire portion 822. A second wire portion 832 is provided between the third active region 8531 and the fourth active region 8532, and the third active region 8531 and the fourth active region 8532 are separated by the second wire portion 832.

[0131] When the process is shifted, the sum of the overlapping areas of the first active layer region 8431 and the first gate portion 822 and the second active layer region 8432 and the first line connection portion 823 can also be made equal to the sum of the overlapping areas of the third active layer region 8531 and the second gate portion 831 and the fourth active layer region 8532 and the second line connection portion 833. That is, the overlapping area of ​​the active layer on the left side of the data line and the first gate line is equal to the overlapping area of ​​the active layer on the right side of the data line and the second gate line, so the parasitic capacitance Cgs formed remains unchanged, which can improve the shaking head wrinkles.

[0132] The present invention also provides an array substrate 1 .

[0133] Reference Figures 1 to 6 In one embodiment of the present invention, the array substrate 100 includes: a substrate 1, a plurality of pixel units 8 are arranged on the substrate 1, each pixel unit 8 includes a data line 81, a first gate line 82, a second gate line 83, a first thin film transistor 84 and a second thin film transistor 85, wherein the first gate line 82 and the second gate line 83 are arranged at intervals, and the data line 81 is arranged to cross the first gate line 82 and the second gate line 83;

[0134] The first thin film transistor 84 and the second thin film transistor 85 are respectively disposed on one side of the data line 81, and the first thin film transistor 84 and the second thin film transistor 85 are connected to the data line 81;

[0135] The first thin film transistor 84 includes a first source electrode 8441, a first drain electrode 8442 and a first active layer 843, the first active layer 843 overlaps with the first gate line 82, and the first source electrode 8441 and the first drain electrode 8442 overlap with the first active layer 843 at least partially, respectively.

[0136] The second thin film transistor 85 includes a second source electrode 8541 , a second drain electrode 8542 , and a second active layer 853 . The second active layer 853 overlaps with the second gate line 83 . The second source electrode 8541 and the second drain electrode 8542 overlap with the first active layer 843 at least partially, respectively.

[0137] In this embodiment, the first active layer 843 overlaps with the first gate line 82, the first source 8441 and the first drain 8442 respectively overlap with the first active layer 843 at least partially to form a first thin film transistor 84, the second thin film transistor 85 includes a second source 8541, a second drain 8542 and a second active layer 853, the second active layer 853 overlaps with the second gate line 83, the second source 8541 and the second drain 8542 respectively overlap with the first active layer 843 at least partially to form a second thin film transistor 85, when the Array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), the parasitic capacitance Cgs of the first thin film transistor 84 is the same as the parasitic capacitance Cgs of the second film, so the shaking head pattern can be suppressed.

[0138] In this embodiment, the first thin film transistor 84 and the second thin film transistor 85 are U-shaped thin film transistors, that is, the source 4 (or drain 5) of the thin film transistor is a U-shaped electrode, and at least part of the drain 5 (or source 4) of the thin film transistor is disposed in the opening of the U-shaped electrode. The opening directions of the first thin film transistor 84 and the second thin film transistor 85 are opposite, for example, the opening direction of the first thin film transistor 84 is to the left, and the opening direction of the second thin film transistor 85 is to the right.

[0139] Figures 1 to 6 In one embodiment of the present invention, the value of the overlapping area of ​​the first source 8441 and the first drain 8442 with the first active layer 843 is equal to the value of the overlapping area of ​​the second source 8541 and the second drain 8542 with the second active layer 853.

[0140] In this embodiment, the value of the overlapping area of ​​the first source 8441 and the first drain 8442 with the first active layer 843 is equal to the value of the overlapping area of ​​the second source 8541 and the second drain 8542 with the second active layer 853. When the overlapping areas are equal, the parasitic capacitance Cgs of the long-connected pixel thin film transistor and the parasitic capacitance Cgs of the drain 5 overlapping the active layer 3 are the same; the pixel voltage jump amount ΔVp of the long-connected pixel and the pixel voltage jump amount ΔVp of the short-connected pixel are the same, so the generation of the shaking head phenomenon can be suppressed.

[0141] Figures 1 to 6 In one embodiment of the present invention, the first gate line 82 includes a first gate portion 822 and a first line connection portion 823 connected to each other, and the first gate portion 822 is configured as a first gate 841;

[0142] The first active layer 843 overlaps the first gate portion 822 and the first wire connection portion 823;

[0143] The second gate line 83 includes a second gate portion 831 and a second line connection portion 833 connected to each other, and the second gate portion 831 is configured as a second gate 852;

[0144] The second active layer 853 overlaps the second gate portion 831 and the second wire connection portion 833 .

[0145] In this embodiment, the first gate line 82 and the second gate line 83 have a rotationally symmetrical structure. When the Array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), the overlapping area between the first active layer 843 and the first gate portion 822 on one side of the data line 81 is reduced, and at the same time, the overlapping area between the first active layer 843 and the first line connecting portion 823 is increased. Since the left and right ends of the first active layer 843 on one side of the data line 81 have the same structure, the reduction in the overlapping area between the first active layer 843 and the first gate portion 822 is offset by the increase in the overlapping area between the first active layer 843 and the first line connecting portion 823, and the overlapping area between the first active layer 843 and the first gate line 82 on one side of the data line 81 remains unchanged. It can be understood that, according to the same principle, when the Array process is offset (such as the active layer 3 moves 1um to the left and the second metal layer moves 1um to the right), the overlapping area of ​​the second active layer 853 on the other side of the data line 81 and the second gate portion 831 and the second line connection portion 833 remains unchanged. The overlapping area of ​​the first active layer 843 and the first gate line 82 is equal to the overlapping area of ​​the second active layer 853 and the second gate portion 831 and the second line connection portion 833. The pixel voltage jump amount ΔVp of the long connection pixel is the same as the pixel voltage jump amount ΔVp of the short connection pixel, so the generation of the shaking head phenomenon can be suppressed.

[0146] Reference Figures 1 to 6 , in order to make the parasitic capacitance Cgs of the long-connected pixel thin film transistor and the parasitic capacitance Cgs overlapped by the drain 5 and the active layer 3 the same; the pixel voltage jump amount ΔVp of the long-connected pixel and the pixel voltage jump amount ΔVp of the short-connected pixel are the same, thereby suppressing the generation of the shaking head phenomenon. In one embodiment of the present invention, both ends of the first source electrode 8441 overlap with the first active layer 843; both ends of the second source electrode 8541 overlap with the second active layer 853.

[0147] Reference Figure 2 , Figure 3 , Figure 6 , Fig. 9 and Fig.10 , in order to make the parasitic capacitance Cgs of the long-connected pixel thin film transistor and the parasitic capacitance Cgs overlapped by the drain 5 and the active layer 3 the same; the pixel voltage jump amount ΔVp of the long-connected pixel and the pixel voltage jump amount ΔVp of the short-connected pixel are the same, thereby suppressing the generation of the shaking head phenomenon. In one embodiment of the present invention, the first source electrode 8441 is entirely overlapped with the first active layer 843; the second source electrode 8541 is entirely overlapped with the second active layer 853.

[0148] In this embodiment, in addition to the active layer 3 being provided at the corresponding positions below the first drain 8442 and the second drain 8542, the active layer 3 is also provided at the corresponding positions below the first source 8441 and the second source 8541. The first drain 8442 is entirely overlapped with the first active layer 843, the second drain 8542 is entirely overlapped with the second active layer 853, the first source 8441 is entirely overlapped with the first active layer 843; the second source 8541 is entirely overlapped with the second active layer 853, and the Cgs of the first thin film transistor 84 and the second thin film transistor 85 are the same, so there is no voltage difference, which is equivalent to the compensation effect of 4mask. Compared with the Cgs compensation scheme in the 4mask process, the present invention does not have an active layer 3 provided under the data line 81, so the loading of the data line 81 is not increased, and the shaking head pattern improvement effect is better.

[0149] Reference Figure 4 and Figure 5 In one embodiment of the present invention, the first gate line 82 further includes a first gate portion 822, a first line portion 822 and a first line connection portion 823. The second gate line 83 includes a second gate portion 831, a second line portion 832 and a second line connection portion 833;

[0150] A first gap 824 is formed between the first gate portion 822 , the first line portion 822 and the first line connection portion 823 ;

[0151] The first active layer 843 overlaps with the first gate portion 822 , the first notch 824 , and the first line connection portion 823 , and does not overlap with the data line 81 ;

[0152] A second gap 834 is formed between the second gate portion 831 , the second line portion 832 and the second line connection portion 833 ;

[0153] The second active layer 853 overlaps with the second gate portion 831 , the second notch 834 , and the second line connection portion 833 , but does not overlap with the data line 81 .

[0154] In this embodiment, the first gate lines 82 and the second gate lines 83 are arranged to have a bent structure, which can better improve the aperture ratio of the array substrate 100 .

[0155] See also Fig. 9 and Fig.10In the compensation scheme of Cgs in the 4-mask process, since the first gap 824 is formed on the first gate line 82 and the second gap 834 is formed on the second gate line 83; when the backlight is turned on, the backlight will pass through the first gap 824 and the second gap 834 to illuminate the first active layer 843 and the second active layer 853, causing light leakage.

[0156] Reference Figures 4 to 6 In one embodiment of the present invention, the first active layer 843 includes a first active area 8431 and a second active area 8432, wherein the first active area 8431 and the second active area 8432 are spaced apart from each other, the first active area 8431 overlaps with the first gate portion 822, and the second active area 8432 overlaps with the first wire connection portion 823.

[0157] The second active layer 853 includes a third active region 8531 and a fourth active region 8532 , wherein the third active region 8531 and the fourth active region 8532 are arranged at intervals, the third active region 8531 overlaps with the second gate portion 831 , and the fourth active region 8532 overlaps with the second wire connection portion 833 .

[0158] In this embodiment, since the active layer 3 is not set at the positions corresponding to the first notch 824 and the second notch 834, when the backlight is turned on, the first gate portion 822, the first wire connection portion 823, the second gate portion 831 and the second wire connection portion 833 completely block the first active layer 843 and the second active layer 853, and the generated light leakage is small. This solution will neither increase the loading of the data line 81 nor increase the risk of light leakage.

[0159] Reference Figures 4 to 6 Specifically, one end of the first drain electrode 8442 and the first source electrode 8441 opposite to the data line 81 overlaps with the first active area 8431, and one end of the first source electrode 8441 opposite to the data line 81 overlaps with the second active area 8432;

[0160] One end of the second drain electrode 8542 and the second source electrode 8541 opposite to the data line 81 overlaps with the third active area 8531 , and one end of the second source electrode 8541 opposite to the data line 81 overlaps with the fourth active area 8532 .

[0161] The present invention also proposes a display panel, which includes an array substrate 1 prepared by the array substrate 1 preparation method as described above. The specific structure of the array substrate 1 refers to the above embodiment. Since the display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here one by one.

[0162] The present invention further provides a display device, including the array substrate 1 manufactured by the manufacturing method of the array substrate 1 as described above, or including the display panel as described above.

[0163] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing an array substrate, characterized in that: The method for manufacturing the array substrate comprises: providing a substrate; Depositing a first metal layer on the substrate, and patterning the first metal layer using a photomask to form a gate; Depositing a gate insulating layer and a semiconductor layer in sequence on the gate, and patterning the semiconductor layer using a photomask to form an active layer; After depositing a second metal layer on the active layer, the second metal layer is patterned using a photomask to form a source electrode and a drain electrode; wherein, The gate has: a first gate portion and a first wire connection portion connected to each other, and a second gate portion and a second wire connection portion connected to each other; The active layer specifically includes a first active layer region, a second active layer region, a third active layer region and a fourth active layer region: wherein, The first active layer region is disposed correspondingly and overlapped with the first gate portion, and the second active layer region is disposed correspondingly and overlapped with the first wire connection portion; The third active layer region is disposed correspondingly to and overlaps with the second gate portion, and the fourth active layer region is disposed correspondingly to and overlaps with the second wire connection portion.

2. The method for manufacturing an array substrate according to claim 1, wherein: In the step of sequentially depositing a gate insulating layer and a semiconductor layer on the gate and patterning the semiconductor layer using a mask to form an active layer: the sum of the overlapping area of ​​the first active layer region and the first gate portion and the overlapping area of ​​the second active layer region and the first wire connection portion is recorded as a first overlapping area value; The sum of the overlapping area between the third active layer region and the second gate portion and the overlapping area between the fourth active layer region and the second wire connection portion is recorded as a second overlapping area value; The first overlapping area value is equal to the second overlapping area value.

3. The method for manufacturing an array substrate according to claim 1, wherein: In the step of patterning the first metal layer using a first photomask to form a first gate line: The gate further comprises a first line portion and a second line portion; The first gate portion, the first line portion and the first line connecting portion form a first gap; The second gate portion, the second line portion, and the second line connecting portion form a second notch.

4. The method for manufacturing an array substrate according to claim 1, wherein: The step of patterning the semiconductor layer by using a photomask to form an active layer specifically includes: The first active region and the second active region are arranged at intervals, the first active region overlaps with the first gate portion, and the second active region overlaps with the first wire connection portion; The third active region and the fourth active region are arranged at intervals, the third active region overlaps with the second gate portion, and the fourth active region overlaps with the second wire connection portion.

5. The method for manufacturing an array substrate according to claim 1, wherein: In the step of patterning the second metal layer by using a photomask to form a source electrode, a drain electrode and a pixel electrode: An end of the first drain electrode close to the data line overlaps with the first active area; An end of the first source electrode close to the data line overlaps with the first active area; An end of the first source electrode away from the data line overlaps with the second active area; An end of the second drain electrode close to the data line overlaps with the third active area; An end of the second source electrode close to the data line overlaps with the third active area; One end of the second source electrode away from the data line overlaps with the fourth active area.

6. An array substrate, prepared by the method for manufacturing an array substrate according to any one of claims 1 to 5, characterized in that: A substrate is provided on which a plurality of pixel units are arranged, each pixel unit comprises a data line, a first gate line, a second gate line, a first thin film transistor and a second thin film transistor, wherein the first gate line and the second gate line are arranged at intervals, and the data line is arranged to cross the first gate line and the second gate line; The first thin film transistor and the second thin film transistor are respectively arranged at one side of the data line and connected to the data line; The first thin film transistor includes a first source electrode, a first drain electrode and a first active layer, the first active layer overlaps with the first gate line, and the first source electrode and the first drain electrode at least partially overlap with the first active layer, respectively. The second thin film transistor comprises a second source electrode, a second drain electrode and a second active layer, the second active layer overlaps with the second gate line, and the second source electrode and the second drain electrode at least partially overlap with the first active layer respectively; The value of the area of ​​the overlapping portion of the first source electrode and the first drain electrode with the first active layer is equal to the value of the area of ​​the overlapping portion of the second source electrode and the second drain electrode with the second active layer.

7. The array substrate according to claim 6, characterized in that: The first active layer includes a first active region and a second active region, wherein the first active region is spaced apart from the second active region, the first active region is correspondingly arranged and overlapped with the first gate portion, and the second active region is correspondingly arranged and overlapped with the first wire connection portion; And / or, the second active layer includes a third active region and a fourth active region, wherein the third active region is spaced apart from the fourth active region, the third active region is correspondingly arranged and overlapped with the second gate portion, and the fourth active region is correspondingly arranged and overlapped with the second wire connection portion.

8. The array substrate according to claim 6, wherein: Also includes a first gate portion, a first line portion and a first line connection portion and a second gate portion, a second line portion and a second line connection portion; A first gap is formed between the first gate portion, the first line portion and the first line connecting portion; The first active layer overlaps with the first gate portion, the first notch and the first line connection portion, and does not overlap with the data line; A second gap is formed between the second gate portion, the second line portion and the second line connecting portion; The second active layer overlaps with the second gate portion, the second notch and the second line connection portion, but does not overlap with the data line.

9. The array substrate according to claim 7, characterized in that: An end of the first drain electrode close to the data line overlaps with the first active area; An end of the first source electrode that is close to the data line and opposite to the data line overlaps with the first active area; An end of the first source electrode away from the data line overlaps with the second active area; An end of the second drain electrode close to the data line overlaps with the third active area; An end of the second source electrode that is close to the data line and is opposite to the data line overlaps with the third active area; One end of the second source electrode away from the data line overlaps with the fourth active area.

10. A display panel, comprising the array substrate as claimed in any one of claims 6 to 9.

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