Three-dimensional memory devices including variable thickness semiconductor channels and methods of forming same

Abstract

A semiconductor structure includes an alternating stack of insulating layers and conductive layers, wherein the conductive layers include word line conductive layers and first selection level conductive layers; memory openings extending vertically through the alternating stack; and a memory opening filling structure in the memory opening and including a memory film and a vertical semiconductor channel. A vertical cross-sectional profile of an outer sidewall of the vertical semiconductor channel is straight throughout the word line conductive layer and includes lateral protrusions at a level of the first select level conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] For all purposes, this application claims the benefit of the entire contents of U.S. non-provisional application No. 17 / 811,145, filed on July 7, 2022, entitled “THREE-DIMENSIONAL MEMORY DEVICE INCLUDING VARIABLE THICKNESS SEMICONDUCTOR CHANNELS AND METHOD OF FORMING THE SAME,” and is hereby incorporated by reference into this document. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to a three-dimensional memory device including a locally thickened semiconductor channel for gate induced drain leakage (GIDL) enhancement and a method of manufacturing the same. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor structure includes: an alternating stack of insulating layers and conductive layers, wherein the conductive layers include a word line conductive layer and a first selection level conductive layer; a memory opening extending vertically through the alternating stack; and a memory opening filling structure, the memory opening filling structure being located in the memory opening and including a memory film and a vertical semiconductor channel. The vertical cross-sectional profile of the outer sidewall of the vertical semiconductor channel is straight throughout the word line conductive layer and includes a lateral protrusion located at the level of the first selection level conductive layer.

[0006] According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers above a substrate, wherein the sacrificial material layers include a word line level sacrificial material layer including a first sacrificial material and at least one selected level sacrificial material layer including a second sacrificial material; forming a memory opening through the alternating stack; expanding the memory opening at each level of the at least one sacrificial material layer by performing an isotropic etching process for etching the second sacrificial material at a higher etching rate than the first sacrificial material; forming a memory opening filling structure in the memory opening, wherein the memory opening filling structure includes a memory film and a vertical semiconductor channel; and replacing the sacrificial material layer with a conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming a semiconductor device, a lower level dielectric layer, and a lower metal interconnection on a semiconductor substrate according to an embodiment of the present disclosure.

[0008] Figure 1B is a vertical cross-sectional view of an exemplary structure after forming a source level material layer in a process.

[0009] Figure 2 is a schematic vertical cross-sectional view of an exemplary structure after forming a stepped surface according to an embodiment of the present disclosure.

[0010] Figure 3 is a schematic vertical cross-sectional view of an exemplary structure after forming a patterned plate, a stepped dielectric material portion, and a drain select level isolation structure according to an embodiment of the present disclosure.

[0011] Figure 4 is a schematic vertical cross-sectional view of an exemplary structure after forming a storage opening and a support opening according to an embodiment of the present disclosure.

[0012] FIG. 5A to FIG. 5I are sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure according to an embodiment of the present disclosure.

[0013] Figure 6 is a schematic vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure and a support pillar structure according to an embodiment of the present disclosure.

[0014] Fig. 7A is a schematic vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric layer and through-stack trenches according to an embodiment of the present disclosure.

[0015] Figure 7B yes Fig. 7AA partial perspective top view of an exemplary structure of FIG. The articulated vertical plane A-A' is Fig. 7A A schematic vertical cross-sectional view of a plane.

[0016] Figure 8 is a schematic vertical cross-sectional view of an exemplary structure after forming sacrificial etch stop spacers according to an embodiment of the present disclosure.

[0017] Fig. 9 is a schematic vertical cross-sectional view of an exemplary structure after forming a substrate cavity according to an embodiment of the present disclosure.

[0018] Fig.10 is a schematic vertical cross-sectional view of an exemplary structure after forming a horizontal source layer according to an embodiment of the present disclosure.

[0019] Fig.11A is an enlarged view of a region surrounding a memory opening filling structure in an exemplary structure after an annealing process is performed according to an embodiment of the present disclosure.

[0020] Fig. 11B is an enlarged view of a region surrounding a memory opening fill structure in an alternative configuration of the exemplary structure after performing an annealing process according to an embodiment of the present disclosure.

[0021] Fig.12 is a schematic vertical cross-sectional view of an exemplary structure after removal of sacrificial etch stop spacers and formation of backside recesses according to an embodiment of the present disclosure.

[0022] Fig.13 is a schematic vertical cross-sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0023] Fig.14A yes Fig.13 Magnified view of the area surrounding the memory opening fill structure in an exemplary structure of FIG.

[0024] Fig. 14B yes Fig.13 Magnified view of the area surrounding the memory opening fill structure in an alternative configuration of an exemplary structure.

[0025] Fig.15 is a schematic vertical cross-sectional view of an exemplary structure after forming a trench-fill dielectric structure according to an embodiment of the present disclosure.

[0026] Fig.16A is a schematic vertical cross-sectional view of an exemplary structure after forming additional contact via structures, connecting via structures, and bitline level metal lines according to an embodiment of the present disclosure.

[0027] Fig. 16B yes Fig.16A A partial perspective top view of an exemplary structure of FIG. A vertical plane AA' is Fig.16A A schematic vertical cross-sectional view of a plane.

[0028] Fig.17A is a schematic vertical cross-sectional view of a first alternative configuration of a memory opening filling structure immediately after forming the memory opening filling structure according to an embodiment of the present disclosure.

[0029] Fig. 17B is a schematic vertical cross-sectional view of a first alternative configuration of a memory opening fill structure after replacing the sacrificial material layer with a conductive layer according to an embodiment of the present disclosure.

[0030] Fig.18A is a schematic vertical cross-sectional view of a second alternative configuration of a memory opening filling structure immediately after forming the memory opening filling structure according to an embodiment of the present disclosure.

[0031] Fig.18B is a schematic vertical cross-sectional view of a second alternative configuration of the memory opening fill structure after replacing the sacrificial material layer with a conductive layer according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] As discussed above, embodiments of the present disclosure relate to a three-dimensional memory device including a locally thickened semiconductor channel adjacent to a select gate electrode for gate induced drain leakage (GIDL) enhancement and a method of manufacturing the same, and various aspects of the three-dimensional memory device are described below. Embodiments of the present disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include semiconductor devices such as a three-dimensional memory array device including a plurality of NAND memory strings.

[0033] The accompanying drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of the present disclosure. The same figure numerals represent the same element or similar elements. Unless otherwise specified, elements with the same figure numerals are assumed to have the same composition. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, an element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the element and the surface of the second element, the element is "directly" located on the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components. As used herein, if there is a conductive path between an electronic component and a second electronic component, the electronic component is electrically connected to the second electronic component.

[0034] As used herein, "semiconductor material" refers to a semiconductor material having a -6 S / cm to 1.0×10 5 S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5 S / cm, and can produce materials with electrical conductivity in the range of 1.0 S / cm to 1.0×10 5 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / cm. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -6 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / cm). A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -6S / cm to 1.0×10 5 S / cm) in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0035] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0036] Typically, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded to each other, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. Each plane includes multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each storage block contains multiple pages, which are the smallest units that can be selected for programming.

[0037] refer to Figure 1A, showing an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a substrate 9 (such as a silicon wafer) and a semiconductor device 710 formed thereon. A shallow trench isolation structure 720 may be formed in the upper portion of the substrate 9 to provide electrical isolation from other semiconductor devices. The semiconductor device 710 may include, for example, field effect transistors, which include corresponding transistor active regions 742 (i.e., source regions and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. The semiconductor device 710 may include any semiconductor circuit to support the operation of the memory structure to be subsequently formed, which is generally referred to as a driver circuit, which is also referred to as a peripheral circuit. As used herein, peripheral circuits refer to any, each, or all of word line decoder circuits, word line switching circuits, bit line decoder circuits, bit line sensing and / or switching circuits, power supply / distribution circuits, data buffers, and / or latches, or may be any other semiconductor circuit that may be implemented outside of a memory array structure of a memory device. For example, a semiconductor device may include a word line switching device for electrically biasing a word line of a three-dimensional memory structure to be subsequently formed.

[0038] A dielectric material layer is formed over the semiconductor device, which is referred to herein as a lower level dielectric material layer 760. The lower level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and / or applies appropriate stress to underlying structures), a first dielectric material layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier) 766 overlying the first dielectric material layer 764, and at least one second dielectric layer 768.

[0039] The dielectric layer stack (which includes the lower level dielectric material layer 760) serves as a matrix of lower level metal interconnects 780 that provide electrical routing to and from various nodes of the semiconductor device and landing pads of subsequently formed through-memory level contact via structures. The lower level metal interconnects 780 are formed within the dielectric layer stack of the lower level dielectric material layer 760 and include a lower level metal line structure positioned below and optionally in contact with the bottom surface of the silicon nitride layer 766.

[0040] For example, the lower-level metal interconnect 780 may be formed within the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers in which various elements of the lower-level metal interconnect 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layer 764 may include any one of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and a dielectric metal oxide such as aluminum oxide. In one embodiment, the first dielectric material layer 764 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide). The lower level metal interconnect 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting corresponding source and drain nodes or gate electrodes of the contact device), intermediate lower level metal wire structures 784, lower level metal via structures 786, and landing pad level metal wire structures 788, wherein the landing pad level metal wire structures are configured to serve as landing pads for subsequently formed through memory level via structures.

[0041] A landing pad level metal line structure 788 may be formed within the topmost dielectric material layer of the first dielectric material layer 764 (which may be a plurality of dielectric material layers). Each of the lower level metal interconnects 780 may include a metal nitride liner and a metal fill structure. The top surface of the landing pad level metal line structure 788 and the topmost surface of the first dielectric material layer 764 may be planarized by a planarization process such as chemical mechanical planarization. A silicon nitride layer 766 may be formed directly on the top surface of the landing pad level metal line structure 788 and the topmost surface of the first dielectric material layer 764.

[0042] At least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organic silicate glass. In one embodiment, at least one second dielectric material layer 768 may include or consist essentially of a dielectric material layer having a dielectric constant of no more than 3.9 of undoped silicate glass (silicon oxide).

[0043] The region of semiconductor device 710 and the combination of lower level dielectric material layer 760 and lower level metal interconnect 780 is referred to herein as lower peripheral device region 700, which is positioned below subsequently formed memory level components and includes peripheral devices for the memory level components.

[0044] refer to Figure 1B, a source level material layer 110' in the process is formed on the lower level dielectric material layer 760, and the source level material layer in the process may include various layers that are subsequently modified to form the source level material layer. The source level material layer includes a source contact layer when formed, which is used as a common source region of the vertical field effect transistor of the three-dimensional memory device. In one embodiment, the source level material layer 110' in the process may include from bottom to top: a source level semiconductor layer 112 including a doped semiconductor material, a source level dielectric layer 113, a source level sacrificial layer 104 including a source level sacrificial material, a second source level dielectric layer 115, and a second source level semiconductor layer 116 including a doped semiconductor material.

[0045] The doped semiconductor material of the second source-level semiconductor layer 116 may be the same as or different from the doped semiconductor material of the source-level semiconductor layer 112. For example, the doped semiconductor material may include heavily doped polysilicon. Each of the source-level semiconductor layer 112 and the second source-level semiconductor layer 116 may have a thickness in a range of 100 nm to 1,000 nm, although lesser or greater thicknesses may also be employed.

[0046] Source level dielectric layer 113 and second source level dielectric layer 115 include a dielectric material such as silicon oxide. Each of source level dielectric layer 113 and second source level dielectric layer 115 may have a thickness in a range of 5 nm to 200 nm, although lesser and greater thicknesses may also be employed.

[0047] The source-level sacrificial material of the source-level sacrificial layer 104 includes a material that can be selectively removed relative to the doped semiconductor material of the source-level semiconductor layer 112 and the second source-level semiconductor layer 116. The source-level sacrificial material of the source-level sacrificial layer 104 may include silicon nitride, silicon-germanium alloy, undoped amorphous silicon, undoped polysilicon, organosilicate glass, or any other material that can be subsequently selectively removed relative to the material of the source-level semiconductor layer 112 and the second source-level semiconductor layer 116. The thickness of the source-level sacrificial layer 104 may be in the range of 50 nm to 600 nm, such as 100 nm to 300 nm, although lesser and greater thicknesses may also be employed.

[0048] In the process, a stack of multiple insulating layers 32 and sacrificial material layers 42 are formed alternately on the top surface of the source level material layer (112, 113, 104, 115, 116). As used herein, "material layer" refers to a layer including a material throughout its entirety. As used herein, an alternating plurality of elements and a second element refers to a structure in which an instance of an element and an instance of a second element are alternating. Each instance of an element that is not an end element of an alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of a second element that is not an end element of an alternating plurality of elements adjoins two instances of the element on both ends. The elements may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of an element and an instance of a second element may form a unit that is periodically repeated within an alternating plurality of elements.

[0049] The stack of alternating multiple insulating layers 32 and sacrificial material layers 42 is referred to herein as an alternating stack (32, 42). In one embodiment, each insulating layer 32 may be substantially composed of an insulating material. Insulating materials that can be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (such as aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials, which are generally referred to as high dielectric constant (high-k) dielectric oxides. In one embodiment, the material of the insulating layer 32 may be silicon oxide.

[0050] The sacrificial material layer 42 includes, from bottom to top, at least one source selection level sacrificial material layer 42S, a word line level sacrificial material layer 42W, and at least one drain selection level sacrificial material layer 42D. The word line level sacrificial material layer 42W includes a first sacrificial material, and at least one source selection level sacrificial material layer 42S and at least one drain selection level sacrificial material layer 42D include a second sacrificial material having a higher etching rate than the first sacrificial material. The second sacrificial material may have a different composition and / or a different density than the first sacrificial material to provide a higher etching rate.

[0051] According to one aspect of the present disclosure, the first sacrificial material and the second sacrificial material are selected so that there is an isotropic etching process that can etch the second sacrificial material at a higher etching rate than the first sacrificial material and the insulating material of the insulating layer 32. In one embodiment, the first sacrificial material and the second sacrificial material are selected so that the isotropic etching process selectively etches the first sacrificial material relative to the first sacrificial material and the insulating material of the insulating layer 32. As used herein, the removal of a first material is "selective" relative to a second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0052] In one embodiment, the isotropic etching process can provide an etching selectivity of greater than 10 and / or greater than 100 between the second sacrificial material and the insulating material of the insulating layer 32. In one embodiment, the isotropic etching process can provide an etching selectivity of greater than 2, and / or greater than 5, and / or greater than 10 between the second sacrificial material and the first sacrificial material.

[0053] In an illustrative example, the insulating layer 32 may include a silicon oxide material such as undoped silicate glass or doped silicate glass, the first sacrificial material of the word line level sacrificial material layer 42W may include a first silicon nitride material that is not doped with oxygen, and the second sacrificial material of the at least one source select level sacrificial material layer 42S and the at least one drain select level sacrificial material layer 42D may include a second silicon nitride material doped with oxygen (e.g., silicon oxynitride). In one embodiment, in an etchant including hot phosphoric acid, or a mixture of dilute hydrofluoric acid and ethylene glycol, or a mixture of dilute hydrofluoric acid and propylene glycol, the etching rate of the second silicon nitride material may be at least twice, and / or at least 5 times, and / or at least 10 times, that of the first silicon nitride material.

[0054] The insulating layer 32 may be deposited by, for example, chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0055] The topmost layer of the alternating stack (32, 42) may be an insulating layer 32, which is referred to as the topmost insulating layer 32T hereinafter. The thickness of the insulating layer 32 and the sacrificial material layer 42 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the paired insulating layer 32 and the sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 42 may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. The top gate electrode and the bottom gate electrode in the stack may be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) may have a uniform thickness that is substantially constant within each corresponding sacrificial material layer 42.

[0056] refer to Figure 2 , optionally by patterning the alternating stacks (32, 42) to form a stepped surface. The area including the stepped surface is referred to herein as a step area. As used herein, a "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from an edge of the horizontal surface, and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. An optional stepped cavity 69 is formed within the volume, and portions of the alternating stacks (32, 42) are removed from the volume by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0057] The stepped cavity 69 may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the bottom surface of the buffer dielectric layer 111. In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the cavity depth by one or more levels and a second type of etching process that laterally expands the area to be vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including an alternating plurality is defined as the relative position of a pair of first material layers and a second material layer within the structure.

[0058] Each sacrificial material layer 42 except the topmost sacrificial material layer 42 in the alternating stack (32, 42) extends laterally further than any overlying sacrificial material layer 42 in the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that extend continuously from a bottommost layer in the alternating stack (32, 42) to a topmost layer in the alternating stack (32, 42).

[0059] In one embodiment, all layers of the alternating stack (32, 42) except the bottommost insulating layer 32 may be patterned to provide a stepped surface. In this case, each layer of the alternating stack (32, 42) except the bottommost insulating layer 32 may have a corresponding physically exposed sidewall exposed to the stepped cavity 69. In one embodiment, each physically exposed sidewall of the sacrificial material layer 42 may vertically coincide with a physically exposed sidewall of a corresponding overlying or underlying insulating material layer 32. After forming the stepped surface, the lateral extent of the sacrificial material layer 42 decreases with the vertical distance from the source level material layer (112, 113, 104, 115, 116) in the process.

[0060] refer to Figure 3 , if a stepped cavity 69 is formed, a stepped dielectric material portion 65 (i.e., an insulating filling material portion) may be formed in the stepped cavity 69 by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F. In one embodiment, the stepped dielectric material portion 65 has a gradually increasing lateral extent that increases with the vertical distance from the substrate 9 .

[0061] The stepped dielectric material portion 65 contacts the sidewalls of the insulating layer 32 of the alternating stack (32, 42). In one embodiment, the stepped dielectric material portion 65 contacts the stepped surface of the alternating stack (32, 42) and has a variable lateral extent that increases with the vertical distance from a horizontal plane including the interface between the alternating stack (32, 42) and the in-process source level material layer (112, 113, 104, 115, 116).

[0062] Optionally, a drain selection level isolation structure 72 may be formed through the topmost insulating layer 32T and at least one drain selection level sacrificial material layer 42D located at the drain selection level. The drain selection level isolation structure 72 may be formed, for example, by forming a drain selection level isolation trench and filling the drain selection level isolation trench with a dielectric material such as silicon oxide. Excess portions of the dielectric material may be removed from above the top surface of the topmost insulating layer 32T.

[0063] refer to Figure 4 A photolithographic material stack (not shown) including at least a photoresist layer may be formed over the topmost insulating layer 32T and the stepped dielectric material portion 65, and the photolithographic material stack including at least a photoresist layer may be photolithographically patterned to form openings therein. The openings include a first group of openings formed over the memory array region 100 where each layer of the alternating stack (32, 42) exists and a second group of openings formed over the staircase region 300 including the stepped surface of the alternating stack (32, 42). The pattern in the photolithographic material stack may be transferred through the topmost insulating layer 32T or the stepped dielectric material portion 65, and the pattern in the photolithographic material stack may be transferred through the alternating stack (32, 42) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. Portions of the alternating stack (32, 42) below the openings in the patterned photolithographic material stack are etched to form memory openings 49 and support openings 19. As used herein, "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, "support opening" refers to a structure in which a support structure (such as a support post structure) is subsequently formed to mechanically support other elements. Memory opening 49 is formed through the topmost insulating layer 32T and the entire alternating stack (32, 42) in the memory array area 100. Support opening 19 is formed through the stepped dielectric material portion 65 and the portion of the alternating stack (32, 42) located below the stepped surface in the staircase area 300.

[0064] The memory opening 49 extends through the entirety of the alternating stack (32, 42). The support opening 19 extends through a subset of the layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch the material through the alternating stack (32, 42) can be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0065] The memory openings 49 and the support openings 19 may extend from the top surface of the alternating stack (32, 42) to the upper portion of the source-level semiconductor layer 112. The surface of the source-level semiconductor layer 112 may be physically exposed at the bottom of each memory opening 49 and at the bottom of each support opening 19.

[0066] FIG. 5A to FIG. 5I are sequential vertical cross-sectional views of memory opening 49 during formation of memory opening filling structure 58 according to an embodiment of the present disclosure.

[0067] refer to Figure 5A , a memory opening 49 is shown, which vertically extends from the topmost insulating layer 32T to the source-level semiconductor layer 112 .

[0068] refer to Figure 5B , a selective isotropic etching process may be performed to expand each memory opening 49 at each level of the selection level sacrificial material layer (42S, 42D). The selective isotropic etching process may be an isotropic etching process that etches the second sacrificial material of the selection level sacrificial material layer (42S, 42D) at a higher etching rate than the first sacrificial material of the word line level sacrificial material layer 42W. The selective isotropic etching process may also selectively etch the second sacrificial material relative to the material of the insulating layer 32. In one embodiment, the ratio of the etching rate of the second sacrificial material to the first sacrificial material may be greater than 2, and / or may be greater than 5, and / or may be greater than 10. In one embodiment, the etching rate of the second sacrificial material to the material of the insulating layer 32 may be greater than 10 and / or greater than 100.

[0069] In one embodiment, the insulating layer 32 may include silicon oxide and / or may consist essentially of silicon oxide, the first sacrificial material of the word line level sacrificial material layer 42W may include a first silicon nitride material having a relatively low etching rate (e.g., undoped silicon nitride), and the second sacrificial material of the selection level sacrificial material layer (42S, 42D) may include a second silicon nitride material having a relatively high etching rate (e.g., oxygen-doped silicon nitride). In this case, the selective isotropic etching process may include a wet etching process using hot phosphoric acid, or a mixture of dilute hydrofluoric acid and ethylene glycol, or a mixture of dilute hydrofluoric acid and propylene glycol.

[0070] Each memory opening is laterally expanded at each level of the selective level sacrificial material layer (42S, 42D). Each portion of the memory opening 49 located at the level of the selective level sacrificial material layer (42S, 42D) is expanded by an isotropic etching process to form an annular recessed cavity 49R. Each annular recessed cavity 49R can be vertically defined by the corresponding overlying insulating layer 32 and the corresponding underlying insulating layer 32, and can be laterally defined by the recessed sidewalls of the corresponding selective level sacrificial material layer (42S, 42D). The duration of the selective isotropic etching process can be performed so that the recessed sidewalls of the selective level sacrificial material layer (42S, 42D) are vertically offset outwardly from the cylindrical vertical plane including the sidewalls of the corresponding overlying insulating layer 32 and the corresponding underlying insulating layer 32 by a lateral offset distance. The lateral offset distance can be in the range of 20nm to 200nm (such as between 30nm and 100nm), but smaller or larger lateral offset distances can also be used.

[0071] Although Figure 5A and Figure 5B , an embodiment in which the alternating stack includes two source selection level sacrificial material layers 42S and one drain selection level sacrificial material layer 42D is shown, but the total number of source selection level sacrificial material layers 42S may be any integer in the range of 1 to 8, and the total number of drain selection level sacrificial material layers 42D may be any integer in the range of 1 to 8. Therefore, although only one drain selection level sacrificial material layer 42D is shown, in other embodiments, there may be two or more (such as, two to eight) drain selection level sacrificial material layers 42D overlying the word line level sacrificial material layers 42W. In this case, the uppermost drain selection level sacrificial material layer 42D includes the second sacrificial material (e.g., oxygen-doped silicon nitride), and the additional drain selection level sacrificial material layers 42D may include the second sacrificial material and / or the first sacrificial material (e.g., undoped silicon nitride). Other alternative embodiments in which the total number of source select level sacrificial material layers 42S and / or the total number of drain select level sacrificial material layers 42D are different than those represented in the drawings.

[0072] refer to Figure 5C , a memory film 50 including a layer stack including a blocking dielectric layer 52, a memory material layer 54 and a dielectric material liner 56 may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

[0073] Subsequently, a memory material layer 54 may be formed. In general, the memory material layer may include any memory material, such as a charge storage material, a ferroelectric material, a phase change material, or any material that can store a data bit in the form of the presence or absence of charge, ferroelectric polarization direction, resistivity, or another measurable physical parameter. In one embodiment, the memory material layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the memory material layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within a lateral recess. In one embodiment, the memory material layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the memory material layer 54 may be formed as a single continuous layer.

[0074] The memory material layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of the memory material layer 54 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be employed.

[0075] The dielectric material liner 56 is an optional material layer that may or may not be used. In the case where the memory material layer 54 includes a charge storage layer, the dielectric material liner 56 may include a tunneling dielectric layer, which includes a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The dielectric material liner 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, their alloys and / or their combinations. In one embodiment, the dielectric material liner 56 may include a stack of a silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the dielectric material liner 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of dielectric material liner 56 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0076] Generally, the memory film 50 is deposited in each annular recessed cavity 49R and on the sidewalls of the insulating layer 32 around the memory opening 49. In one embodiment, the thickness of the memory film 50 is less than half the height of each annular recessed cavity 49R. Therefore, after the memory film 50 is formed, an unfilled annular gap exists at each level of the annular recessed cavity 49R.

[0077] refer to Figure 5D , an amorphous channel material layer 60A may be deposited over the memory film 50. The amorphous channel material layer 60A includes at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, or other semiconductor materials known in the art. The amorphous channel material layer 60A may include amorphous silicon. In one embodiment, the amorphous channel material layer 60A completely fills the recess 49R.

[0078] The amorphous channel material layer 60A may include a low-doped or undoped amorphous semiconductor material, i.e., intrinsic amorphous silicon or a low-doped amorphous silicon doped with a dopant of a first conductivity type (e.g., p-type). Therefore, the amorphous channel material layer 60A may include a total atomic concentration of not more than 1.0×10 15 / cm 3 , and / or not more than 1.0×10 14 / cm 3 , and / or not more than 1.0×10 13 / cm 3 The thickness of the amorphous channel material layer 60A is selected so that a vertically extending unfilled gap 49V remains in each memory opening 49. For example, the thickness of the amorphous channel material layer 60A can be in the range of 20nm to 100nm, but lesser or greater thicknesses can also be used.

[0079] refer to Figure 5E , an annealing process may be performed to transform the amorphous channel material layer 60A into a polycrystalline channel material layer 60P (e.g., a polysilicon layer). The elevated temperature of the annealing process may be in the range of 650 degrees Celsius to 1,100 degrees Celsius. The duration of the annealing process may be in the range of 1 second to 2 hours. Generally speaking, the higher the elevated temperature of the annealing process, the shorter the duration of the annealing process.

[0080] refer to Fig. 5F, the polycrystalline channel material layer 60P may be isotropically etched back so that the remaining portion of the polycrystalline channel material layer 60P has a thickness in the range of 3 nm to 60 nm (such as 6 nm to 20 nm). The thinned remaining portion of the polycrystalline channel material layer 60P is referred to herein as a thinned semiconductor channel material layer 60T. The thinned semiconductor channel material layer 60T includes a polycrystalline semiconductor material (e.g., intrinsic or low-doped polysilicon of the first conductivity type).

[0081] refer to Figure 5G , a dielectric core layer can be deposited in the unfilled volume of the memory opening 49 and / or the support opening 19 (e.g., in the void 49V). The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method, such as low pressure chemical vapor deposition (LPCVD), or by a self-planarization deposition process, such as spin coating. The horizontal portion of the dielectric core layer overlying the top surface of the alternating stack (32, 42) can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the topmost insulating layer 32T and the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0082] See also Figure 5H , an amorphous drain semiconductor material may be deposited in a cavity overlying the dielectric core 62. The amorphous drain semiconductor material, the thinned semiconductor channel material layer 60T, and the portion of the memory film 50 overlying a horizontal plane including the top surface of the topmost insulating layer 32T may be removed by a planarization process such as a chemical mechanical planarization (CMP) process. Each remaining portion of the amorphous drain semiconductor material constitutes an amorphous drain semiconductor material portion 67. In one embodiment, the amorphous drain semiconductor material portion 67 may include doped amorphous silicon containing an atomic concentration of 1.0×10 18 / cm 3 to 1.0×10 21 / cm 3 Dopants of the second conductivity type (e.g., phosphorus and / or arsenic) are present in the range of about 100 Å to about 500 Å, although lesser or greater dopant concentrations may also be used.

[0083] refer to Fig.5I, a post-deposition annealing process (e.g., rapid thermal annealing or furnace annealing) may be performed to outdiffuse the second conductivity type dopant into the top region of the thinned semiconductor channel material layer 60T. In this case, the amorphous drain semiconductor material portion 67 may be transformed into a polycrystalline (e.g., polysilicon) drain region 63, and the out-diffused dopant forms a drain extension region 63E in the top region of the thinned semiconductor channel material layer 60T. The atomic concentration of the second conductivity type dopant in the drain extension region 60E may be in the range of 1.0×10 16 / cm 3 to 1.0×10 18 / cm 3 range, but smaller or larger dopant concentrations may also be used.

[0084] The remaining portion of the thinned semiconductor channel material layer 60T includes the vertical semiconductor channel 60. In some embodiments, the boundary between the vertical semiconductor channel 60 of the first conductivity type and the drain extension region 63E of the second conductivity type may be formed at or below a portion of the semiconductor material filling the volume of the annular recess cavity 49R at the level of the drain selection level sacrificial material layer 42D. A pn ​​junction may be formed between the drain extension region 63E and the vertical semiconductor channel 60.

[0085] The combination of all material portions located in the memory openings 49 constitutes a memory opening filling structure 58. Each support opening 19 can be filled with a corresponding set of material portions having the same material composition as the corresponding components in the memory opening filling structure 58. Each set of material portions filling the support openings 19 is referred to herein as a support pillar structure 20. Each of the memory opening filling structures 58 includes a corresponding vertical semiconductor channel 60 and a corresponding vertical stack of memory elements, which can be implemented, for example, as a portion of a corresponding memory material layer 54 located at the level of the sacrificial material layer 42. Each memory opening filling structure 58 is formed on the sidewalls of the source level sacrificial layer 104.

[0086] According to one aspect of the present disclosure, the vertical semiconductor channel 60 includes at least one lateral protrusion portion formed in the corresponding annular recessed cavity 49R. In one embodiment, the vertical cross-sectional profile of the outer sidewall of the memory film 50 is straight in the entire word line sacrificial material layer 42W, and includes a first lateral protrusion 501 located at the level of the first selection level sacrificial material layer (42S, 42D) in the at least one selection level sacrificial material layer (42S, 42D). The first selection level sacrificial material layer (42S, 42D) may be any one of the at least one source selection level sacrificial material layer 42S and / or the at least one drain selection level sacrificial material layer 42D. In one embodiment, the memory film 50 has a uniform thickness in the vertical extension section in the first lateral protrusion 501, in the horizontal extension section in the first lateral protrusion 501, and in the portion extending straightly in the entire word line sacrificial material layer 42W. In other words, the memory film 50 is continuous and has a uniform thickness.

[0087] In one embodiment, the vertical cross-sectional profile of the outer sidewall of the vertical semiconductor channel 60 includes a second lateral protrusion 601 located at the level of a first selection level sacrificial material layer (42S, 42D), which may be any one of at least one source selection level sacrificial material layer 42S and at least one drain selection level sacrificial material layer 42D. In one embodiment, the vertical cross-sectional profile of the inner sidewall of the vertical semiconductor channel 60 is straight throughout each of the word line sacrificial material layer 42W and at least one selection level sacrificial material layer (42S, 42D). In one embodiment, the vertical extent of the first lateral protrusion 501 is the same as the vertical spacing between the overlying insulating layer 32 in the insulating layer 32 that contacts the annular top surface of the first lateral protrusion and the underlying insulating layer 32 in the insulating layer 32 that contacts the annular bottom surface of the first lateral protrusion 501. In one embodiment, the memory film 50 has a uniform thickness in the vertically extending segments within the first lateral protrusion 501, in the horizontally extending segments within the first lateral protrusion 501, and in the portions extending linearly throughout the word line sacrificial material layer 42W. In one embodiment, the vertical extent of the second lateral protrusion 601 (e.g., source selection level) is the same as the vertical extent of the first lateral protrusion 501 minus twice the uniform thickness of the memory film 50.

[0088] In one embodiment, the memory opening filling structure 58 includes a drain region 63, which is located at the upper end of the vertical semiconductor channel 60 of the first conductivity type and includes a dopant of a second conductivity type opposite to the first conductivity type. In one embodiment, the drain extension region 63E is adjacent to the drain region 63 and forms a pn junction at the interface with the vertical semiconductor channel 60.

[0089] In one embodiment, the vertical semiconductor channel 60 has a uniform lateral thickness between the straight inner sidewall segments and the straight outer sidewall segments of the entire word line sacrificial material layer 42W. In one embodiment, the second lateral protrusion 601 has a lateral thickness between the outer sidewall and the inner sidewall, which is greater than the uniform lateral thickness of the vertical semiconductor channel. The lateral thickness of the second lateral protrusion 601 can be approximately the same as the lateral recess distance of the annular recess cavity 49R. In one embodiment, the second lateral protrusion 601 includes the end region of the vertical semiconductor channel, and the entire inner sidewall of the vertical semiconductor channel 60 can be straight. In one embodiment, the outer sidewall of the vertical semiconductor channel 60 is straight at each level of the word line sacrificial material layer 42W and includes a first lateral protrusion 501 located at the level of the first selected level sacrificial material layer (42S and / or 42D).

[0090] refer to Figure 6 , shows an exemplary structure after forming the memory opening filling structure 58 and the support pillar structure 20. Each memory opening 49 is filled with the memory opening filling structure 58. Each support opening 19 is filled with the support pillar structure 20.

[0091] refer to Fig. 7A and Figure 7B A contact level dielectric layer 80 may be formed over the alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42 and over the memory opening fill structure 58 and the support pillar structure 20. The contact level dielectric layer 80 includes a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the contact level dielectric layer 80 may include silicon oxide. The contact level dielectric layer 80 may have a thickness in the range of 50 nm to 500 nm, although smaller and larger thicknesses may also be used.

[0092] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and photolithographically patterned to form openings in the areas between the clusters of memory opening fill structures 58. Anisotropic etching may be used to transfer the pattern in the photoresist layer through the contact level dielectric layer 80, the alternating stacks (32, 42), and / or the stepped dielectric material portions 65 to form through-stack trenches 79 extending vertically from the top surface of the contact level dielectric layer 80 to at least the top surface of the source level sacrificial layer 104.

[0093] In one embodiment, a memory opening filling structure 58 may be formed in the memory array region 100, and a support pillar structure 20 and a stepped surface of alternating stacks (32, 42) may be formed in the staircase region 300. A connection via region 200 may be provided in which no sacrificial material layer 42 is present. The through-stack trench 79 may extend continuously through each of the memory array region 100, the staircase region 300, and the connection via region 200.

[0094] In one embodiment, the through-stack trench 79 may extend laterally along a first horizontal direction hd1, and may be spaced apart from each other laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The memory opening filling structure 58 may be arranged in a row extending along the first horizontal direction hd1. The drain selection level isolation structure 72 may extend laterally along the first horizontal direction hd1. Each through-stack trench 79 may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain selection level isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, and the uniform vertical cross-sectional profile does not change with translation along the first horizontal direction hd1. Multiple rows of memory opening filling structures 58 may be located between adjacent pairs of through-stack trenches 79 and drain selection level isolation structures 72, or between adjacent pairs of drain selection level isolation structures 72. In one embodiment, the through-stack trench 79 may include a source contact opening in which a source contact via structure may be subsequently formed. The photoresist layer may be removed, for example, by ashing.

[0095] refer to Figure 8 , a sacrificial etch stop material can be conformally deposited in the through-stack trenches 79 and over the contact level dielectric layer 80, and the sacrificial etch stop material can be anisotropically etched to form sacrificial etch stop spacers 75 at peripheral portions of each of the through-stack trenches 79. The sacrificial etch stop material is different from the material of the source level sacrificial layer 104. In an illustrative example, if the source level sacrificial layer 104 includes silicon nitride, the sacrificial etch stop material can include silicon oxide. The thickness of the sacrificial etch stop spacers 75 measured between the inner sidewall and the outer sidewall of the respective sacrificial etch stop spacers 75 can be in the range of 10 nm to 100 nm, but lesser or greater thicknesses can also be employed.

[0096] refer to Fig. 9, a selective isotropic etching process may be performed to selectively etch the material of the source level sacrificial layer 104 relative to the material of the first source level dielectric layer and the second source level dielectric layer (113, 115), to selectively etch the material of the source level sacrificial layer relative to the material of the first source level semiconductor layer and the second source level semiconductor layer (112, 116), and to selectively etch the material of the source level sacrificial layer relative to the material of the sacrificial etch stop spacer 75. For example, if the source level sacrificial layer 104 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to selectively etch the source level sacrificial layer 104 relative to the source level semiconductor layer (112, 116), the sacrificial etch stop spacer 75, and the contact level dielectric layer 80. If the source-level sacrificial layer 104 includes undoped amorphous silicon, a wet etching process using tetramethylammonium hydroxide may be performed to selectively etch the source-level sacrificial layer 104 relative to the source-level semiconductor layer (112, 116), the sacrificial etch stop spacers 75, and the contact-level dielectric layer 80. A substrate cavity 109 may be formed in the volume from which the source-level sacrificial layer 104 is removed. The first source-level dielectric layer and the second source-level dielectric layer (113, 115) may be removed together during the etching step.

[0097] Subsequently, a series of isotropic etching processes may be performed to remove the physically exposed portions of the memory film 50. For example, the isotropic etching process sequence may sequentially etch portions of the blocking dielectric layer 52, the memory material layer 54, and the dielectric material liner 56. After the series of isotropic etching processes, the tubular bottom portion of each memory film 50 may be physically exposed. The cylindrical outer surface segment of each vertical semiconductor channel 60 may be physically exposed to the substrate cavity 109.

[0098] refer to Fig.10 , a horizontal source layer (e.g., a discrete strap contact) may be formed in the substrate cavity 109 by depositing a doped semiconductor material having a doping of the second conductivity type in the substrate cavity 109. The horizontal source layer 114 may include a doped polysilicon layer containing an atomic concentration of 1.0×10 18 / cm 3 to 1.0×10 21 / cm 3 The second conductivity type dopant may be present in the range of about 100 to about 100 Å, although smaller or larger dopant concentrations may also be used.

[0099] In one embodiment, the horizontal source layer 114 may be formed by a non-selective doped semiconductor deposition process. In this case, a doped semiconductor material having a doping of the first conductivity type may be deposited on all physically exposed surfaces of the exemplary structure. The duration of the non-selective doped semiconductor deposition process may be selected so that the entire volume of the substrate cavity 109 is filled with the doped semiconductor material. An etch-back process may be performed to remove portions of the doped semiconductor material present in the through-stack trench 79 or above the contact level dielectric layer 80. The etch-back process may include an isotropic etching process or an anisotropic etching process. The remaining portion of the doped semiconductor material filling the substrate cavity 109 constitutes the horizontal source layer 114. Optionally, a selective semiconductor deposition process may be performed to selectively deposit semiconductor material on the physically exposed surfaces of the horizontal source layer 114 so that a portion of the horizontal source layer 114 is present at the bottom of each through-stack trench 79.

[0100] The combination of source-level semiconductor layer 112, horizontal source layer 114, and second source-level semiconductor layer 116 constitutes source-level material layers (112, 114, 116). Generally, the source-level material layers include at least one semiconductor material layer including a doped semiconductor material. In one embodiment, each of vertical semiconductor channels 60 includes a corresponding cylindrical surface in contact with a corresponding surface segment of horizontal source layer 114.

[0101] refer to Fig.11A , an annealing process may be performed to diffuse the second conductivity type dopant outward from the horizontal source layer 114 into the lower portion of the vertical semiconductor channel 60. The second conductivity type dopant transforms the bottom portion of the vertical semiconductor channel 60 into the source extension region 114E. The atomic concentration of the first conductivity type dopant of the source side doped channel portion 60S may be 1.0×10 16 / cm 3 to 1.0×10 18 / cm 3 range, but smaller and larger dopant concentrations may also be used.

[0102] The interface between the source extension region 114 and the vertical semiconductor channel may be formed in a lateral protrusion portion 601 of the vertical semiconductor channel 60 located at one of the source selection level sacrificial material layers 42S (e.g., the level of the bottommost source selection level sacrificial material layer 42S), such as Fig.11A Alternatively, Fig. 11B As shown in , an interface may be formed at a level of any source select level sacrificial material layer 42S overlying the bottommost source select level sacrificial material layer 42S.

[0103] refer to Fig.12, the sacrificial etch stop spacer 75 may be removed by selective etching. Thereafter, for example, an etchant that selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32 may be introduced into the through-stack trench 79. A backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The removal of the second material of the sacrificial material layer 42 may be selective relative to the material of the insulating layer 32, the material of the stepped dielectric material portion 65, the semiconductor material of the horizontal source layer 114 and the second source level semiconductor layer 116, and the material of the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric material portion 65 may be silicon oxide.

[0104] The etching process that selectively removes the second material relative to the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the through-stack trench 79 in a vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which the exemplary structure is immersed in a wet etching tank including phosphoric acid, which selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the art. When the backside recess 43 exists in the volume previously occupied by the sacrificial material layer 42, the support column structure 20, the stepped dielectric material portion 65, and the memory opening filling structure 58 provide structural support. In general, the backside recess 43 can be formed by selectively removing the sacrificial material layer 42 relative to the insulating layer 32 and the silicon oxide layer 58.

[0105] refer to Fig.13 , an optional backside blocking dielectric layer (not shown) may be optionally formed in the backside recess 43 and the trench 79 by conformal deposition on the physically exposed surfaces of the memory opening filling structure 58, the support pillar structure 20, the insulating layer 32, the contact level dielectric layer 80, the horizontal source layer 114, and the second source level semiconductor layer 116. The backside blocking dielectric layer, if present, includes a dielectric material that serves as a control gate dielectric for a control gate to be subsequently formed in the backside recess 43. In the case where a blocking dielectric layer 52 is present within each memory opening, the backside blocking dielectric layer is optional. In the case where the blocking dielectric layer 52 is omitted, the backside blocking dielectric layer is present.

[0106] At least one conductive material may be deposited in the plurality of backside recesses, on the sidewalls of the through-stack trenches 79, and on the contact-level dielectric layer 80. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0107] In one embodiment, at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive filling material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material used to fill the backside recess may be a combination of a titanium nitride layer and a tungsten filling material.

[0108] A conductive layer 46 may be formed in the backside recess 43 by depositing at least one conductive material. A plurality of conductive layers 46 may be formed in a plurality of backside recesses 43, and a continuous metal material layer (not shown) may be formed on the sidewalls of each through-stack trench 79 and on the contact-level dielectric layer 80. Each of the conductive layers may include a corresponding conductive metal nitride liner and a corresponding conductive filling material. Thus, the sacrificial material layer 42 may be replaced with a conductive layer 46. Specifically, each sacrificial material layer 42 may be replaced with an optional portion of the backside blocking dielectric layer and a conductive layer 46. A backside cavity exists in a portion of each through-stack trench 79 that is not filled with a continuous metal material layer.

[0109] The remaining conductive material may be removed from the inside of the through-stack trench 79. Specifically, the deposited metal material of the continuous metal material layer may be etched back from the sidewalls of each through-stack trench 79 and from above the contact-level dielectric layer 80, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive layer 46. The sidewalls of the conductive material layer 46 may be physically exposed to the corresponding through-stack trench 79.

[0110] The conductive layer 46 may include, from bottom to top, at least one source selection level conductive layer (i.e., source side selection gate electrode) 46S, a word line level conductive layer (i.e., word line) 46W, and at least one drain selection level conductive layer (i.e., drain side selection gate electrode) 46D. Each source selection level conductive layer 46S replaces a corresponding source selection level sacrificial material layer 42S. Each word line level conductive layer 46W replaces a corresponding word line level sacrificial material layer 42W. Each drain selection level sacrificial material layer 46D replaces a corresponding drain selection level sacrificial material layer 42D.

[0111] Each conductive layer 46 may be a conductive sheet including openings therein. A subset of the openings through each conductive layer 46 may be filled with a memory opening fill structure 58. A second subset of the openings through each conductive layer 46 may be filled with a support pillar structure 20. A subset of conductive layers 46 may include word lines for memory elements.

[0112] The lateral extent of the conductive layer 46 decreases with the vertical distance from the source level material layer (112, 114, 116). The dielectric material portion 65 contacts the stepped surface of the alternating stack (32, 46) and has a variable lateral extent that increases stepwise with the vertical distance from a horizontal plane including the interface between the alternating stack (32, 46) and the source level material layer (112, 114, 116).

[0113] Fig.14A Shown in Fig.13 A region including a memory opening filling structure 58 or supporting opening filling structure 20 of an exemplary structure after the processing steps of FIG. Fig. 14B Shown in Fig.13 Alternative embodiments of exemplary structures after the processing steps include a region of a memory opening filling structure or a support opening filling structure 20 .

[0114] refer to Fig.15 , a dielectric filling material (such as silicon oxide) may be deposited in the through-stack trench 79. A recess etching process may be performed to remove the portion of the dielectric filling material deposited above the contact level dielectric layer 80. The remaining portion of the dielectric filling material filling the portion of the through-stack trench 79 constitutes a trench dielectric filling structure 76. In one embodiment, the dielectric trench filling structure 76 may contact the sidewalls of the dielectric material portion 65 and the sidewalls of at least one of the conductive layers 46.

[0115] refer to Fig.16A and Fig. 16B, various via cavities may be formed through the contact level dielectric layer 80 and the stepped dielectric material portion 65. The via cavities may include a drain contact via cavity extending downward to the corresponding drain region 63 in the memory opening filling structure 58, a layer contact via cavity extending downward to the corresponding conductive layer 46 at or below the stepped surface of the alternating stack (32, 46) below the stepped dielectric material portion 65, and a connection via cavity extending downward to the source level material layer (112, 114, 116).

[0116] At least one conductive material may be deposited in each of the via cavities, and excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the contact-level dielectric layer 80. Each remaining portion of the at least one conductive material constitutes a via structure (88, 86, 84). The via structure (88, 86, 84) includes a drain contact via structure 88 formed in the drain contact via cavity and contacting a top surface of a corresponding one of the drain regions 63. Thus, the drain contact via structure 88 extends vertically through the contact-level dielectric layer 80 and contacts an end surface of a corresponding one of the memory opening filling structures 58. The via structure (88, 86, 84) also includes a layer contact via structure 86 formed in the layer contact via cavity and contacting a top surface of a corresponding one of the conductive layers 46. The via structures (88, 86, 84) also include at least one connecting via structure 84 formed in the connecting via cavity and contacting the source level material layer (112, 114, 116).

[0117] refer to Fig.17A , shows a first alternative configuration of memory opening filling structure 58 immediately after forming memory opening filling structure 58 according to an embodiment of the present disclosure. Fig.17A The processing steps correspond to Fig.5I In the first alternative configuration, the word line level sacrificial material layer 42W and the source selection level sacrificial material layer 42S include a first sacrificial material, and the drain selection level sacrificial material layer 42D includes a second sacrificial material. Therefore, only at least one drain selection level sacrificial material layer 42D is at a level corresponding to Figure 5B The annular recessed cavity 49R is formed at the processing step of ...

[0118] refer to Fig. 17B, shows a first alternative configuration of memory opening filling structure 58 after replacing sacrificial material layer 42 with conductive layer 46 in accordance with an embodiment of the present disclosure. Fig. 17B The processing steps correspond to Fig.14A The lateral protrusions 501 in the memory film 50 are formed only at the level of at least one drain selection level conductive layer 46D. In addition, the lateral protrusions 601 of the vertical semiconductor channel 60 are formed only at the level of at least one drain selection level conductive layer 46D.

[0119] refer to Fig.18A , shows a second alternative configuration of memory opening filling structure 58 immediately after forming memory opening filling structure 58 according to an embodiment of the present disclosure. Fig.18A The processing steps correspond to Fig.5I In a second alternative configuration, the word line level sacrificial material layer 42W and the drain select level sacrificial material layer 42D include a first sacrificial material, and the source select level sacrificial material layer 42S includes a second sacrificial material. Thus, only at least one source select level sacrificial material layer 42S is at a level corresponding to Figure 5B The annular recessed cavity 49R is formed at the processing step of ...

[0120] refer to Fig.18B , shows a second alternative configuration of memory opening filling structure 58 after replacing sacrificial material layer 42 with conductive layer 46 according to an embodiment of the present disclosure. Fig.18B The processing steps correspond to Fig.14A The lateral protrusions 501 in the memory film 50 are formed only at the level of at least one source selection level conductive layer 46S. In addition, the lateral protrusions 601 of the vertical semiconductor channel 60 are formed only at the level of at least one source selection level conductive layer 46S.

[0121] With reference to all the drawings and in accordance with various embodiments of the present disclosure, there is provided a semiconductor structure including: an alternating stack (32, 46) of insulating layers 32 and conductive layers 46, wherein the conductive layers 46 include word line conductive layers 46W and first selection level conductive layers (46S, 46D); a memory opening 49 extending vertically through the alternating stack (32, 46); and a memory opening filling structure 58 located in the memory opening 49 and including a memory film 50 and a vertical semiconductor channel 60. The vertical cross-sectional profile of the outer sidewall of the vertical semiconductor channel 60 is straight throughout the word line conductive layer 46W and includes a lateral protrusion 601 located at the level of the first selection level conductive layer (46S, 46D).

[0122] In one embodiment, the vertical cross-sectional profile of the outer side wall of the memory film 50 is straight throughout the word line conductive layer 46W and includes a first lateral protrusion 501 located at the level of the first selection level conductive layer (46S, 46D), and the lateral protrusion 601 in the vertical semiconductor channel 60 includes a second lateral protrusion.

[0123] In one embodiment, the vertical cross-sectional profile of the inner sidewall of the vertical semiconductor channel 60 is straight throughout the word line conductive layer 46W and throughout each of the first selection level conductive layers ( 46S, 46D).

[0124] In one embodiment, the vertical extent of the first lateral protrusion is the same as the vertical spacing between the overlying insulating layer 32 in contact with the annular top surface of the first lateral protrusion and the underlying insulating layer 32 in contact with the annular bottom surface of the first lateral protrusion.

[0125] In one embodiment, the memory film 50 has a uniform thickness in the vertical extension within the first lateral protrusion 501, in the horizontal extension within the first lateral protrusion 501, and in the portion extending linearly throughout the word line conductive layer 46W; and the vertical extent of the second lateral protrusion 601 is the same as the vertical extent of the first lateral protrusion 501 minus twice the uniform thickness of the memory film 50. In one embodiment, the memory film 50 is continuous throughout the entire alternating stack (32, 46) and has no discrete, vertically isolated regions.

[0126] In one embodiment, the vertical semiconductor channel 60 includes a dopant of a first conductivity type. In one embodiment, the memory opening filling structure 58 also includes a drain region 63, which is located at the upper end of the vertical semiconductor channel 60 and includes a dopant of a second conductivity type opposite to the first conductivity type. In one embodiment, the drain extension region 63E is adjacent to the drain region 63 and forms a first pn junction at a first interface with the vertical semiconductor channel 60.

[0127] In one embodiment, horizontal source layer 114 including dopants of the second conductivity type contacts a lower cylindrical surface segment of vertical semiconductor channel 60. Vertical source extension region 114E adjoins horizontal source layer 114 and forms a second pn junction at a second interface with vertical semiconductor channel 60.

[0128] In one embodiment, the first selection level conductive layer includes the drain side select gate electrode 46D, and the lateral protrusion 601 is located at the drain side select gate electrode. In another embodiment, the first selection level conductive layer includes the source side select gate electrode 46S, and the lateral protrusion 601 is located at the source side select gate electrode. In one embodiment, the vertical semiconductor channel 60 also includes another protrusion 601 located at the level of the drain side select gate electrode 46D.

[0129] In one embodiment, the vertical semiconductor channel 60 includes a uniform thickness portion having a uniform lateral thickness between the straight inner sidewall segment and the straight outer sidewall segment of the entire word line conductive layer 46W, and a lateral protrusion portion 601 having a lateral thickness between the outer sidewall and the inner sidewall that is greater than the uniform lateral thickness.

[0130] Various embodiments of the present disclosure may provide a locally thickened vertical semiconductor channel 60 including at least one lateral protrusion 601 located at one or more source selection levels and / or at one or more drain selection levels. The protrusion and the drain and / or source extension regions (63E, 114E) are used to increase the gate induced drain leakage (GIDL) current and reduce the erase voltage variation. The increase in GIDL current may speed up the speed at which charges (e.g., holes) are supplied to the vertical semiconductor channel 60 during an erase operation of a memory cell in the memory material layer 54 that stores electrons at the level of the word line 42W. Therefore, the locally thickened vertical semiconductor channel 60 of the embodiments of the present disclosure may be advantageously used to speed up the operation speed of a three-dimensional memory device.

[0131] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments employing specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, comprising: an alternating stack of insulating layers and conductive layers, wherein the conductive layers include a word line conductive layer and a first selection level conductive layer; a storage opening extending vertically through the alternating stacks; as well as a memory opening filling structure located in the memory opening and comprising a memory film and a vertical semiconductor channel, A vertical cross-sectional profile of an outer sidewall of the vertical semiconductor channel is straight throughout the word line conductive layer and includes a lateral protrusion located at the level of the first selection-level conductive layer.

2. The semiconductor structure according to claim 1, wherein: A vertical cross-sectional profile of an outer sidewall of the memory film is straight throughout the word line conductive layer and includes a first lateral protrusion at the level of the first selection level conductive layer; and The lateral protrusion in the vertical semiconductor channel includes a second lateral protrusion. 3 . The semiconductor structure of claim 2 , wherein the vertical cross-sectional profile of the inner sidewall of the vertical semiconductor channel is straight throughout the word line conductive layer and throughout the select level conductive layer.

4. The semiconductor structure according to claim 2, wherein the vertical extent of the first lateral protrusion is the same as the vertical spacing between an overlying insulating layer of the insulating layer in contact with the annular top surface of the first lateral protrusion and a lower insulating layer of the insulating layer in contact with the annular bottom surface of the first lateral protrusion.

5. The semiconductor structure of claim 4, wherein: The memory film has a uniform thickness in a vertically extending section within the first lateral protrusion, in a horizontally extending section within the first lateral protrusion, and in a portion extending linearly throughout the word line conductive layer; and The vertical extent of the second lateral protrusion is twice the vertical extent of the first lateral protrusion minus the uniform thickness of the memory film.

6. The semiconductor structure of claim 2 wherein said memory film is continuous throughout said overall alternating stack.

7. The semiconductor structure of claim 1 wherein the vertical semiconductor channel comprises dopants of a first conductivity type. 8 . The semiconductor structure of claim 7 , wherein the memory opening filling structure further comprises a drain region located at an upper end of the vertical semiconductor channel and comprising a dopant of a second conductivity type opposite to the first conductivity type. 9 . The semiconductor structure of claim 8 , further comprising a drain extension region adjoining the drain region and forming a first pn junction at a first interface with the vertical semiconductor channel. 10 . The semiconductor structure of claim 9 , further comprising a horizontal source layer including dopants of the second conductivity type, the horizontal source layer contacting a lower cylindrical surface segment of the vertical semiconductor channel.

11. The semiconductor structure of claim 10, further comprising a vertical source extension region adjoining the horizontal source layer and forming a second pn junction at a second interface with the vertical semiconductor channel. 12 . The semiconductor structure of claim 1 , wherein the first selection level conductive layer comprises a drain side selection gate electrode, and the lateral protrusion is located at the drain side selection gate electrode. 13 . The semiconductor structure of claim 1 , wherein the first selection-level conductive layer comprises a source-side selection gate electrode, and the lateral protrusion is located at the source-side selection gate electrode. 14 . The semiconductor structure of claim 13 , wherein the vertical semiconductor channel further comprises a further protrusion at the level of the drain-side select gate electrode.

15. The semiconductor structure of claim 1, wherein: The vertical semiconductor channel includes a uniform thickness portion having a uniform lateral thickness between the straight inner sidewall segment and the straight outer sidewall segment throughout the word line conductive layer; and The laterally protruding portion has a lateral thickness between the outer sidewall and the inner sidewall, the lateral thickness being greater than the uniform lateral thickness.

16. A method of forming a semiconductor structure, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers over the substrate, wherein the sacrificial material layers include a word line level sacrificial material layer including a first sacrificial material and at least one select level sacrificial material layer including a second sacrificial material; forming a memory opening through the alternating stack; expanding the memory opening at each level of the at least one selective level of sacrificial material layer by performing an isotropic etch process that etches the second sacrificial material at a higher etch rate than the first sacrificial material; forming a memory opening filling structure in the memory opening, wherein the memory opening filling structure includes a memory film and a vertical semiconductor channel; as well as The sacrificial material layer is replaced with a conductive layer.

17. The method of claim 16, wherein: The isotropic etching process selectively etches the second sacrificial material relative to the material of the insulating layer; and Each portion of the memory opening expanded by the isotropic etching process includes an annular recessed cavity.

18. The method of claim 17, wherein: depositing the memory film in each annular recessed cavity and on the sidewalls of the insulating layer around the memory opening; The thickness of the memory film is less than half the height of each annular recessed cavity; and The vertical semiconductor channel includes at least one lateral protrusion portion formed within a corresponding annular recessed cavity.

19. The method of claim 16, wherein: The at least one select level sacrificial material layer comprises a drain select level sacrificial material layer; forming a drain region in contact with an upper region of the vertical semiconductor channel; and The upper region of the vertical semiconductor channel is converted into a drain extension region by out-diffusing dopants from the drain region into the upper region of the vertical semiconductor channel.

20. The method of claim 16, wherein: The at least one select level sacrificial material layer comprises a source select level sacrificial material layer; forming a horizontal source layer in contact with a lower region of the vertical semiconductor channel; and The lower region of the vertical semiconductor channel is converted into a source extension region by out-diffusing dopants from the horizontal source layer into the lower region of the vertical semiconductor channel.

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