Quality detection method and system for intelligent card chip

Abstract

The invention provides an intelligent card chip quality detection method and system, and the method comprises the steps: collecting the electric signal data of an intelligent card chip, and obtaining the collected data; performing feature extraction processing on the acquired data to obtain feature data including a signal strength feature, a signal frequency feature and a signal waveform feature; classifying the feature data into normal feature data and abnormal feature data; analyzing an association relationship between the abnormal feature data to obtain an association analysis result; and carrying out fault positioning processing according to the correlation analysis result, determining the position of the quality problem of the intelligent card chip, and obtaining a quality detection result. According to the method, the association analysis result is obtained by analyzing the association relationship among the abnormal feature data, the fault positioning processing is carried out, the position of the quality problem of the intelligent card chip is determined, and the defect that the root of the chip quality problem cannot be accurately judged at present is overcome.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a quality detection method and system for a smart card chip. Background Art

[0002] During the manufacturing process of smart card chips, various quality problems are prone to occur due to factors such as process complexity, differences in raw materials, and equipment accuracy, such as short circuits and open circuits within the chip, abnormal signal transmission, etc. The above quality problems will cause the smart card to not work properly, such as data reading errors, communication interruptions, etc., causing serious losses and inconveniences to users and related businesses.

[0003] Traditional smart card chip quality testing methods often have limitations. Some methods rely on simple functional tests, that is, only testing whether the chip is normal when performing a specific function. This method cannot fully and deeply detect potential signal quality problems inside the chip. In addition, some testing methods focus on checking the appearance of the chip or a single electrical parameter, such as only checking the connectivity of the chip pins or whether the power supply voltage is within a fixed range, while ignoring the comprehensive performance of complex electrical signals in the actual working process of the chip.

[0004] Currently, there is a lack of quality detection methods based on multi-dimensional signal characteristics for the detection and analysis of smart card chip electrical signal data. Especially in the face of complex chip internal circuits and high-frequency data transmission scenarios, it is impossible to effectively extract and analyze the rich information contained in the electrical signals, and it is impossible to accurately determine the root cause of chip quality problems, thus failing to meet the needs of high-precision smart card chip quality detection. Summary of the invention

[0005] The main purpose of the present invention is to provide a smart card chip quality detection method and system, aiming to overcome the current defect that the root cause of chip quality problems cannot be accurately determined.

[0006] To achieve the above object, the present invention provides a method for quality inspection of a smart card chip, comprising the following steps:

[0007] Collecting electrical signal data of the smart card chip to obtain collected data;

[0008] Performing feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features;

[0009] Classifying the feature data into normal feature data and abnormal feature data;

[0010] Analyze the correlation between each of the abnormal feature data to obtain a correlation analysis result;

[0011] Perform fault location processing according to the correlation analysis result to determine the location of the quality problem of the smart card chip and obtain the quality detection result.

[0012] Furthermore, the collected data includes power supply signals, data transmission signals, and electromagnetic radiation signals.

[0013] Furthermore, the correlation relationship between each of the abnormal feature data is analyzed to obtain a correlation analysis result, including:

[0014] Constructing a correlation matrix based on each of the abnormal feature data; wherein the rows and columns of the correlation matrix correspond to different abnormal feature data respectively, and the value of each matrix element is determined according to the correlation between the abnormal feature data;

[0015] Performing principal component analysis on the correlation matrix to extract principal component vectors of the correlation matrix;

[0016] Determine the correlation direction and correlation strength according to the eigenvalue size and direction of the principal component vector, and use it as the initial correlation analysis result;

[0017] The Bayesian network model is used to model each of the abnormal feature data as a node, and the conditional probability relationship between the nodes is determined. The probability of the simultaneous occurrence of different abnormal feature data is analyzed through Bayesian reasoning. The initial association analysis result is corrected based on the probability situation to obtain the final association analysis result.

[0018] Further, a fault location process is performed according to the correlation analysis result to determine the location of the quality problem of the smart card chip and obtain a quality detection result, including:

[0019] The abnormal characteristic data in the association analysis result is used as a node of the tree to construct a fault tree; the causal relationship between the nodes is analyzed to determine the combination of fault causes; the combination of fault causes includes the combination of signals that cause the fault;

[0020] Acquire the design layout of the smart card chip, and determine the target circuit module generating the fault signal in the smart card chip based on the combination of fault causes;

[0021] Through the signal injection method, verify whether the target circuit module is an abnormal module;

[0022] If it is an abnormal module, the electrical parameters of the target circuit module are detected through micro-resistance test or capacitance test, and compared with the standard component parameters to determine the location of the quality problem and obtain the quality test results.

[0023] Furthermore, the collecting of electrical signal data of the smart card chip includes:

[0024] In the initialization phase when the smart card chip starts working, all monitoring points are coarsely sampled at the initial sampling frequency to obtain coarse sampling data; the monitoring points include the power pins, clock signal pins, data transmission pins and connection points between functional modules of the chip;

[0025] Analyzing the coarse sampling data by a machine learning algorithm to identify signal change areas and signal stable areas;

[0026] For the signal change area, control the sampling device to sample at an exponentially increasing sampling frequency until a preset maximum sampling frequency is reached to capture the rapid jump and short pulse of the signal;

[0027] For the signal stable region, the sampling device is controlled to reduce the sampling frequency to a minimum limit satisfying the Nyquist theorem to perform sampling.

[0028] Further, after obtaining the quality test result, the method further comprises:

[0029] Encoding the collected data to obtain coded data; wherein all the coded data are digital characters;

[0030] Add all characters in the encoded data to a preset graph structure to obtain a character graph; wherein each character is added to a node, and the difference between characters on adjacent nodes is used as the value of each edge;

[0031] Add all characters in the coded data into a preset matrix to generate a character matrix, and perform XOR calculation on the character matrix and a preset digital matrix to obtain an XOR value matrix;

[0032] A permission code is generated based on the XOR value matrix and the character map, and is used for performing permission management on the collected data and the quality detection results.

[0033] Further, generating a permission code based on the XOR value matrix and the character map includes:

[0034] The XOR value matrix and the character image are superimposed according to a preset rule; the XOR value matrix includes two types of numbers, namely, a first number and a second number;

[0035] Clearing characters on each node in the character graph, and calculating the shortest distance between each edge of the character graph and the first number in the XOR value matrix;

[0036] Each edge whose nearest distance is less than a preset value is taken as a target edge, and the values ​​on each target edge are obtained and combined to obtain a combined character as the permission code.

[0037] The present invention also provides a smart card chip quality detection system, comprising:

[0038] A collection unit, used for collecting electrical signal data of the smart card chip to obtain collected data;

[0039] An extraction unit, used to perform feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features;

[0040] A classification unit, used for classifying the feature data into normal feature data and abnormal feature data;

[0041] An analysis unit, used to analyze the correlation between each of the abnormal feature data to obtain a correlation analysis result;

[0042] The positioning unit is used to perform fault positioning processing according to the correlation analysis result, determine the location of the quality problem of the smart card chip, and obtain the quality detection result.

[0043] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0044] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods are implemented.

[0045] The quality detection method and system of the smart card chip provided by the present invention include: collecting the electrical signal data of the smart card chip to obtain the collected data; performing feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features; classifying the feature data into normal feature data and abnormal feature data; analyzing the correlation between each of the abnormal feature data to obtain a correlation analysis result; performing fault location processing according to the correlation analysis result to determine the location of the quality problem of the smart card chip to obtain a quality detection result. In the present invention, by analyzing the correlation between each of the abnormal feature data to obtain a correlation analysis result, and performing fault location processing to determine the location of the quality problem of the smart card chip, the defect of being unable to accurately determine the root cause of the chip quality problem is overcome. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 1 is a schematic diagram of the steps of a quality detection method for a smart card chip according to an embodiment of the present invention;

[0047] Figure 2 is a block diagram of a quality inspection system for a smart card chip according to an embodiment of the present invention;

[0048] Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0049] The implementation, functional features and advantages of the present invention will be further described in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0051] Reference Figure 1 In one embodiment of the present invention, a quality detection method for a smart card chip is provided, comprising the following steps:

[0052] Step S1, collecting electrical signal data of the smart card chip to obtain collected data;

[0053] Step S2, performing feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features;

[0054] Step S3, classifying the feature data into normal feature data and abnormal feature data;

[0055] Step S4, analyzing the correlation between each of the abnormal feature data to obtain a correlation analysis result;

[0056] Step S5, performing fault location processing according to the correlation analysis result, determining the location of the quality problem of the smart card chip, and obtaining a quality detection result.

[0057] In this embodiment, as described in step S1 above, first, professional electrical signal acquisition equipment is used. These devices should have sufficiently high accuracy and sensitivity to accurately capture the electrical signal changes at each pin and internal key nodes of the chip in different working scenarios (such as data reading and writing, communication interaction, etc.). The collected electrical signal data can cover multiple aspects, including but not limited to the chip's power supply signal (such as power supply voltage, current, etc.), clock signal (frequency, phase, etc.), data transmission signal (level change, transmission rate, etc.), etc. The above signals are crucial to the normal operation of the chip, and any abnormality implies that the chip has quality problems.

[0058] In order to ensure the integrity and accuracy of the collected data, the collection process usually needs to be carried out in a stable working environment to avoid external electromagnetic interference and other factors affecting the collected signals. At the same time, according to the specific working frequency and signal characteristics of the chip, the sampling frequency, sampling time and other parameters of the collection equipment should be reasonably set to ensure that the required electrical signal data can be fully obtained.

[0059] As described in the above step S2, in order to extract representative and distinguishing key features from the original collected data, so as to more efficiently evaluate and analyze the working state of the chip. By performing amplitude analysis on the collected electrical signal data, the intensity of different signals at a specific time or time period is determined. For example, for a data transmission signal, its signal strength should be maintained within a certain reasonable range. If the intensity is too low, the receiving end will not be able to accurately identify the signal. If it is too high, it will cause signal distortion or interfere with other circuits. Through methods such as statistical analysis, characteristic parameters such as the mean, variance, maximum value, and minimum value of the signal strength can be obtained, and these parameters can intuitively reflect the stability and change of the signal strength.

[0060] For electrical signals containing frequency information (such as clock signals, certain high-frequency data transmission signals, etc.), frequency components of the signals and their related characteristics are extracted using spectrum analysis and other technical means. For example, the fundamental frequency, harmonic frequency, and frequency drift of the signal are calculated. When the chip is working normally, the frequencies of its various signals are usually relatively stable and meet the design requirements. By analyzing the frequency characteristics, it can be determined whether the clock circuit and frequency synthesis circuit inside the chip are working normally.

[0061] Observe and analyze the waveform shape of the electrical signal, including the rising edge, falling edge, pulse width, duty cycle and other parameters of the waveform. Different types of chip functions correspond to specific waveform characteristics. For example, during data transmission, the waveform of the data signal should comply with the corresponding communication protocol standard. By extracting the waveform features, we can further understand the change law of the signal in the time domain and discover abnormal conditions such as waveform distortion and glitches.

[0062] As described in step S3 above, by establishing a classification standard, feature data that matches the normal working state of the chip and abnormal feature data that suggests the chip has quality problems can be quickly distinguished, so as to focus on the target for subsequent in-depth analysis.

[0063] First, it is necessary to build a reference model based on the distribution of characteristic data under normal working conditions of smart card chips. This model can be obtained by collecting, analyzing and counting characteristic data of a large number of smart card chips that have undergone strict quality inspections and confirmed to be working normally. For example, for signal strength characteristics, determine its mean range, variance range, etc. under normal conditions; for signal frequency characteristics, clarify its normal frequency fluctuation range, etc.; for signal waveform characteristics, specify the waveform parameter range that conforms to the standard communication protocol. Then, compare the current characteristic data to be classified with the reference model. If the parameters of the characteristic data in each characteristic dimension (signal strength, frequency, waveform) fall within the normal range specified by the reference model, it is classified as normal characteristic data; conversely, if the parameters in any characteristic dimension exceed the normal range, it is judged as abnormal characteristic data.

[0064] As described in step S4 above, the correlation relationship between each of the abnormal feature data is analyzed to obtain the correlation analysis result in order to deeply explore the internal connection between the abnormal feature data so as to more accurately understand the complexity and root cause of chip quality problems and provide strong support for the final fault location.

[0065] In one embodiment, a statistical method (such as calculating the Pearson correlation coefficient, etc.) is used to analyze the linear correlation between different types of abnormal feature data. For example, it is analyzed whether there is a certain correlation between the signal strength abnormal data and the signal frequency abnormal data, that is, when the signal strength deviates, whether it is accompanied by a corresponding change in the signal frequency. Through this correlation analysis, some systemic problems hidden behind a single abnormal feature can be found. Based on the circuit principle and functional logic of the smart card chip, an attempt is made to determine the causal relationship between different abnormal feature data. For example, in a certain functional module of the chip, if the power signal strength is abnormal, it will cause the waveform of the data transmission signal in the module to be distorted, then it can be determined that the power signal strength abnormality is the cause of the waveform distortion. Through this causal relationship analysis, the order and causal chain of the generation of abnormal feature data can be sorted out, and the evolution path of chip quality problems can be further clarified. Clustering algorithms (such as K-Means clustering algorithms, etc.) are used to cluster abnormal feature data with similar characteristics into one category. In this way, the distribution of abnormal feature data of different categories can be observed from a macro perspective, and it can be understood which abnormal feature data tend to appear at the same time, thereby providing more targeted clues for subsequent fault location. The clustering results obtained through cluster analysis and the relationship between categories are also important components of the association analysis results.

[0066] As described in step S5 above, the abnormal feature data and their relationships in the association analysis results are mapped one by one to the actual physical position of the chip and the corresponding circuit module according to the design circuit diagram and functional module division of the smart card chip. For example, if the association analysis results show that the signal strength abnormality is related to a specific functional module, then the focus can be on the specific location of the module in the chip.

[0067] For the mapped circuit modules or specific locations with quality problems, more sophisticated detection methods (such as micro-resistance test, capacitance test, signal injection test, etc.) are used for local detection. By injecting test signals into these parts and observing their response signals, and comparing them with the response signals under normal conditions, it is further verified whether there are indeed quality problems and the specific manifestations of the problems are determined.

[0068] Based on the results of local inspections, the severity of the chip quality problem, the impact on the overall function of the chip, and other factors are comprehensively evaluated to ultimately provide a complete quality inspection result. For example, it is determined whether the problem only slightly affects a certain local function or causes the entire chip to not work properly, thereby deciding whether to take repair measures or directly scrap it.

[0069] In one embodiment, the collected data includes a power signal, a data transmission signal, and an electromagnetic radiation signal. The power signal is an electrical signal that provides electrical energy to the smart card chip to enable it to work normally. Smart card chips usually require a specific voltage and current supply to operate stably, such as the common stable DC voltages of 3.3V or 1.8V. The stability of the power signal directly affects the working state of each circuit module inside the chip. If the power supply voltage is too high, the electronic components inside the chip will be damaged, while if it is too low, the chip will not start normally or function abnormally. For example, some logic circuits cannot flip the state correctly due to insufficient voltage, which in turn affects data processing, storage and other operations.

[0070] The data transmission signal is an electrical signal involved in the data interaction between the smart card chip and external devices (such as card readers). It carries various information, such as account information, transaction instructions, etc. Its accuracy and integrity are crucial for the normal use of smart cards. If there is an error in the data transmission signal, it will lead to serious consequences such as data reading errors and transaction failures.

[0071] Electromagnetic radiation signals are electrical signals corresponding to electromagnetic waves emitted by smart card chips to the surrounding space during operation. Although the electromagnetic radiation power of smart card chips is relatively small, they also need to meet certain electromagnetic compatibility (EMC) requirements. On the one hand, excessive electromagnetic radiation will interfere with other electronic devices around them and affect their normal operation; on the other hand, electromagnetic radiation can also reflect the working status of the internal circuit of the chip from the side. For example, some abnormal electromagnetic radiation indicates that there are problems such as signal leakage and imperfect electromagnetic shielding inside the chip, which in turn affects the quality and reliability of the chip.

[0072] The acquisition of electromagnetic radiation signals mainly involves data such as the intensity and frequency distribution of electromagnetic radiation. The electromagnetic radiation detection equipment can measure the electromagnetic radiation intensity of the smart card chip in different frequency bands, compare it with the relevant electromagnetic compatibility standards, and determine whether the electromagnetic radiation exceeds the standard. At the same time, analyzing the frequency distribution of electromagnetic radiation can understand which circuit modules inside the chip are generating electromagnetic radiation of a specific frequency, which helps to further troubleshoot problems inside the chip.

[0073] In one embodiment, the analysis of the correlation relationship between each of the abnormal feature data to obtain the correlation analysis result includes:

[0074] Constructing a correlation matrix based on each of the abnormal feature data; wherein the rows and columns of the correlation matrix correspond to different abnormal feature data respectively, and the value of each matrix element is determined according to the correlation between the abnormal feature data;

[0075] Performing principal component analysis on the correlation matrix to extract principal component vectors of the correlation matrix;

[0076] Determine the correlation direction and correlation strength according to the eigenvalue size and direction of the principal component vector, and use it as the initial correlation analysis result;

[0077] The Bayesian network model is used to model each of the abnormal feature data as a node, and the conditional probability relationship between the nodes is determined. The probability of the simultaneous occurrence of different abnormal feature data is analyzed through Bayesian reasoning. The initial association analysis result is corrected based on the probability situation to obtain the final association analysis result.

[0078] In this embodiment, first, determine all abnormal feature data sets that need to analyze the association relationship. The above-mentioned abnormal feature data covers data that are abnormal in aspects such as signal strength characteristics, signal frequency characteristics, and signal waveform characteristics. Then, construct a matrix, and the rows and columns of the matrix correspond to different abnormal feature data. For example, if there are n different abnormal feature data, then construct an n×n square matrix. For each element in the matrix, its value is determined according to the correlation between the abnormal feature data. The above-mentioned correlation measurement can be used in a variety of ways, such as by calculating the Pearson correlation coefficient and other statistical methods to determine the linear correlation between two abnormal feature data. If the correlation between the two abnormal feature data is strong (for example, the absolute value of the Pearson correlation coefficient is close to 1), the corresponding matrix element value is set to a higher value (such as 1 or a value close to 1, and the specific value can be based on the set rules); if the correlation is weak (the absolute value of the Pearson correlation coefficient is close to 0), the corresponding matrix element value is set to a lower value (such as 0 or a value close to 0). In this way, by performing correlation analysis and assigning values ​​to each pair of abnormal feature data, the construction of the association matrix is ​​completed. This correlation matrix can generally reflect the degree of correlation between different abnormal feature data.

[0079] The main purpose of principal component analysis (PCA) is to reduce the dimensionality of high-dimensional data (here, the data represented by the correlation matrix) while retaining the main information of the data, so as to more clearly see the main structure and characteristics of the data. By extracting the principal component vector, the main direction that best represents the data change in the correlation matrix can be found, thereby simplifying the subsequent analysis of the correlation relationship.

[0080] Perform principal component analysis on the constructed association matrix. The basic principle of PCA is to find the eigenvalues ​​and corresponding eigenvectors of the covariance matrix by performing eigenvalue decomposition on the covariance matrix of the data. In the context of the association matrix, first calculate the covariance matrix of the association matrix (this step involves a series of matrix operations, which are calculated according to the definition of covariance and matrix operation rules). Then perform eigenvalue decomposition on the covariance matrix to obtain a series of eigenvalues ​​and corresponding eigenvectors. The eigenvalue represents the contribution of each principal component (i.e. the direction corresponding to the eigenvector) to the data variance. The larger the eigenvalue, the stronger the ability of the principal component to explain the data change. In the order of eigenvalues ​​from large to small, select the eigenvectors corresponding to the first few eigenvalues ​​(the specific number of selections can be determined according to actual conditions and experience, and generally the number of principal components that can explain most of the data variance) eigenvalues. These eigenvectors are the principal component vectors we want to extract. The principal component vectors represent the main direction of data changes in the association matrix. Through them, we can more intuitively understand the main association patterns between the abnormal feature data reflected in the association matrix.

[0081] Based on the eigenvalues ​​and directional information of the principal component vector obtained by principal component analysis, the specific correlation direction (i.e. which abnormal characteristic data has an impact on other abnormal characteristic data and the direction of the impact) and correlation strength (i.e. the degree of impact) between the abnormal feature data are further clarified, thereby preliminarily forming the analysis results on the correlation relationship and laying the foundation for subsequent more accurate analysis.

[0082] For the extracted principal component vector, the size of its eigenvalue reflects the importance of the association pattern represented by the principal component vector in the entire association matrix data. The larger the eigenvalue, the stronger the ability of the association pattern to explain the overall data changes, that is, the greater the association strength. The direction of the principal component vector can indicate the direction of the association. For example, if a principal component vector has a positive component in a certain dimension (corresponding to a certain abnormal feature data) and a negative component in another dimension, this means that there is an inverse association relationship between the two abnormal feature data, that is, when one abnormal feature data increases, the other abnormal feature data will decrease. By analyzing the size and direction of the eigenvalue of each principal component vector and combining this information, the association direction and association strength between different abnormal feature data can be determined to form the initial association analysis results. The above initial results can give a general framework and main features of the association relationship between abnormal feature data.

[0083] The above-mentioned Bayesian network model can more accurately analyze the probability of the simultaneous occurrence of different abnormal characteristic data on the basis of taking into account the uncertainty and conditional probability relationship between various factors, thereby supplementing and correcting the initial association analysis results obtained based on principal component analysis, so as to obtain a more accurate and more realistic final association analysis result.

[0084] First, each abnormal feature data is modeled as a node in the Bayesian network. Each node represents an abnormal feature data, such as a signal strength abnormal node, a signal frequency abnormal node, etc. Then, based on prior knowledge, historical data, and an understanding of the working principle and failure mode of the smart card chip, the conditional probability relationship between each node is determined. The above conditional probability relationship reflects the probability of other nodes (abnormal feature data) appearing in a certain state when a certain node (abnormal feature data) is known. For example, when the signal strength is known to be abnormal, what is the probability of the signal frequency being abnormal? This requires a large amount of experimental data, previous failure case analysis, etc. to determine. Then, Bayesian reasoning is used for analysis. Bayesian reasoning is based on the Bayesian theorem. According to the known prior probability (that is, the initial probability distribution of each node, which can also be determined by historical data, etc.) and the conditional probability relationship, the probability of other abnormal feature data appearing at the same time under certain given conditions (such as when some abnormal feature data are known to have appeared) is calculated. Finally, based on the calculated probability of different abnormal feature data appearing at the same time, the initial association analysis results are corrected. If the probability of certain abnormal feature data appearing at the same time is found to be much higher or lower than expected by the initial correlation analysis results through Bayesian reasoning, then it is necessary to make corresponding adjustments to the correlation relationship and correlation strength between these abnormal feature data in the initial correlation analysis results, so as to obtain a more accurate final correlation analysis result. This final result can more comprehensively and accurately reflect the true correlation relationship between the abnormal feature data, and provide a more reliable basis for subsequent fault location and other processing.

[0085] In one embodiment, fault location processing is performed according to the correlation analysis result to determine the location of the quality problem of the smart card chip and obtain the quality detection result, including:

[0086] The abnormal characteristic data in the association analysis result is used as a node of the tree to construct a fault tree; the causal relationship between the nodes is analyzed to determine the combination of fault causes; the combination of fault causes includes the combination of signals that cause the fault;

[0087] Acquire the design layout of the smart card chip, and determine the target circuit module generating the fault signal in the smart card chip based on the combination of fault causes;

[0088] Through the signal injection method, verify whether the target circuit module is an abnormal module;

[0089] If it is an abnormal module, the electrical parameters of the target circuit module are detected through micro-resistance test or capacitance test, and compared with the standard component parameters to determine the location of the quality problem and obtain the quality test results.

[0090] In this embodiment, the complex relationship between the abnormal feature data in the correlation analysis results is sorted out in a structured and visual manner, and a fault tree is constructed to deeply analyze the various causes of chip quality problems and their interrelationships, so as to determine which signal abnormality combinations jointly cause the fault, laying the foundation for subsequent precise positioning of the fault location.

[0091] First, treat each abnormal characteristic data in the association analysis result as a node of the fault tree. For example, if there are data such as abnormal signal strength, abnormal signal frequency, abnormal signal waveform, etc. in the association analysis result, then treat them as independent nodes respectively. Then, based on the understanding of the working principle of the smart card chip and the causal relationship between these abnormal characteristic data, determine the connection relationship between the nodes. If a certain abnormal characteristic data (such as abnormal signal strength) is the cause of another abnormal characteristic data (such as abnormal signal waveform), then establish a directed edge between the two nodes, from the cause node to the result node. In this way, a complete fault tree is gradually constructed, which can clearly show the sequence and causal relationship of different abnormal characteristic data in the process of causing the fault.

[0092] After constructing the fault tree, carefully analyze the causal relationship represented by the directed edges between the nodes. Along the direction of these directed edges, the propagation path of a series of abnormal characteristic data from the initial abnormal feature data (which is the root cause of the fault) to the final cause of the chip's obvious fault phenomenon can be traced. Through this analysis, it is possible to determine which combinations of abnormal feature data (i.e., the combination of fault causes) are most likely to cause chip quality problems. For example, when it is found that signal strength abnormalities and signal frequency abnormalities occur at the same time, it often causes a series of subsequent problems such as signal waveform distortion, thereby affecting the normal function of the chip. Then the combination of "abnormal signal strength + abnormal signal frequency" is determined as a combination of fault causes, which includes the signal combination that causes the fault.

[0093] Furthermore, the abstract fault cause combination is combined with the specific physical structure of the smart card chip (i.e., the design layout), and the signal abnormality that causes the fault is mapped to the actual circuit module on the chip, so as to further perform targeted detection and verification at the chip level and narrow the scope of troubleshooting.

[0094] First, obtain the detailed design layout of the smart card chip, which clearly shows the layout of each circuit module inside the chip, the connection relationship, and their connection with external interfaces such as chip pins. Then, according to the previously determined fault cause combination, the design layout is used to find the circuit modules associated with these abnormal characteristic data (signals in the fault cause combination). For example, if the fault cause combination involves signal anomalies related to data transmission, then the circuit module responsible for the data transmission function is found in the design layout and identified as the target circuit module that generates the fault signal. This is based on the familiarity with the working principle of the chip and the physical structure information provided by the design layout, mapping the fault cause from the signal level to the actual circuit module level of the chip, so that subsequent detection can be more targeted.

[0095] After initially determining the target circuit module, we actively inject test signals into it and observe its response to further verify whether the circuit module is indeed abnormal, thereby more accurately determining whether the module is the real root cause of chip quality problems.

[0096] Select a suitable signal injection device that can inject test signals into the input port of the target circuit module according to the set parameters (such as signal type, frequency, amplitude, etc.). For example, for a target circuit module responsible for data transmission, you can inject a signal similar to that during normal data transmission, but adjust some parameters to better detect its performance. After injecting the signal, closely observe the response signal output by the output port of the target circuit module. Compare this response signal with the standard response signal that the circuit module should output under normal circumstances. If there are obvious differences between the two, such as inconsistencies in the waveform, amplitude, frequency, etc. of the signal, then it can be preliminarily determined that the target circuit module is an abnormal module, that is, there is a quality problem that causes it to be unable to process the input test signal normally; on the contrary, if the response signal is basically consistent with the standard response signal, then it means that the circuit module performs normally under the current test conditions, and the cause of the failure is not in this module, and other target circuit modules need to be further checked.

[0097] When the target circuit module is determined to be an abnormal module, its internal key electrical parameters (such as microresistance, capacitance, etc.) are accurately tested and compared with the parameters of standard components. Further in-depth testing is carried out to the internal component level of the circuit module to accurately locate the specific quality problem. Ultimately, comprehensive and accurate quality inspection results are obtained, providing a basis for subsequent treatment measures (such as repair, scrapping, etc.).

[0098] For target circuit modules that are determined to be abnormal, use equipment such as a microresistance tester or a capacitance tester. For microresistance testing, connect the probes of the tester to both ends of the components or lines to be tested in the target circuit module to measure their actual resistance values. For capacitance testing, similarly connect the tester to the corresponding capacitance components to measure their actual capacitance values. These tests can obtain the actual electrical parameters of key components inside the target circuit module.

[0099] Compare the actual electrical parameters obtained through micro-resistance test or capacitance test with the standard component parameters of the corresponding components in the circuit module. Standard component parameters are parameter values ​​under normal working conditions specified in the chip design and manufacturing process. If there is a significant deviation between the actual electrical parameters and the standard component parameters, such as the resistance value is too large or too small, the capacitance value deviates from the standard value, etc., then it can be determined that there is a quality problem in the component. By performing such comparative tests on each problematic component, the scope is gradually narrowed down, and the location of the quality problem is finally determined, such as determining whether a specific resistor component is open circuit, a capacitor component is short circuit, and other specific situations.

[0100] Based on the location of the quality problem and the assessment of the severity of the problem (such as whether the problem affects the function of the entire circuit module, whether it will cause the chip to not work properly, etc.), a comprehensive and accurate quality inspection result is obtained. The above inspection results include not only information on the specific location of the quality problem, but also a description of the degree of impact on the overall function of the chip, so that corresponding treatment measures can be taken according to different situations in the future. For example, minor problems can be considered for repair, while problems that seriously affect the function of the chip need to be considered for scrapping, etc.

[0101] In one embodiment, collecting the electrical signal data of the smart card chip includes:

[0102] In the initialization phase when the smart card chip starts working, all monitoring points are coarsely sampled at the initial sampling frequency to obtain coarse sampling data; the monitoring points include the power pins, clock signal pins, data transmission pins and connection points between functional modules of the chip;

[0103] Analyzing the coarse sampling data by a machine learning algorithm to identify signal change areas and signal stable areas;

[0104] For the signal change area, control the sampling device to sample at an exponentially increasing sampling frequency until a preset maximum sampling frequency is reached to capture the rapid jump and short pulse of the signal;

[0105] For the signal stable region, the sampling device is controlled to reduce the sampling frequency to a minimum limit satisfying the Nyquist theorem to perform sampling.

[0106] In this embodiment, at the initial moment when the chip starts working, a preliminary and relatively broad sampling operation is performed on each key part (monitoring point) of the chip at a relatively low and relatively uniform sampling frequency. This is done to quickly obtain the basic situation of the electrical signals of each important position of the chip during the startup phase, and to provide an initial data basis for subsequent more detailed sampling and analysis; secondly, it avoids using too high a sampling frequency at the beginning, which leads to excessive data volume and contains too much unnecessary information, thereby improving the collection efficiency and making rational use of collection resources.

[0107] According to the general operating frequency range of the smart card chip, signal characteristics, and the performance of the acquisition equipment, a suitable initial sampling frequency is pre-set. This frequency should be able to capture the general characteristics of the electrical signals at each monitoring point when the chip is started, but it should not be too high to generate too much redundant data. For example, for common smart card chips, the initial sampling frequency is set to a few hundred hertz to a few thousand hertz, and the specific value needs to be determined in combination with the actual situation of the chip.

[0108] The above-mentioned monitoring points cover the power pins of the chip, because the electrical signal condition of the power pins is directly related to whether the chip can obtain stable power supply normally, and the changes in its voltage and current are crucial to the overall operation of the chip; clock signal pins, the clock signal is the metronome for the coordinated work of various modules inside the chip, and the accurate collection of its frequency, phase and other characteristics is very critical for analyzing the chip timing logic; data transmission pins, these pins are responsible for data interaction between the chip and external devices, and collecting their electrical signals can understand the situation during the data transmission process; and the connection points between functional modules, the different functional modules inside the chip transmit signals through these connection points, and monitoring the electrical signals here helps to discover whether the signal transmission between modules is normal.

[0109] Use the electrical signal acquisition equipment to sample all the above monitoring points at the same time according to the set initial sampling frequency. The acquisition equipment will record the electrical signal values ​​(such as voltage value, current value, etc.) of each monitoring point at each sampling moment. After a period of continuous sampling, the coarse sampling data is obtained. These coarse sampling data can reflect the general outline of the electrical signals of each monitoring point of the chip during the initialization stage, including the basic level of the signal, whether there is obvious abnormal fluctuation, etc.

[0110] By using the powerful data processing and pattern recognition capabilities of machine learning algorithms, the coarse sampling data collected initially is deeply analyzed so as to quickly and accurately distinguish which areas of electrical signals are in a state of frequent changes (signal change areas) and which areas of electrical signals are relatively stable (signal stable areas) from a large amount of seemingly chaotic data. This distinction is crucial for the subsequent targeted adjustment of the sampling frequency and more efficient collection of valuable electrical signal data. A variety of machine learning algorithms can be used to achieve this goal, such as clustering algorithms (such as K-Means clustering algorithms), decision tree algorithms, neural network algorithms, etc. Taking the K-Means clustering algorithm as an example, it can divide the coarse sampling data into different categories according to the characteristics of the data. Before the coarse sampling data is input into the machine learning algorithm, it is usually necessary to perform some preprocessing operations on the data, such as data cleaning (removing outliers, noise, etc.), data standardization (making data from different monitoring points comparable), etc. This can improve the performance of the algorithm and the accuracy of the analysis results. The preprocessed coarse sampling data is input into the selected machine learning algorithm. The algorithm will analyze according to the characteristics of the data (such as the amplitude change and frequency change of the electrical signal). For the K-Means clustering algorithm, it will cluster data points into different clusters. By setting appropriate clustering standards and parameters, those electrical signal data points with frequent amplitude changes and obvious frequency changes can be clustered into clusters corresponding to signal change areas, while those electrical signal data points with relatively stable amplitudes and small frequency changes can be clustered into clusters corresponding to signal stable areas. Through such an analysis process, it is possible to accurately identify signal change areas and signal stable areas in coarse sampling data.

[0111] For the signal change areas that have been identified, since the electrical signals in these areas have the characteristics of rapid changes, such as rapid jumps and short pulses, in order to fully and accurately capture these subtle and rapidly changing signal characteristics, the sampling frequency needs to be greatly increased. The exponentially increasing sampling frequency method can ensure that key signal changes are captured while flexibly adjusting the sampling frequency increase speed according to actual conditions until the preset maximum sampling frequency is reached, ensuring that no important signal details are missed.

[0112] For example, for the electrical signal of a data transmission pin, there will be a short pulse signal at the beginning or end of data transmission. If the sampling frequency is not high enough, these pulse signals will be missed or recorded inaccurately. However, by increasing the sampling frequency exponentially, they can be accurately captured, providing complete and accurate signal data for subsequent analysis.

[0113] For signal stable areas, since the electrical signal changes relatively slowly and steadily, a high sampling frequency is not required to capture its characteristics. By reducing the sampling frequency to the minimum limit that satisfies the Nyquist theorem, the amount of collected data can be greatly reduced while ensuring that the signal can be accurately restored, thereby saving storage resources and processing time of the collection equipment, improving collection efficiency, and avoiding the collection of too much unnecessary data.

[0114] The Nyquist theorem states that in order to accurately reconstruct the original analog signal, the sampling frequency should be no less than twice the highest frequency in the analog signal spectrum. For the signal stable area, the highest frequency of the electrical signal is relatively low, so the highest frequency can be determined based on the analysis of the electrical signal spectrum in this area. According to the Nyquist theorem, the lowest sampling frequency that satisfies the theorem is determined. After determining the highest frequency by means of spectrum analysis of the electrical signal in the signal stable area, the lowest sampling frequency that satisfies the Nyquist theorem can be calculated. Sampling at this sampling frequency can ensure that the electrical signal in this area can be accurately restored. At the same time, due to the low sampling frequency, the amount of data collected will be greatly reduced, thereby improving the collection efficiency and resource utilization. For example, for the electrical signal of a power pin, its voltage remains basically stable when the chip is working normally. By reducing the sampling frequency to the minimum limit that satisfies the Nyquist theorem, the amount of data collected can be reduced without affecting the judgment of its voltage stability.

[0115] In one embodiment, after obtaining the quality inspection result, the following steps are included:

[0116] Encoding the collected data to obtain coded data; wherein all the coded data are digital characters;

[0117] Add all characters in the encoded data to a preset graph structure to obtain a character graph; wherein each character is added to a node, and the difference between characters on adjacent nodes is used as the value of each edge;

[0118] Add all characters in the coded data to a preset matrix to generate a character matrix, and perform XOR calculation on the character matrix and a preset digital matrix to obtain an XOR value matrix;

[0119] A permission code is generated based on the XOR value matrix and the character map, and is used for performing permission management on the collected data and the quality detection results.

[0120] In this embodiment, the original collected data is digitally encoded and processed to be converted into a form consisting only of digital characters. This is convenient for subsequent unified management and operation in various data processing and storage operations, and on the other hand, it can enhance the confidentiality and standardization of the data, and lay the foundation for subsequent complex operations based on the encoded data (such as generating permission codes, etc.). A variety of encoding methods can be used to realize the conversion of collected data into encoded data in the form of digital characters. For example, common ones include ASCII code encoding (if the collected data is information related to text form), binary encoding (converting collected data such as analog signals into binary digital sequences according to certain rules), Gray code encoding, etc. The specific encoding method needs to be selected according to the type and characteristics of the collected data.

[0121] Furthermore, by constructing the coded data into a character graph in a specific way, the structure and relationship of the data can be presented from a completely new perspective. This graph structure can mine the potential connections between characters in the coded data, and provide a graph-based feature information for the subsequent generation of permission codes, so that the permission codes are not only related to the original collected data, but also reflect the characteristics of the data at the graph structure level.

[0122] First, a graph structure needs to be pre-set, such as a simple undirected graph or directed graph, and the number of nodes should be sufficient to accommodate all the characters of the encoded data. For example, the number of nodes of the graph can be determined according to the length of the encoded data to ensure that each character of the encoded data can be placed in a corresponding node. Each character in the encoded data is added to each node of the preset graph structure in turn. Assuming that the encoded data is a sequence of several digital characters, such as "12345", then "1" is added to the first node, "2" is added to the second node, and so on. For adjacent nodes in the graph structure, the difference between the characters added to them is calculated, and this difference is used as the value of the edge connecting the two adjacent nodes. For example, in the above example, the character "1" on the first node and the character "2" on the second node have a difference of "1", so the value of the edge connecting the two nodes is set to "1". In this way, a complete character graph is gradually constructed, which can show the adjacent relationship and difference changes between the characters in the encoded data in the form of a graph.

[0123] Furthermore, by constructing the coded data into a character matrix and performing an XOR calculation with a preset digital matrix, the characteristic information of the coded data at the matrix operation level is further mined. The XOR calculation can produce a unique result matrix, which combines the characteristics of the coded data and the preset digital matrix, and provides another basis for generating the permission code based on matrix operation, so that the permission code can integrate more dimensions of information related to the collected data. Obtain a preset matrix structure, the number of rows and columns of which is determined according to factors such as the length of the coded data and the subsequent operation requirements. Add the characters in the coded data to each element position of the preset matrix in a certain order (such as from left to right, from top to bottom) to generate a character matrix. For example, if the coded data is "12345" and the preset matrix is ​​a 2×3 matrix, then "1" can be added to the first row and first column of the matrix, "2" to the first row and second column, "3" to the first row and third column, "4" to the second row and first column, and "5" to the second row and second column to obtain the corresponding character matrix.

[0124] According to specific application requirements and design rules, a digital matrix is ​​pre-set. This digital matrix can be a fixed matrix with a specific digital combination, and its purpose is to perform XOR calculation with the character matrix to produce a result matrix with specific properties.

[0125] Perform XOR calculation on the generated character matrix and the preset digital matrix. The rule of XOR operation is: for the corresponding matrix elements in the two matrices, when their values ​​are different, the XOR result is "1"; when their values ​​are the same, the XOR result is "0". According to this rule, perform XOR calculation on each pair of corresponding elements of the character matrix and the preset digital matrix, and finally obtain an XOR value matrix. For example, for the above character matrix and digital matrix examples, after XOR calculation, a new 2×3 XOR value matrix will be obtained, and its element values ​​are determined according to the specific XOR calculation results.

[0126] Finally, by comprehensively utilizing the XOR value matrix and the multi-dimensional feature information about the collected data contained in the character graph obtained in the previous steps, a unique permission code is generated. The above permission code will be used to manage the permissions of the collected data and the quality inspection results related to it, ensuring that only personnel or systems with corresponding permissions can access, modify or use these important data, thereby ensuring the security and confidentiality of the data.

[0127] In one embodiment, key feature information can be extracted from the XOR value matrix and the character graph. For the XOR value matrix, it is possible to consider extracting features such as the determinant value of the matrix and the sum of the main diagonal elements; for the character graph, it is possible to extract the connectivity features of the graph (such as whether it is connected, the number of connected branches, etc.), the node degree distribution features, etc. These feature information will serve as an important basis for generating the permission code. According to the extracted feature information, a suitable algorithm or rule is used to generate the permission code. For example, the various extracted feature information can be combined in a certain order, and then processed by a hash function to obtain a hash value of a fixed length as the permission code. Or other encryption algorithms, such as symmetric encryption algorithms (such as AES algorithms) or asymmetric encryption algorithms (such as RSA algorithms), etc., are used to take the extracted feature information as input to generate the encrypted permission code. The permission code generated by the above process will be unique and confidential, and only those who know the correct decryption method or have the corresponding authority can obtain the original collection data and quality inspection results. In this way, the authority management of the collection data and quality inspection results is realized, and the security of the data is guaranteed.

[0128] In one embodiment, generating a permission code based on the XOR value matrix and the character map includes:

[0129] The XOR value matrix and the character image are superimposed according to a preset rule; the XOR value matrix includes two types of numbers, namely a first number and a second number; the first number is 1, and the second number is 0.

[0130] Clearing characters on each node in the character graph, and calculating the shortest distance between each edge of the character graph and the first number in the XOR value matrix;

[0131] Each edge whose nearest distance is less than a preset value is taken as a target edge, and the values ​​on each target edge are obtained and combined to obtain a combined character as the permission code.

[0132] In this embodiment, the XOR value matrix and the character map are superimposed according to specific preset rules, aiming to fuse the characteristic information about the collected data contained in these two different data structures, and create a comprehensive basis containing more dimensional information for the subsequent generation of permission codes. The above superposition is not a simple merger, but based on carefully designed rules, the information of the two can be related and interacted with each other, so as to mine more unique features that are closely related to the original collected data for the generation of permission codes.

[0133] First, it is necessary to clarify the preset superposition rules, which are determined according to the specific application scenario, data processing requirements and the overall design of permission code generation. For example, the preset rules may stipulate that the elements in the XOR value matrix are stacked in a certain order (such as row by row and column by column from the upper left corner to the lower right corner) with the nodes or edges in the corresponding positions in the character graph (the corresponding relationship can be determined according to a certain ordering method of the nodes, such as the order in which the characters are added to the nodes). Or the above-mentioned XOR value matrix and the character graph are generated into layers for visual superposition.

[0134] After the superposition operation is completed, the characters originally added to each node in the character graph are cleared so that the node only retains its position information in the graph structure and no longer contains the specific character content. After this processing, the character graph becomes a pure graph structure consisting of only nodes and edges, which is convenient for subsequent calculations and analysis focused on edges.

[0135] For each edge in the character graph, it is necessary to calculate the closest distance between it and the first number in the XOR value matrix. The closest distance calculation method here can be determined according to a specific definition, such as the smallest value in physical distance. By performing such a distance calculation on each edge of the character graph, the distance information between each edge and the first number can be obtained, thereby preparing for screening out the target edge.

[0136] By setting a preset value, the edges that are closer to the first digit in the XOR value matrix are selected as target edges. These target edges are considered to be the parts that are more closely related to the generation of the permission code after the XOR value matrix and the character graph information are integrated. The values ​​on these target edges are obtained and combined to form a unique combined character, which is used as the permission code, so that the permission code contains both the feature information related to the collected data extracted from the character graph edge and the relevant characteristics of the XOR value matrix through the distance screening mechanism with the first digit in the XOR value matrix, thereby realizing a permission management tool with specific meaning and closely related to the original collected data and related processing.

[0137] For example, the preset value is set to 2. Then, the calculated closest distance between each edge and the first number in the XOR value matrix is ​​compared with the preset value. If the closest distance of an edge is less than the preset value, then this edge is determined as the target edge. Continuing with the above example, if there are other edges whose distances from the first number are 1, 2.5, 0.5, etc., then the edges with distances of 1 and 0.5 will be determined as target edges because their distances are less than the preset value 2.

[0138] For each target edge that is determined, obtain the value on the edge. Assuming that there are multiple target edges, and the values ​​of the multiple edges are 1, 8, 7, 3, 4, 4, and 2, then combine the values ​​of these target edges in a certain order (which can be the natural order of the edges in the character graph, or according to other pre-set orders) to obtain a combined character, such as "1873442" here. The above combined character is used as the final permission code. In this way, the generated permission code is closely related to the information of the XOR value matrix and the character graph, and has uniqueness through a specific screening and combination mechanism, which can be used to manage the permissions of the collected data and quality inspection results, and ensure the security and confidentiality of the data.

[0139] In one embodiment, generating a permission code based on the XOR value matrix and the character map includes:

[0140] For the XOR value matrix, calculate the ratio of the first number or the second number in each row element to form a ratio vector. For example, if the XOR value matrix is ​​a 3×3 matrix, where the first number is 1, the second number is 0, and a row element is [1,0,1], then the ratio of the row is 2 / 3 (the number of 1s divided by the total number of elements). This calculation is performed for each row to obtain a ratio vector with the same dimension as the number of rows. At the same time, calculate the sum of all elements of the XOR value matrix as an overall eigenvalue.

[0141] For the character graph, the degree of each node (the number of edges connected to the node) is recorded to form a degree vector. In addition, the variance of the edge values ​​in the character graph is calculated as another eigenvalue.

[0142] Each proportional value in the proportional vector obtained by the XOR value matrix is ​​multiplied by a first preset integer (such as 100) and then rounded to the integer to obtain an integer sequence. This integer sequence is concatenated with the overall eigenvalue of the XOR value matrix to form a new XOR value encoding vector.

[0143] A similar process is performed on each degree value in the degree vector of the character graph, multiplied by a second preset integer (different from the previous one, such as 50) and rounded, and then this integer sequence is concatenated with the edge value variance eigenvalue of the character graph to form a character graph encoding vector.

[0144] Create a hash table with an initial size based on the length of the encoding vector and the expected collision rate. Choose an appropriate hash function, which can be, for example, a simple modulo hash function (modulo the hash table size after converting the encoding vector to an integer) or a more complex hash function based on a partial function of a cryptographic hash algorithm.

[0145] The XOR value encoding vector and the character image encoding vector are used as key-value pairs and inserted into the hash table. If a hash conflict occurs, the chain address method (connecting the conflicting key-value pairs with a linked list) or the open addressing method (finding the next available position through a certain detection sequence) can be used to handle it.

[0146] Traverse the hash table and concatenate the values ​​in each key-value pair (i.e., the value part of the XOR value encoding vector and the character map encoding vector) into a long string in a certain order (e.g., the value of the XOR value encoding vector first, then the value of the character map encoding vector).

[0147] Apply a hash algorithm (such as MD5, SHA-256, etc.) to this long string to obtain a fixed-length hash value, which is used as the permission code. Through the above steps, a permission code with high security and uniqueness is generated by using the XOR value matrix and multiple features of the character graph, which is used to manage the permissions of the collected data and quality inspection results.

[0148] Reference Figure 2 In one embodiment of the present invention, a quality inspection system for a smart card chip is provided, comprising:

[0149] A collection unit, used for collecting electrical signal data of the smart card chip to obtain collected data;

[0150] An extraction unit, used to perform feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features;

[0151] A classification unit, used for classifying the feature data into normal feature data and abnormal feature data;

[0152] An analysis unit, used to analyze the correlation between each of the abnormal feature data to obtain a correlation analysis result;

[0153] The positioning unit is used to perform fault positioning processing according to the correlation analysis result, determine the location of the quality problem of the smart card chip, and obtain the quality detection result.

[0154] In this embodiment, for the specific implementation of each unit in the above system embodiment, please refer to the above method embodiment, which will not be repeated here.

[0155] Reference Figure 3 In an embodiment of the present invention, a computer device is also provided. The computer device may be a server, and its internal structure may be as follows: Figure 3As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0156] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0157] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0158] In summary, the quality detection method and system of the smart card chip provided in the embodiment of the present invention include: collecting the electrical signal data of the smart card chip to obtain the collected data; performing feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features; classifying the feature data into normal feature data and abnormal feature data; analyzing the correlation between each of the abnormal feature data to obtain a correlation analysis result; performing fault location processing according to the correlation analysis result to determine the location of the quality problem of the smart card chip to obtain a quality detection result. In the present invention, by analyzing the correlation between each of the abnormal feature data to obtain a correlation analysis result, and performing fault location processing to determine the location of the quality problem of the smart card chip, the defect of being unable to accurately determine the root cause of the chip quality problem is overcome.

[0159] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0160] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0161] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A quality inspection method for a smart card chip, characterized in that: The following steps are involved: Collecting electrical signal data of the smart card chip to obtain collected data; Performing feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features; Classifying the feature data into normal feature data and abnormal feature data; Analyze the correlation between each of the abnormal feature data to obtain a correlation analysis result; Perform fault location processing according to the correlation analysis result to determine the location of the quality problem of the smart card chip and obtain the quality detection result.

2. The quality inspection method for smart card chips according to claim 1, characterized in that: The collected data includes power supply signals, data transmission signals, and electromagnetic radiation signals.

3. The quality inspection method for smart card chips according to claim 1, characterized in that: The analysis of the correlation between each of the abnormal feature data to obtain the correlation analysis result includes: Constructing a correlation matrix based on each of the abnormal feature data; wherein the rows and columns of the correlation matrix correspond to different abnormal feature data respectively, and the value of each matrix element is determined according to the correlation between the abnormal feature data; Performing principal component analysis on the correlation matrix to extract principal component vectors of the correlation matrix; Determine the correlation direction and correlation strength according to the eigenvalue size and direction of the principal component vector, and use it as the initial correlation analysis result; The Bayesian network model is used to model each of the abnormal feature data as a node, and the conditional probability relationship between the nodes is determined. The probability of the simultaneous occurrence of different abnormal feature data is analyzed through Bayesian reasoning. The initial association analysis result is corrected based on the probability situation to obtain the final association analysis result.

4. The quality inspection method for smart card chips according to claim 1, characterized in that: Perform fault location processing according to the correlation analysis result to determine the location of the quality problem of the smart card chip and obtain the quality inspection result, including: The abnormal characteristic data in the association analysis result is used as a node of the tree to construct a fault tree; the causal relationship between the nodes is analyzed to determine the combination of fault causes; the combination of fault causes includes the combination of signals that cause the fault; Acquire the design layout of the smart card chip, and determine the target circuit module generating the fault signal in the smart card chip based on the combination of fault causes; Through the signal injection method, verify whether the target circuit module is an abnormal module; If it is an abnormal module, the electrical parameters of the target circuit module are detected through micro-resistance test or capacitance test, and compared with the standard component parameters to determine the location of the quality problem and obtain the quality test results.

5. The quality inspection method for smart card chips according to claim 1, characterized in that: The collecting of electrical signal data of the smart card chip includes: In the initialization phase when the smart card chip starts working, all monitoring points are coarsely sampled at the initial sampling frequency to obtain coarse sampling data; the monitoring points include the power pins, clock signal pins, data transmission pins and connection points between functional modules of the chip; Analyzing the coarse sampling data by a machine learning algorithm to identify signal change areas and signal stable areas; For the signal change area, control the sampling device to sample at an exponentially increasing sampling frequency until a preset maximum sampling frequency is reached to capture the rapid jump and short pulse of the signal; For the signal stable region, the sampling device is controlled to reduce the sampling frequency to a minimum limit satisfying the Nyquist theorem to perform sampling.

6. The quality inspection method for smart card chips according to claim 1, characterized in that: After obtaining the quality test result, the method includes: Encoding the collected data to obtain coded data; wherein all the coded data are digital characters; Add all characters in the encoded data to a preset graph structure to obtain a character graph; wherein each character is added to a node, and the difference between characters on adjacent nodes is used as the value of each edge; Add all characters in the coded data to a preset matrix to generate a character matrix, and perform XOR calculation on the character matrix and a preset digital matrix to obtain an XOR value matrix; A permission code is generated based on the XOR value matrix and the character map, and is used for performing permission management on the collected data and the quality detection results.

7. The quality inspection method for smart card chips according to claim 6, characterized in that: Generating a permission code based on the XOR value matrix and the character map includes: The XOR value matrix and the character image are superimposed according to a preset rule; the XOR value matrix includes two types of numbers, namely, a first number and a second number; Clearing characters on each node in the character graph, and calculating the shortest distance between each edge of the character graph and the first number in the XOR value matrix; Each edge whose nearest distance is less than a preset value is taken as a target edge, and the values ​​on each target edge are obtained and combined to obtain a combined character as the permission code.

8. A quality inspection system for smart card chips, characterized in that: include: A collection unit, used for collecting electrical signal data of the smart card chip to obtain collected data; An extraction unit, used to perform feature extraction processing on the collected data to obtain feature data including signal strength features, signal frequency features and signal waveform features; A classification unit, used for classifying the feature data into normal feature data and abnormal feature data; An analysis unit, used to analyze the correlation between each of the abnormal feature data to obtain a correlation analysis result; The positioning unit is used to perform fault positioning processing according to the correlation analysis result, determine the location of the quality problem of the smart card chip, and obtain the quality detection result.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

Images