An LDO chip without external capacitors

Abstract

This application relates to the field of semiconductor integrated circuit technology and provides an LDO chip without external capacitors. The LDO chip includes an error amplifier, a buffer circuit, an overshoot / undershoot suppression circuit, a power transistor, a feedback circuit, and a feedforward circuit. The positive input terminal of the error amplifier is connected to the feedback terminal of the feedback circuit, the inverting input terminal of the error amplifier is connected to a first reference voltage, and the output terminal of the error amplifier is connected to the input terminal of the buffer circuit. The output terminal of the buffer circuit is connected to the input terminal of the overshoot / undershoot suppression circuit, the output terminal of the feedforward circuit, and the gate of the power transistor. The source terminal of the power transistor is connected to the input power supply and the input terminal of the feedforward circuit, and the drain terminal of the power transistor is connected to the output terminal of the overshoot / undershoot suppression circuit, the input terminal of the feedback circuit, and the output terminal of the LDO chip. This application can improve the performance of the LDO chip without external capacitors.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to an LDO chip without external capacitors. Background Technology

[0002] Power management chips play a crucial role in analog, digital, and mixed-signal chips. These chips typically require multiple power systems of different types and voltage levels to ensure their proper operation and performance. Low-dropout regulators (LDOs) are widely used power management integrated circuits that provide a stable output voltage, maintaining relative stability even under varying input voltage and output load current. LDOs are favored for their low noise, high efficiency, small size, and good load regulation. However, traditional LDO designs usually require a large external ceramic capacitor to ensure stability and reduce output noise. This external capacitor not only increases material costs but also increases board space requirements. Therefore, capacitor-free LDOs have become a research hotspot, but this design also brings new challenges, such as transient response performance, power ripple, and output noise control. Thus, current capacitor-free LDO chips suffer from low performance. Summary of the Invention

[0003] This application provides an LDO chip without external capacitors, which can solve the problem of low performance of LDO chips without external capacitors.

[0004] This application provides an LDO chip without external capacitors, the LDO chip including an error amplifier, a buffer circuit, an overshoot and undershoot suppression circuit, a power transistor, a feedback circuit, and a feedforward circuit;

[0005] The positive input terminal of the error amplifier is connected to the feedback terminal of the feedback circuit, the inverting input terminal of the error amplifier is connected to the first reference voltage, the output terminal of the error amplifier is connected to the input terminal of the buffer circuit, the output terminal of the buffer circuit is connected to the input terminal of the overshoot / undershoot suppression circuit, the output terminal of the feedforward circuit, and the gate of the power transistor, respectively. The source of the power transistor is connected to the input power supply and the input terminal of the feedforward circuit, respectively. The drain of the power transistor is connected to the output terminal of the overshoot / undershoot suppression circuit, the input terminal of the feedback circuit, and the output terminal of the LDO chip, respectively.

[0006] Optionally, the feedforward circuit includes an operational amplifier, a summing amplifier, a boosting capacitor, and a boosting resistor. The first terminal of the boosting capacitor is the input terminal of the feedforward circuit, and the output terminal of the summing amplifier is the output terminal of the feedforward circuit.

[0007] The first end of the boosting resistor is connected to the second reference voltage. The second end of the boosting resistor is connected to the second end of the boosting capacitor and the positive input terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier and the input terminal of the summing amplifier.

[0008] Optionally, the operational amplifier includes a first operational transistor, a second operational transistor, a third operational transistor, a fourth operational transistor, and a fifth operational transistor;

[0009] The gate of the third operational transistor is the positive input terminal of the operational amplifier, the gate of the fourth operational transistor is the inverting input terminal of the operational amplifier, and the drain of the fourth operational transistor and the drain of the second operational transistor are both output terminals of the operational amplifier.

[0010] The source of the first operational transistor is connected to the source of the second operational transistor. The gate of the first operational transistor is connected to the gate of the second operational transistor, the drain of the second operational transistor, and the drain of the third operational transistor. The source of the third operational transistor is connected to the source of the fourth operational transistor and the drain of the fifth operational transistor. The source of the fifth operational transistor is connected to the ground terminal. The gate of the fifth operational transistor is connected to the reverse control voltage.

[0011] The first, second, third, fourth, and fifth operational transistors are all P-type MOS transistors.

[0012] Optionally, the overshoot and undershoot suppression circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, an initial transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor.

[0013] The first terminal of the first capacitor, the second terminal of the second capacitor, the first terminal of the third capacitor, and the second terminal of the fourth capacitor are all output terminals of the overshoot and undershoot suppression circuit, and the gate of the fourteenth transistor and the gate of the fifteenth transistor are both input terminals of the overshoot and undershoot suppression circuit.

[0014] The second terminal of the first capacitor is connected to the source of the initial transistor and the first terminal of the first resistor. The drain of the initial transistor is connected to the drain of the thirteenth transistor. The gate of the initial transistor is connected to the gate of the sixth transistor, the drain of the fourteenth transistor, and the drain of the fifth transistor. The second terminal of the first resistor is connected to the source of the first transistor, the source of the thirteenth transistor, and the source of the sixth transistor. The drain of the first transistor is connected to the drain of the second transistor and the gate of the fifth transistor. The gate of the second transistor is connected to the gate of the fifth transistor. The source of the second transistor is connected to the drain of the third transistor, the gate of the third transistor, the gate of the fourth transistor, and the second terminal of the third capacitor. The source of the third transistor is connected to the source of the fourth transistor. The drain of the fourth transistor is connected to the source of the fifth transistor. The drain of the fifth transistor is connected to the drain of the sixth transistor.

[0015] The first terminal of the second capacitor is connected to the gate of the ninth transistor and the gate of the tenth transistor, respectively. The source of the tenth transistor is connected to the source of the ninth transistor, and the drain of the tenth transistor is connected to the source of the eleventh transistor. The drain of the ninth transistor is connected to the gate of the ninth transistor and the source of the eighth transistor, respectively. The gate of the eighth transistor is connected to the gate of the eleventh transistor, the drain of the seventh transistor, and the drain of the eighth transistor, respectively. The drain of the tenth transistor is connected to the source of the eleventh transistor, respectively. The drain of the eleventh transistor is connected to the gate of the thirteenth transistor, the drain of the twelfth transistor, the gate of the twelfth transistor, and the drain of the fifteenth transistor, respectively. The source of the twelfth transistor is connected to the source of the fifteenth transistor, the source of the seventh transistor, and the first terminal of the second resistor, respectively. The first terminal of the second resistor is connected to the source of the thirteenth transistor and the first terminal of the fourth capacitor, respectively. The gate of the seventh transistor is connected to a positive control voltage, and the gate of the first transistor is connected to a reverse control voltage.

[0016] Optionally, the initial transistor, the first transistor, the sixth transistor, the fourteenth transistor, the eleventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all P-type MOS transistors;

[0017] The second, third, fourth, fifth, seventh, twelfth, thirteenth, and fifteenth transistors are all N-type MOS transistors.

[0018] Optionally, the feedback circuit includes a first feedback resistor, a second feedback resistor, and a feedback capacitor;

[0019] The first end of the first feedback resistor and the first end of the feedback capacitor are both input terminals of the feedback circuit. The second end of the first feedback resistor and the first end of the second feedback resistor are both feedback terminals of the feedback circuit. The second end of the second feedback resistor is connected to the second end of the feedback capacitor and the ground terminal, respectively.

[0020] Optionally, the error amplifier includes a first error transistor, a second error transistor, a third error transistor, a fourth error transistor, a fifth error transistor, a sixth error transistor, a seventh error transistor, an eighth error transistor, a ninth error transistor, and a tenth error transistor.

[0021] The gate of the second error transistor is the positive input terminal of the error amplifier, the gate of the third error transistor is the inverted input terminal of the error amplifier, and the drains of the seventh and ninth error transistors are both output terminals of the error amplifier.

[0022] The gate of the first error transistor is connected to a positive control voltage. The source of the first error transistor is connected to the source of the tenth error transistor and the source of the eleventh error transistor. The drain of the first error transistor is connected to the source of the second error transistor and the source of the third error transistor. The drain of the second error transistor is connected to the drain of the fourth error transistor and the source of the sixth error transistor. The drain of the third error transistor is connected to the drain of the fifth error transistor and the source of the seventh error transistor. The source of the fourth transistor is connected to the source of the fifth transistor. The gates of the fourth and fifth error transistors are both connected to a first bias voltage. The gates of the sixth and seventh error transistors are both connected to a second bias voltage. The drain of the sixth error transistor is connected to the drain of the eighth error transistor, the gate of the tenth error transistor, and the gate of the eleventh error transistor. The gates of the eighth and ninth error transistors are both connected to a third bias voltage. The source of the eighth error transistor is connected to the drain of the tenth error transistor. The source of the ninth error transistor is connected to the drain of the eleventh error transistor.

[0023] Optionally, the first error transistor, the second error transistor, the third error transistor, the eighth error transistor, the ninth error transistor, the tenth error transistor, and the eleventh error transistor are all N-type MOS transistors;

[0024] The fourth, fifth, sixth, and seventh error transistors are all P-type MOS transistors.

[0025] Optionally, the buffer circuit includes a first push-pull transistor, a second push-pull transistor, a third push-pull transistor, a fourth push-pull transistor, a fifth push-pull transistor, a sixth push-pull transistor, a seventh push-pull transistor, an eighth push-pull transistor, a ninth push-pull transistor, and a tenth push-pull transistor.

[0026] The gates of the second and sixth push-pull transistors are both input terminals of the buffer circuit, while the drain of the eighth and ninth push-pull transistors are both output terminals of the buffer circuit.

[0027] The gate of the first push-pull transistor is connected to a positive control voltage. The source of the first push-pull transistor is connected to the source of the seventh push-pull transistor, the drain of the fifth push-pull transistor, and the source of the eighth push-pull transistor. The drain of the first push-pull transistor is connected to the source of the second push-pull transistor and the gate of the fifth push-pull transistor. The drain of the second push-pull transistor is connected to the drain of the third push-pull transistor, the gate of the third push-pull transistor, and the gate of the fourth push-pull transistor. The source of the third push-pull transistor is connected to the source of the tenth push-pull transistor, the source of the fourth push-pull transistor, and the drain of the ninth push-pull transistor. The drain of the tenth push-pull transistor is connected to the source of the sixth push-pull transistor and the gate of the ninth push-pull transistor. The gate of the tenth push-pull transistor is connected to a negative control voltage. The drain of the fourth push-pull transistor is connected to the source of the fifth push-pull transistor, the drain of the eighth push-pull transistor, and the source of the ninth push-pull transistor. The drain of the sixth push-pull transistor is connected to the drain of the seventh push-pull transistor, the gate of the sixth push-pull transistor, and the gate of the eighth push-pull transistor.

[0028] Optionally, the first push-pull transistor, the second push-pull transistor, the seventh push-pull transistor, the eighth push-pull transistor, and the ninth push-pull transistor are all N-type MOS transistors;

[0029] The third, fourth, fifth, sixth, and tenth push-pull transistors are all P-type MOS transistors.

[0030] The above-mentioned solution in this application has the following beneficial effects:

[0031] In some embodiments of this application, by superimposing the feedforward circuit with the main path of the LDO in opposite phase, ripple is effectively suppressed, and differential power input is achieved, thereby enhancing the power supply rejection performance of the entire LDO chip and reducing the interference of power supply ripple on the output voltage. By introducing a buffer circuit, the LDO chip can quickly adopt different paths in the buffer circuit for different loads in practical applications, improving the transient response of the LDO chip without external capacitors. At the same time, by connecting an overshoot and undershoot suppression circuit at the output of the buffer circuit, the voltage output by the buffer circuit can be processed to reduce the degree of voltage overshoot and undershoot, improve the stability of the output voltage, and further improve the performance of the LDO chip without external capacitors.

[0032] Other beneficial effects of this application will be described in detail in the following detailed description section. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a topology diagram of an LDO chip without external capacitors provided in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of the structure of an operational amplifier provided in one embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the overshoot and undershoot suppression circuit provided in an embodiment of this application;

[0037] Figure 4 A specific circuit topology diagram of an LDO chip without external capacitors provided in an embodiment of this application;

[0038] Figure 5 A schematic diagram of a PSR curve provided in an embodiment of this application;

[0039] Figure 6 This is a schematic diagram of the first instantaneous result provided in an embodiment of this application;

[0040] Figure 7 This is a schematic diagram of the second instantaneous result provided in an embodiment of this application;

[0041] Figure 8 This is a schematic diagram of the third instantaneous result provided in an embodiment of this application;

[0042] Figure 9 The topology of a hybrid DC-DC and LDO circuit provided in an embodiment of this application is shown. Detailed Implementation

[0043] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0044] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0045] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0046] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0047] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0048] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0049] To address the low performance issue of LDO chips without external capacitors, this application provides an LDO chip without external capacitors. By superimposing a feedforward circuit with the main path of the LDO in opposite phase, ripple is effectively suppressed, enabling differential power input. This enhances the overall power supply rejection performance of the LDO chip and reduces the interference of power supply ripple on the output voltage. By introducing a buffer circuit, the LDO chip can quickly adopt different paths in the buffer circuit for different loads in practical applications, improving the transient response of the LDO chip without external capacitors. At the same time, by connecting an overshoot and undershoot suppression circuit to the output of the buffer circuit, the output voltage of the buffer circuit can be processed to reduce the degree of voltage overshoot and undershoot, improve the stability of the output voltage, and further improve the performance of the LDO chip without external capacitors.

[0050] The LDO chip without external capacitors provided in this application will be described exemplarily below.

[0051] like Figure 1 As shown, the LDO chip without external capacitors provided in this application includes: an error amplifier (such as...) Figure 1 EA-amp in the middle), buffer circuit (such as Figure 1 (buffer in the middle), overshoot and undershoot suppression circuit (such as) Figure 1 Undershoot / Overshoot), power transistors (such as...) Figure 1 The MP, feedback circuit, and feedforward circuit in the circuit.

[0052] The positive input terminal of the aforementioned error amplifier is connected to the feedback terminal of the feedback circuit, and the inverting input terminal of the error amplifier is connected to the first reference voltage (e.g., ...). Figure 1 In the VREF1 section, the output of the error amplifier is connected to the input of the buffer circuit. The output of the buffer circuit is connected to the input of the overshoot / undershoot suppression circuit, the output of the feedforward circuit, and the gate of the power transistor. The source of the power transistor is connected to the input power supply (e.g., VREF1). Figure 1 The power transistor is connected to the input terminal of the feedforward circuit (VDD), and the drain of the power transistor is connected to the output terminal of the overshoot and undershoot suppression circuit, the input terminal of the feedback circuit, and the output terminal of the LDO chip.

[0053] Feedforward circuitry includes operational amplifiers (such as...) Figure 1 FA-amp), summing amplifier (such as Figure 1 SA-amp in the middle), reinforcement capacitor (such as Figure 1 Ch1 in the middle), enhancing resistor (such as Figure 1 In the circuit, Rh1), the first terminal of the enhancement capacitor is the input terminal of the feedforward circuit, and the output terminal of the summing amplifier is the output terminal of the feedforward circuit.

[0054] The first terminal of the boost resistor is connected to the second reference voltage (e.g.) Figure 1 In the above, the second end of the enhancement resistor (VREF2) is connected to the second end of the enhancement capacitor and the positive input terminal of the operational amplifier, respectively. The output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier and the input terminal of the summing amplifier, respectively.

[0055] The feedback circuit includes a first feedback resistor (e.g., Figure 1 R1 in the middle), the second feedback resistor (such as R1 in the middle), and the second feedback resistor (such as R1 in the Figure 1 R2 in the middle), feedback capacitor (such as Figure 1 (CL in the text).

[0056] The first terminal of the first feedback resistor and the first terminal of the feedback capacitor are both input terminals of the feedback circuit. The second terminal of the first feedback resistor and the first terminal of the second feedback resistor are both feedback terminals of the feedback circuit. The second terminal of the second feedback resistor is connected to the second terminal of the feedback capacitor and the ground terminal (e.g., ...). Figure 1 The VSS in the middle is connected.

[0057] It should be noted that, Figure 1 In this context, VG represents the gate voltage of the power transistor, VFB represents the feedback voltage, and Vout represents the output voltage of the LDO chip.

[0058] like Figure 2 As shown, the operational amplifier includes a first operational transistor (such as...). Figure 2 Mf1 in the second operational transistor (such as Mf1) Figure 2 Mf2 in the middle), the third operational transistor (such as Mf2), and the third operational transistor (such as Mf2) Figure 2 Mf3 in the fourth operational transistor (such as Mf3) Figure 2 Mf4 in the fifth operational transistor (such as Mf4) Figure 2 Mf5 in (the text is incomplete and cannot be translated).

[0059] The gate of the third operational transistor is the positive input terminal of the operational amplifier (e.g., Figure 2In the Vp), the gate of the fourth operational transistor is the inverting input of the operational amplifier (e.g., Vp). Figure 2 In the above, Vn), the drain of the fourth operational transistor and the drain of the second operational transistor are both output terminals of the operational amplifier (e.g., Vn). Figure 2 Vout_FA in (the context of Vout_FA).

[0060] The source of the first operational transistor is connected to the source of the second operational transistor. The gate of the first operational transistor is connected to the gate of the second operational transistor, the drain of the second operational transistor, and the drain of the third operational transistor. The source of the third operational transistor is connected to the source of the fourth operational transistor and the drain of the fifth operational transistor. The source of the fifth operational transistor is connected to ground (e.g., ...). Figure 2 The fifth operational transistor is connected to the VSS, and its gate is connected to the reverse control voltage (such as VSS). Figure 2 (Vn_bias in the text).

[0061] The first, second, third, fourth, and fifth operational transistors are all P-type MOS transistors.

[0062] It should be noted that since both the first and second operational transistors are P-type MOSFETs, and for P-type MOSFETs, the source needs to be connected to the input power supply, therefore the sources of both the first and second operational transistors are also connected to the input power supply (e.g., Figure 2 The sources of the first and second operational transistors are connected to VDD, which is a fixed connection method for P-type MOSFETs. Figure 1 (Not shown in the diagram). Source negative feedback is achieved through a feedforward circuit, and the voltage ripple transmitted from the operational amplifier is summed by a summing amplifier and injected into the gate of the power transistor, thus partially eliminating the voltage ripple that directly enters the power transistor from VDD.

[0063] like Figure 3 As shown, the overshoot and undershoot suppression circuit includes a first transistor (such as...). Figure 3 Mc1 in the middle), the second transistor (such as Figure 3 Mc2 in the middle), the third transistor (such as Figure 3 Mc3 in the middle), the fourth transistor (such as Figure 3 Mc4 in the middle), the fifth transistor (such as Figure 3 Mc5 in the middle), the sixth transistor (such as Figure 3 Mc6 in the middle), the seventh transistor (such as Figure 3 Mc7 in the middle), the eighth transistor (such as Figure 3 Mc8 in the middle), the ninth transistor (such as Figure 3 Mc9 in the middle), the tenth transistor (such as Mc9), Figure 3 Mc10 in the middle), the eleventh transistor (such as Figure 3 Mc11 in the middle), the twelfth transistor (such as Figure 3 Mc12 in the middle), the thirteenth transistor (such as Figure 3 Mc13 in the middle), the fourteenth transistor (such as Figure 3 MI1 in the middle), the fifteenth transistor (such as MI1 ...) Figure 3 MI2 in the middle), initial transistor (such as MI2 ...) Figure 3 Mc0 in the first resistor (e.g., Mc0) Figure 3 R1 in the middle), the second resistor (such as Figure 3 R2 in the middle), the first capacitor (such as R2 in the middle), and the first capacitor (such as R2 in the middle). Figure 3 C1 in the middle), the second capacitor (such as C1), and the second capacitor (such as C1) Figure 3 C2 in the middle), the third capacitor (such as C2), and the third capacitor (such as C2) Figure 3 C3) and the fourth capacitor (such as Figure 3 (C4 in the middle).

[0064] The first terminal of the first capacitor, the second terminal of the second capacitor, the first terminal of the third capacitor, and the second terminal of the fourth capacitor are all output terminals of the overshoot and undershoot suppression circuit (e.g., Figure 3 In the above, Vout), the gates of the fourteenth and fifteenth transistors are both input terminals of the overshoot and undershoot suppression circuit (e.g., Vout). Figure 3 (Vp_bias1 and Vn_bias1 in the text).

[0065] The second terminal of the first capacitor is connected to the source of the initial transistor and the first terminal of the first resistor. The drain of the initial transistor is connected to the drain of the thirteenth transistor. The gate of the initial transistor is connected to the gate of the sixth transistor, the drain of the fourteenth transistor, and the drain of the fifth transistor. The second terminal of the first resistor is connected to the source of the first transistor, the source of the thirteenth transistor, and the source of the sixth transistor. The drain of the first transistor is connected to the drain of the second transistor and the gate of the fifth transistor. The gate of the second transistor is connected to the gate of the fifth transistor. The source of the second transistor is connected to the drain of the third transistor, the gate of the third transistor, the gate of the fourth transistor, and the second terminal of the third capacitor. The source of the third transistor is connected to the source of the fourth transistor. The drain of the fourth transistor is connected to the source of the fifth transistor. The drain of the fifth transistor is connected to the drain of the sixth transistor.

[0066] The first terminal of the second capacitor is connected to the gate of the ninth transistor and the gate of the tenth transistor, respectively. The source of the tenth transistor is connected to the source of the ninth transistor, and the drain of the tenth transistor is connected to the source of the eleventh transistor. The drain of the ninth transistor is connected to the gate of the ninth transistor and the source of the eighth transistor, respectively. The gate of the eighth transistor is connected to the gate of the eleventh transistor, the drain of the seventh transistor, and the drain of the eighth transistor, respectively. The drain of the tenth transistor is connected to the source of the eleventh transistor, respectively. The drain of the eleventh transistor is connected to the gate of the thirteenth transistor, the drain of the twelfth transistor, the gate of the twelfth transistor, and the drain of the fifteenth transistor, respectively. The source of the twelfth transistor is connected to the source of the fifteenth transistor, the source of the seventh transistor, and the first terminal of the second resistor, respectively. The first terminal of the second resistor is connected to the source of the thirteenth transistor and the first terminal of the fourth capacitor, respectively. The gate of the seventh transistor is connected to a positive control voltage (e.g., ...). Figure 3 In the Vp_bias parameter, the gate of the first transistor is connected to an inverted control voltage (e.g., Vp_bias). Figure 3 (Vn_bias in the text).

[0067] It should be noted that the sources of the third transistor, the fourth transistor, the first terminal of the second resistor, the seventh transistor, the fifteenth transistor, and the twelfth transistor are all connected to the input power supply (e.g., Figure 3 In the VDD configuration, the second terminal of the first resistor, the source of the first transistor, the source of the fourteenth transistor, the source of the sixth transistor, the source of the ninth transistor, and the source of the tenth transistor are all connected to the ground terminal (e.g., VDD). Figure 3 VSS in the middle), Figure 3 The connections between the transistor and VDD, and between the transistor and VSS, are both fixed connection methods for transistors. Figure 1 (Not shown in the text) Figure 3 VG in the diagram represents the gate voltage of the power transistor. The initial transistor, first transistor, sixth transistor, fourteenth transistor, eleventh transistor, eighth transistor, ninth transistor, and tenth transistor are all P-type MOSFETs; the second transistor, third transistor, fourth transistor, fifth transistor, seventh transistor, twelfth transistor, thirteenth transistor, and fifteenth transistor are all N-type MOSFETs.

[0068] according to Figure 1 The structure of the LDO chip without external capacitors shown is as follows: Figure 2 The specific circuit topology of the LDO chip (without overshoot / undershoot suppression circuits and filtering enhancement capacitor Ch1 and enhancement resistor Rh1) obtained from the operational amplifier structure shown is as follows: Figure 4 As shown.

[0069] like Figure 4As shown, the error amplifier includes a first error transistor (such as...). Figure 4 Ma1 in the middle), the second error transistor (such as...) Figure 4 Ma2 in the middle), the third error transistor (such as Ma2), and the third error transistor (such as Ma2) Figure 4 Ma3 in the middle), the fourth error transistor (such as Figure 4 Ma4 in the middle), the fifth error transistor (such as Figure 4 Ma5 in the middle), the sixth error transistor (such as Figure 4 Ma6 in the middle), the seventh error transistor (such as Figure 4 Ma7 in the middle), the eighth error transistor (such as Ma7 ...) Figure 4 Ma8 in the middle), the ninth error transistor (such as Ma8), and the ninth error transistor (such as Ma8) Figure 4 Ma9 in the middle), the tenth error transistor (such as Ma9), and the tenth error transistor (such as Ma9). Figure 4 (Ma10 in the middle).

[0070] The gate of the second error transistor is the positive input terminal of the error amplifier (e.g., Figure 4 In the VFB), the gate of the third error transistor is the inverting input of the error amplifier (e.g., VFB). Figure 4 In the above, VREF1), the drains of the seventh and ninth error transistors are both output terminals of the error amplifier (e.g., VREF1). Figure 4 (VEA in the text).

[0071] The gate of the first error transistor is connected to a positive control voltage (e.g., Figure 4 In the `vp_bias` parameter, the source of the first error transistor is connected to the source of the tenth and eleventh error transistors, respectively. The drain of the first error transistor is connected to the source of the second and third error transistors, respectively. The drain of the second error transistor is connected to the drain of the fourth and sixth error transistors, respectively. The drain of the third error transistor is connected to the drain of the fifth and seventh error transistors, respectively. The source of the fourth transistor is connected to the source of the fifth transistor. The gates of the fourth and fifth error transistors are both connected to a first bias voltage (e.g., ...). Figure 4 In the second bias voltage (vb1), the gates of the sixth and seventh error transistors are both connected to the second bias voltage (e.g., vb1). Figure 4 In the context of VB2), the drain of the sixth error transistor is connected to the drain of the eighth error transistor, the gate of the tenth error transistor, and the gate of the eleventh error transistor, respectively. The gates of the eighth and ninth error transistors are both connected to a third bias voltage (e.g., ...). Figure 4 In the VB3 configuration, the source of the eighth error transistor is connected to the drain of the tenth error transistor, and the source of the ninth error transistor is connected to the drain of the eleventh error transistor.

[0072] It should be noted that the first, second, third, eighth, ninth, tenth, and eleventh error transistors are all N-type MOS transistors; while the fourth, fifth, sixth, and seventh error transistors are all P-type MOS transistors.

[0073] The buffer circuit includes a first push-pull transistor (such as...) Figure 4 Mb1 in the middle), the second push-pull transistor (such as Mb1), and the second push-pull transistor (such Figure 4 Mb2 in the middle), the third push-pull transistor (such as Mb2), and the third push-pull transistor (such Figure 4 Mb3 in the middle), the fourth push-pull transistor (such as Mb3), and the fourth push-pull transistor (such Figure 4 Mb4 in the middle), the fifth push-pull transistor (such as Figure 4 Mb5 in the middle), the sixth push-pull transistor (such as Figure 4 Mb6 in the middle), the seventh push-pull transistor (such as Figure 4 Mb7 in the middle), the eighth push-pull transistor (such as Mb7), the eighth push-pull transistor (such as Figure 4 Mb8 in the middle), the ninth push-pull transistor (such as Figure 4 Mb9 in the middle), the tenth push-pull transistor (such as Figure 4 Mb10 in the middle).

[0074] The gates of the second and sixth push-pull transistors are both input terminals of the buffer circuit, while the drain of the eighth and ninth push-pull transistors are both output terminals of the buffer circuit.

[0075] The gate of the first push-pull transistor is connected to a positive control voltage. The source of the first push-pull transistor is connected to the source of the seventh push-pull transistor, the drain of the fifth push-pull transistor, and the source of the eighth push-pull transistor. The drain of the first push-pull transistor is connected to the source of the second push-pull transistor and the gate of the fifth push-pull transistor. The drain of the second push-pull transistor is connected to the drain of the third push-pull transistor, the gate of the third push-pull transistor, and the gate of the fourth push-pull transistor. The source of the third push-pull transistor is connected to the source of the tenth push-pull transistor, the source of the fourth push-pull transistor, and the drain of the ninth push-pull transistor. The drain of the tenth push-pull transistor is connected to the source of the sixth push-pull transistor and the gate of the ninth push-pull transistor. The gate of the tenth push-pull transistor is connected to a negative control voltage. The drain of the fourth push-pull transistor is connected to the source of the fifth push-pull transistor, the drain of the eighth push-pull transistor, and the source of the ninth push-pull transistor. The drain of the sixth push-pull transistor is connected to the drain of the seventh push-pull transistor, the gate of the sixth push-pull transistor, and the gate of the eighth push-pull transistor.

[0076] It should be noted that the first push-pull transistor, the second push-pull transistor, the seventh push-pull transistor, the eighth push-pull transistor, and the ninth push-pull transistor are all N-type MOSFETs; the third push-pull transistor, the fourth push-pull transistor, the fifth push-pull transistor, the sixth push-pull transistor, and the tenth push-pull transistor are all P-type MOSFETs. Figure 4 In this diagram, VDD represents the input voltage, VSS represents the ground terminal, RD represents the first adding resistor, RS represents the second adding resistor, Ms1 represents the first adding transistor, Ms2 represents the second adding transistor, and Mf6 represents the third adding transistor. The sources of the second and first adding transistors are both output terminals of the summing amplifier. The gate, source, and first terminal of the second adding resistor of the third adding transistor are both input terminals of the summing amplifier. The gate of the third adding transistor is connected to the output terminal of the operational amplifier. The source of the third adding transistor is connected to the inverting input terminal of the operational amplifier and the first terminal of the second adding resistor. The drain of the third adding transistor is connected to the second terminal of the first adding resistor and the gate of the first adding transistor. The second terminal of the second adding resistor is connected to the ground terminal and the drain of the second adding transistor. The gate of the second adding transistor is the Vb terminal, which represents the bias voltage. The first terminal of the first adding resistor is connected to the first terminal of the first adding transistor. Figure 4 The plus sign indicates the addition of current.

[0077] The working principle of the LDO chip without external capacitors of this application will be illustrated by example below.

[0078] The feedforward circuit in the LDO chip without external capacitors of this application is used to reduce the impact of voltage ripple generated by the input voltage on the output voltage. It mainly consists of a five-transistor operational amplifier, a common-source transistor with source-level negative feedback, and a common-source transistor with bias voltage. Without the feedforward circuit, the transfer function of the LDO chip is:

[0079]

[0080] Where VOUT represents the output voltage, VDD represents the input voltage, gm,mp is the transconductance of the power transistor, rds,mp is the channel resistance of the power transistor, Zl(s) is the impedance at the LDO output, R1 represents the first feedback resistor, R2 represents the second feedback resistor, AEA is the gain of the error amplifier, Abuffer is the gain of the buffer circuit, and wout is the dominant pole of the LDO.

[0081] With the addition of a feedforward circuit, the transfer function of the LDO chip is:

[0082]

[0083] Where Hff(s) is the gain of the feedforward circuit, As0 is the gain of the summing amplifier, ws is the dominant pole of the summing amplifier, and s represents a purely imaginary number used to describe the system's response to sinusoidal input signals of different frequencies.

[0084] Since gm,mp*rds,mp>>1, only the following settings need to be configured in the added feedforward circuit: Theoretically, the voltage ripple can be made infinitely small, approaching zero, resulting in excellent power supply rejection (PSR). In the feedforward circuit, a 1:1 voltage ripple replication is used. Here, a five-transistor operational amplifier is used as the first stage of the feedforward amplification. The voltage ripple at the output of the operational amplifier can be expressed as:

[0085]

[0086] Since Ro2 >> 1 / gm1, therefore

[0087]

[0088] Where Vout_FA is the voltage ripple at the output of the operational amplifier, I2 is the current flowing through the input transistor, and Ro1 and Ro2 are the channel resistances of the load transistor and the input transistor, respectively.

[0089] The voltage ripple of the feedforward circuit proposed in this application is replicated 1:1 and then passed through the feedback loop. In the loop with deep negative feedback, a resistor is used as the connection method, at which point the voltage gain... After passing through the common-source terminal of the summing amplifier, the gain attenuation caused by the dominant pole of the summing amplifier is negligible because its dominant pole is far outside the bandwidth. Furthermore, the use of an independently biased voltage in this structure avoids the gain reduction in the feedforward ripple circuit caused by the reduction in voltage gain in the loop, which would decrease the replication ratio, leading to inaccurate replication and no enhancement effect. Compared to existing structures where the summing op-amp is connected in the loop, this structure exhibits high stability and better PSR enhancement capability, achieving ripple suppression in the mid-to-low frequency range. Finally, the voltage ripple of the input power transistor is differentially eliminated with the voltage ripple of the power transistor branch, achieving a high PSR effect.

[0090] This application incorporates a buffer circuit for transient enhancement. The buffer circuit controls the tail current variation of the overshoot / undershoot suppression circuit and utilizes the subthreshold current characteristics of the transistor to achieve transient enhancement. The buffer circuit employs two load paths: under light load conditions, the VEA voltage and VG voltage are both higher. Figure 4As shown, Mb6-Mb9 start working, while Mb1-Mb5 are off. Under heavy load, Mb1-Mb5 conduct, and Mb6-Mb9 are off. During load current switching (light load to heavy load), due to insufficient loop bandwidth, the loop cannot respond in time and cannot provide the large current required by the power transistors. At this time, the load capacitor provides the required charge, causing the output voltage to drop, which in turn causes the feedback voltage to drop. After passing through the cascode op-amp output, the output voltage of the op-amp drops. At this time, the Mb1-Mb5 loop comes into play. Due to the current source constraint of Mb1, the gate voltage of Mb2 decreases, thus reducing the source voltage of Mb2. Current is replicated through Mb3 to Mb4. Similarly, the gate voltage of Mb5, equal to the source voltage of Mb2, decreases, leading to a further decrease in the source voltage of Mb5. The power transistor's gate voltage VG equals the source voltage of Mb5, thus pulling down the power transistor's gate voltage and increasing its current (the increased current equals gmp * ΔVGS). This regulates the power transistor to meet the load current, resulting in a faster response. Under heavy load and light load conditions, the power transistor requires less current, and the excess charge charges the output capacitor, causing the output voltage to rise. The op-amp's output voltage also increases. At this point, the Mb6-Mb10 loop comes into play, with Mb10 acting as a current source to clamp the current. The source voltage of Mb6 increases, passing through Mb8, and finally, the source voltage of Mb8 also increases, thus increasing VG. This raises the PMOS gate voltage, reducing the power transistor's current and achieving a fast response.

[0091] However, due to loop bandwidth and transistor state limitations, the current cannot change too much, resulting in insufficient transient response. Therefore, an additional overshoot / undershoot suppression circuit, controlled by a buffer circuit, is added, and the transistor size is increased to ensure all transistors operate in the subthreshold region. The current change formula in the subthreshold region is:

[0092]

[0093] Where ID is the changed current, I0 is the current before the change, Vgs is the gate-source voltage, ξ is a non-ideal factor, and VT is an intermediate parameter. K represents the Boltzmann constant, T represents the absolute temperature, and q represents the elementary charge.

[0094] When the voltage changes, the current changes exponentially. For example... Figure 4As shown, the current source MI1 at the tail of the buffer circuit is controlled by the source terminal of transistor Mb6. The principle of increasing the current is that, under DC conditions, the current of MI1 completely absorbs the current from Mc4 and Mc5, so that no current flows through Mc6, and therefore no current flows through Mc0, causing no impact in steady state. During the switching process from light load to heavy load, as the output voltage decreases, the voltage at the source terminal of Mb6 will eventually decrease as well. The current consumed by the circuit source MI1 gradually decreases, and the excess current is transferred to Mc0 through Mc6, increasing the current of Mc0. Finally, all the changing current flows through Mc0 to regulate the gate voltage of the power transistor. The current formula at this time is:

[0095]

[0096] In this context, the channel length modulation effect is ignored, Vgs is the gate-source voltage of the transistor, μn is the electron mobility, Cox is the gate oxide thickness, and W and L are the width and length of the transistor, respectively.

[0097] Simultaneously, the capacitive coupling path added to Mc0 causes a decrease in its source voltage and an increase in its gate voltage. Therefore, at the instant Vgs increases and the replication current increases, Mc0's current changes from the nA level to the uA level. The large current charged by this change charges the power transistor, thus enhancing transient response and reducing undershoot voltage. During the heavy-load to light-load switching process, the source of Mb2, connected to the bias voltage of MI2, experiences an increase in output voltage, leading to an increase in the error amplifier's output voltage, a rise in the source voltage of Mb2, and an increase in the gate voltage of MI2. This reduces the current consumed, and the excess current flows through Mc13. Simultaneously, the capacitive coupling path added to Mc13 causes an increase in its source voltage and a decrease in its gate voltage. The current replicated through Mc12 increases, so at the instant Vgs decreases and the replication current increases, Mc13's current changes from the nA level to the uA level. The final current changes and discharges the power transistor through Mc3, consuming the excess current. This further enhances transient response and reduces overshoot voltage.

[0098] The performance of the LDO chip without external capacitors of this application will be illustrated by a specific example below.

[0099] Simulation models of the LDO chip without external capacitors proposed in this application were constructed using circuit simulation software such as Proteus and Multisim, and related experiments were conducted. The resulting PSR curve is shown in the figure below. Figure 5 As shown in the figure, the horizontal axis represents the frequency Freq, in Hertz (Hz), and the vertical axis represents the PSR value, in decibels (dB). The dashed line in the figure is the PSR curve of the LDO chip without PSR enhancement (i.e. without feedforward circuit), and the solid line is the PSR curve with PSR enhancement (i.e. the LDO chip of this application).

[0100] The transient results for 1us are as follows Figure 6 As shown in the figure, the horizontal axis represents time, and the unit is microseconds (µs). Figure 6 (a) is a load current curve of the LDO chip of this application, with the vertical axis representing current in milliamperes (mA). Figure 6 (b) is a transient curve of the output voltage of the LDO chip of this application. The vertical axis represents the output voltage in volts (V). The two curves are the output voltage transient curves of the LDO chip of this application (with transient enhancement) and the LDO chip without transient enhancement, respectively.

[0101] The transient results for 100 ns are as follows Figure 7 As shown in the figure, the horizontal axis represents time, and the unit is microseconds (µs). Figure 7 (a) is a load current curve of the LDO chip of this application, with the vertical axis representing current in milliamperes (mA). Figure 7 (b) is a transient curve of the output voltage of the LDO chip of this application. The vertical axis represents the output voltage in volts (V). The two curves are the output voltage transient curves of the LDO chip of this application (with transient enhancement) and the LDO chip without transient enhancement, respectively.

[0102] The transient results at 500 ns are as follows Figure 8 As shown in the figure, the horizontal axis represents time, and the unit is microseconds (µs). Figure 8 (a) is a load current curve of the LDO chip of this application, with the vertical axis representing current in milliamperes (mA). Figure 8 (b) is a transient curve of the output voltage of the LDO chip of this application. The vertical axis represents the output voltage in volts (V). The two curves are the output voltage transient curves of the LDO chip of this application (with transient enhancement) and the LDO chip without transient enhancement, respectively.

[0103] Therefore, the LDO chip of this application achieves rapid voltage and current switching during load switching, significantly improving the gate switching rate and thus enhancing transient response. This design significantly reduces overcharge and undercharge voltage values ​​and shortens recovery time. During load switching times of 100ns, 500ns, and 1us, this LDO chip exhibits excellent transient performance. Particularly during the 100ns load switching, overcharge and undercharge voltages are reduced by 113mV and 107mV, respectively, resulting in a 40% improvement in transient response performance. Furthermore, the phase margin is consistently maintained above 45°, ensuring circuit stability.

[0104] Regarding PSR ripple cancellation, this application introduces a feedforward circuit between the gate and power rail (VDD) of the power transistor (MP). This feedforward circuit is superimposed in phase with the main path of the voltage ripple, effectively suppressing the ripple. Through synergy with the transconductance and channel resistance in the MP, this design achieves differential power input in the MP, thereby enhancing the overall PSR performance of the LDO chip. An overall PSR enhancement is achieved up to 1MHz, with some embodiments showing an enhancement of up to 41dB.

[0105] In some embodiments, the LDO chip of this application can be combined with a DC-DC circuit to form a voltage regulator circuit, such as... Figure 9 As shown, the voltage regulator circuit includes a first switch, a second switch, a third switch, a fourth switch, a DC-DC converter circuit, an LDO circuit (i.e., the LDO chip of this application), and a comparator. The second terminal of the first switch and the first terminal of the second switch are both connected to the input voltage (Vcc). The second terminal of the first switch is connected to the common terminal of the third switch and the first terminal of the DC-DC converter circuit. The normally open terminal of the third switch is connected to the normally open terminal of the fourth switch and the output terminal of the comparator. The normally closed terminal of the third switch is connected to the second terminal of the DC-DC converter circuit, the normally closed terminal of the fourth switch, and the positive input terminal of the comparator. The second terminal of the second switch is connected to the common terminal of the fourth switch and the first terminal of the LDO circuit. The second terminal of the LDO circuit is connected to the output voltage (Vout), and the inverting input terminal of the comparator is connected to the reference voltage (VRFF_3V).

[0106] In the circuit described above, the first switch opens only when the voltage is greater than 3V, the second switch opens only when the voltage is less than or equal to 3V, the third switch is connected to the normally closed terminal when the voltage is high, and the fourth switch is connected to the normally closed terminal when the voltage is low. After comparing and determining the voltage, the final output voltage passes through an LDO. However, the LDO's step-down range is below 3V, so voltages greater than 3V will generate different duty cycles, returning to the initial voltage. A buck-type DC-DC converter is used. In continuous clock pulse (CCM mode), the relationship between the output voltage and the input voltage is vout / vin = duty, where duty is the duty cycle. The voltage gradually decreases to below 3V before passing through the LDO and outputting.

[0107] The aforementioned voltage regulator circuit, through a dual configuration of DC-DC-LDO and direct LDO paths, can adapt to a wider input voltage range. The voltage after DC-DC processing enters the LDO circuit, where a simple feedforward circuit is used for further ripple elimination, resulting in high stability without affecting the LDO main loop function, ensuring a clean and stable output voltage.

[0108] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0109] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principles described in this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. An LDO chip without external capacitors, characterized in that, The LDO chip includes an error amplifier, a buffer circuit, an overshoot / undershoot suppression circuit, a power transistor, a feedback circuit, and a feedforward circuit. The positive input terminal of the error amplifier is connected to the feedback terminal of the feedback circuit, the inverting input terminal of the error amplifier is connected to the first reference voltage, the output terminal of the error amplifier is connected to the input terminal of the buffer circuit, the output terminal of the buffer circuit is connected to the input terminal of the overshoot / undershoot suppression circuit, the output terminal of the feedforward circuit, and the gate of the power transistor, respectively, the source of the power transistor is connected to the input power supply and the input terminal of the feedforward circuit, respectively, and the drain of the power transistor is connected to the output terminal of the overshoot / undershoot suppression circuit, the input terminal of the feedback circuit, and the output terminal of the LDO chip, respectively. The buffer circuit includes a first push-pull transistor, a second push-pull transistor, a third push-pull transistor, a fourth push-pull transistor, a fifth push-pull transistor, a sixth push-pull transistor, a seventh push-pull transistor, an eighth push-pull transistor, a ninth push-pull transistor, and a tenth push-pull transistor. The gate of the second push-pull transistor and the gate of the sixth push-pull transistor are both input terminals of the buffer circuit, and the drain of the eighth push-pull transistor and the source of the ninth push-pull transistor are both output terminals of the buffer circuit. The gate of the first push-pull transistor is connected to a positive control voltage. The source of the first push-pull transistor is connected to the source of the seventh push-pull transistor, the drain of the fifth push-pull transistor, and the source of the eighth push-pull transistor. The drain of the first push-pull transistor is connected to the source of the second push-pull transistor and the gate of the fifth push-pull transistor. The drain of the second push-pull transistor is connected to the drain of the third push-pull transistor, the gate of the third push-pull transistor, and the gate of the fourth push-pull transistor. The source of the third push-pull transistor is connected to the source of the tenth push-pull transistor. The source of the fourth push-pull transistor and the drain of the ninth push-pull transistor are connected together. The drain of the tenth push-pull transistor is connected to the source of the sixth push-pull transistor and the gate of the ninth push-pull transistor. The gate of the tenth push-pull transistor is connected to a reverse control voltage. The drain of the fourth push-pull transistor is connected to the source of the fifth push-pull transistor, the drain of the eighth push-pull transistor, and the source of the ninth push-pull transistor. The drain of the sixth push-pull transistor is connected to the drain of the seventh push-pull transistor, the gate of the sixth push-pull transistor, and the gate of the eighth push-pull transistor.

2. The LDO chip according to claim 1, characterized in that, The feedforward circuit includes an operational amplifier, a summing amplifier, a boosting capacitor, and a boosting resistor. The first terminal of the boosting capacitor is the input terminal of the feedforward circuit, and the output terminal of the summing amplifier is the output terminal of the feedforward circuit. The first end of the enhancement resistor is connected to the second reference voltage, the second end of the enhancement resistor is connected to the second end of the enhancement capacitor and the positive input terminal of the operational amplifier, and the output terminal of the operational amplifier is connected to the inverting input terminal of the operational amplifier and the input terminal of the summing amplifier.

3. The LDO chip according to claim 2, characterized in that, The operational amplifier includes a first operational transistor, a second operational transistor, a third operational transistor, a fourth operational transistor, and a fifth operational transistor; The gate of the third operational transistor is the positive input terminal of the operational amplifier, the gate of the fourth operational transistor is the inverting input terminal of the operational amplifier, and the drain of the fourth operational transistor and the drain of the second operational transistor are both output terminals of the operational amplifier. The source of the first operational transistor is connected to the source of the second operational transistor. The gate of the first operational transistor is connected to the gate of the second operational transistor, the drain of the second operational transistor, and the drain of the third operational transistor. The source of the third operational transistor is connected to the source of the fourth operational transistor and the drain of the fifth operational transistor. The source of the fifth operational transistor is connected to the ground terminal. The gate of the fifth operational transistor is connected to a reverse control voltage. The first, second, third, fourth, and fifth operational transistors are all P-type MOS transistors.

4. The LDO chip according to claim 1, characterized in that, The overshoot and undershoot suppression circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, an initial transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first terminal of the first capacitor, the second terminal of the second capacitor, the first terminal of the third capacitor, and the second terminal of the fourth capacitor are all output terminals of the overshoot and undershoot suppression circuit, and the gate of the fourteenth transistor and the gate of the fifteenth transistor are both input terminals of the overshoot and undershoot suppression circuit. The second terminal of the first capacitor is connected to the source of the initial transistor and the first terminal of the first resistor, respectively. The drain of the initial transistor is connected to the drain of the thirteenth transistor. The gate of the initial transistor is connected to the gate of the sixth transistor, the drain of the fourteenth transistor, and the drain of the fifth transistor, respectively. The second terminal of the first resistor is connected to the source of the first transistor, the source of the thirteenth transistor, and the source of the sixth transistor, respectively. The drain of the first transistor is connected to the drain of the second transistor and the gate of the fifth transistor, respectively. The gate of the second transistor is connected to the gate of the fifth transistor, respectively. The source of the second transistor is connected to the drain of the third transistor, the gate of the third transistor, the gate of the fourth transistor, and the second terminal of the third capacitor, respectively. The source of the third transistor is connected to the source of the fourth transistor, the drain of the fourth transistor is connected to the source of the fifth transistor, and the drain of the fifth transistor is connected to the drain of the sixth transistor. The first terminal of the second capacitor is connected to the gate of the ninth transistor and the gate of the tenth transistor, respectively. The source of the tenth transistor is connected to the source of the ninth transistor. The drain of the tenth transistor is connected to the source of the eleventh transistor. The drain of the ninth transistor is connected to the gate of the ninth transistor and the source of the eighth transistor, respectively. The gate of the eighth transistor is connected to the gate of the eleventh transistor, the drain of the seventh transistor, and the drain of the eighth transistor, respectively. The drain of the tenth transistor is connected to the source of the eleventh transistor, respectively. The drain of the eleventh transistor is connected to the gate of the thirteenth transistor, the drain of the twelfth transistor, the gate of the twelfth transistor, and the drain of the fifteenth transistor, respectively. The source of the twelfth transistor is connected to the source of the fifteenth transistor, the source of the seventh transistor, and the first terminal of the second resistor, respectively. The first terminal of the second resistor is connected to the source of the thirteenth transistor and the first terminal of the fourth capacitor, respectively. The gate of the seventh transistor is connected to a positive control voltage, and the gate of the first transistor is connected to a reverse control voltage.

5. The LDO chip according to claim 4, characterized in that, The initial transistor, the first transistor, the sixth transistor, the fourteenth transistor, the eleventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all P-type MOS transistors; The second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, the twelfth transistor, the thirteenth transistor, and the fifteenth transistor are all N-type MOS transistors.

6. The LDO chip according to claim 1, characterized in that, The feedback circuit includes a first feedback resistor, a second feedback resistor, and a feedback capacitor; The first end of the first feedback resistor and the first end of the feedback capacitor are both input terminals of the feedback circuit. The second end of the first feedback resistor and the first end of the second feedback resistor are both feedback terminals of the feedback circuit. The second end of the second feedback resistor is connected to the second end of the feedback capacitor and the ground terminal, respectively.

7. The LDO chip according to claim 4, characterized in that, The error amplifier includes a first error transistor, a second error transistor, a third error transistor, a fourth error transistor, a fifth error transistor, a sixth error transistor, a seventh error transistor, an eighth error transistor, a ninth error transistor, a tenth error transistor, and an eleventh error transistor. The gate of the second error transistor is the positive input terminal of the error amplifier, the gate of the third error transistor is the inverting input terminal of the error amplifier, and the drains of the seventh error transistor and the ninth error transistor are both output terminals of the error amplifier. The gate of the first error transistor is connected to a positive control voltage. The source of the first error transistor is connected to the source of the tenth error transistor and the source of the eleventh error transistor. The drain of the first error transistor is connected to the source of the second error transistor and the source of the third error transistor. The drain of the second error transistor is connected to the drain of the fourth error transistor and the source of the sixth error transistor. The drain of the third error transistor is connected to the drain of the fifth error transistor and the source of the seventh error transistor. The source of the fourth transistor is connected to the source of the fifth transistor. The gates of the fourth and fifth error transistors are both connected to a first bias voltage, the gates of the sixth and seventh error transistors are both connected to a second bias voltage, the drain of the sixth error transistor is connected to the drain of the eighth error transistor, the gate of the tenth error transistor, and the gate of the eleventh error transistor, respectively, the gates of the eighth and ninth error transistors are both connected to a third bias voltage, the source of the eighth error transistor is connected to the drain of the tenth error transistor, and the source of the ninth error transistor is connected to the drain of the eleventh error transistor.

8. The LDO chip according to claim 7, characterized in that, The first error transistor, the second error transistor, the third error transistor, the eighth error transistor, the ninth error transistor, the tenth error transistor, and the eleventh error transistor are all N-type MOS transistors; The fourth error transistor, the fifth error transistor, the sixth error transistor, and the seventh error transistor are all P-type MOS transistors.

9. The LDO chip according to claim 1, characterized in that, The first push-pull transistor, the second push-pull transistor, the seventh push-pull transistor, the eighth push-pull transistor, and the ninth push-pull transistor are all N-type MOS transistors; The third push-pull transistor, the fourth push-pull transistor, the fifth push-pull transistor, the sixth push-pull transistor, and the tenth push-pull transistor are all P-type MOS transistors.

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