Radar signal processor FPGA program design method and device

Abstract

The invention relates to a radar signal processor FPGA (Field Programmable Gate Array) program design method and device. The device comprises an ADC (Analog to Digital Converter) module, an MATLAB (Matrix Laboratory) simulation program module and an FPGA program module, the ADC module is used for realizing analog-to-digital conversion of the intermediate frequency signal to be detected; the MATLAB simulation program module is used for realizing correlation filter coefficient configuration required by different bandwidth and frequency point requirements in a signal processing process; and the FPGA program module is used for realizing communication interface demand configuration, pulse signal demand configuration and related demand configuration in a digital signal processing process. According to the invention, the customization time and the customization cost of the customized radar signal processor can be effectively reduced; corresponding parameter configuration modification can be more flexibly carried out according to different requirements, the compatibility and interaction capability between different systems and equipment can be improved, and different models of radars of different manufacturers can be more simply matched.

Description

Technical Field

[0001] The present invention relates to the field of radar applications, and in particular to a radar signal processor FPGA program design method and device. Background Art

[0002] The continuous expansion of radar application fields has led to more diversified requirements for radar system functions and performance, and traditional customized radar system signal processors often find it difficult to meet different requirements. Traditional customized radar system signal processing functions are usually implemented by dedicated hardware, which usually requires a lot of time for customized design and consumes high development and maintenance costs. The extremely fast development speed of radar technology will also lead to the continuous updating and iteration of signal processing algorithms and technologies. Traditional hardware implementation methods are more difficult to meet rapidly changing needs, and the design and maintenance costs of customized components will also increase further. When radar systems are widely used in different application fields, interoperability and compatibility between radar equipment produced by different manufacturers is also an important issue. Therefore, how to solve this problem is currently a matter of consideration. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a radar signal processor FPGA programming method and device to solve the deficiencies of the prior art.

[0004] The object of the present invention is achieved by the following technical solutions: a radar signal processor FPGA program design method, the method comprising a communication interface configuration step, a pulse signal configuration step and a digital signal processing process configuration step by an FPGA program module; The digital signal processing process configuration step comprises: A1. The intermediate frequency signal to be processed input by the external receiver is converted into a digital signal through the ADC module. The relevant bandpass filter coefficients are configured according to the frequency requirements of the system working mode to complete the ADC process related coefficient configuration; A2. Perform digital down-conversion processing on the filtered digital signal, configure the relevant low-pass filter coefficient and local oscillator frequency generation according to the pulse width requirements of the system working mode, and complete the configuration of the relevant coefficients of the digital down-conversion process; A3. After completing the digital down-conversion, the generated baseband IQ data is pulse compressed, and the relevant matching filter coefficients are configured according to the pulse width requirements of the system working mode to complete the relevant coefficient configuration of the pulse compression process.

[0005] The communication interface configuration step comprises: Using universal communication interfaces and communication protocols, I / O interfaces are reserved in the FPGA program module. According to the actual communication interface and communication protocol requirements, the required communication interfaces are allocated and connected for use. The communication interface configuration is completed by modifying the allocated I / O interfaces through the FPGA program module.

[0006] The pulse signal configuration step comprises: Quantify the time delay and pulse width requirements of the excitation pulse signal into the FPGA program module for counter counting; According to different needs, modify the counter counting threshold in the FPGA program module to achieve the purpose of configuring the corresponding delay and pulse width parameters, and complete the pulse signal parameter configuration by modifying the corresponding calculator calculation in the FPGA program module.

[0007] The step A1 specifically includes: According to the sampling frequency, frequency point, pulse width and bandwidth configuration requirements, the required filter configuration parameters are obtained by simulation calculation in the MATLAB simulation program module; Input the parameters into the preset FIR IPcore in the FPGA program module to complete the ADC sampling filter parameter configuration; Based on the high-frequency modulated RF signal, the bandpass sampling theorem is used to sample the signal data, and the sampling filter parameter configuration is completed by modifying the bandwidth parameters of the frequency point in the MATLAB simulation program module.

[0008] The step A2 specifically includes: According to the output frequency and bandwidth configuration requirements, the NCO (numerically controlled oscillator) frequency required in the digital down-conversion process is configured in the FPGA program module, and the corresponding frequency parameters are calculated and input into the DDS (direct data synthesizer) IPcore to complete the NCO frequency configuration and generate a sine wave or cosine wave of the configured frequency as the local oscillator signal; The mixing of the sampled and filtered digital signal and the NCO signal is completed in the FPGA program module. In the MATLAB simulation program module, the parameter simulation of the low-pass filter required for filtering extraction is completed according to the frequency and bandwidth requirements, and the corresponding parameters are input into the FIR (digital filter) IPcore preset in the FPGA program module. The digital down-conversion filter configuration is completed by modifying the frequency and bandwidth parameters in the MATLAB simulation program module, and the NCO frequency configuration is completed by obtaining the corresponding NOC parameters through the NCO demand calculation.

[0009] The step A3 specifically includes: According to the output frequency and bandwidth configuration requirements, the MATLAB simulation calculation process of generating the required linear frequency modulation signal or nonlinear frequency modulation signal, down-converting the frequency and calculating the matching filter coefficients is performed in the MATLAB simulation program module; Obtain the matching filter coefficients required for the pulse compression process, modify the frequency point and bandwidth parameters in the MATLAB simulation program module by configuring, modify the generated linear frequency modulation signal or nonlinear frequency modulation signal, achieve the purpose of modifying the matching filter coefficients generated thereby, and complete the pulse compression parameter configuration.

[0010] A radar signal processor FPGA programming device, the device comprising an ADC module, a MATLAB simulation program module and an FPGA program module; The ADC module is used to realize the conversion of the intermediate frequency signal to be measured from analog to digital; The MATLAB simulation program module is used to realize the configuration of relevant filter coefficients required by different bandwidth and frequency requirements in the signal processing process; The FPGA program module is used to implement communication interface requirement configuration, pulse signal requirement configuration and related requirement configuration of digital signal processing process.

[0011] The communication interface configuration process includes: using a general communication interface and communication protocol, reserving an I / O interface in the FPGA program module, allocating and connecting the required communication interface according to the actual communication interface and communication protocol requirements, and completing the communication interface configuration by modifying the allocated I / O interface through the FPGA program module.

[0012] The pulse signal configuration process includes: quantifying the time delay and pulse width requirements of the excitation pulse signal into the FPGA program module for counter counting; modifying the counter counting threshold in the FPGA program module according to different requirements, so as to achieve the purpose of configuring the corresponding time delay and pulse width parameters, and completing the pulse signal parameter configuration by modifying the corresponding counter count in the FPGA program module.

[0013] The FPGA program module includes an ADC sampling filter parameter configuration unit, a down-conversion parameter configuration unit and a pulse compression parameter configuration unit; The ADC sampling filter parameter configuration unit is used to obtain the required filter configuration parameters by simulation calculation in the MATLAB simulation program module according to the sampling frequency, frequency point and bandwidth configuration requirements; input the parameters into the FIR IPcore preset in the FPGA program module to complete the ADC sampling filter parameter configuration; based on the high-frequency modulated radio frequency signal, the bandpass sampling theorem is selected to perform signal data sampling, and the sampling filter parameter configuration is completed by modifying the frequency point and bandwidth parameters in the MATLAB simulation program module; The down-conversion parameter configuration unit is used to configure the required NCO frequency in the digital down-conversion process in the FPGA program module according to the output frequency and bandwidth configuration requirements, and calculate the corresponding frequency parameters and input them into the DDS IPcore to complete the NCO frequency configuration; and complete the mixing of the digital signal after sampling and filtering and the NCO signal in the FPGA program module, complete the parameter simulation of the low-pass filter required for filtering extraction in the MATLAB simulation program module according to the frequency and bandwidth requirements, input the corresponding parameters into the FIR IPcore preset by the FPGA program module, complete the digital down-conversion filter configuration by modifying the frequency and bandwidth parameters in the MATLAB simulation program module, and complete the NCO frequency configuration by calculating the corresponding NOC parameters according to the NCO requirements; The pulse compression parameter configuration unit is used to perform a MATLAB simulation calculation process of generating the required linear frequency modulation signal, down-converting the frequency, and calculating and generating the matching filter coefficient in the MATLAB simulation program module according to the output frequency and bandwidth configuration requirements; obtain the matching filter coefficient required for the pulse compression process, modify the frequency and bandwidth parameters in the MATLAB simulation program module by configuring, modifying the generated linear frequency modulation signal or nonlinear frequency modulation signal, so as to achieve the purpose of modifying the matching filter coefficient generated thereby, and complete the pulse compression parameter configuration.

[0014] The present invention has the following advantages: a radar signal processor FPGA programming method and device, which can effectively reduce the customization time and customization cost of a customized radar signal processor; can more flexibly perform corresponding parameter configuration modifications according to different needs, and can more quickly complete related process operations when hardware and software technology updates and upgrades are required; can improve the compatibility and interaction capabilities between different systems and devices, and can more easily cooperate with different models of radars from different manufacturers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided below in conjunction with the drawings is not intended to limit the scope of protection of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application. The present invention is further described below in conjunction with the drawings.

[0017] like Figure 1 As shown, the present invention specifically relates to a radar signal processor FPGA (programmable logic device) programming method, which is mainly composed of an ADC module, a MATLAB simulation program module and an FPGA program module. The ADC module realizes the conversion of the intermediate frequency signal to be measured from analog to digital. The MATLAB simulation program module realizes the configuration of the relevant filter coefficients required for different bandwidths and frequency points in the signal processing process. The FPGA program module realizes the configuration of communication interface requirements, pulse signal requirements and related requirements of the digital signal processing process; the configuration modification in the data processing process is mainly carried out by performing corresponding simulation calculations in the MATLAB simulation program module to obtain the corresponding filter coefficients. The filter coefficients are input into the FPGA program module to complete the configuration modification. For the standardized configuration of the communication interface, a design method of reserving an I / O interface in the FPGA program module is adopted to achieve the configuration of different communication interface requirements; it specifically includes the following contents: 1. Communication interface configuration: Use common communication interfaces and communication protocols, reserve I / O interfaces in the FPGA program module, and allocate and connect the required communication interfaces according to the actual communication interface and communication protocol requirements. Modify and allocate I / O interfaces through the FPGA program module to complete the communication interface configuration.

[0018] 2. Pulse signal parameter configuration: Quantify the specific requirements of the excitation pulse signal, such as the delay and pulse width, into the FPGA program module for counter counting. According to different requirements, modify the counter counting threshold in the FPGA program module to achieve the purpose of configuring the corresponding delay, pulse width and other parameters. The pulse signal parameter configuration is completed by modifying the corresponding counter count in the FPGA program module.

[0019] 3. Related requirements and configuration of digital signal processing process: A1. The intermediate frequency signal to be processed input by the external receiver is converted into a digital signal through the ADC (Analog-to-Digital Converter, i.e. A / D Converter). The relevant bandpass filter coefficients are configured according to the frequency requirements of the system working mode to complete the ADC process related coefficient configuration; Furthermore, according to the configuration requirements such as sampling frequency, frequency point, bandwidth, etc., in the MATLAB simulation program module, according to the specific requirements (frequency point, pulse width, bandwidth, etc.), simulation calculation is performed to obtain the required filter configuration parameters, and the parameters are input into the preset FIR IPcore (IPcore: a reusable module in the form of logic unit and chip design provided by FPGA development software, a circuit function module with pre-designed modifiable parameters) in the FPGA program module to complete the ADC sampling filter parameter configuration. Based on high-frequency modulated RF signals, the bandpass sampling theorem is selected for signal data sampling, which can avoid the related problems caused by sampling using the Nyquist sampling theorem to the greatest extent and reduce the impact of related problems. The sampling filter parameter configuration is completed by modifying the frequency point, bandwidth and other parameters in the MATLAB simulation program module.

[0020] A2. The filtered digital signal is processed by digital down conversion (DDC). The relevant low-pass filter coefficients and local oscillator frequency (NCO) are configured according to the pulse width requirements of the system working mode to complete the configuration of the relevant coefficients of the digital down conversion process. Furthermore, according to the configuration requirements such as output frequency and bandwidth, the NCO frequency required in the digital down-conversion process is configured in the FPGA program module. This process is based on the frequency control word calculation formula required by the DDS IPcore (N is the number of bits of the control word set, f out is the desired output NCO frequency, f clk The corresponding frequency parameters are calculated from the input clock used by the current IPcore and input into the DDS (direct data frequency synthesizer) IPcore to complete the NCO frequency configuration. The mixing of the sampled and filtered digital signal and the NCO signal is completed in the FPGA program module. In the MATLAB simulation program module, according to the requirements of frequency and bandwidth, the parameter simulation of the low-pass filter required for filter extraction is completed, and the corresponding parameters are input into the FIR IPcore preset by the FPGA program module. The digital down-conversion filter configuration is completed by modifying the frequency, pulse width, bandwidth and other parameters in the MATLAB simulation program module, and the corresponding NCO parameters are calculated through the NCO requirement calculation formula to complete the NCO frequency configuration.

[0021] A3. After completing the digital down-conversion, the generated baseband IQ data is pulse compressed, and the relevant matched filter coefficients are configured according to the specific frequency requirements to complete the relevant coefficient configuration of the pulse compression process.

[0022] According to the configuration requirements of output frequency, bandwidth, etc., a series of MATLAB simulation calculation processes such as the generation of the required linear frequency modulation signal, down-conversion (mixing, filtering extraction), calculation and generation of matched filter coefficients are performed in the MATLAB simulation program module to obtain the matched filter coefficients required for the pulse compression process. By configuring and modifying the parameters such as frequency and bandwidth in the MATLAB simulation program module, the generated linear frequency modulation signal is modified to achieve the purpose of modifying the generated matched filter coefficients and complete the pulse compression parameter configuration.

[0023] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used for various other combinations, modifications and improvements, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not deviate from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A radar signal processor FPGA programming method, characterized in that: The method comprises a communication interface configuration step, a pulse signal configuration step and a digital signal processing process configuration step performed by an FPGA program module; The digital signal processing process configuration step comprises: A1. The intermediate frequency signal to be processed input by the external receiver is converted into a digital signal through the ADC module. The relevant bandpass filter coefficients are configured according to the frequency requirements of the system working mode to complete the ADC process related coefficient configuration; A2. Perform digital down-conversion processing on the filtered digital signal, configure the relevant low-pass filter coefficient and local oscillator frequency generation according to the pulse width requirements of the system working mode, and complete the configuration of the relevant coefficients of the digital down-conversion process; A3. After completing the digital down-conversion, the generated baseband IQ data is pulse compressed, and the relevant matching filter coefficients are configured according to the pulse width requirements of the system working mode to complete the relevant coefficient configuration of the pulse compression process.

2. A radar signal processor FPGA programming method according to claim 1, characterized in that: The communication interface configuration step comprises: Using universal communication interfaces and communication protocols, I / O interfaces are reserved in the FPGA program module. According to the actual communication interface and communication protocol requirements, the required communication interfaces are allocated and connected for use. The communication interface configuration is completed by modifying the allocated I / O interfaces through the FPGA program module.

3. A radar signal processor FPGA programming method according to claim 1, characterized in that: The pulse signal configuration step comprises: Quantify the time delay and pulse width requirements of the excitation pulse signal into the FPGA program module for counter counting; According to different needs, modify the counter counting threshold in the FPGA program module to achieve the purpose of configuring the corresponding delay and pulse width parameters. The pulse signal parameter configuration is completed by modifying the corresponding counter count in the FPGA program module.

4. The radar signal processor FPGA programming method according to claim 1, characterized in that: The step A1 specifically includes: According to the sampling frequency, frequency point and bandwidth configuration requirements, the required filter configuration parameters are obtained by simulation calculation in the MATLAB simulation program module; Input the parameters into the preset FIR IPcore in the FPGA program module to complete the ADC sampling filter parameter configuration; Based on the high-frequency modulated RF signal, the bandpass sampling theorem is used to sample the signal data, and the sampling filter parameter configuration is completed by modifying the bandwidth parameters of the frequency point in the MATLAB simulation program module.

5. The radar signal processor FPGA programming method according to claim 1, characterized in that: The step A2 specifically includes: According to the output frequency and bandwidth configuration requirements, the NCO required in the digital down-conversion process is configured in the FPGA program module, and the corresponding frequency parameters are calculated and input into the DDSIPcore to complete the NCO frequency configuration and generate a sine wave or cosine wave of the configured frequency as the local oscillator signal; The mixing of the sampled and filtered digital signal and the NCO signal is completed in the FPGA program module. In the MATLAB simulation program module, the parameter simulation of the low-pass filter required for filtering extraction is completed according to the frequency and bandwidth requirements, and the corresponding parameters are input into the FIR IPcore preset in the FPGA program module. The digital down-conversion filter configuration is completed by modifying the frequency and bandwidth parameters in the MATLAB simulation program module.

6. A radar signal processor FPGA programming method according to claim 1, characterized in that: The step A3 specifically includes: According to the output frequency and bandwidth configuration requirements, the MATLAB simulation calculation process of generating the required linear frequency modulation signal or nonlinear frequency modulation signal, down-converting the frequency and calculating the matching filter coefficients is performed in the MATLAB simulation program module; Obtain the matching filter coefficients required for the pulse compression process, modify the frequency point and bandwidth parameters in the MATLAB simulation program module by configuring, modify the generated linear frequency modulation signal or nonlinear frequency modulation signal, achieve the purpose of modifying the matching filter coefficients generated thereby, and complete the pulse compression parameter configuration.

7. A radar signal processor FPGA programming device, characterized in that: The device comprises an ADC module, a MATLAB simulation program module and an FPGA program module; The ADC module is used to realize the conversion of the intermediate frequency signal to be measured from analog to digital; The MATLAB simulation program module is used to realize the configuration of relevant filter coefficients required by different bandwidth and frequency requirements in the signal processing process; The FPGA program module is used to implement communication interface requirement configuration, pulse signal requirement configuration and related requirement configuration of digital signal processing process.

8. A radar signal processor FPGA programming device according to claim 7, characterized in that: The communication interface configuration process includes: using a general communication interface and communication protocol, reserving an I / O interface in the FPGA program module, allocating and connecting the required communication interface according to the actual communication interface and communication protocol requirements, and completing the communication interface configuration by modifying the allocated I / O interface through the FPGA program module.

9. A radar signal processor FPGA programming device according to claim 7, characterized in that: The pulse signal configuration process includes: quantifying the time delay and pulse width requirements of the excitation pulse signal into the FPGA program module for counter counting; modifying the counter counting threshold in the FPGA program module according to different requirements, so as to achieve the purpose of configuring the corresponding time delay and pulse width parameters, and completing the pulse signal parameter configuration by modifying the corresponding counter count in the FPGA program module.

10. The radar signal processor FPGA programming device according to claim 7, characterized in that: The FPGA program module includes an ADC sampling filter parameter configuration unit, a down-conversion parameter configuration unit and a pulse compression parameter configuration unit; The ADC sampling filter parameter configuration unit is used to obtain the required filter configuration parameters by simulation calculation in the MATLAB simulation program module according to the sampling frequency, frequency point and bandwidth configuration requirements; the parameters are input into the FIR IPcore preset in the FPGA program module to complete the ADC sampling filter parameter configuration; Based on high-frequency modulated RF signals, the bandpass sampling theorem is used to sample signal data, and the sampling filter parameter configuration is completed by modifying the bandwidth parameters of the frequency points in the MATLAB simulation program module. The down-conversion parameter configuration unit is used to configure the required NCO frequency in the digital down-conversion process in the FPGA program module according to the output frequency and bandwidth configuration requirements, and calculate the corresponding frequency parameters and input them into the DDS IPcore to complete the NCO frequency configuration; and complete the mixing of the digital signal after sampling and filtering and the NCO signal in the FPGA program module, complete the parameter simulation of the low-pass filter required for filtering extraction in the MATLAB simulation program module according to the frequency and bandwidth requirements, input the corresponding parameters into the FIR IPcore preset by the FPGA program module, complete the digital down-conversion filter configuration by modifying the frequency and bandwidth parameters in the MATLAB simulation program module, and complete the NCO frequency configuration by calculating the corresponding NOC parameters according to the NCO requirements; The pulse compression parameter configuration unit is used to perform a MATLAB simulation calculation process of generating and down-converting the required linear frequency modulation signal and calculating and generating the matched filter coefficients in the MATLAB simulation program module according to the output frequency and bandwidth configuration requirements; Obtain the matching filter coefficients required for the pulse compression process, modify the frequency point and bandwidth parameters in the MATLAB simulation program module by configuring, modify the generated linear frequency modulation signal or nonlinear frequency modulation signal, achieve the purpose of modifying the matching filter coefficients generated thereby, and complete the pulse compression parameter configuration.

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