Instruction conversion method across chip platforms

Abstract

The embodiment of the present application provides a cross-chip platform instruction conversion method, the method comprising: collecting instruction set information of a source chip platform and a target chip platform, establishing an instruction feature analysis model, and using a kernel function to calculate a semantic similarity matrix between instructions in a feature vector space; training a multi-layer graph attention neural network based on the semantic similarity matrix, mapping feature vectors of source platform instructions and target platform instructions to a shared embedding space, and applying a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; loading the instruction equivalent conversion rules in an instruction conversion engine, decoding and analyzing the input source platform instructions, and outputting a converted target platform instruction sequence to an instruction execution unit of the target chip platform; the present application can optimize the resource overhead of the conversion process and improve the overall efficiency of the system while ensuring the correctness of the conversion.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a method for converting instructions across chip platforms. Background Art

[0002] Instruction conversion across chip platforms is an important research topic in computer architecture, but existing instruction conversion methods have problems such as low efficiency and poor compatibility. Traditional conversion schemes mainly rely on static rule mapping, which is difficult to handle complex instruction semantic relationships and lacks consideration for optimizing instruction execution efficiency.

[0003] The current instruction conversion system faces many challenges when processing instruction sets of different architectures. First, the understanding of instruction semantics is not deep enough, and simple feature matching cannot accurately capture the equivalent relationship between instructions, making it difficult to ensure the correctness of the conversion results. Secondly, the construction process of the conversion rules is relatively mechanical and lacks adaptive learning capabilities, making it difficult to cope with the expansion requirements of new instruction sets. In addition, the performance overhead of the conversion process is large, especially when processing complex instruction sequences, which often leads to significant performance losses.

[0004] Cache management is also a key factor affecting conversion efficiency. Existing systems generally adopt simple cache replacement strategies, which cannot effectively utilize the local characteristics of instructions. Frequent cache failures will lead to a large number of repeated conversion calculations. At the same time, the lack of in-depth analysis of instruction execution characteristics makes it difficult to implement targeted optimization strategies.

[0005] Therefore, a smarter and more efficient instruction conversion scheme is needed. Summary of the invention

[0006] In response to the problems in the prior art, the present application provides a cross-chip platform instruction conversion method that can optimize the resource overhead of the conversion process and improve the overall efficiency of the system while ensuring the correctness of the conversion.

[0007] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0008] In a first aspect, the present application provides a cross-chip platform instruction conversion method, comprising:

[0009] Collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions;

[0010] Based on the semantic similarity matrix, a multi-layer graph attention neural network is trained to map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, a spectral clustering algorithm is used to construct an instruction mapping relationship graph, and a reinforcement learning method is used to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules;

[0011] The instruction equivalent conversion rules are loaded into the instruction conversion engine, the input source platform instructions are decoded and analyzed, the complex instructions are split into basic instruction sequences using a recursive neural network model, the basic instruction sequences are re-encoded into target platform instructions according to the conversion rules, a multi-level cache structure is established for the re-encoded instructions, the conversion results of hot instructions are stored in the first-level cache, the mapping relationship of the basic instruction blocks is stored in the second-level cache, the cache content is dynamically adjusted based on the historical access data training prediction model, and the converted target platform instruction sequence is output to the instruction execution unit of the target chip platform.

[0012] Furthermore, the instruction set information of the source chip platform and the target chip platform is collected, an instruction feature analysis model is established, the instruction set information is formatted to extract instruction format, operation code and operand features, and a multi-dimensional feature vector space of the instruction set is constructed, including:

[0013] Establish a chip platform instruction set scanner to extract instruction set data from the instruction manuals of the source chip and the target chip, use a text parser to perform structured analysis on the instruction manual to generate an instruction description file, use a feature extractor to identify the opcode field and operand field position of the instruction from the instruction description file, and parse each instruction into a standardized intermediate representation format;

[0014] The word embedding model is used to calculate the semantic features of the standardized instruction representation, and the instruction structural features are extracted through a convolutional neural network. The semantic features and structural features are concatenated to construct a multi-dimensional feature vector. The principal component analysis method is used to reduce the dimension of the feature vector to generate the instruction feature vector space.

[0015] Furthermore, the using a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions includes:

[0016] In the feature vector space, a Gaussian kernel function is selected as a similarity measurement tool, the feature vector of the instruction pair to be compared is input, the feature vector is mapped to a high-dimensional Hilbert space to calculate the vector inner product, and the bandwidth parameter of the kernel function is determined by the kernel function parameter adaptive adjustment algorithm;

[0017] Based on the calculation results of the kernel function, the similarity score of each pair of instructions in the instruction set is calculated, and an N×N dimensional similarity score matrix is ​​constructed. The similarity matrix is ​​normalized so that the matrix element values ​​are in the interval [0,1], and the sparse matrix storage method is used to compress the similarity matrix data.

[0018] Furthermore, the multi-layer graph attention neural network is trained based on the semantic similarity matrix, the feature vectors of the source platform instructions and the target platform instructions are mapped to a shared embedding space, and a spectral clustering algorithm is used to construct an instruction mapping relationship graph, including:

[0019] Construct a three-layer graph attention neural network structure, input the semantic similarity matrix into the network as the adjacency matrix of the graph, calculate the attention weight coefficient and node representation vector of each attention layer, update the network parameters through the back propagation algorithm until the network converges, and apply the trained network to the mapping conversion of the instruction feature vectors of the source platform and the target platform;

[0020] A similarity matrix is ​​constructed for the mapped feature vector, and the Laplace matrix of the feature vector is calculated using the spectral clustering algorithm. The Laplace matrix is ​​decomposed by eigenvalue to obtain the feature vector, and the feature vector is grouped based on the K-means clustering algorithm to obtain the instruction mapping relationship graph.

[0021] Furthermore, the application of the reinforcement learning method to iteratively optimize the mapping relationship graph to obtain the instruction equivalent conversion rule includes:

[0022] A deep Q-learning network model is established, and the mapping relationship graph is used as the state space. The optimization action set is defined, including node merging, edge weight adjustment, and path reconstruction. The ε-greedy strategy is used to select the optimization action, and the Q network is trained based on the experience replay mechanism to update the strategy parameters.

[0023] The trained Q network is used to optimize the action sequence of the mapping relationship graph, and the optimized graph is converted into a set of instruction conversion rules. A unique identifier and priority attribute are assigned to each rule in the rule set, and the rules are stored as a lookup table structure in the form of key-value pairs.

[0024] Furthermore, the instruction equivalent conversion rules are loaded in the instruction conversion engine, the input source platform instructions are decoded and analyzed, the complex instructions are split into basic instruction sequences using a recursive neural network model, and the basic instruction sequences are re-encoded into target platform instructions according to the conversion rules, including:

[0025] Load the instruction equivalent conversion rules into the rule library of the instruction conversion engine, build an instruction parser to read the binary code stream of the source platform instruction, extract the operation code segment and operand segment of the instruction according to the instruction format template, and use the recursive neural network model to analyze the grammatical structure of the instruction to build a syntax tree;

[0026] The parsed syntax tree is traversed to decompose complex instructions into basic instruction sequences. The target platform conversion rules corresponding to each basic instruction are searched in the rule base. The basic instructions are reassembled according to the instruction format specifications of the target platform to generate a binary instruction code stream for the target platform.

[0027] Furthermore, the re-encoded instructions are provided with a multi-level cache structure, the conversion results of hot instructions are stored in the first-level cache, the mapping relationship of basic instruction blocks is stored in the second-level cache, the cache content is dynamically adjusted based on the historical access data training prediction model, and the converted target platform instruction sequence is output to the instruction execution unit of the target chip platform, including:

[0028] Create a multi-level cache system including the first-level cache and the second-level cache. Establish a hash table structure based on the LRU replacement strategy in the first-level cache to store the conversion results of hot instructions. Build a red-black tree structure in the second-level cache to store the mapping data of basic instruction blocks. Analyze the cache access sequence based on the long short-term memory network model to generate an access prediction model.

[0029] According to the output results of the prediction model, the contents of the first-level cache and the second-level cache are updated, the re-encoded target platform instructions are verified and calculated, the execution dependency graph of the instruction sequence is established, and the converted instruction sequence is transmitted to the instruction execution unit of the target chip platform through the buffer queue.

[0030] In a second aspect, the present application provides a cross-chip platform instruction conversion device, comprising:

[0031] A similarity matrix construction module is used to collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions;

[0032] A conversion rule determination module is used to train a multi-layer graph attention neural network based on the semantic similarity matrix, map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, use a spectral clustering algorithm to construct an instruction mapping relationship graph, and use a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules;

[0033] An instruction conversion module is used to load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, use a recursive neural network model to split complex instructions into basic instruction sequences, re-encode the basic instruction sequences into target platform instructions according to the conversion rules, establish a multi-level cache structure for the re-encoded instructions, store the conversion results of hot instructions in the first-level cache, store the mapping relationship of the basic instruction blocks in the second-level cache, dynamically adjust the cache content based on the historical access data training prediction model, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform.

[0034] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the cross-chip platform instruction conversion method when executing the program.

[0035] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the cross-chip platform instruction conversion method.

[0036] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which implements the steps of the cross-chip platform instruction conversion method when executed by a processor.

[0037] It can be seen from the above technical scheme that the present application provides a cross-chip platform instruction conversion method, which establishes an instruction feature analysis model by collecting instruction set information of the source chip platform and the target chip platform, and uses a kernel function to calculate the semantic similarity matrix between instructions in the feature vector space; a multi-layer graph attention neural network is trained based on the semantic similarity matrix, and the feature vectors of the source platform instructions and the target platform instructions are mapped to a shared embedding space, and a reinforcement learning method is applied to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; the instruction equivalent conversion rules are loaded in the instruction conversion engine, the input source platform instructions are decoded and analyzed, and the converted target platform instruction sequence is output to the instruction execution unit of the target chip platform, thereby optimizing the resource overhead of the conversion process and improving the overall efficiency of the system while ensuring the correctness of the conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 This is one of the flow charts of the cross-chip platform instruction conversion method in the embodiment of the present application;

[0040] Figure 2 This is a second flow chart of the cross-chip platform instruction conversion method in the embodiment of the present application;

[0041] Figure 3 The third flowchart of the cross-chip platform instruction conversion method in the embodiment of the present application;

[0042] Figure 4 This is a fourth flow chart of the cross-chip platform instruction conversion method in the embodiment of the present application;

[0043] Figure 5 This is a fifth flow chart of the cross-chip platform instruction conversion method in the embodiment of the present application;

[0044] Figure 6 This is a sixth flow chart of the cross-chip platform instruction conversion method in the embodiment of the present application;

[0045] Figure 7 FIG7 is a flowchart of a method for converting instructions across chip platforms in an embodiment of the present application;

[0046] Figure 8 It is a structural diagram of a cross-chip platform instruction conversion device in an embodiment of the present application;

[0047] Fig. 9 It is a schematic diagram of the structure of an electronic device in an embodiment of the present application.

[0048] Reference numerals:

[0049] Electronic device 9600, central processing unit 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0052] In view of the problems existing in the prior art, the present application provides a cross-chip platform instruction conversion method, which establishes an instruction feature analysis model by collecting instruction set information of the source chip platform and the target chip platform, and uses a kernel function to calculate the semantic similarity matrix between instructions in the feature vector space; a multi-layer graph attention neural network is trained based on the semantic similarity matrix, and the feature vectors of the source platform instructions and the target platform instructions are mapped to a shared embedding space, and a reinforcement learning method is used to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; the instruction equivalent conversion rules are loaded in the instruction conversion engine, the input source platform instructions are decoded and analyzed, and the converted target platform instruction sequence is output to the instruction execution unit of the target chip platform, thereby optimizing the resource overhead of the conversion process and improving the overall efficiency of the system while ensuring the correctness of the conversion.

[0053] In order to optimize the resource overhead of the conversion process and improve the overall efficiency of the system on the basis of ensuring the correctness of the conversion, the present application provides an embodiment of an instruction conversion method across chip platforms, see Figure 1 The cross-chip platform instruction conversion method specifically includes the following contents:

[0054] Step S101: Collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions;

[0055] Optionally, this embodiment provides a specific implementation of instruction feature analysis in a cross-chip platform instruction conversion method. First, an instruction set acquisition system is constructed, which includes two core modules: a document parser and a feature extractor. The document parser extracts instruction description information from the instruction manuals of the source chip platform and the target chip platform through predefined grammar rules and semantic templates. During the parsing process, the system maintains a feature tag table for identifying key instruction attribute tags, including instruction format identifiers, opcode fields, operand types, etc. For unstructured text descriptions, natural language processing technology is used to extract implicit instruction feature information.

[0056] The feature analysis model uses a deep neural network structure, and through multi-level feature extraction and representation learning, it uniformly maps the explicit and implicit features of instructions to the feature vector space. The input layer of the network receives the original description text and structured attributes of the instruction. The middle layer contains multiple feature extraction modules, each of which is responsible for extracting feature representations of a specific dimension. Among them, the opcode features are extracted through the convolution layer, the operand features are processed through the recurrent neural network, and the instruction format features are enhanced through the attention mechanism. Finally, the features of each dimension are fused through the fully connected layer to generate a unified feature vector representation.

[0057] In the process of constructing the feature vector space, this embodiment designs an adaptive feature organization scheme. First, the extracted features are normalized to eliminate the scale differences of features of different dimensions. Then, the weight coefficients of the features of each dimension are determined by feature importance analysis, and a weighted feature space is established. In order to improve the expressive power of the feature space, a nonlinear transformation layer is introduced to map the original features to a high-dimensional space. At the same time, the complexity of the feature space is controlled by regularization constraints to avoid overfitting problems.

[0058] The semantic similarity calculation adopts an improved kernel function method. In the feature vector space, the radial basis kernel function is selected as the basic measurement tool, and the feature vector is mapped to the high-dimensional Hilbert space through the kernel function for similarity calculation. In order to improve the calculation efficiency, a block-based parallel computing strategy is designed to decompose the calculation task of the large-scale similarity matrix into multiple subtasks for simultaneous processing. At the same time, a dynamic optimization mechanism of the kernel function parameters is implemented, and the bandwidth parameters of the kernel function are adaptively adjusted according to the characteristics of the instruction set.

[0059] In a practical application scenario, the solution successfully completed the task of instruction feature analysis between the X86 architecture and the ARM architecture. The system can accurately identify and represent the instruction features of the two architectures, providing a reliable data basis for subsequent instruction mapping. When processing complex instruction sequences, the feature analysis model shows good robustness and generalization ability.

[0060] The technical solution of this embodiment solves the problems of incomplete feature extraction and low efficiency of similarity calculation in traditional instruction feature analysis. Through the organic combination of deep learning and kernel methods, automatic extraction of instruction features and efficient similarity calculation are realized. The system has good scalability and can adapt to the feature analysis requirements of different instruction set architectures, providing strong support for cross-platform instruction conversion.

[0061] In engineering practice, the implementation of this solution has significantly improved the intelligence level and processing efficiency of instruction feature analysis. Through continuous optimization and improvement, the stability and reliability of the system have been continuously improved, and a complete set of instruction feature analysis solutions has been gradually formed. The successful implementation of this solution provides an important technical foundation for subsequent instruction conversion and optimization.

[0062] Step S102: training a multi-layer graph attention neural network based on the semantic similarity matrix, mapping feature vectors of source platform instructions and target platform instructions to a shared embedding space, using a spectral clustering algorithm to construct an instruction mapping relationship graph, and applying a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules;

[0063] Optionally, this embodiment constructs a multi-layer graph attention neural network based on the semantic similarity matrix to achieve efficient mapping of the instruction features of the source platform and the target platform. The network structure includes a feature encoding layer, a multi-head attention layer, and a feature fusion layer. The feature encoding layer receives the semantic similarity matrix as input and converts the matrix into a graph structure representation, where the nodes represent the instruction feature vectors and the edge weights correspond to the similarity scores between the instructions. The multi-head attention layer adaptively aggregates neighborhood information by calculating the attention scores between nodes to enhance the discriminability of the feature representation. The feature fusion layer performs a weighted combination of the outputs of multiple attention heads to generate the final node representation.

[0064] During the training process, an end-to-end approach is used to optimize network parameters. First, a training sample set is constructed, which contains known equivalent instruction pairs as supervisory information. Then, a loss function is designed, taking into account both node classification loss and feature reconstruction loss, and the network weights are updated through the back-propagation algorithm. In order to improve the generalization ability of the model, a dropout mechanism and a residual connection structure are introduced to effectively prevent overfitting. After training, the network is able to map the instruction feature vectors of the source and target platforms to the same shared embedding space.

[0065] In the shared embedding space, this embodiment uses a spectral clustering algorithm to construct an instruction mapping relationship map. First, the similarity matrix of the mapped feature vector is calculated to construct a Laplace matrix. The eigenvectors of the Laplace matrix are obtained by eigenvalue decomposition, and the eigenvectors with significant discriminant information are selected to construct a low-dimensional representation. Then, the improved K-means algorithm is used to cluster the feature vectors to form the initial instruction mapping relationship. In order to improve the clustering quality, density constraints and balance constraints are introduced to ensure the rationality of the clustering results.

[0066] The optimization of the mapping relationship graph adopts the deep reinforcement learning method. Construct a policy network and a value network, where the policy network is responsible for generating optimization actions and the value network evaluates the state value. Define the action space including operations such as node merging, edge weight adjustment, and path reconstruction. The reward function comprehensively considers the accuracy of instruction mapping, conversion efficiency, and resource overhead. By interacting with the environment, the agent continuously accumulates experience and updates strategies, gradually optimizing the structure of the mapping relationship graph.

[0067] During the optimization process, the experience replay mechanism is used to improve learning efficiency. An experience pool is maintained to store historical interaction data, and a batch of experiences are randomly sampled for learning each time training. At the same time, a priority sampling strategy is implemented to give priority to experiences with larger time series difference errors for training. This method can accelerate strategy convergence and improve optimization results.

[0068] The technical solution of this embodiment solves the problems of poor adaptability and low optimization efficiency of traditional instruction mapping methods. Intelligent mapping of instruction features is achieved through the graph attention network, and the reinforcement learning method ensures the continuous optimization of the mapping relationship. In practical applications, this solution can effectively handle complex instruction mapping scenarios and provide reliable rule support for subsequent instruction conversion. The system shows good scalability and robustness, and can adapt to instruction conversion needs of different scales and types.

[0069] Step S103: Load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, use a recursive neural network model to split complex instructions into basic instruction sequences, re-encode the basic instruction sequences into target platform instructions according to the conversion rules, establish a multi-level cache structure for the re-encoded instructions, store the conversion results of hot instructions in the first-level cache, store the mapping relationship of the basic instruction blocks in the second-level cache, dynamically adjust the cache content based on the historical access data training prediction model, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform.

[0070] Optionally, this embodiment provides an efficient instruction conversion execution solution. First, a rule loader is built in the instruction conversion engine to parse the equivalent conversion rules generated in the above steps into an internal representation and establish a fast index structure. The rule loader adopts an incremental update mechanism to support dynamic updating of the rule set during the operation of the conversion engine, ensuring that the system can adapt to new conversion requirements in a timely manner.

[0071] The decoding and analysis module adopts a multi-stage pipeline architecture, including three stages: instruction acquisition, format parsing, and semantic analysis. In the instruction acquisition stage, the instruction pre-reading and buffering mechanism is implemented to reduce waiting delays. The format parsing stage uses an adaptive decoding algorithm that can handle instructions of different lengths and formats. The semantic analysis stage extracts key information such as the instruction operation type and data dependency.

[0072] The improved recursive neural network model is used to split complex instructions. The network structure consists of two parts: the encoder and the decoder. The encoder converts the input instructions into a hidden state sequence, and the decoder generates a basic instruction sequence based on the hidden state. In order to improve the accuracy of the splitting, the attention mechanism is introduced into the network so that the model can focus on the key components of the instructions. At the same time, the beam search strategy is implemented to retain multiple candidate solutions during the decoding process and select the optimal splitting result.

[0073] The recoding process performs mapping conversion based on the conversion rule base. First, the basic instruction sequence is matched with the pattern in the rule base to find the best conversion rule. Then, the instruction sequence of the target platform is generated according to the conversion template defined by the rule. During the conversion process, the register allocation table and memory mapping table are maintained to ensure the correctness of data access. For instructions that cannot be directly mapped, the system will generate the necessary auxiliary instruction sequence to ensure functional equivalence.

[0074] The design of the multi-level cache structure fully considers the local characteristics of instruction conversion. The first-level cache adopts a fully associative structure and uses an LRU replacement strategy to manage the conversion results of hot instructions. The second-level cache adopts a set-associative structure to store the mapping relationship of commonly used basic instruction blocks. A collaborative working mechanism is implemented between the two levels of cache to optimize cache efficiency through prefetching and replacement strategies.

[0075] The cache prediction model is implemented based on deep learning methods. The model input includes instruction sequence features and historical access patterns, and the output predicts the instructions that may be accessed at the next moment. The training data is collected from the system operation log, which contains instruction access sequence and timestamp information. Through online learning, the model can continuously adapt to the dynamic behavior characteristics of the program. The prediction results are used to guide the pre-fetching and replacement of cache content to improve the cache hit rate.

[0076] Finally, the conversion engine normalizes the converted instruction sequence to ensure that it meets the instruction format requirements of the target platform. Instruction pipeline optimization is implemented in the output stage to reduce pipeline hazards by adjusting the instruction sequence. At the same time, an exception handling mechanism is provided to detect and handle errors in the conversion process in a timely manner.

[0077] The technical solution of this embodiment solves the efficiency and reliability problems in the instruction conversion process. Through the combination of multi-level cache and prediction model, the conversion performance is significantly improved. The system shows excellent stability and adaptability in practical applications and can meet the instruction conversion needs in different scenarios.

[0078] From the above description, it can be seen that the cross-chip platform instruction conversion method provided in the embodiment of the present application can establish an instruction feature analysis model by collecting instruction set information of the source chip platform and the target chip platform, and use the kernel function to calculate the semantic similarity matrix between instructions in the feature vector space; train a multi-layer graph attention neural network based on the semantic similarity matrix, map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, and apply the reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform, thereby optimizing the resource overhead of the conversion process and improving the overall efficiency of the system while ensuring the correctness of the conversion.

[0079] In one embodiment of the cross-chip platform instruction conversion method of the present application, see Figure 2 , and can also include the following:

[0080] Step S201: Establish a chip platform instruction set scanner to extract instruction set data from the instruction manuals of the source chip and the target chip, use a text parser to perform structured analysis on the instruction manual to generate an instruction description file, use a feature extractor to identify the position of the instruction's opcode field and operand field from the instruction description file, and parse each instruction into a standardized intermediate representation format;

[0081] Step S202: Use a word embedding model to calculate the semantic features of the standardized instruction representation, extract the instruction structural features through a convolutional neural network, concatenate the semantic features and structural features to construct a multi-dimensional feature vector, and use the principal component analysis method to reduce the dimension of the feature vector to generate an instruction feature vector space.

[0082] Optionally, this embodiment first constructs a complete instruction set data collection and processing system. The chip platform instruction set scanner adopts a distributed crawler architecture to obtain instruction manuals from the official document libraries of different chip manufacturers through configurable rule templates. The scanner supports parsing of multiple document formats, including PDF, HTML, and text files, and performs format unification processing through the document preprocessing module. During the data collection process, an incremental update mechanism is implemented to regularly detect and synchronize the latest instruction set documents.

[0083] The text parser adopts a hierarchical analysis strategy. First, it identifies the overall structure of the document through layout analysis and locates the instruction description part. Then it uses natural language processing technology to perform word segmentation and syntactic analysis on the instruction description text to identify key semantic units. The parser maintains an instruction pattern library that contains common instruction description templates and extracts basic attribute information of the instruction through template matching. For descriptions in non-standard formats, the system uses heuristic rules for supplementary analysis.

[0084] The feature extractor implements the automatic instruction field recognition function. By building a field feature model, the system can accurately locate the opcode and operand position in the instruction. The model adopts a bidirectional long short-term memory network structure to improve the recognition accuracy by learning the context information of the instruction description. In the field recognition process, a verification mechanism is introduced to ensure the reliability of the extraction results through cross-checking.

[0085] The design of the intermediate representation format adopts a hierarchical data structure, which includes the instruction basic information layer, the operation feature layer and the constraint condition layer. The basic information layer records the static attributes of the instruction such as the identifier and mnemonics. The operation feature layer describes the functional characteristics and data flow of the instruction. The constraint condition layer contains the preconditions and state effects of the instruction execution. This standardized representation facilitates the subsequent feature analysis and conversion processing.

[0086] In the feature calculation stage, the system first uses the improved Word2Vec model to calculate the semantic features of the instructions. The training corpus of the model contains a large amount of instruction description text, and the semantic association between instructions is captured through the context window method. In order to enhance the expressiveness of the model, domain-specific words and phrases are introduced during the training process.

[0087] The structural features are extracted using a deep convolutional neural network. The network is designed with multiple feature extraction layers, each layer uses convolution kernels of different sizes to extract structural patterns of different scales. Pooling operations and batch normalization are used to improve the robustness of features. The output of the network is connected to the fully connected layer to generate a fixed-dimensional structural feature vector.

[0088] The feature vector is constructed by using a feature fusion strategy, which dynamically weights and combines semantic features and structural features through an attention mechanism. The principal component analysis method is then used to reduce the dimensionality of high-dimensional features and retain the main distinguishing information. During the dimensionality reduction process, the dimensionality reduction ratio is adaptively adjusted according to the feature importance scores to balance information retention and computational efficiency.

[0089] The technical solution of this embodiment solves the problems of low automation and insufficient feature expression in traditional instruction feature extraction methods. Through the combination of deep learning and natural language processing technology, efficient extraction and representation of instruction features are achieved. The system has good scalability and can adapt to the instruction set feature extraction requirements of different chip platforms, laying the foundation for subsequent instruction conversion tasks.

[0090] In one embodiment of the cross-chip platform instruction conversion method of the present application, see Figure 3 , and can also include the following:

[0091] Step S301: Selecting a Gaussian kernel function as a similarity measurement tool in a feature vector space, inputting a feature vector of the instruction pair to be compared, mapping the feature vector to a high-dimensional Hilbert space to calculate the vector inner product, and determining a bandwidth parameter of the kernel function through a kernel function parameter adaptive adjustment algorithm;

[0092] Step S302: Calculate the similarity score for each pair of instructions in the instruction set based on the kernel function calculation result, construct an N×N dimensional similarity score matrix, normalize the similarity matrix so that the matrix element values ​​are in the interval [0,1], and compress the similarity matrix data using a sparse matrix storage method.

[0093] Optionally, this embodiment proposes an instruction similarity calculation scheme based on the kernel method. The main reason for selecting the Gaussian kernel function is that it has good mathematical properties and can transform nonlinear problems into linearly separable forms. The Gaussian kernel function realizes the implicit transformation of features by mapping vectors in the original feature space to the high-dimensional Hilbert space, avoiding the computational burden brought by the explicit calculation of high-dimensional features. In the specific implementation, the kernel function is calculated using matrix operations, and the processing efficiency is improved through parallel computing.

[0094] The bandwidth parameter of the kernel function has an important impact on the similarity calculation results. This scheme designs an adaptive parameter adjustment algorithm to dynamically determine the optimal bandwidth value by analyzing the distribution characteristics of the feature vector. The algorithm first samples several instruction pairs in the training set as reference samples and calculates the Euclidean distance distribution between samples. Then the bandwidth parameter is initialized using the median estimation method, and the parameter is fine-tuned in combination with the cross-validation method. During the adjustment process, local sensitivity constraints are introduced to ensure that the similarity calculation is robust to noise.

[0095] The similarity calculation process adopts a batch processing mechanism to organize the instruction pairs to be processed into mini-batches, making full use of the parallel computing capabilities of modern processors. For each pair of instructions, its feature vector is first extracted, and then the inner product value in the mapping space is calculated by the kernel function. In order to improve numerical stability, logarithmic space transformation is used in the calculation process to avoid numerical overflow problems. At the same time, a cache mechanism for calculation results is implemented to reduce repeated calculation overhead.

[0096] The construction process of the similarity matrix requires processing a large number of instruction pairs. In order to improve efficiency, the system adopts a block calculation strategy to decompose large-scale matrix calculations into multiple small blocks for parallel processing. After the calculation is completed, the similarity score is mapped to the [0,1] interval through normalization. Normalization uses an improved min-max method and combines local statistical features for scale adjustment to ensure the rationality of the score distribution.

[0097] Considering the sparse nature of the similarity relationship between instructions in practical applications, this solution uses compressed storage technology to optimize the matrix storage space. Specifically, the CSR (Compressed Sparse Row) format is used to store non-zero elements, which includes three parts: value array, column index array, and row pointer array. In order to further improve storage efficiency, the similarity score is threshold filtered to retain only the information of significantly similar instruction pairs. At the same time, a fast retrieval mechanism is implemented to support efficient similarity query operations.

[0098] In terms of storage optimization, the system also implements a hierarchical storage architecture. Highly accessed matrix blocks are stored in memory, and low-frequency accessed data is stored on disk. Access patterns are analyzed through predictive models to achieve intelligent preloading of data blocks and improve system response speed. For dynamic update scenarios, an incremental update strategy is adopted to recalculate only the changed matrix elements.

[0099] The technical solution of this embodiment solves the problems of low computational efficiency and high storage overhead in traditional similarity calculation methods. By combining the kernel method with the optimized storage strategy, efficient instruction similarity analysis is achieved. The system shows good performance and scalability in practical applications, can handle the similarity calculation requirements of large-scale instruction sets, and provide a reliable similarity measurement basis for subsequent instruction mapping.

[0100] In one embodiment of the cross-chip platform instruction conversion method of the present application, see Figure 4 , and can also include the following:

[0101] Step S401: construct a three-layer graph attention neural network structure, input the semantic similarity matrix into the network as the adjacency matrix of the graph, calculate the attention weight coefficient and node representation vector of each attention layer, update the network parameters through the back propagation algorithm until the network converges, and apply the trained network to the mapping conversion of the instruction feature vectors of the source platform and the target platform;

[0102] Step S402: construct a similarity matrix for the mapped feature vector, use the spectral clustering algorithm to calculate the Laplace matrix of the feature vector, perform eigenvalue decomposition on the Laplace matrix to obtain the feature vector, and group the feature vectors based on the K-means clustering algorithm to obtain an instruction mapping relationship graph.

[0103] Optionally, this embodiment designs an instruction feature mapping method based on a graph attention mechanism. The architecture of the three-layer graph attention network includes a feature conversion layer, a multi-head attention layer, and a feature aggregation layer. The feature conversion layer uses a nonlinear transformation function to initialize the input features, and the feature vector of each node is mapped to a new feature space through a weight matrix. The multi-head attention layer implements multiple independent attention calculation units, and each attention head is responsible for capturing node-related features at different levels. The feature aggregation layer generates the final node representation by weighted combination of the output results of the multi-head attention.

[0104] In the attention calculation process, the system adopts an improved attention mechanism. First, the attention score between node pairs is calculated, considering the similarity and structural relationship of node features. Then the softmax function is used to normalize the attention score to obtain the attention weight coefficient. Based on the attention weight, the features of the neighborhood nodes are weighted and aggregated to update the representation of the central node. In order to improve the expressiveness of the model, edge feature information is introduced in the attention calculation so that the network can consider the relationship attributes between nodes.

[0105] The network training adopts an end-to-end optimization method. The loss function design includes three parts: node classification loss, feature reconstruction loss and regularization term. The classification loss uses the cross entropy function to measure the difference between the predicted label and the true label. The feature reconstruction loss ensures that the mapped features maintain the original structural information. The regularization term is used to prevent the model from overfitting. The Adam optimizer is used in the training process to improve the convergence speed by dynamically adjusting the learning rate. At the same time, the early stopping strategy is implemented to terminate the training in time when the performance of the validation set no longer improves.

[0106] In the feature mapping phase, the trained network can map the instruction feature vectors of the source and target platforms to the same space. The mapping process maintains the semantic relationship between instructions, and similar instructions are close in the mapping space. In order to improve the robustness of the mapping, an integration strategy is used in the test phase to fuse the model prediction results of multiple training rounds.

[0107] The implementation of the spectral clustering algorithm adopts a multi-scale analysis method. First, a similarity matrix based on the mapping features is constructed and the normalized Laplace matrix is ​​calculated. Then, the eigenvalue decomposition problem is efficiently solved by the Lanczos algorithm to select eigenvectors with significant discriminant information. In the feature selection process, spectral interval analysis is used to determine the optimal number of features to balance the clustering effect and computational complexity.

[0108] The K-means clustering process is implemented using an improved algorithm. The initial cluster center is selected using the K-means++ method to improve the stability of the clustering results. In the iterative process, a local search strategy is introduced to optimize the center point position and accelerate the convergence speed. At the same time, an adaptive K value selection mechanism is implemented to determine the optimal number of clusters through evaluation indicators such as the silhouette coefficient.

[0109] The resulting instruction mapping relationship graph adopts a hierarchical organizational structure. The nodes in the graph represent instructions, the edges represent the mapping relationship between instructions, and the edge weights reflect the credibility of the mapping. Through the visualization of the graph, the conversion relationship between instructions is intuitively displayed, which facilitates the analysis and verification of the rationality of the mapping results.

[0110] The technical solution of this embodiment solves the problems of insufficient feature expression ability and inaccurate mapping relationship in traditional instruction mapping methods. Through the combination of graph attention network and spectral clustering, high-quality instruction mapping relationship discovery is achieved. The system has good scalability and adaptability, and can handle instruction mapping requirements of different scales and types.

[0111] In one embodiment of the cross-chip platform instruction conversion method of the present application, see Figure 5 , and can also include the following:

[0112] Step S501: Establish a deep Q learning network model, use the mapping relationship graph as the state space, define an optimization action set including three operations: node merging, edge weight adjustment, and path reconstruction, use the ε-greedy strategy to select the optimization action, and train the Q network to update the strategy parameters based on the experience replay mechanism;

[0113] Step S502: Use the trained Q network to optimize the action sequence of the mapping relationship graph, convert the optimized graph into an instruction conversion rule set, assign a unique identifier and priority attribute to each rule in the rule set, and store the rules as a lookup table structure in the form of key-value pairs.

[0114] Optionally, this embodiment proposes a mapping relationship optimization method based on deep reinforcement learning. The deep Q learning network adopts a dual network architecture, including a main network and a target network. The main network is responsible for action selection and value function estimation, and the target network is used to generate training targets, and the network stability is maintained through periodic updates. The network structure is designed with multiple layers of convolutional layers and fully connected layers to extract local and global features of the graph. The state representation includes three parts: node features, edge features, and global topological features, and a graph convolutional network is used for feature extraction.

[0115] The design of the action space takes into account multiple dimensions of graph optimization. The node merging operation is used to eliminate redundant mapping relationships, and the node pairs to be merged are determined by similarity threshold and connectivity analysis. The edge weight adjustment operation dynamically updates the credibility of the mapping relationship based on historical feedback information. The path reconstruction operation optimizes the topological structure of the mapping path by adding or removing edges. The execution of each action will update the state representation of the graph, and the system evaluates the effect of the action through the reward function.

[0116] The implementation of the ε-greedy strategy adopts a dynamic adjustment mechanism. A larger exploration probability is used in the initial stage, and the exploration rate is gradually reduced as the training progresses to achieve a balance between exploration and utilization. At the same time, the temperature parameter is introduced to control the randomness of action selection to prevent the strategy from converging to the local optimal solution too early. During the action execution process, a validity check mechanism is implemented to filter out illegal actions that may cause damage to the graph structure.

[0117] The experience replay mechanism uses a priority sampling method. The system maintains an experience pool that stores state transition samples and corresponding reward values. The sampling process assigns priorities based on the time difference (TD) error of the samples, focusing on experiences with high learning value. In order to ensure sample diversity, random factors are combined during sampling to avoid excessive focus on specific types of experience during the training process.

[0118] During the network training phase, the target network decoupling method is used to update parameters. The loss function is based on temporal difference learning, taking into account the discount accumulation of immediate rewards and future rewards. The training stability is improved through techniques such as gradient truncation and batch normalization. At the same time, a checkpoint mechanism is implemented in the training process, which regularly saves the model status and supports breakpoint continuation.

[0119] When the optimized graph is converted into a rule set, the conversion rules are extracted by path traversal. For each mapping path, the system analyzes the node and edge attributes on the path and generates the corresponding conversion rule description. The priority of the rule is determined based on the credibility score and frequency of use of the path. In the process of rule extraction, a conflict detection mechanism is implemented to ensure the consistency of the rule set.

[0120] The rule storage adopts a hierarchical hash table structure. The primary index is established based on the source instruction characteristics, and the secondary index contains the target instruction and conversion parameter information. The implementation of the lookup table takes cache friendliness into consideration, and stores the frequently accessed rules in a continuous memory area. At the same time, a rule version management mechanism is implemented to support dynamic update and rollback operations of the rules.

[0121] The technical solution of this embodiment solves the problems of low efficiency and poor adaptability in traditional mapping optimization methods. Through the deep reinforcement learning method, automatic optimization and rule extraction of mapping relationships are achieved. The system shows good optimization effect and operation efficiency in practical applications, and can generate a high-quality instruction conversion rule set.

[0122] In one embodiment of the cross-chip platform instruction conversion method of the present application, see Figure 6 , and can also include the following:

[0123] Step S601: Load the instruction equivalent conversion rules into the rule base of the instruction conversion engine, build an instruction parser to read the binary code stream of the source platform instruction, extract the operation code segment and operand segment of the instruction according to the instruction format template, and use the recursive neural network model to analyze the grammatical structure of the instruction to build a syntax tree;

[0124] Step S602: traverse the parsed syntax tree to decompose the complex instructions into a basic instruction sequence, search the rule base for the target platform conversion rule corresponding to each basic instruction, reassemble the basic instructions according to the instruction format specification of the target platform, and generate a binary instruction code stream for the target platform.

[0125] Optionally, this embodiment proposes a rule-based instruction conversion execution method. The instruction conversion engine adopts a modular design, including three core components: a rule manager, an instruction parser, and a conversion executor. The rule manager implements dynamic loading and index construction of rules, and uses memory mapping technology to improve rule access efficiency. The organization of the rule base adopts a hierarchical structure, establishes multi-level indexes according to instruction types and operation characteristics, and supports fast rule matching queries.

[0126] The implementation of the instruction parser is based on the state machine model. First, the binary code stream is preprocessed to identify instruction boundaries and alignment information. Then, the instructions are divided into different fields according to the predefined instruction format template. The parsing of the opcode segment uses a table lookup method to quickly identify the instruction type, and the parsing of the operand segment is specially processed according to different addressing modes. During the parsing process, an error detection and recovery mechanism is implemented to handle irregular instruction encoding situations.

[0127] The syntax analysis adopts an improved recursive neural network model. The network structure includes an embedding layer, a bidirectional LSTM layer, and an attention layer. The embedding layer maps the instruction field to a vector representation, the LSTM layer captures the contextual dependencies of the instruction sequence, and the attention layer highlights important grammatical features. The network training uses a large-scale instruction syntax sample and optimizes the model parameters through supervised learning. In order to improve the analysis accuracy, grammatical rule constraints are introduced to integrate prior knowledge into the network reasoning process.

[0128] The process of constructing the syntax tree implements a bottom-up assembly strategy. First, the basic syntax units are identified, and then the high-level syntax structure is gradually constructed according to the syntax rules. The tree nodes contain attribute information such as instruction type, operand type, and dependency. During the tree construction process, the tree structure is optimized by merging and reordering nodes to improve the efficiency of subsequent conversions.

[0129] Instruction decomposition uses a pattern matching method. The system maintains a complex instruction pattern library and identifies decomposable instruction patterns through a tree matching algorithm. The decomposition process takes into account the data dependency and control dependency between instructions to ensure that the decomposed basic instruction sequence maintains the original semantics. At the same time, an optimization mechanism is implemented to merge redundant operations and reduce the number of generated instructions.

[0130] The rule matching process adopts a multi-level search strategy. First, a coarse-grained match is performed based on the opcode, and then an accurate match is performed based on the operand type and constraints. For multiple matching rules, the system selects the most suitable conversion rule based on the rule priority and context information. During the rule application process, parameter replacement and condition checking mechanisms are implemented to ensure the correctness of the conversion.

[0131] The instruction reassembly phase implements an intelligent scheduling algorithm. The system analyzes the dependencies between instructions, builds a data flow graph, and optimizes the instruction execution order. When encoding instructions, it considers the alignment requirements and optimization constraints of the target platform to generate an efficient instruction sequence. At the same time, it implements a resource allocation mechanism to reasonably arrange the use of registers and memory.

[0132] The binary code stream is generated in a pipelined manner. The system maintains an instruction buffer and performs encoding conversion in batches. The encoding process uses a table lookup method to quickly generate the machine code of the target platform, while performing integrity checks and checksum calculations. For instructions that need to be relocated, relevant information is retained for subsequent linking.

[0133] The technical solution of this embodiment solves the problems of low parsing efficiency and poor conversion accuracy in traditional instruction conversion. Through the combination of deep learning and rule system, efficient and reliable instruction conversion is achieved. The system has good scalability and can support new instruction set conversion requirements by updating the rule base.

[0134] In one embodiment of the cross-chip platform instruction conversion method of the present application, see Figure 7 , and can also include the following:

[0135] Step S701: Create a multi-level cache system including a first-level cache and a second-level cache, establish a hash table structure based on an LRU replacement strategy in the first-level cache to store the conversion results of hot instructions, build a red-black tree structure in the second-level cache to store the mapping data of basic instruction blocks, and analyze the cache access sequence based on the long short-term memory network model to generate an access prediction model;

[0136] Step S702: Update the contents of the first-level cache and the second-level cache according to the output results of the prediction model, verify and calculate the re-encoded target platform instructions, establish an execution dependency graph of the instruction sequence, and transmit the converted instruction sequence to the instruction execution unit of the target chip platform through the buffer queue.

[0137] Optionally, this embodiment designs an intelligent instruction cache management method. The multi-level cache system adopts a layered architecture, and the first-level cache and the second-level cache use different data structures and replacement strategies. The first-level cache uses an open chain method to resolve hash conflicts. Each bucket maintains a bidirectional linked list, supporting query and update operations with O(1) time complexity. The cache items contain instruction characteristics, conversion results, and access statistics. The LRU replacement strategy is implemented through a bidirectional linked list, and the cache items that have not been used for the longest time are eliminated when the capacity is full.

[0138] The red-black tree structure of the secondary cache ensures logarithmic time complexity for search, insertion, and deletion operations. The tree nodes store the feature vectors of instruction blocks as key values, and the height balance of the tree is maintained through a self-balancing mechanism. In order to improve space utilization, a node merging mechanism is implemented to combine adjacent small instruction blocks into larger blocks. At the same time, access frequency and timestamp information are maintained in the nodes to support replacement decisions based on multiple dimensions.

[0139] The long short-term memory network model is used for cache access prediction. The network input includes historical access sequences, instruction features, and system status information. The model architecture contains multiple layers of LSTM units, and dropout is used in each layer to prevent overfitting. The attention mechanism is used to capture long-term dependencies in the sequence and highlight important historical access patterns through soft attention weights. The training process uses online learning to continuously update model parameters to adapt to changes in access patterns.

[0140] The prediction model is applied in batch mode. The system collects cache access data regularly and generates prediction sequences using a sliding window method. The prediction results include the access probability distribution of each instruction in the future time window. Based on the prediction results, the system implements an active prefetch mechanism to load instructions with high probability of access into the cache in advance. At the same time, the weight parameters of the replacement strategy are adjusted according to the prediction results to optimize the use of cache space.

[0141] The cache update process implements a hierarchical warm-up strategy. The system maintains an observation queue to record the access of newly entered instructions. When the access frequency exceeds the threshold, the instruction is promoted to the secondary cache. For hot instructions in the secondary cache, whether to promote them to the primary cache is determined based on the access pattern and prediction results. The update process adopts a batch method to reduce the overhead of cache consistency maintenance.

[0142] Instruction verification uses an incremental calculation method. The system calculates the checksum synchronously when re-encoding the instruction, and uses a table lookup method to improve calculation efficiency. The verification process includes two parts: opcode verification and operand verification, which are combined through XOR operations to generate the final check value. For instruction sequences spanning multiple basic blocks, a segmented verification mechanism is implemented to support local retransmission and recovery.

[0143] The dependency graph is constructed using a dynamic analysis method. The system tracks the data flow and control flow relationships between instructions and uses a directed acyclic graph to represent the dependencies. The nodes of the graph represent instructions, and the edges represent dependency types and delay constraints. The execution order of instructions is determined by a topological sorting algorithm, which achieves instruction scheduling optimization within a basic block.

[0144] The implementation of the buffer queue takes into account multi-threaded concurrent access. The queue adopts a ring buffer structure and ensures data consistency through atomic operations. The producer-consumer model is used to coordinate the working rhythm of the conversion engine and the execution unit. The queue management includes a flow control mechanism to prevent the buffer from overflowing due to excessive production speed. At the same time, a priority queue is implemented to support priority scheduling of key instructions.

[0145] The technical solution of this embodiment solves the performance bottleneck problem in the instruction conversion process. Through intelligent cache management and prediction mechanism, the throughput of instruction conversion is significantly improved. The system shows excellent cache hit rate and stable conversion delay in practical applications, which can meet the needs of high-performance computing scenarios.

[0146] In order to optimize the resource overhead of the conversion process and improve the overall efficiency of the system on the basis of ensuring the correctness of the conversion, the present application provides an embodiment of a cross-chip platform instruction conversion device for implementing all or part of the contents of the cross-chip platform instruction conversion method, see Figure 8 , the cross-chip platform instruction conversion device specifically includes the following contents:

[0147] A similarity matrix construction module 10 is used to collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions;

[0148] A conversion rule determination module 20 is used to train a multi-layer graph attention neural network based on the semantic similarity matrix, map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, use a spectral clustering algorithm to construct an instruction mapping relationship graph, and use a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules;

[0149] The instruction conversion module 30 is used to load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, use a recursive neural network model to split complex instructions into basic instruction sequences, re-encode the basic instruction sequences into target platform instructions according to the conversion rules, establish a multi-level cache structure for the re-encoded instructions, store the conversion results of hot instructions in the first-level cache, store the mapping relationship of the basic instruction blocks in the second-level cache, dynamically adjust the cache content based on the historical access data training prediction model, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform.

[0150] From the above description, it can be seen that the cross-chip platform instruction conversion device provided in the embodiment of the present application can establish an instruction feature analysis model by collecting instruction set information of the source chip platform and the target chip platform, and use the kernel function to calculate the semantic similarity matrix between instructions in the feature vector space; train a multi-layer graph attention neural network based on the semantic similarity matrix, map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, and apply the reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform, thereby optimizing the resource overhead of the conversion process and improving the overall efficiency of the system while ensuring the correctness of the conversion.

[0151] From the hardware level, in order to optimize the resource overhead of the conversion process and improve the overall efficiency of the system on the basis of ensuring the correctness of the conversion, the present application provides an embodiment of an electronic device for implementing all or part of the contents of the cross-chip platform instruction conversion method, and the electronic device specifically includes the following contents:

[0152] Processor, memory, communication interface and bus; wherein the processor, memory and communication interface communicate with each other through the bus; the communication interface is used to realize information transmission between the cross-chip platform instruction conversion device and the core business system, user terminal and related database and other related devices; the logic controller can be a desktop computer, a tablet computer and a mobile terminal, etc., but the present embodiment is not limited thereto. In the present embodiment, the logic controller can be implemented with reference to the embodiment of the cross-chip platform instruction conversion method and the embodiment of the cross-chip platform instruction conversion device in the embodiment, and the contents thereof are incorporated herein, and the repeated parts are not repeated.

[0153] It is understandable that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0154] In practical applications, part of the instruction conversion method across chip platforms can be executed on the electronic device side as described above, or all operations can be completed in the client device. The selection can be made based on the processing capability of the client device and the limitations of the user's usage scenario. This application does not limit this. If all operations are completed in the client device, the client device may also include a processor.

[0155] The client device may have a communication module (i.e., a communication unit) that can communicate with a remote server to achieve data transmission with the server. The server may include a server on the task scheduling center side, and other implementation scenarios may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, or a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0156] Fig. 9 FIG. 9 is a schematic block diagram of the system structure of the electronic device 9600 according to an embodiment of the present application. Fig. 9 As shown, the electronic device 9600 may include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that Fig. 9 is exemplary; other types of structures may also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0157] In one embodiment, the cross-chip platform instruction conversion method function may be integrated into the central processing unit 9100. The central processing unit 9100 may be configured to perform the following control:

[0158] Step S101: Collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions;

[0159] Step S102: training a multi-layer graph attention neural network based on the semantic similarity matrix, mapping feature vectors of source platform instructions and target platform instructions to a shared embedding space, using a spectral clustering algorithm to construct an instruction mapping relationship graph, and applying a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules;

[0160] Step S103: Load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, use a recursive neural network model to split complex instructions into basic instruction sequences, re-encode the basic instruction sequences into target platform instructions according to the conversion rules, establish a multi-level cache structure for the re-encoded instructions, store the conversion results of hot instructions in the first-level cache, store the mapping relationship of the basic instruction blocks in the second-level cache, dynamically adjust the cache content based on the historical access data training prediction model, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform.

[0161] From the above description, it can be seen that the electronic device provided in the embodiment of the present application establishes an instruction feature analysis model by collecting instruction set information of the source chip platform and the target chip platform, and uses a kernel function to calculate the semantic similarity matrix between instructions in the feature vector space; a multi-layer graph attention neural network is trained based on the semantic similarity matrix, and the feature vectors of the source platform instructions and the target platform instructions are mapped to a shared embedding space, and a reinforcement learning method is applied to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; the instruction equivalent conversion rules are loaded in the instruction conversion engine, the input source platform instructions are decoded and analyzed, and the converted target platform instruction sequence is output to the instruction execution unit of the target chip platform, thereby optimizing the resource overhead of the conversion process and improving the overall efficiency of the system while ensuring the correctness of the conversion.

[0162] In another embodiment, the cross-chip platform instruction conversion device can be configured separately from the central processing unit 9100. For example, the cross-chip platform instruction conversion device can be configured as a chip connected to the central processing unit 9100, and the function of the cross-chip platform instruction conversion method can be implemented through the control of the central processing unit.

[0163] like Fig. 9 As shown, the electronic device 9600 may also include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It is worth noting that the electronic device 9600 does not necessarily have to include Fig. 9 In addition, the electronic device 9600 may also include Fig. 9 For components not shown, reference may be made to the prior art.

[0164] like Fig. 9 As shown, the central processing unit 9100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor device and / or logic device, which receives input and controls the operation of various components of the electronic device 9600.

[0165] The memory 9140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 9100 may execute the program stored in the memory 9140 to implement information storage or processing, etc.

[0166] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or a touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and texts. The display may be, for example, an LCD display, but is not limited thereto.

[0167] The memory 9140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 9140 may also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 may include an application / function storage unit 9142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 9600 through the central processor 9100.

[0168] The memory 9140 may also include a data storage unit 9143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0169] The communication module 9110 is a transmitter / receiver that sends and receives signals via the antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processor 9100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0170] Based on different communication technologies, multiple communication modules 9110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless LAN module. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide an audio output via the speaker 9131 and receive an audio input from the microphone 9132, thereby realizing a common telecommunication function. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, so that recording can be performed on the local machine through the microphone 9132, and the sound stored on the local machine can be played through the speaker 9131.

[0171] The embodiments of the present application also provide a computer-readable storage medium capable of implementing all steps of the instruction conversion method for a cross-chip platform in the above-mentioned embodiment in which the execution subject is a server or a client. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, all steps of the instruction conversion method for a cross-chip platform in the above-mentioned embodiment in which the execution subject is a server or a client are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0172] Step S101: Collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions;

[0173] Step S102: training a multi-layer graph attention neural network based on the semantic similarity matrix, mapping feature vectors of source platform instructions and target platform instructions to a shared embedding space, using a spectral clustering algorithm to construct an instruction mapping relationship graph, and applying a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules;

[0174] Step S103: Load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, use a recursive neural network model to split complex instructions into basic instruction sequences, re-encode the basic instruction sequences into target platform instructions according to the conversion rules, establish a multi-level cache structure for the re-encoded instructions, store the conversion results of hot instructions in the first-level cache, store the mapping relationship of the basic instruction blocks in the second-level cache, dynamically adjust the cache content based on the historical access data training prediction model, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform.

[0175] From the above description, it can be seen that the computer-readable storage medium provided in the embodiment of the present application establishes an instruction feature analysis model by collecting instruction set information of the source chip platform and the target chip platform, and uses a kernel function to calculate the semantic similarity matrix between instructions in the feature vector space; based on the semantic similarity matrix, a multi-layer graph attention neural network is trained to map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, and a reinforcement learning method is applied to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; the instruction equivalent conversion rules are loaded in the instruction conversion engine, the input source platform instructions are decoded and analyzed, and the converted target platform instruction sequence is output to the instruction execution unit of the target chip platform, thereby optimizing the resource overhead of the conversion process and improving the overall efficiency of the system while ensuring the correctness of the conversion.

[0176] The embodiments of the present application also provide a computer program product capable of implementing all steps of the cross-chip platform instruction conversion method in the above embodiments, where the execution subject is a server or a client. When the computer program / instruction is executed by a processor, the steps of the cross-chip platform instruction conversion method are implemented. For example, the computer program / instruction implements the following steps:

[0177] Step S101: Collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions;

[0178] Step S102: training a multi-layer graph attention neural network based on the semantic similarity matrix, mapping feature vectors of source platform instructions and target platform instructions to a shared embedding space, using a spectral clustering algorithm to construct an instruction mapping relationship graph, and applying a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules;

[0179] Step S103: Load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, use a recursive neural network model to split complex instructions into basic instruction sequences, re-encode the basic instruction sequences into target platform instructions according to the conversion rules, establish a multi-level cache structure for the re-encoded instructions, store the conversion results of hot instructions in the first-level cache, store the mapping relationship of the basic instruction blocks in the second-level cache, dynamically adjust the cache content based on the historical access data training prediction model, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform.

[0180] From the above description, it can be seen that the computer program product provided in the embodiment of the present application establishes an instruction feature analysis model by collecting instruction set information of the source chip platform and the target chip platform, and uses a kernel function to calculate the semantic similarity matrix between instructions in the feature vector space; trains a multi-layer graph attention neural network based on the semantic similarity matrix, maps the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, and applies a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; loads the instruction equivalent conversion rules in the instruction conversion engine, decodes and analyzes the input source platform instructions, and outputs the converted target platform instruction sequence to the instruction execution unit of the target chip platform, thereby optimizing the resource overhead of the conversion process and improving the overall efficiency of the system while ensuring the correctness of the conversion.

[0181] It should be understood by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0182] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0183] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0184] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0185] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A cross-chip platform instruction conversion method, characterized in that: The method comprises: Collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions; Based on the semantic similarity matrix, a multi-layer graph attention neural network is trained to map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, a spectral clustering algorithm is used to construct an instruction mapping relationship graph, and a reinforcement learning method is used to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; The instruction equivalent conversion rules are loaded into the instruction conversion engine, the input source platform instructions are decoded and analyzed, the complex instructions are split into basic instruction sequences using a recursive neural network model, the basic instruction sequences are re-encoded into target platform instructions according to the conversion rules, a multi-level cache structure is established for the re-encoded instructions, the conversion results of hot instructions are stored in the first-level cache, the mapping relationship of the basic instruction blocks is stored in the second-level cache, the cache content is dynamically adjusted based on the prediction model trained based on historical access data, and the converted target platform instruction sequence is output to the instruction execution unit of the target chip platform.

2. The cross-chip platform instruction conversion method according to claim 1, characterized in that: The method collects instruction set information of the source chip platform and the target chip platform, establishes an instruction feature analysis model, formats the instruction set information, extracts instruction format, operation code and operand features, and constructs a multi-dimensional feature vector space of the instruction set, including: Establish a chip platform instruction set scanner to extract instruction set data from the instruction manuals of the source chip and the target chip, use a text parser to perform structured analysis on the instruction manual to generate an instruction description file, use a feature extractor to identify the opcode field and operand field position of the instruction from the instruction description file, and parse each instruction into a standardized intermediate representation format; The word embedding model is used to calculate the semantic features of the standardized instruction representation, and the instruction structural features are extracted through a convolutional neural network. The semantic features and structural features are concatenated to construct a multi-dimensional feature vector. The principal component analysis method is used to reduce the dimension of the feature vector to generate the instruction feature vector space.

3. The cross-chip platform instruction conversion method according to claim 1, characterized in that: The step of calculating the semantic similarity matrix between instructions using a kernel function in the feature vector space includes: In the feature vector space, a Gaussian kernel function is selected as a similarity measurement tool, the feature vector of the instruction pair to be compared is input, the feature vector is mapped to a high-dimensional Hilbert space to calculate the vector inner product, and the bandwidth parameter of the kernel function is determined by the kernel function parameter adaptive adjustment algorithm; Based on the calculation results of the kernel function, the similarity score of each pair of instructions in the instruction set is calculated, and an N×N dimensional similarity score matrix is ​​constructed. The similarity matrix is ​​normalized so that the matrix element values ​​are in the interval [0,1], and the sparse matrix storage method is used to compress the similarity matrix data.

4. The cross-chip platform instruction conversion method according to claim 1, characterized in that: The method of training a multi-layer graph attention neural network based on the semantic similarity matrix, mapping the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, and constructing an instruction mapping relationship graph using a spectral clustering algorithm includes: Construct a three-layer graph attention neural network structure, input the semantic similarity matrix into the network as the adjacency matrix of the graph, calculate the attention weight coefficient and node representation vector of each attention layer, update the network parameters through the back propagation algorithm until the network converges, and apply the trained network to the mapping conversion of the instruction feature vectors of the source platform and the target platform; A similarity matrix is ​​constructed for the mapped feature vector, and the Laplace matrix of the feature vector is calculated using the spectral clustering algorithm. The Laplace matrix is ​​decomposed by eigenvalue to obtain the feature vector, and the feature vector is grouped based on the K-means clustering algorithm to obtain the instruction mapping relationship graph.

5. The cross-chip platform instruction conversion method according to claim 1, characterized in that: The application of the reinforcement learning method to iteratively optimize the mapping relationship graph to obtain the instruction equivalent conversion rule includes: A deep Q-learning network model is established, and the mapping relationship graph is used as the state space. The optimization action set is defined, including node merging, edge weight adjustment, and path reconstruction. The ε-greedy strategy is used to select the optimization action, and the Q network is trained based on the experience replay mechanism to update the strategy parameters. The trained Q network is used to optimize the action sequence of the mapping relationship graph, and the optimized graph is converted into a set of instruction conversion rules. A unique identifier and priority attribute are assigned to each rule in the rule set, and the rules are stored as a lookup table structure in the form of key-value pairs.

6. The cross-chip platform instruction conversion method according to claim 1, characterized in that: The instruction equivalent conversion rule is loaded in the instruction conversion engine, the input source platform instruction is decoded and analyzed, a recursive neural network model is used to split the complex instruction into a basic instruction sequence, and the basic instruction sequence is re-encoded into a target platform instruction according to the conversion rule, including: Load the instruction equivalent conversion rules into the rule library of the instruction conversion engine, build an instruction parser to read the binary code stream of the source platform instruction, extract the operation code segment and operand segment of the instruction according to the instruction format template, and use the recursive neural network model to analyze the grammatical structure of the instruction to build a syntax tree; The parsed syntax tree is traversed to decompose complex instructions into basic instruction sequences. The target platform conversion rules corresponding to each basic instruction are searched in the rule base. The basic instructions are reassembled according to the instruction format specifications of the target platform to generate a binary instruction code stream for the target platform.

7. The cross-chip platform instruction conversion method according to claim 1, characterized in that: The method establishes a multi-level cache structure for the re-encoded instructions, stores the conversion results of hot spot instructions in the first-level cache, stores the mapping relationship of basic instruction blocks in the second-level cache, dynamically adjusts the cache content based on the historical access data training prediction model, and outputs the converted target platform instruction sequence to the instruction execution unit of the target chip platform, including: Create a multi-level cache system including the first-level cache and the second-level cache. Establish a hash table structure based on the LRU replacement strategy in the first-level cache to store the conversion results of hot instructions. Build a red-black tree structure in the second-level cache to store the mapping data of basic instruction blocks. Analyze the cache access sequence based on the long short-term memory network model to generate an access prediction model. According to the output results of the prediction model, the contents of the first-level cache and the second-level cache are updated, the re-encoded target platform instructions are verified and calculated, the execution dependency graph of the instruction sequence is established, and the converted instruction sequence is transmitted to the instruction execution unit of the target chip platform through the buffer queue.

8. A cross-chip platform instruction conversion device, characterized in that: The device comprises: A similarity matrix construction module is used to collect instruction set information of the source chip platform and the target chip platform, establish an instruction feature analysis model, format the instruction set information to extract instruction format, operation code and operand features, construct a multi-dimensional feature vector space of the instruction set, and use a kernel function in the feature vector space to calculate the semantic similarity matrix between instructions; A conversion rule determination module is used to train a multi-layer graph attention neural network based on the semantic similarity matrix, map the feature vectors of the source platform instructions and the target platform instructions to a shared embedding space, use a spectral clustering algorithm to construct an instruction mapping relationship graph, and use a reinforcement learning method to iteratively optimize the mapping relationship graph to obtain instruction equivalent conversion rules; An instruction conversion module is used to load the instruction equivalent conversion rules in the instruction conversion engine, decode and analyze the input source platform instructions, split complex instructions into basic instruction sequences using a recursive neural network model, re-encode the basic instruction sequences into target platform instructions according to the conversion rules, establish a multi-level cache structure for the re-encoded instructions, store the conversion results of hot instructions in the first-level cache, store the mapping relationship of the basic instruction blocks in the second-level cache, dynamically adjust the cache content based on the historical access data training prediction model, and output the converted target platform instruction sequence to the instruction execution unit of the target chip platform.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the cross-chip platform instruction conversion method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the cross-chip platform instruction conversion method described in any one of claims 1 to 7 are implemented.

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