System and method for voltage drift monitoring

Abstract

Embodiments of the present disclosure relate to a system and method for monitoring voltage drift, the method comprising measuring a voltage across a diode of a power device, providing the measured voltage as an input to a controller, the controller configured to operate a converter-based model, and predicting a range of expected future values of the voltage across the diode of the power device using the converter-based model. The transformer-based model may include a time fusion transformer with a time convolutional neural network and a antagonism compensation model with a back propagation algorithm.

Description

Technical Field

[0001] The present invention generally relates to systems and methods for voltage drift monitoring, and in particular embodiments to systems and methods for monitoring power module health. Background Art

[0002] A power module is a power electronic device that can handle large currents. A power module includes power devices such as transistors, diodes, and the like. Some types of power devices, such as power devices based on silicon carbide (SiC), may allow for higher power efficiency and / or higher switching frequencies. SiC-based power devices may be used in electric vehicle power applications such as on-board chargers (OBCs), electric traction drives, and power converter solutions; and in industrial applications such as motor drives, solar inverters, charging stations, UPS, welding tools, and power converter solutions. In particular, SiC power modules may be used in cooling systems for traction drives of electric vehicles. However, problems may arise in SiC-based power devices that require new solutions. Summary of the invention

[0003] According to one embodiment, a method for monitoring voltage drift includes: measuring a voltage across a diode of a power device; providing the measured voltage as an input to a controller, the controller being configured to run a converter-based model, wherein the converter-based model includes a time fusion converter having a time convolutional neural network, the converter-based model also including an adversarial compensation model having a back-propagation algorithm; and predicting a range of expected future values ​​of the voltage across the diode of the power device using the converter-based model.

[0004] According to another embodiment, a method for monitoring the health of a power device includes: training an artificial intelligence model using a voltage input, the voltage input being generated by power cycling a first power device; loading the trained artificial intelligence model into firmware of a microcontroller; and using the trained artificial intelligence model to predict when a second power device will reach the end of its operating life, the second power device being coupled to the microcontroller.

[0005] According to another embodiment, a system for monitoring voltage drift includes: a power device; a non-volatile memory including a program; and a microprocessor coupled to the non-volatile memory and the power device, the microprocessor being configured to execute the program, the program including a converter-based model, wherein the converter-based model includes a time fusion converter having a time convolutional neural network, the converter-based model also includes an adversarial compensation model having a back-propagation algorithm, and based on the converter-based model, the voltage drift of the power device is monitored and the future voltage drift of the power device is predicted.

[0006] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1A and Figure 1B shows a cross-sectional view and a top view of a semiconductor die according to some embodiments;

[0009] Figure 2 shows a top view of a power module according to some embodiments;

[0010] Figure 3A shows a block diagram of a system for monitoring voltage drift of a power module according to some embodiments;

[0011] Figure 3B shows a graph of voltage versus time measured across a body diode of a power module according to some embodiments;

[0012] Figure 4 A graph showing experimental results of predicted and actual drain-source voltage variations over time for a power module according to some embodiments;

[0013] Figure 5 shows a block diagram of an example AI model according to some embodiments;

[0014] Fig. 6A and Figure 6B shows an example graph of experimental data according to some embodiments, comparing actual drain-source voltage to predicted drain-source voltage from an AI model;

[0015] Figure 7 a table showing error values ​​between predicted drain-source voltage and measured drain-source voltage according to some embodiments;

[0016] Figure 8 A flow chart illustrating a method for monitoring the health of a power device according to some embodiments; and

[0017] Fig. 9 A flow chart of a method for monitoring voltage drift according to some embodiments is shown.

[0018] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the drawings do not necessarily indicate the end of the range of the features. DETAILED DESCRIPTION

[0019] The making and use of various embodiments will be discussed in detail below. However, it should be understood that the various embodiments described herein can be applied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrations of specific ways to make and use the various embodiments and should not be interpreted in a limited scope.

[0020] Due to the power losses caused by load current and frequency, power modules (e.g., SiC power modules) may be repeatedly heated during their operation. These repeated temperature fluctuations may generate thermal fatigue on device interfaces (such as wire bonds). Due to the positive feedback between wire bond degradation and the on-state drain-source voltage of the silicon carbide (SiC) MOSFET, the power loss in the device may increase with degradation. This may lead to undesirable consequences such as system overheating, efficiency loss, and if no countermeasures are taken, it may also lead to complete system failure. If a component or subsystem of a power electronics system (such as a power module) exhibits abnormal behavior, the normal operation of the entire system may be jeopardized. For automotive applications, these undesirable behaviors may have a significant impact on the safety of the traction system and thus the overall safety of the vehicle. For example, in an electric or hybrid electric vehicle, a fault in a system based on a SiC power module may have an impact on the cooling system of the traction drive. This may affect the overall performance of the electric vehicle engine, thereby affecting driving safety.

[0021] Therefore, it would be advantageous to identify precursor parameters to power module degradation, monitor the precursor parameters during operation, and predict the remaining device life of the power module before reaching a critical threshold of system reliability. This can help avoid critical device failures.

[0022] According to one or more embodiments of the present disclosure, the present application relates to a system and method for voltage drift monitoring in order to monitor and predict the health of a power module (also referred to as a power device). An AI-based algorithm (such as a converter model-based algorithm) is used to use the drain-source voltage (V ds ) as input to predict the health of a power module (e.g., a SiC power module). The AI-based algorithm based on the converter model combines a self-attention mechanism, parallelization, and position encoding. The AI-based algorithm can be trained and tested through power cycling tests to analyze module interface reliability. The AI-based algorithm can further use Jacobian regularization, an adversarial compensation model, to compensate for noise in the drain-source voltage input.

[0023] Embodiments of the present disclosure are described in the context of the accompanying drawings. Figure 1A , Figure 1B and Figure 2 An embodiment of an example power module is described. Figure 3A An embodiment of a system for monitoring voltage drift of a power module is described. Figure 3B The experimental results describe the voltage versus time measured across the body diode of the power module. Figure 4 Experimental results describing the predicted and actual drain-source voltage variation over time for a power module will be used. Figure 5 Describe an embodiment of an AI model. Fig. 6A and Figure 6B Experimental results describing the actual drain-source voltage versus the predicted drain-source voltage from the AI ​​model. Figure 7 Experimental results describing the error between the predicted drain-source voltage and the measured drain-source voltage. Figure 8 An embodiment of a method for monitoring the health of a power device is described. Fig. 9 Embodiments of methods for monitoring voltage drift are described.

[0024] Figure 1A-1B is a view of a power semiconductor die 100 . Figure 1A is a cross-sectional view, and Figure 1B 1 is a top view. The power semiconductor die 100 includes a power device capable of operating at high voltage and / or high frequency, such as a power device based on silicon carbide (SiC), a power device based on gallium nitride (GaN), etc. The power device can be a transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), a bipolar transistor, etc.; a diode, such as a Schottky barrier diode (SBD); etc. The power semiconductor die 100 can be formed in a suitable front end of line (FEOL) process by acceptable deposition, lithography and etching techniques.

[0025] In some embodiments, the power semiconductor die 100 is a silicon carbide die including a SiC MOSFET. Such a power semiconductor die 100 includes a drain electrode 102, a semiconductor layer 104, a source electrode 106, and a gate electrode 108. Other types of power semiconductor dies may have other feature arrangements. In addition, it should be understood that the power semiconductor die 100 may include other features (not shown separately).

[0026] The drain electrode 102 may be formed of a conductive material such as titanium, aluminum, nickel, gold, combinations thereof, etc., which may be formed by a deposition process such as physical vapor deposition (PVD) or CVD, a plating process such as electrolytic or electroless plating, etc. The drain electrode 102 may (or may not) be wider than the overlying feature (e.g., the semiconductor layer 104).

[0027] The semiconductor layer 104 is formed on the drain electrode 102. The semiconductor layer 104 includes any desired number of channel layers, well layers, drift layers, etc. Each of the semiconductor layers 104 may be formed of: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. Each of the semiconductor layers 104 may be epitaxially grown using a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited using a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the like. In some embodiments, the semiconductor layer 104 includes a silicon carbide layer.

[0028] The source electrode 106 and the gate electrode 108 are formed on the semiconductor layer 104. The source electrode 106 and the gate electrode 108 can each be formed of a conductive material, such as titanium, aluminum, nickel, gold, a combination thereof, etc., which can be formed by a deposition process such as physical vapor deposition (PVD) or CVD, a plating process such as electrolytic or electroless plating, etc. The source electrode 106 and the gate electrode 108 can be formed in the same cross section (such as Figure 1A ), or may be formed in different cross sections (such as Figure 1B 104). Additional layers (not separately shown) may also be formed, such as dielectric layers, interface layers, work function tuning layers, etc. For example, a gate dielectric layer may be formed between the gate electrode 108 and the semiconductor layer 104.

[0029] The power semiconductor die 100 of this example includes a SiC MOSFET having a planar structure. Other structures may be used. For example, the SiC MOSFET may have a trench structure, such as a single trench structure, a double trench structure, etc.

[0030] Figure 2 is a top view of a power module 200 (also referred to as a power device). The power module 200 includes a packaging substrate 202 and a power electronic circuit, which includes one or more power semiconductor dies 100 mounted to the packaging substrate 202. The power electronic circuit can be any desired type of circuit, such as a chopper circuit, a DC-DC converter circuit, an inverter circuit, or a relay circuit. It should be understood that the power electronic circuit may include other circuit elements (not shown separately) mounted to the packaging substrate 202, such as passive devices, gate drivers, etc. In an embodiment where the power semiconductor die 100 is a SiC MOSFET, the power module 200 is a SiC power module. The power electronic circuit may include a plurality of power semiconductor dies 100. In this example, 16 power semiconductor dies 100 are used. However, the power module 200 may include any suitable number of power semiconductor dies 100. As Figure 2As shown, the power module 200 includes a low side region 206 close to a battery terminal (not shown) and a high side region 208 away from the battery terminal. The drain-source voltage measured in the low side region 206 or the high side region 208 can be used for health monitoring and prediction of the power module 200.

[0031] The package substrate 202 includes a substrate core and a bonding pad on the substrate core. The substrate core can be formed of semiconductor materials such as silicon, germanium, diamond, etc. In an alternative embodiment, the substrate core is based on an insulating core such as a glass fiber reinforced resin core. An example core material is a glass fiber resin such as FR4. Alternatives to the core material include bismaleimide triazine BT resin, or alternatively, include other PCB materials or films. Stacked films such as ABF or other laminates can be used for the substrate core. The substrate core may (or may not) include active and / or passive devices. Various devices such as transistors, capacitors, resistors, combinations thereof, etc. can be used to generate the structural and functional requirements of the design of the power module 200. The device can be formed using any suitable method. The substrate core may also include a metallization layer and a via (not shown), wherein the bonding pad is physically and / or electrically coupled to the metallization layer and the via. The metallization layer can be formed on active and passive devices and is designed to connect various devices to form a functional circuit system. The metallization layers may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers, and may be formed by any suitable process, such as deposition, damascene, dual damascene, etc. In some embodiments, the substrate core is substantially free of active devices and passive devices.

[0032] The power semiconductor die 100 is attached to the bonding pads of the packaging substrate 202. For example, a conductive connector (such as a reflowable connector, not separately shown) can be used to electrically and / or physically couple the packaging substrate 202 (including the metallization layer of the packaging substrate 202) to the power semiconductor die 100, such as to the drain electrode 102 (see Figure 1A ). Wire bonds (not separately shown) may be connected to the source electrode 106 and the gate electrode 108 (see Figure 1A ). For example, a branch of a power electronic circuit can be formed by coupling multiple source electrodes 106 of multiple power semiconductor dies 100 together using wire bonding. The wire bonding and metallization layers of the package substrate 202 connect the power semiconductor dies 100 and other circuit elements (if present) together to form the desired power electronic circuit.

[0033] The wire bonds of the package substrate 202 may be subject to repeated temperature fluctuations, such as from heating caused by load current and frequency during operation of the power semiconductor die 100. Device interfaces such as wire bonds may experience thermal fatigue due to temperature fluctuations. Due to positive feedback, the power loss of the power module 200 may increase as the wire bonds deteriorate. This may lead to system overheating, efficiency loss, and overall system failure. It is advantageous to monitor the performance of the power module 200 and predict when the performance exceeds a critical point to avoid unexpected system failures, such as shutdown of automotive applications.

[0034] The power module 200 may also include an external connector 204. The external connector 204 may be a pin, an inline package switch, etc., which may be electrically and / or physically coupled to a metallization layer of the package substrate 202. External devices (such as devices implementing the power module 200) may be connected to the power electronic circuit through the external connector 204.

[0035] Additional features may be included in the power module 200. In some embodiments, the power module 200 further includes a passivation layer (not separately shown). The passivation layer is formed on the package substrate 202, the power semiconductor die 100, the wire bonds, any other circuit elements (if present), etc., so that the passivation layer covers and protects the components of the power module 200.

[0036] In order to monitor the health of a power module such as power module 200, it is advantageous to use dedicated instruments to monitor parameters such as gate-source voltage (V GS ), drain-source voltage (V DS ), and the current at the drain terminal of the power module (I D ). These parameters can be measured to determine if the power module has reached the effective end of its life due to, for example, thermal damage to the wire bonds. For some devices such as SiC power modules, the source-drain voltage (V SD ) can be useful.

[0037] Figure 3A 1 shows a block diagram of a system 300 for monitoring voltage drift of a power module 200 to monitor and predict the health of the power module 200 according to some embodiments. The system 300 includes a power module 200 (e.g., as described above in Figure 1A , Figure 1B and Figure 2), the power module 200 is coupled to a controller 302 to provide drain-source voltage data. In some embodiments, the controller 302 is a microcontroller unit (MCU), such as a small computer on a single very large scale integrated circuit (VLSI) integrated circuit chip, and in some embodiments may also be part of a distributed system. However, the controller 302 may be any suitable processing unit(s), microcontroller unit(s), microprocessor(s), etc., or a combination thereof.

[0038] Controller 302 includes an analog-to-digital converter (ADC) 304 and an AI model 400. ADC 304 may be part of the same chip as the rest of controller 302 (e.g., an MCU), or may be an integrated circuit on a separate chip coupled to the rest of controller 302. In some embodiments, ADC 304 is a 12-bit ADC. However, ADC 304 may be any suitable analog-to-digital converter and may have any suitable number of bits, such as 8 to 16 bits.

[0039] The AI ​​model 400 is implemented in the programming of the controller 302 through instructions contained in a non-transitory memory such as software, firmware, hardware, or a combination thereof. For example, the AI ​​model 400 may be loaded into the firmware of the controller 302. However, the controller 302 may also be programmed with the AI ​​model 400 through software instructions, or the controller 302 may contain instructions for the AI ​​model 400 in its hardware (e.g., as an ASIC). As described below with respect to Figure 5 As described, the AI ​​model 400 can be a deep learning system, such as a transformer-based model. In some embodiments, the AI ​​model 400 is a time-fusion transformer (TFT) embedded in a layer of a time convolutional network (TCN) with a multi-head attention block. In some embodiments, the multi-head attention block uses 10 heads. However, the multi-head attention block can have any suitable number of heads.

[0040] like Figure 3AAs shown, the power module 200 provides an input (e.g., a drain-source voltage) to the ADC 304. Next, the ADC 304 converts the analog voltage signal from the power module 200 into a digital signal and provides the digital signal to the AI ​​model 400 in the controller 302. The AI ​​model 400 uses the digital signal to generate a voltage prediction 308, which can be used to predict future degradation of the performance of the power module 200. The voltage prediction 308 can be used to predict the beginning of performance degradation of the power module 200 and to monitor the health of the power module 200, because voltage drift can be used as an early marker of performance degradation. For example, the controller 300 can be programmed to generate an alarm message and display the alarm message to the user if it is predicted that the performance degradation of the power module 200 will occur within a set time range, such as within twenty weeks of additional use. However, any suitable method can be performed by the controller 300 to predict future power module degradation and warn the user.

[0041] Figure 3B An example voltage versus time graph of a drain-source voltage measured across a body diode of a power module (e.g., a SiC power module) according to some embodiments is shown. The drain-source voltage may be used as an input to the AI ​​model 400, such as an analog voltage signal converted to a digital signal by the ADC 304.

[0042] Figure 4 Graphs of experimental results showing predicted and actual drain-source voltages versus time according to some embodiments show a power module reaching the end of its useful life taken from a power cycling test. The actual drain-source voltage across the body diode of a power module 200 (e.g., a SiC power module) may be measured, and the predicted drain-source voltage may be taken from the AI ​​model 400 (see above, Figure 3A ). Power cycling can be used to test the interface reliability (e.g., wire bonding) of a power module to simulate accelerated aging compared to normal power module use.

[0043] In a power cycling test, a high DC current is cyclically supplied to a power module in order to generate device self-heating in the power module. During the cooling phase (in other words, when the high DC current is disconnected), a sense current (e.g., a voltage probe from a voltage sensor such as a multimeter) flows through the body diode of the power module in order to measure a drain-source voltage that is linearly related to a virtual junction temperature (in other words, a temperature representing the temperature of the (multiple) junctions of the power module calculated based on a simplified model of the thermal and electrical behavior of the semiconductor device). The virtual junction temperature can be used as a parameter for measuring and predicting thermal fatigue of the power module. The relevant physical parameters of thermal fatigue (e.g., device temperature fluctuations and coolant temperature) can be set at the beginning of the power cycling test. During the power cycling test, the drain-source voltage is monitored. Each time sample in the power cycling test can correspond to one week of real-time power module use in an automotive application (e.g., in automotive applications such as cooling systems for traction drives of electric vehicles).

[0044] Dashed line 320 is the average of the predicted drain-source voltage and the actual drain-source voltage after the effective end of life has been reached, and dashed line 330 is the time at which the end of life is reached. The effective end of the operating life of the power module (also called the end of life of the power module) is characterized by the degradation of interfaces such as wire bonds. This can be seen by the resistance R between the drain and source of the body diode. DS_ON A significant increase in R DS_ON A drift equal to or greater than 5% can be considered confirmation of device electrical death, beyond which the device should not be used further.

[0045] R DS_ON The actual measurement may involve the measurement of voltage and current in the bridge of the power module. Because of this, the voltage between the drain and source of the bridge (also referred to as the low-side drain-source voltage (V DS_LS ) and the high-side drain-source voltage (V DS_HS )) can be used as a proportional end-of-life marker because it is proportional to R DS_ON In direct proportion. Figure 4 , an example of the low side drain source voltage is shown, which shows that when the end of the life of the device is reached at the dashed line 330, the predicted and actual low side drain source voltage drifts over time. Figure 4 As shown, the predicted value of the drain-source voltage matches the actual value of the drain-source voltage very well.

[0046] Figure 5A block diagram of an example AI model 400 implemented using a converter-based deep learning system according to some embodiments is shown. The AI ​​model 400 retrieves long-term temporal dependencies in an input signal (e.g., drain-source voltage from a power module) in order to predict future values ​​of the input signal, such as predicting the end of the life of the power module. The converter combines self-attention mechanisms, parallelism, and position encoding. Figure 5 As shown, the example AI model 400 includes an encoder 410 and a decoder 450. The encoder 410 includes an input layer 412, a position encoding layer 414, a first encoder layer 420, and a second encoder layer 430. The first encoder layer includes a self-attention layer 422, a first addition and normalization layer 424, a feedforward layer 426, and a second addition and normalization layer 430. The input layer 412 parses the input (e.g., a digitized drain-source voltage signal from the power module 200) into tags (e.g., tags T1, T2, T3, and T4), which are converted into vectors through word embedding. The position encoding layer 414 then adds the position information of the tag to the word embedding of the vector.

[0047] Next, the encoding layers (e.g., the first encoder layer 420 and the second encoder layer 430) of the encoder 410 iteratively process the input layer by layer. Each encoder layer utilizes an attention mechanism (e.g., a self-attention layer 422). For each part of the input, the attention mechanism weights the relevance of each other part and draws from it to produce an output. Each encoder sublayer (e.g., the first encoder layer 420 and the second encoder layer 430) of the encoder 410 layer generates an encoding containing information about which parts of the input are related to each other. Each encoder sublayer then passes its encoding as input to the next encoder sublayer. For example, the self-attention layer 422 (which may include a multi-head attention head) encodes the correlation relationship between each tag. In the context of the current disclosure, this can be used to predict future voltage drifts in a power module based on past voltage drifts used in the training of the AI ​​model 400.

[0048] The self-attention layer 422 then passes its encoding to a first addition and normalization layer 424, which adds and normalizes the encoding based on the weights from the self-attention layer 422. The first addition and normalization layer 424 then passes its encoding to a feedforward layer 426. This can be a feedforward neural network for additional processing of the encoding, which includes residual connections and additional layer normalization steps. Next, the feedforward layer 426 passes the encoding to a second addition and normalization layer 428, which adds and normalizes the encoding based on the weights from the feedforward layer 426. Although the first encoder layer 420 is shown as having one self-attention layer, two addition and normalization layers, and one feedforward layer, the first encoder layer 420 can have any suitable number and arrangement of encoder sublayers, and all such combinations are within the scope of the disclosed embodiments.

[0049] The first encoder layer 420 then passes its encoding to the second encoder layer 430, which can have a similar structure and similar encoder sublayers as the first encoder layer 420. Therefore, these details are not repeated here. The second encoder layer 430 then passes its encoding (e.g., markers T4 and T5) to the decoder 450.

[0050] The decoder 450 includes decoding sublayers that iteratively process the output of the encoder 410, layer by layer. Each decoder layer of the decoder 450 performs in the opposite manner to the encoder layer of the encoder 410 by receiving the codes from the encoder 410 and using its incorporated context information to produce an output sequence. The decoder 450 includes an input layer 452, a first decoder layer 460, a second decoder layer 480, and a linear mapping layer 490. The input layer 452 receives the codes (e.g., tags T4 and T5) from the encoder 410 and passes them to the first decoder layer 460.

[0051] exist Figure 5 In the example shown, a first decoder layer 460 of the decoder 450 includes a self-attention layer 462, a first summation and normalization layer 464, an encoder-decoder attention layer 466, a second summation and normalization layer 468, a feed-forward layer 470, and a third summation and normalization layer 472. Each decoder layer has an additional attention mechanism (e.g., encoder-decoder attention layer 466) that draws information from the output of the previous decoder layer before the decoder layer draws information from the encoding.

[0052] The self-attention layer 462 can encode the correlation relationship between each token in a similar manner as described above with respect to the self-attention layer 422. The self-attention layer 462 then passes its output to the first addition and normalization layer 464, which adds and normalizes the output based on the weights from the self-attention layer 462. The first addition and normalization layer 464 then passes its encoding to the encoder-decoder attention layer 466, which draws information from the output of the previous decoder layer. The encoder-decoder attention layer 466 passes its output to the second addition and normalization layer 468, which adds and normalizes the output based on the weights from the encoder-decoder attention layer 466. The second addition and normalization layer 468 passes its output to the feedforward layer 470, which can be a feedforward neural network for additional processing of encoding, which includes residual connections and additional layer normalization steps. The feed-forward layer 470 passes the codes to a third addition and normalization layer 472 , which adds and normalizes the codes based on the weights from the feed-forward layer 470 .

[0053] Although the first decoder layer 450 is shown as having one self-attention layer, one feed-forward layer, one encoder-decoder layer, and three addition and normalization layers, the first decoder layer 450 may have any suitable number and arrangement of decoder sub-layers, and all such combinations are within the scope of the disclosed embodiments.

[0054] The first decoder layer 450 then passes its output to the second decoder layer 480, which can have a similar structure and similar encoder sublayers as the first decoder layer 450. Therefore, these details are not repeated here. Next, the second decoder layer 480 passes its output to the linear mapping layer 490, which maps the output to tags (e.g., tags T5 and T6). Tags T5 and T6 are predicted as the next tags in the sequence of tags T1 to T4 and can be compared with actual data to further train the AI ​​model 400.

[0055] although Figure 4 The example illustrates that the encoder 410 and the decoder 450 each have two corresponding encoder and decoder layers, but the encoder 410 and the decoder 450 can each have any suitable number of encoder and decoder layers (e.g., five encoders and decoders), and all such combinations are within the scope of the disclosed embodiments.

[0056] In some embodiments, the transformer-based deep learning system of the AI ​​model 400 is a time fusion transformer (TFT). TFT is an attention-based deep neural network that can be used for multi-horizon data forecasting. An example of TFT is described in: "B. Lim, S. O. Arik, N. Loeff, and T. Pfister, 'Temporal fusion transformers for interpretable multi-horizon time series forecasting, 'International Journal of Forecasting, vol. 37, no. 4, pp. 1748–1764, 2021. [Online]. Available: https: / / www.sciencedirect.com / science /

[0057] article / pii / S0169207021000637", which is incorporated herein by reference in its entirety.

[0058] The time fusion transformer (TFT) consists of a multi-layer encoder-decoder architecture combined with a self-attention mechanism to capture and model time dependencies. The encoder receives the input sequential data and uses a self-attention layer to calculate the contextualized representation at each time step. The self-attention mechanism allows TFT to weigh the importance of different elements in the sequence (e.g., the voltage drift of the drain-source voltage data from a power module undergoing a power cycle test) by considering both local and global information. This enables TFT to capture long-range dependencies and contextual relationships throughout the sequence. This is conducive to predicting the future behavior of time-dependent data sequences, such as voltage drifts from the drain-source voltage of a power module.

[0059] The decoder component of TFT further enhances the analysis and prediction capabilities by fusing temporal information from multiple time steps. Through the fusion process, the decoder leverages the contextualized representations obtained from the encoder to generate accurate predictions or perform downstream tasks on sequence data. Temporal fusion enables TFT to incorporate historical information while making predictions, thereby improving the overall accuracy and robustness of the system.

[0060] In addition, TFT can be extended to include additional components, such as positional encoding, feedforward neural networks, or auxiliary tasks to enhance its performance and adaptability to specific applications. These extensions allow TFT to process sequential data with different characteristics and domain-specific requirements.

[0061] TFT is able to achieve high performance relative to classic deep architectures commonly used for 1D time series prediction, such as long short-term memory (LSTM) networks, temporal convolutional neural (TCN) networks, etc. TFT includes internal processing blocks such as: a static covariant encoder block, which is used to encode a context vector of additional input data, which can be used to improve the overall prediction performance of TFT; a gated residual network (GRN) combined with a variable selection layer, which can reduce the impact of irrelevant input data; a sequence-to-sequence (Seq2Seq) encoding / decoding block, which is used to perform local encoding / decoding on input data including past input data and known future input data (where the past and future are measured relative to a certain time point in the input data sequence); and a temporal self-attention decoder, which is used to learn long-term dependencies embedded in the input data. In addition, in some embodiments, TFT uses a temporal convolutional neural network. An example of a TCN is described in: "S. Bai, JZ Kolter, and V. Koltun, 'An empirical evaluation of generic convolutional and recurrent networks for sequence modeling,' ArXiv, vol. abs / 1803.01271, 2018," which is incorporated herein by reference in its entirety.

[0062] TCN is a deep architecture with causal convolutional embedding. In other words, TCN can process inputs assuming that no information leakage from future data samples to past data samples occurs. Past data and future samples are measured relative to a certain point in time in the input data sequence, so future samples refer to samples that already exist in the input data sequence, not samples that have not yet been measured. For example, TCN can take an input sequence of any length and map it to an output sequence of the same length. TCN can outperform classical deep architectures including recurrent networks and linear regressors in time series prediction. Sequence-to-sequence (Seq2Seq) encoding / decoding of preprocessed input data in TCN can provide intelligent evaluation of time series data. Using local correlations between time series data, distinguishing features are constructed to improve downstream performance of processing based on deep system embedding attention. The distinction between input past data and input future samples enables the implemented pipeline to embed deep layers for encoding past data and decoding future samples.

[0063] The AI ​​model 400 also includes an adversarial compensation model, such as a model using Jacobian regularization, to compensate for noise in the drain-source voltage input. In some embodiments, the back propagation algorithm calculates the gradient of the loss function relative to the weights of the network (e.g., a feedforward neural network) of the AI ​​model 400. The loss function can be a mean square error (MSE) loss function. However, any suitable loss function can be used. Any suitable optimization algorithm, such as a stochastic gradient descent (SGD) optimizer or an Adam optimizer, can be used. In some embodiments, the learning rate (LR) value of the optimizer is set to 0.0001.

[0064] The weights of the loss function are trained by back-propagation, which is the propagation of error contributions (via gradients) through the weights of the network. Using Jacobi regularization, the gradients can be forced to keep oscillations caused by noise in the drain-source voltage input within a desired range, such as within 5% of the maximum voltage input value.

[0065] In some embodiments, the AI ​​model 400 is trained using a power cycling method when the AI ​​model 400 is running on, for example, a server having one or more GPU cores. The AI ​​model 400 may be trained for an appropriate amount of time. In some embodiments, the AI ​​model 400 is trained for ten to two hundred epochs, such as one hundred epochs. The trained AI model 400 may then be loaded into a microcontroller unit (e.g., controller 302; see above). Figure 3A ) in the firmware.

[0066] Fig. 6A and Figure 6B A graph of experimental data comparing the actual voltage drift of the drain-source voltage of a power module with the predicted voltage drift from an AI model (eg, AI model 400 ) is shown. Fig. 6A 4 shows the actual measured drain-source voltage trace 492 over 30,000 time steps overlaid with the predicted drain-source voltage trace 494, Figure 6B Traces 492 and 494 are shown over a window of 24500 to 26750 time steps. Each time step corresponds to a power cycle step, which is equivalent to a certain time interval, depending on the type of power module being tested, the technology being tested, etc. On average, the time mapping of one time step to one week of regular operation of the power module can be a good approximation, although this relationship may vary depending on the technological characteristics of the monitored device. In the case of a time mapping of one time step to one week of regular operation, trace 494 predicts a predicted voltage drift of 20 steps, which is equivalent to predicting the voltage drift 20 weeks in advance. As Fig. 6A and 6BAs shown, the predicted drain-source voltage of trace 494 closely matches the actual drain-source voltage, including a significant voltage increase at approximately time step 25,000 when the power module reaches an end-of-life condition due to interface degradation. The vertical offset in amplitude between traces 492 and 494 exists due to the physics of the system, but does not affect the accuracy of the prediction of the behavior of the predicted drain-source voltage of trace 494 with respect to the actual drain-source voltage of trace 492. Therefore, Fig. 6A and Figure 6B It shows that the AI ​​model 400 can be used to predict the health of the power module for a considerable period of time in advance (e.g., twenty weeks).

[0067] Figure 7 A table showing the error values ​​between the predicted drain-source voltage of the power module (such as predicted by the AI ​​model 400) and the actual measured drain-source voltage of the power module within various pre-prediction step sizes, including pre-prediction step sizes of 5, 10, 20, 30, and 50. The values ​​of mean absolute error, mean square error, root mean square error, mean percentage error, and mean absolute percentage error are shown. Thus, the minimum value of the mean absolute percentage error (7.3717) is obtained with a pre-prediction interval of 20 steps, which is equivalent to 20 weeks of conventional power module operation in an automotive application.

[0068] Figure 8 FIG. 5 is a flow chart of a method 500 for monitoring the health of a power device according to some embodiments. In step 502, a first power device (eg, power module 200; see above) is used to monitor the health of a power device. Figure 2 ) is used to train an AI model (e.g., AI model 400; see above, Figure 3A In step 504, the trained AI model is loaded into a microcontroller (e.g., controller 302; see above, Figure 3A ). In step 506, the trained AI model is used to predict when a second power device (eg, another power module 200) will reach the end of its operating life. The second power device is coupled to the microcontroller.

[0069] Fig. 9 6 is a flow chart of a method 600 for monitoring voltage drift according to some embodiments. In step 602, a voltage across a diode of a power module 200 is measured. In step 604, the measured voltage is provided as an input to a controller 300, which is configured to run a converter-based model (e.g., AI model 400), as described above with respect to Figure 3A The transformer-based models include a temporal fusion transformer with a temporal convolutional neural network and an adversarial compensation model with a back-propagation algorithm, as described above. Figure 5 In step 606, a range of expected future values ​​of the voltage across the diode of the power module is predicted using a converter-based model, as described above with respect to Figure 6A-6B described.

[0070] Embodiments can achieve advantages. An AI-based algorithm can robustly characterize health monitoring of power modules and predict future performance degradation. The AI-based algorithm can be trained using drain-source voltage inputs generated by repeatedly power cycling the power module. The AI-based algorithm includes techniques such as regularization of the Jacobian order of the gradient of the input. This can compensate for measurement and conversion noise that may occur in a controller-based (e.g., microcontroller unit) system. The AI-based algorithm can accurately predict power module failures weeks in advance by monitoring drain-source voltage drift as a predictive marker.

[0071] Example embodiments of the present disclosure are summarized here. Other embodiments may also be understood from the entirety of the specification and the claims filed herein.

[0072] Example 1. A method for monitoring voltage drift, the method comprising:

[0073] Measuring the voltage across the diode of the power device;

[0074] providing the measured voltage as an input to a controller configured to run a transformer-based model, wherein the transformer-based model includes a temporal fusion transformer having a temporal convolutional neural network, and the transformer-based model further includes an adversarial compensation model having a back-propagation algorithm; and

[0075] A converter-based model is utilized to predict a range of expected future values ​​of the voltage across a diode of a power device.

[0076] Example 2. The method of Example 1, wherein the adversarial compensation model is configured to utilize Jacobian regularization to compensate for noise.

[0077] Example 3. The method of any of Examples 1 or 2, further comprising training the converter-based model using a power cycling test.

[0078] Example 4. The method of any of Examples 1 to 3, further comprising predicting when the power device will reach the end of its operational lifetime based on a range of expected future values ​​of a voltage across a diode of the power device.

[0079] Example 5. The method of any one of Examples 1 to 4, wherein the temporal fusion transformer comprises a multi-head attention block.

[0080] Example 6. A method according to any one of Examples 1 to 5, wherein the back-propagation algorithm calculates the gradient of a loss function, and the loss function is a mean square error (MSE) loss function.

[0081] Example 7. A method for monitoring the health of a power device, the method comprising:

[0082] training an artificial intelligence model using a voltage input generated by power cycling a first power device;

[0083] Loading the trained AI model into the microcontroller’s firmware; and

[0084] The trained artificial intelligence model is used to predict when a second power device will reach the end of its operating life, the second power device being coupled to the microcontroller.

[0085] Example 8. The method of Example 7, wherein the voltage input is a drain-source voltage across a body diode of the first power device.

[0086] Example 9. The method of any of Examples 7 or 8, wherein the first power device and the second power device include silicon carbide MOSFETs.

[0087] Example 10. A method according to any of Examples 7 to 9, wherein the trained artificial intelligence model predicts when the second power device reaches the end of its operating life at least two weeks before the end of the operating life of the second power device.

[0088] Example 11. A method according to any one of Examples 7 to 10, wherein the artificial intelligence model includes a time fusion transformer.

[0089] Example 12. The method of Example 11, wherein the temporal fusion transformer comprises a temporal convolutional neural network.

[0090] Example 13. A method according to any of Examples 7 to 12, wherein training the artificial intelligence model includes using an adversarial compensation model with Jacobi regularization.

[0091] Example 14. The method of any of Examples 7 to 13, wherein the second power device is coupled to an electric traction drive.

[0092] Example 15. The method of any of Examples 7 to 14, wherein the first power device and the second power device are different power devices.

[0093] Example 16. A system for monitoring voltage drift, the system comprising:

[0094] Power devices;

[0095] non-transitory memory, the non-transitory memory including the program; and

[0096] A microprocessor is coupled to a non-volatile memory and a power device, the microprocessor being configured to execute a program, the program including a converter-based model, wherein the converter-based model includes a time fusion converter having a time convolutional neural network, the converter-based model also includes an adversarial compensation model having a back-propagation algorithm, and based on the converter-based model, a voltage drift of the power device is monitored and a future voltage drift of the power device is predicted.

[0097] Example 17. The system of Example 16, wherein the non-volatile memory is firmware.

[0098] Example 18. The system of any of Examples 16 or 17, wherein the power device is a SiC power device.

[0099] Example 19. The system of any of Examples 16 to 18, wherein the power device is coupled to a cooling system of the traction drive.

[0100] Example 20. The system of any of Examples 16 to 19, wherein the program further comprises instructions for generating an alarm message in response to determining that degradation in performance of the power device is predicted to occur within twenty weeks of additional use.

[0101] Although the present invention has been described with reference to exemplary embodiments, this description should not be construed as having a limiting meaning. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be clear to those skilled in the art with reference to the specification. Therefore, the appended claims are intended to include any such modifications or embodiments.

Claims

1. A method for monitoring voltage drift, the method comprising: Measuring the voltage across the diode of the power device; providing the measured voltage as an input to a controller configured to run a transformer-based model, wherein the transformer-based model includes a temporal fusion transformer having a temporal convolutional neural network, and the transformer-based model also includes an adversarial compensation model having a back-propagation algorithm; and A range of expected future values ​​of the voltage across the diode of the power device is predicted using the converter-based model.

2. The method of claim 1, wherein the adversarial compensation model is configured to utilize Jacobian regularization to compensate for noise. 3 . The method of claim 1 , further comprising training the converter-based model using a power cycling test. 4 . The method of claim 1 , further comprising predicting when the power device will reach the end of its operating lifetime based on the range of expected future values ​​of the voltage across the diode of the power device. The method of claim 1 , wherein the temporal fusion transformer comprises a multi-head attention block.

6. The method according to claim 1, wherein the back propagation algorithm calculates the gradient of a loss function, and the loss function is a mean square error (MSE) loss function.

7. A method for monitoring the health of a power device, the method comprising: training an artificial intelligence model using a voltage input generated by power cycling a first power device; Loading the trained AI model into the microcontroller’s firmware; as well as The trained artificial intelligence model is used to predict when a second power device will reach the end of its operating life, the second power device being coupled to the microcontroller. 8 . The method of claim 7 , wherein the voltage input is a drain-source voltage across a body diode of the first power device. 9 . The method of claim 7 , wherein the first power device and the second power device comprise silicon carbide MOSFETs.

10. The method of claim 7, wherein the trained artificial intelligence model predicts when the second power device reaches the end of its operating lifetime at least two weeks before the end of the operating lifetime of the second power device.

11. The method of claim 7, wherein the artificial intelligence model comprises a time fusion transformer.

12. The method of claim 11, wherein the temporal fusion transformer comprises a temporal convolutional neural network.

13. The method of claim 7, wherein training the artificial intelligence model comprises using an adversarial compensation model with Jacobi regularization.

14. The method of claim 7, wherein the second power device is coupled to an electric traction drive.

15. The method of claim 7, wherein the first power device and the second power device are different power devices.

16. A system for monitoring voltage drift, the system comprising: Power devices; Non-transitory memory, including programs; as well as A microprocessor is coupled to the non-volatile memory and the power device, the microprocessor is configured to execute the program, the program includes a converter-based model, wherein the converter-based model includes a time fusion converter with a time convolutional neural network, the converter-based model also includes an adversarial compensation model with a back-propagation algorithm, and based on the converter-based model, the voltage drift of the power device is monitored and the future voltage drift of the power device is predicted.

17. The system of claim 16, wherein the non-volatile memory is firmware.

18. The system of claim 16, wherein the power device is a SiC power device.

19. The system of claim 16, wherein the power device is coupled to a cooling system of a traction drive.

20. The system of claim 16, wherein the program further comprises instructions for generating an alarm message in response to determining that degradation in performance of the power device is predicted to occur within twenty weeks of additional use.

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