SRAM (Static Random Access Memory) data protection method and system, computer equipment, medium and product

Abstract

The invention discloses an SRAM (Static Random Access Memory) data protection method and system, computer equipment, a medium and a product, and relates to the technical field of data protection, the disclosed SRAM data protection method comprises the following steps: determining a random number corresponding to each address interval, and taking the address interval corresponding to a to-be-executed program as a target address interval; determining a first target address of each piece of data in the to-be-executed program in the target address interval; based on the random number corresponding to the target address interval, performing XOR on each first target address to obtain each second target address, and performing XOR on each piece of data to obtain each piece of target data; based on a first corresponding relation between each piece of data and each first target address, determining a second corresponding relation between each piece of target data and each second target address; and based on the second corresponding relationship, storing each target data corresponding to the to-be-executed program to each second target address. The technical scheme of the invention aims to solve the technical problem of how to improve the security of data stored in the SRAM.

Description

Technical Field

[0001] The present application relates to the field of data protection technology, and in particular to a SRAM data protection method, system, computer equipment, medium and product. Background Art

[0002] SRAM (Static Random-Access Memory) is a commonly used storage unit. However, the traditional memory protection unit does not protect the SRAM itself, causing the processor to leak sensitive information through the current and photons emitted by the SRAM circuit structure when accessing the SRAM. At the same time, hackers can also directly change the data stored in the SRAM by laser photon injection. Therefore, the traditional memory protection unit has no protection against attacks against SRAM.

[0003] Therefore, how to improve the security of SRAM stored data is a technical problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] The main purpose of this application is to provide a SRAM data protection method, system, computer device, medium and product, aiming to solve the technical problem of how to improve the security of SRAM stored data.

[0005] To achieve the above object, the present application proposes a SRAM data protection method, the method comprising:

[0006] Determine the random number corresponding to each address interval in the SRAM, and use the preset address interval corresponding to the program to be executed as the target address interval;

[0007] Determine, in the target address interval, first target addresses corresponding to respective data in the program to be executed;

[0008] Based on the random number corresponding to the target address interval, performing an XOR operation on each of the first target addresses to obtain each second target address, and based on the random number corresponding to the target address interval, performing an XOR operation on each of the data to obtain each target data;

[0009] Determining a second corresponding relationship between each of the target data and each of the second target addresses based on a first corresponding relationship between each of the data and each of the first target addresses;

[0010] Based on the second corresponding relationship, each of the target data corresponding to the program to be executed is stored at each of the second target addresses.

[0011] In one embodiment, the step of storing each of the target data corresponding to the program to be executed at each of the second target addresses based on the second corresponding relationship includes:

[0012] Correcting the errors of the target data by using an error correction code to obtain the target data after error correction;

[0013] Based on the second corresponding relationship, each of the target data after error correction is stored at each of the second target addresses.

[0014] In one embodiment, the address interval includes various storage addresses, and the storage addresses in each of the address intervals are arranged in an alternating manner.

[0015] In one embodiment, after the step of determining the random number corresponding to each address interval in the SRAM, the method further includes:

[0016] Each of the random numbers is written into each of the address intervals to erase the sensitive data in each of the address intervals.

[0017] In one embodiment, after the step of storing each of the target data corresponding to the to-be-executed program at each of the second target addresses based on the second corresponding relationship, the method further includes:

[0018] When executing the program to be executed, determining an address to be accessed based on each of the target data;

[0019] Determining whether each of the to-be-accessed addresses is legal based on a preset address interval attribute corresponding to the target address interval;

[0020] If it is determined that each of the addresses to be accessed is legal, integrity check is performed on the data stored in each of the addresses to be accessed;

[0021] If it is detected that the stored data in each of the to-be-accessed addresses passes the integrity check, the stored data are processed based on each of the target data.

[0022] In one embodiment, the step of judging whether each of the to-be-accessed addresses is legal based on the preset address interval attribute corresponding to the target address interval includes:

[0023] If it is detected that each of the to-be-accessed addresses matches a preset address interval attribute corresponding to the target address interval, then it is determined that each of the to-be-accessed addresses is legal;

[0024] Otherwise, it is determined that each of the addresses to be accessed is illegal.

[0025] In addition, to achieve the above purpose, the present application also proposes an SRAM data protection system, the SRAM data protection system comprising:

[0026] A random number generation module is used to determine the random number corresponding to each address interval in the SRAM, and use the preset address interval corresponding to the program to be executed as the target address interval;

[0027] A first address determination module, used to determine, in the target address interval, first target addresses corresponding to respective data in the program to be executed;

[0028] an XOR module, configured to perform an XOR operation on each of the first target addresses based on a random number corresponding to the target address interval to obtain each second target address, and perform an XOR operation on each of the data based on a random number corresponding to the target address interval to obtain each target data;

[0029] a correspondence determination module, configured to determine a second correspondence between each of the target data and each of the second target addresses based on a first correspondence between each of the data and each of the first target addresses;

[0030] The data storage module is used to store each of the target data corresponding to the program to be executed at each of the second target addresses based on the second corresponding relationship.

[0031] In addition, to achieve the above objectives, the present application also proposes a computer device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the SRAM data protection method as described above.

[0032] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the SRAM data protection method described above are implemented.

[0033] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the SRAM data protection method described above are implemented.

[0034] In the present application, the present application determines the random numbers corresponding to each address interval in the SRAM, and uses the preset address interval corresponding to the program to be executed as the target address interval, so as to determine a random number for each address interval, thereby reducing the success rate of the attack; then, in the target address interval, the first target address corresponding to each data in the program to be executed is determined, and the address corresponding to each data can be obtained on the premise of storing the data in sequence; then, based on the random number corresponding to the target address interval, each first target address is XORed to obtain each second target address, and based on the random number corresponding to the target address interval, each data is XORed to obtain each target data, and the address and the data to be stored can be changed based on the random number, so that the data will be randomly distributed in the target address interval; then, based on the first corresponding relationship between each data and each first target address, the second corresponding relationship between each target data and each second target address is determined, and the corresponding relationship between the address and the data can be determined after the XOR processing; finally, based on the second corresponding relationship, each target data corresponding to the program to be executed is stored at each second target address.

[0035] In this application, the address and the data to be stored can be XORed by a random number, so that the specific storage address of the data is random, and the stored data itself will also be affected by the random number. In this way, attacks on SRAM will not be successful due to the inability to determine the random number, thereby improving the security of SRAM storage data. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0038] Figure 1 A flowchart of the first embodiment of the SRAM data protection method of the present application is provided;

[0039] Figure 2 This is a schematic diagram of data correspondence relationship of XOR processing in an embodiment of the SRAM data protection method of the present application;

[0040] Figure 3 A schematic diagram of staggered arrangement of storage addresses in an embodiment of an SRAM data protection method of the present application;

[0041] Figure 4 A schematic diagram showing each storage address arranged in order;

[0042] Figure 5 This is a structural diagram of a specific embodiment of the SRAM data protection method of the present application;

[0043] Figure 6 A schematic diagram of an address management unit of a specific embodiment of the SRAM data protection method of the present application;

[0044] Figure 7 This is a schematic diagram of the module structure of the SRAM data protection system of the embodiment of the present application;

[0045] Figure 8 Schematic diagram of the device structure of the hardware operating environment involved in the SRAM data protection method in the embodiment of the present application.

[0046] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0047] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0048] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0049] The main solution of the present application is: determine the random numbers corresponding to each address interval in the SRAM, and use the preset address interval corresponding to the program to be executed as the target address interval; determine the first target addresses corresponding to each data in the program to be executed in the target address interval; based on the random numbers corresponding to the target address interval, perform XOR on each of the first target addresses to obtain each second target address, and based on the random numbers corresponding to the target address interval, perform XOR on each of the data to obtain each target data; based on the first corresponding relationship between each of the data and each of the first target addresses, determine the second corresponding relationship between each of the target data and each of the second target addresses; based on the second corresponding relationship, store each of the target data corresponding to the program to be executed at each of the second target addresses.

[0050] SRAM (Static Random-Access Memory) is a commonly used storage unit. However, the traditional memory protection unit does not protect the SRAM itself, causing the processor to leak sensitive information through the current and photons emitted by the SRAM circuit structure when accessing the SRAM. At the same time, hackers can also directly change the data stored in the SRAM by laser photon injection. Therefore, the traditional memory protection unit has no protection against attacks against SRAM.

[0051] Therefore, how to improve the security of SRAM stored data is a technical problem that needs to be solved by those skilled in the art.

[0052] To solve the above problems, the present application determines the random numbers corresponding to each address interval in the SRAM, and uses the preset address interval corresponding to the program to be executed as the target address interval, so as to determine a random number for each address interval, thereby reducing the success rate of the attack; then, in the target address interval, the first target address corresponding to each data in the program to be executed is determined, and the address corresponding to each data can be obtained on the premise of storing the data in sequence; then, based on the random number corresponding to the target address interval, each first target address is XORed to obtain each second target address, and based on the random number corresponding to the target address interval, each data is XORed to obtain each target data, and the address and the data to be stored can be changed based on the random number, so that the data will be randomly distributed in the target address interval; then, based on the first corresponding relationship between each data and each first target address, the second corresponding relationship between each target data and each second target address is determined, and the corresponding relationship between the address and the data can be determined after the XOR processing; finally, based on the second corresponding relationship, each target data corresponding to the program to be executed is stored at each second target address.

[0053] In this application, the address and the data to be stored can be XORed by a random number, so that the specific storage address of the data is random, and the stored data itself will also be affected by the random number. In this way, attacks on SRAM will not be successful due to the inability to determine the random number, thereby improving the security of SRAM storage data.

[0054] It should be noted that the execution subject of the SRAM data protection method of the present application can be a computer device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc. The following takes a computer as an example to illustrate various embodiments of the SRAM data protection method of the present application.

[0055] Based on this, the present application embodiment provides a SRAM data protection method, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the SRAM data protection method of the present application.

[0056] In this embodiment, the SRAM data protection method includes steps S10 to S50:

[0057] Step S10, determining the random numbers corresponding to the respective address intervals in the SRAM, and taking the preset address interval corresponding to the program to be executed as the target address interval;

[0058] It should be noted that, for SRAM, the SRAM can be divided into multiple address intervals, and a random number for increasing the difficulty of attack is generated for each address interval. The target address interval can be an address interval pre-set for the program to be executed.

[0059] Step S20, determining in the target address interval the first target addresses corresponding to the respective data in the program to be executed;

[0060] It is understandable that after determining the target address interval, the start address for storing the program to be executed can be determined in the target address interval, and based on the start address and the data in the program to be executed, the address corresponding to each data can be determined, thereby obtaining the first target address corresponding to each data in the program to be executed.

[0061] Step S30, performing XOR on each of the first target addresses based on the random number corresponding to the target address interval to obtain each second target address, and performing XOR on each of the data based on the random number corresponding to the target address interval to obtain each target data;

[0062] It can be understood that, in this embodiment, by performing XOR on the first target address and performing XOR on each data in the program to be executed, the randomness of the stored data is increased, thereby improving the security of the data.

[0063] Step S40, determining a second corresponding relationship between each of the target data and each of the second target addresses based on the first corresponding relationship between each of the data and each of the first target addresses;

[0064] Please refer to Figure 2 , Figure 2 Schematic diagram of data correspondence for XOR processing is shown. Figure 2For data 7, the first corresponding relationship is: data 7 corresponds to 0b0111, and the second corresponding relationship is: data 7⊕ random number corresponds to 0b0000. Similarly, for data 6, the first corresponding relationship is: data 6 corresponds to 0b0110, and the second corresponding relationship is: data 6⊕ random number corresponds to 0b0111. Figure 2 It can be seen that the present application can use random numbers to randomly distribute data in the target address range, thereby further improving the security of stored data.

[0065] For example, when the target address range is 0x0000 to 0x0FFF, assuming there are three groups of addresses:

[0066] Address 1:3 (binary: 011);

[0067] Address 2: 5 (binary: 101);

[0068] Address 3:7 (binary: 111);

[0069] When the random number is 6 (binary: 110), perform an XOR operation on the random number 6 and the above address:

[0070] Address 1 and 6 are exclusive ORed:

[0071] 011 (address 1),

[0072] 110 (random number 6),

[0073] Result: 101 (binary), converted to decimal is 5;

[0074] Address 2 is XORed with 6:

[0075] 101 (address 2),

[0076] 110 (random number 6),

[0077] Result: 011 (binary), converted to decimal is 3;

[0078] Address 3 and 6 are exclusive ORed:

[0079] 111(address 3),

[0080] 110 (random number 6),

[0081] Result: 001 (binary), converted to decimal is 1;

[0082] It can be seen that the data that should be stored in address 1 can be stored in address 2 after the XOR operation; the data that should be stored in address 2 can be stored in address 1 after the XOR operation; and the data that should be stored in address 3 can be stored in the position of 0x0001 after the XOR operation. Thus, the data in the program to be executed is randomly distributed in the target address range, which improves the security of the stored data.

[0083] Of course, in order to further improve the security of the data, the data to be stored may be XORed with the random number, so that the data obtained after the XOR may be stored based on the address obtained after the XOR.

[0084] It should be noted that, in the above example, the first corresponding relationship may be: data 1 corresponds to address 1, and after XORing data 1 to obtain the first target data, the second corresponding relationship may be: the first target data corresponds to address 2.

[0085] Step S50: based on the second corresponding relationship, storing each of the target data corresponding to the program to be executed at each of the second target addresses.

[0086] In the present application, the present application determines the random numbers corresponding to each address interval in the SRAM, and uses the preset address interval corresponding to the program to be executed as the target address interval, so as to determine a random number for each address interval, thereby reducing the success rate of the attack; then, in the target address interval, the first target address corresponding to each data in the program to be executed is determined, and the address corresponding to each data can be obtained on the premise of storing the data in sequence; then, based on the random number corresponding to the target address interval, each first target address is XORed to obtain each second target address, and based on the random number corresponding to the target address interval, each data is XORed to obtain each target data, and the address and the data to be stored can be changed based on the random number, so that the data will be randomly distributed in the target address interval; then, based on the first corresponding relationship between each data and each first target address, the second corresponding relationship between each target data and each second target address is determined, and the corresponding relationship between the address and the data can be determined after the XOR processing; finally, based on the second corresponding relationship, each target data corresponding to the program to be executed is stored at each second target address.

[0087] In this application, the address and the data to be stored can be XORed by a random number, so that the specific storage address of the data is random, and the stored data itself will also be affected by the random number. In this way, attacks on SRAM will not be successful due to the inability to determine the random number, thereby improving the security of SRAM storage data.

[0088] Furthermore, based on the above-mentioned first embodiment of the SRAM data protection method of the present application, a second embodiment of the SRAM data protection method of the present application is proposed.

[0089] In this embodiment, the above step S50 includes:

[0090] Step S501, correcting the errors of the target data by using an error correction code to obtain the target data after error correction;

[0091] It is understandable that during data transmission, various physical factors (such as electromagnetic interference, equipment failure, signal attenuation, etc.) may cause data errors. Therefore, in order to avoid storing the data with transmission errors in SRAM, it is necessary to correct the errors of each target data based on the error correction code.

[0092] It should be noted that the error correction code refers to the Error Correction Code. Since correction based on ECC technology is a mature technology, this application will not go into details here.

[0093] Step S502: based on the second corresponding relationship, storing each of the target data after error correction at each of the second target addresses.

[0094] In this embodiment, each target data after error correction can be stored according to the second corresponding relationship.

[0095] In this embodiment, the present application avoids the problem of storing erroneous data into SRAM by correcting the target data, thereby improving the correctness of the stored data.

[0096] In a feasible implementation manner, after the above step S10, the method further includes:

[0097] Step S60, writing each of the random numbers into each of the address intervals to erase the sensitive data in each of the address intervals.

[0098] In this embodiment, after the system is reset, in order to prevent the leakage of sensitive data (such as passwords, keys, etc.) previously stored in the SRAM due to not being correctly cleared during the reset process, the sensitive data in each address interval can be erased by writing random numbers into each address interval, thereby avoiding the leakage of data previously stored in the SRAM.

[0099] Furthermore, based on the first embodiment and the second embodiment of the SRAM data protection method of the present application, a third embodiment of the SRAM data protection method of the present application is proposed.

[0100] In this embodiment, the address interval includes various storage addresses, and the storage addresses in each of the address intervals are arranged in an alternating manner.

[0101] Please refer to Figure 3 , Figure 3 FIG. 1 shows a schematic diagram of the staggered arrangement of various storage addresses. Figure 3 There are two address intervals: SRAM0 and SRAM1, and there are multiple storage addresses in SRAM0 and SRAM1 respectively, and the multiple storage addresses corresponding to SRAM0 and SRAM1 are arranged in an interlaced manner.

[0102] It can be understood that when the multiple storage addresses corresponding to SRAM0 and SRAM1 are not in an interleaved state, the storage space allocation in SRAM is as follows: Figure 4 As shown. Figure 4 In the allocation scenario shown, SRAM0 will be frequently accessed when writing data, which makes it impossible for other peripherals to access SRAM0. To solve this problem, the present application interleaves multiple storage addresses corresponding to SRAM0 and SRAM1, so that when writing data to SRAM0, other peripherals can still access SRAM0, thereby improving the use efficiency of SRAM.

[0103] Furthermore, based on the first to third embodiments of the SRAM data protection method of the present application, a fourth embodiment of the SRAM data protection method of the present application is proposed.

[0104] In this embodiment, after the above step S50, the method further includes:

[0105] Step S70, when executing the program to be executed, determining the address to be accessed based on each of the target data;

[0106] It is understandable that when executing the program to be executed, it is necessary to obtain the data of the program to be executed before it is processed by the random number. Therefore, the data in the program to be executed can be restored by performing an XOR operation on the target data and the random number (the random number corresponding to the address interval). Then, based on the data requirements in the program to be executed, the address to be accessed is determined in the SRAM.

[0107] Step S80, judging whether each of the to-be-accessed addresses is legal based on a preset address interval attribute corresponding to the target address interval;

[0108] In a feasible implementation manner, the above step S80 further includes:

[0109] Step S801, if it is detected that each of the to-be-accessed addresses matches a preset address interval attribute corresponding to the target address interval, then it is determined that each of the to-be-accessed addresses is legal;

[0110] Step S802: Otherwise, it is determined that each of the addresses to be accessed is illegal.

[0111] It is understandable that, for each address interval, an address interval attribute may be preset correspondingly to characterize the access rights of the address interval.

[0112] For example, the address range attributes may include five types: safe executable, executable, read-only, readable and writable, and inaccessible. The permissions corresponding to each address range attribute are as follows:

[0113] The secure executable interval has the highest authority and can access any address interval; the executable interval can only access the address interval assigned to the program code; the readable and writable interval can only be accessed by the preset corresponding address interval; the read-only interval can also only be accessed by the preset corresponding address interval; no program code can access the inaccessible interval.

[0114] Therefore, whether the address to be accessed is legal can be determined by determining whether the address to be accessed belongs to the address corresponding to the address range attribute of the target address range.

[0115] Step S90, if it is determined that each of the addresses to be accessed is legal, integrity check is performed on the data stored in each of the addresses to be accessed;

[0116] It is understandable that, under the premise that the address to be accessed is legal, it is also necessary to determine the integrity of the data in each address to be accessed, so as to facilitate determining whether the data in the address to be accessed has been tampered with.

[0117] In addition, when it is determined that the address to be accessed is illegal, access to the address to be accessed corresponding to each instruction can be denied, and illegal access prompt information can be output through interruption. The illegal access address information is used to prompt the user program that there is an illegal access phenomenon.

[0118] In a feasible implementation manner, the above step S90 further includes:

[0119] Step S901, obtaining first hash values ​​corresponding to the addresses to be accessed, and calculating second hash values ​​corresponding to the addresses to be accessed according to data in the addresses to be accessed;

[0120] It should be noted that the first hash value refers to the hash value calculated based on the stored data when storing the data. For example, when writing data A to a certain address, data A can be input into the hash function to obtain the first hash value corresponding to the address. When the address needs to be accessed, the address is the address to be accessed. Since the stored data may be tampered with, in order to identify whether the stored data has been tampered with, it is also necessary to calculate the hash value again based on the accessed data when accessing the data at the address, thereby obtaining the second hash value.

[0121] Step S902: Detect whether the first hash value corresponding to each of the to-be-accessed addresses is the same as the second hash value corresponding to each of the to-be-accessed addresses.

[0122] It is understandable that for the first hash value and the second hash value corresponding to the same address to be accessed, it is possible to determine whether the data in the address to be accessed has been tampered with by comparing whether the first hash value and the second hash value are the same. Specifically, if the first hash value and the second hash value are the same, it indicates that the data in the address to be accessed has not been tampered with; if the first hash value and the second hash value are different, it indicates that the data in the address to be accessed has been tampered with.

[0123] It can be understood that if it is detected that the data in the address to be accessed has not been tampered with, it indicates that the integrity check has passed, and if it is detected that the data in the address to be accessed has been tampered with, it indicates that the integrity check has failed.

[0124] In addition, in a feasible implementation, if it is detected that the data in each address to be accessed fails the integrity check, data tampering prompt information is output through interruption. The data tampering prompt information is used to prompt the user that the stored data has been tampered with, which poses a security risk.

[0125] Step S100: If it is detected that the data in each of the to-be-accessed addresses passes the integrity check, the data is processed based on each of the instructions.

[0126] It is understandable that when it is detected that all addresses to be accessed by the program to be executed match the address range attribute and no tampering has occurred, the data in each address to be accessed can be processed according to the program to be executed.

[0127] Therefore, during data storage and data access, the present application ensures the security of memory protection through address range attributes and integrity verification, and avoids the confidentiality and integrity of data from being damaged.

[0128] Furthermore, based on the first to fourth embodiments of the SRAM data protection method of the present application, a specific embodiment of the SRAM data protection method of the present application is proposed.

[0129] In this embodiment, the above SRAM data protection method is encapsulated as a memory protection unit. The structure of the memory protection unit is as follows: Figure 5 shown.

[0130] exist Figure 5 In the present invention, the processor accesses the instructions and data stored in the SRAM through the SRAM interface and configures the memory protection unit through the peripheral configuration interface. The memory protection unit is composed of an access control unit and a verification unit.

[0131] The access control unit is mainly used to arbitrate and monitor access requests from the verification unit and external processor, and to perform data scrambling, data error correction, and data encryption and decryption on the read and write data of the SRAM. It can also actively identify potential physical attacks to enhance the security and reliability of the SRAM data. The functions of each sub-unit in the access control unit are described as follows:

[0132] The data error correction unit is used to perform error correction encoding and decoding on the data in the SRAM to enhance the reliability of the data. When a hacker conducts a laser photon physical attack on the SRAM physical circuit, the data error correction unit can report the error to the processor for exception processing through an interrupt when the error correction range is exceeded. The data error correction unit can realize active identification and protection against physical attacks.

[0133] The data scrambling unit performs an XOR operation on the data and address written to the SRAM with a random number. With a fixed address segment as the unit, the processor's data access sequence and data to the SRAM will be more random, thereby enhancing the SRAM's ability to resist side channels and enhancing the security of the SRAM data.

[0134] The data encryption and decryption unit is used to encrypt and store data in SRAM. The encryption and decryption key used by the data encryption and decryption unit is determined by the properties of the current address range. Different address ranges use different encryption and decryption keys. When the processor accesses the address range, the data reading and writing of SRAM will also be encrypted and decrypted using the corresponding key.

[0135] The access monitoring unit is used to check whether the processor's access to the specified address range meets the requirements of the address range attributes. Access that does not meet the requirements will be rejected and reported to the processor for processing through an interrupt. At the same time, the processor's access to the safe executable range will trigger the data verification unit to automatically verify the data integrity in the SRAM.

[0136] The access arbitration unit is used to arbitrate access requests from the check unit and the external processor to ensure that the processor's access to the SRAM is not blocked. At the same time, the check unit can also access the idle part of the SRAM, thereby achieving efficient use of the SRAM.

[0137] The verification unit is used to perform data erasure or integrity verification on the data in the specified address range, and can actively identify potential physical attacks to improve the security of SRAM data. The functions of each sub-unit in the verification unit are described as follows:

[0138] The address management unit is used to manage the address interval attributes of the SRAM. The address interval attributes are divided into five types: safe executable, executable, read-only, readable and writable, and inaccessible. The processor program code needs to be stored in the safe executable or executable interval. The program in the safe executable address interval has the highest access rights. The modification of the address attribute definition can only be performed when the processor executes the program code in the safe executable address interval. The address interval attributes cannot be modified after being defined as safe executable unless the system is reset. This mechanism can protect against potential software attacks.

[0139] The data erase unit is mainly used to write random numbers to the specified address range after the system is reset or when the processor needs to erase sensitive data in batches, preventing the leakage of sensitive data stored in the SRAM when the system is reset and reducing the risk of side channel information leakage when erasing sensitive data.

[0140] The data verification unit is used to perform integrity verification on the data in the specified address range actively or under the control of the processor to prevent the execution of tampered programs. When the processor starts a new address range, the data verification unit will automatically perform integrity verification on the data in the address range. If the verification fails, the exception will be reported to the processor through an interrupt signal for processing. The processor needs to update the hash value corresponding to the address area in the key management unit in time to prevent integrity verification failure.

[0141] The key management unit is used to store the keys or hash values ​​required for encryption, decryption and data verification. Each secure executable or executable address range occupies a set of dedicated keys or hash values, and the processor can only access the key management unit when executing the program in the secure executable range.

[0142] The random number generation unit is used to generate the random numbers required by each unit.

[0143] Specifically, the working process of the above memory protection unit is as follows:

[0144] After power-on reset, the data erasing unit will first perform a secure erasure of the SRAM, that is, write random numbers into all address intervals of the SRAM.

[0145] The processor executes the secure and trusted program in the ROM by default and is in a secure and trusted state. After the data erasure unit completes the secure erasure, the processor starts to configure the address management unit and the key management unit, specifies the attributes of each address interval, and writes the encryption and decryption keys and hash values ​​required for each address interval into the key management unit.

[0146] The processor writes the program to be executed into the corresponding address interval of the SRAM, and the program to be executed is stored in the corresponding address interval of the SRAM after being processed by the data encryption, data scrambling and data error correction units.

[0147] The processor pointer jumps to the address interval where the program is located and starts to execute the corresponding instructions. The access monitoring unit will monitor the access to the processor. Access that does not meet the attributes of the corresponding address interval will be rejected and reported to the processor through an interrupt for processing. The data verification unit will synchronously read the program code of the corresponding address interval in the SRAM through the access arbitration unit and calculate the hash value. If the SRAM data is tampered with by a hacker, the hash value calculated by the data verification unit will be inconsistent with the hash value pre-stored in the key management unit. The exception will be reported to the processor through an interrupt for exception processing. The data encryption unit will automatically use the key corresponding to the address interval to encrypt and decrypt the SRAM data during program execution.

[0148] Furthermore, the layout diagram of the address management unit is as follows: Figure 6 Please refer to Figure 6,The address interval attributes are divided into five types: secure executable, executable, read-only, readable and writable, and inaccessible; the program in the secure executable interval has the highest authority and can access any address interval. The address management unit and the key management unit can be configured. The processor can specify the encryption and decryption keys and the hash value for integrity verification through the hash value ID and key ID of the address interval. The ID of 0 means that encryption and decryption and integrity verification are not enabled. The secure executable interval is generally used to store program code for operating system-related tasks; the executable interval can only access the address interval assigned to the program code. The processor can specify the encryption and decryption keys and the hash value for integrity verification through the hash value ID and key ID of the address interval. The executable interval is generally used to store program code for multi-user related tasks; the readable and writable interval is used to store data used in the program running process. The processor The processor can set access rights through the accessible interval ID of the address interval. Only the program code corresponding to the ID can access the address interval. The ID is 0, which means that any program code can access the interval. The processor can specify the encryption and decryption key and the hash value for integrity verification through the hash value ID and key ID of the address interval. The read-only interval is used to store read-only data. The processor can set access rights through the accessible interval ID of the address interval. The ID is 0, which means that any program code can access the interval. The processor can specify the hash value for integrity verification through the hash value ID of the address interval. The write operation to the interval will be blocked by the access monitoring unit and processed by interrupt reporting to the processor; the inaccessible interval has no program code that can access it. The read and write operations to the interval will be blocked by the access monitoring unit and processed by interrupt reporting to the processor. It should be noted that the accessible interval ID is x, which indicates that the address interval can access any address interval, and the accessible interval ID is 0, which indicates that any program code can access the address interval. If the key ID is 2, it indicates that the second set of keys (encryption and decryption keys) are used. The hash value is related to the data stored in the address interval and is not limited here. For example, the hash value ID in address interval 1 is 1, indicating that the hash value of the data stored in address interval 1 is 1.

[0149] In addition, the key management unit is used to store the hash value and secret key specified in the address interval. Only the program code in the high-security executable interval can access the key management unit. When the processor starts a new address interval, the data verification unit will automatically perform integrity verification on the data in the address interval. The processor needs to update the hash value corresponding to the interval in the key management unit in a timely manner. For readable and writable intervals, the processor needs to complete the integrity verification in the data verification unit before writing to the interval or set the ID to 0 to turn off the automatic verification of the data verification unit.

[0150] In the above specific embodiments, the present application extends security from a trust root such as a ROM to a memory protection unit based on a trust chain, so that the processor executes a secure and trusted program by default before initializing the memory protection unit, and is in a secure and trusted state. Then, by specifying a secure executable interval, the security attribute can be passed to the program in the corresponding address interval through the trust chain, thereby improving the security of memory protection. In addition, the SRAM data protection method proposed in the present application is not limited to the processor because it is only related to the storage address in the storage area and is not related to the processor. Thus, processors of any architecture can be adapted to the memory protection method proposed in the present application, thereby improving the versatility of the memory protection method of the present application.

[0151] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the SRAM data protection method of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0152] This application also provides a SRAM data protection system, please refer to Figure 7 , the SRAM data protection system comprises:

[0153] The random number generation module 10 is used to determine the random number corresponding to each address interval in the SRAM, and use the preset address interval corresponding to the program to be executed as the target address interval;

[0154] A first address determination module 20, configured to determine, in the target address interval, first target addresses corresponding to respective data in the program to be executed;

[0155] An XOR module 30 is used to perform XOR on each of the first target addresses based on the random number corresponding to the target address interval to obtain each second target address, and to perform XOR on each of the data based on the random number corresponding to the target address interval to obtain each target data;

[0156] A correspondence determination module 40, configured to determine a second correspondence between each of the target data and each of the second target addresses based on a first correspondence between each of the data and each of the first target addresses;

[0157] The data storage module 50 is used to store each of the target data corresponding to the to-be-executed program at each of the second target addresses based on the second corresponding relationship.

[0158] In one embodiment, the data storage module 50 is further used for:

[0159] Correcting the errors of the target data by using an error correction code to obtain the target data after error correction;

[0160] Based on the second corresponding relationship, each of the target data after error correction is stored at each of the second target addresses.

[0161] In one embodiment, the SRAM data protection system further includes:

[0162] The erasing module is used to write each of the random numbers into each of the address intervals to erase the sensitive data in each of the address intervals.

[0163] In one embodiment, the SRAM data protection system further includes:

[0164] A module for determining an address to be accessed, used for determining an address to be accessed based on each of the target data when executing the program to be executed;

[0165] An access monitoring module, used for judging whether each of the to-be-accessed addresses is legal based on a preset address interval attribute corresponding to the target address interval;

[0166] A data verification module, configured to perform integrity verification on the stored data in each of the addresses to be accessed if it is determined that each of the addresses to be accessed is legal;

[0167] The data processing module is used to process each of the stored data based on each of the target data if it is detected that the stored data in each of the to-be-accessed addresses passes the integrity check.

[0168] In one embodiment, the access monitoring module is further configured to:

[0169] If it is detected that each of the to-be-accessed addresses matches a preset address interval attribute corresponding to the target address interval, then it is determined that each of the to-be-accessed addresses is legal;

[0170] Otherwise, it is determined that each of the addresses to be accessed is illegal.

[0171] The SRAM data protection system provided by the present application adopts the SRAM data protection method in the above embodiment, which can solve the technical problem of how to improve the security of SRAM stored data. Compared with the prior art, the beneficial effects of the SRAM data protection system provided by the present application are the same as the beneficial effects of the SRAM data protection method provided by the above embodiment, and other technical features of the SRAM data protection system are the same as the features disclosed in the above embodiment method, which will not be described in detail here.

[0172] The present application provides a computer device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the SRAM data protection method in the above-mentioned embodiment 1.

[0173] Reference below Figure 8 , which shows a schematic diagram of the structure of a computer device suitable for implementing an embodiment of the present application. Figure 8 The computer device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0174] like Figure 8 As shown, the computer device may include a processing device 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read On ly Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. Various programs and data required for the operation of the computer device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1003 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009. The communication device 1009 may allow the computer device to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows a computer device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have instead.

[0175] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0176] The computer device provided by the present application adopts the SRAM data protection method in the above embodiment, which can solve the technical problem of how to improve the security of SRAM stored data. Compared with the prior art, the beneficial effects of the computer device provided by the present application are the same as the beneficial effects of the SRAM data protection method provided by the above embodiment, and the other technical features in the computer device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0177] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0178] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0179] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the SRAM data protection method in the above-mentioned embodiment.

[0180] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read On ly Memory), an erasable programmable read-only memory (EPROM: Erasable Programmab le Read On ly Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read On ly Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0181] The computer-readable storage medium may be included in the computer device; or may exist independently without being installed in the computer device.

[0182] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by a computer device, the computer device: determines the random numbers corresponding to each address interval in the SRAM, and uses the preset address interval corresponding to the program to be executed as the target address interval; determines the first target addresses corresponding to each data in the program to be executed in the target address interval; based on the random numbers corresponding to the target address interval, performs XOR on each of the first target addresses to obtain each second target address, and based on the random numbers corresponding to the target address interval, performs XOR on each of the data to obtain each target data; based on the first corresponding relationship between each of the data and each of the first target addresses, determines the second corresponding relationship between each of the target data and each of the second target addresses; based on the second corresponding relationship, stores each of the target data corresponding to the program to be executed at each of the second target addresses.

[0183] The computer program code for performing the operation of the present application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider to connect through the Internet).

[0184] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0185] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0186] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned SRAM data protection method, and can solve the technical problem of how to improve the security of SRAM stored data. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the SRAM data protection method provided in the above-mentioned embodiment, and will not be repeated here.

[0187] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned SRAM data protection method when executed by a processor.

[0188] The computer program product provided by the present application can solve the technical problem of how to improve the security of SRAM stored data. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the SRAM data protection method provided by the above embodiment, which will not be repeated here.

[0189] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A SRAM data protection method, characterized in that: The SRAM data protection method comprises: Determine the random number corresponding to each address interval in the SRAM, and use the preset address interval corresponding to the program to be executed as the target address interval; Determine, in the target address interval, first target addresses corresponding to respective data in the program to be executed; Based on the random number corresponding to the target address interval, performing an XOR operation on each of the first target addresses to obtain each second target address, and based on the random number corresponding to the target address interval, performing an XOR operation on each of the data to obtain each target data; Determining a second corresponding relationship between each of the target data and each of the second target addresses based on a first corresponding relationship between each of the data and each of the first target addresses; Based on the second corresponding relationship, each of the target data corresponding to the program to be executed is stored at each of the second target addresses.

2. The SRAM data protection method according to claim 1, characterized in that: The step of storing each of the target data corresponding to the program to be executed at each of the second target addresses based on the second corresponding relationship includes: Correcting the errors of the target data by using an error correction code to obtain the target data after error correction; Based on the second corresponding relationship, each of the target data after error correction is stored at each of the second target addresses.

3. The SRAM data protection method according to claim 1, characterized in that: The address intervals include various storage addresses, and the storage addresses in the address intervals are arranged alternately.

4. The SRAM data protection method according to claim 1, wherein: After the step of determining the random number corresponding to each address interval in the SRAM, the method further includes: Each of the random numbers is written into each of the address intervals to erase the sensitive data in each of the address intervals.

5. The SRAM data protection method according to claim 1, wherein: After the step of storing each of the target data corresponding to the to-be-executed program at each of the second target addresses based on the second corresponding relationship, the method further includes: When executing the program to be executed, determining an address to be accessed based on each of the target data; Determining whether each of the to-be-accessed addresses is legal based on a preset address interval attribute corresponding to the target address interval; If it is determined that each of the addresses to be accessed is legal, integrity check is performed on the data stored in each of the addresses to be accessed; If it is detected that the stored data in each of the to-be-accessed addresses passes the integrity check, the stored data are processed based on each of the target data.

6. The SRAM data protection method according to claim 5, characterized in that: The step of judging whether each of the to-be-accessed addresses is legal based on the preset address interval attribute corresponding to the target address interval includes: If it is detected that each of the to-be-accessed addresses matches a preset address interval attribute corresponding to the target address interval, then it is determined that each of the to-be-accessed addresses is legal; Otherwise, it is determined that each of the addresses to be accessed is illegal.

7. A SRAM data protection system, characterized in that: The SRAM data protection system comprises: A random number generation module is used to determine the random number corresponding to each address interval in the SRAM, and use the preset address interval corresponding to the program to be executed as the target address interval; A first address determination module, used to determine, in the target address interval, first target addresses corresponding to respective data in the program to be executed; an XOR module, configured to perform an XOR operation on each of the first target addresses based on a random number corresponding to the target address interval to obtain each second target address, and perform an XOR operation on each of the data based on a random number corresponding to the target address interval to obtain each target data; a correspondence determination module, configured to determine a second correspondence between each of the target data and each of the second target addresses based on a first correspondence between each of the data and each of the first target addresses; The data storage module is used to store each of the target data corresponding to the program to be executed at each of the second target addresses based on the second corresponding relationship.

8. A computer device, characterized in that: The computer device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the SRAM data protection method according to any one of claims 1 to 6.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the SRAM data protection method according to any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the SRAM data protection method according to any one of claims 1 to 6 are implemented.

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