Simulation end verification method, electronic device and medium

Abstract

The present application relates to the field of computer technology and provides a simulation end verification method, electronic device and medium. It can not only ensure the execution of all test cases, but also flexibly adapt to the customized needs of chip simulation verification personnel, effectively reduce redundant reserved simulation time, and help shorten the debugging time of chip verification personnel, shorten the chip verification cycle, and improve chip development efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a simulation end verification method, electronic equipment and medium. Background Art

[0002] In the development process of network chips, a lot of verification and simulation are required to verify the various functions and characteristics of the chip. To this end, a large number of test cases need to be input into the design under test (DUT), and simulation verification is performed based on methodologies such as Universal Verification Methodology (UVM). Different test cases may have different numbers of packets, packet lengths, etc., and different test cases may also require different processing times after being input into the design under test. In order to ensure that all test cases can be executed, simulation verification personnel generally reserve a certain delay when designing test cases. However, with the increase in the number of test cases and the increase in the workload of chip simulation verification, these reserved simulation times may result in too much simulation time being reserved overall, thereby increasing the debugging time of chip verification personnel, and is not conducive to shortening the chip verification cycle and improving development efficiency.

[0003] To this end, the present application provides a simulation end verification method, electronic device and medium, which can not only ensure the execution of all test cases, but also flexibly adapt to the customized needs of chip simulation and verification personnel, effectively reducing redundant reserved simulation time, which is conducive to shortening the debugging time of chip verification personnel, shortening the chip verification cycle, and improving chip development efficiency. Summary of the invention

[0004] In a first aspect, the present application provides a simulation end verification method. The simulation end verification method comprises: initializing the simulation end verification platform, and then instantiating the top layer, the design to be tested and the interface module, wherein the simulation end verification platform comprises a sequence generator, a test case library, a reference model, a detection module and a monitoring module, wherein the sequence generator is used to generate a stimulus input to the design to be tested, the test case library is used to provide a test case that is simultaneously sent to the design to be tested and the reference model, and the detection module is used to compare the output of the reference model with the output of the design to be tested through the interface module to generate a detection result; configuring the monitoring work enable signal, monitoring priority, timeout time, read-write control signal threshold ratio, and data request signal threshold ratio of the monitoring module, wherein the timeout time is the preset simulation end time associated with the test case; when the configured monitoring work enable signal is enabled, the read-write control signal of the interface module is monitored based on the configured monitoring priority, timeout time, read-write control signal threshold ratio, and data request signal threshold ratio through the monitoring module without jumping and the data request signal without jumping, thereby determining whether to end the simulation of the test case.

[0005] Through the first aspect of the present application, the non-jumping time of the concerned signal of the interface module is monitored by the monitoring module, and combined with various parameters that can be flexibly configured, when the time for the control signal to remain unchanged meets the pre-configured conditions, the simulation is terminated, without waiting for the simulation time of the test case to reach the preset simulation end time associated with the test case, so it can be unaffected by the redundant simulation time reserved when developing the test case, when the number of test cases is large and the chip simulation verification work is complicated, it can also ensure that all test cases are executed, and it can flexibly adapt to the customized needs of chip simulation verification personnel, effectively reducing the redundant reserved simulation time, which is conducive to shortening the debugging time of chip verification personnel, shortening the chip verification cycle, and improving chip development efficiency. In addition, because the non-jumping time of the concerned signal of the interface module is monitored by the monitoring module, so as to determine whether to end the simulation, the simulation end condition can be decoupled from the information such as the number of packets and the package field of the test case in some cases, that is, the test case library can modify the information such as the number of packets and the length of the packet at will, and no longer pay attention to the simulation end condition, which is conducive to reducing the difficulty of test case development. In addition, taking into account the customized needs of certain test cases, by providing configurable monitoring enable signals and monitoring priorities, the monitoring module can be selectively disabled according to the needs of certain test cases, allowing the test cases to control the end of the simulation by themselves. It is also possible to selectively enable the monitoring module for certain test cases by comparing the monitoring priority and the test case priority, so that the monitoring module controls the end of the simulation, and selectively disable the monitoring module for other test cases so that the test cases can control the end of the simulation by themselves, which is conducive to adapting to complex and changeable customized simulation verification needs.

[0006] In a possible implementation of the first aspect of the present application, the simulation end verification method also includes: when the configured monitoring work enable signal is disabled, the monitoring module does not monitor the interface module, and when the simulation time of the test case reaches the timeout time, the simulation of the test case ends.

[0007] In a possible implementation of the first aspect of the present application, the monitoring module monitors the read-write control signal retention time and the data request signal retention time of the interface module based on the configured monitoring priority, timeout period, read-write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case, including: obtaining the test case priority from the monitored signal of the interface module through the monitoring module, and then comparing the test case priority and the monitoring priority; when the test case priority is higher than the monitoring priority, the monitoring module terminates monitoring the interface module, and when the simulation time of the test case reaches the timeout period, the simulation of the test case ends.

[0008] In a possible implementation manner of the first aspect of the present application, the test case priority is configured by the test case library or the design to be tested, and the test case priority corresponds to the test case.

[0009] In a possible implementation of the first aspect of the present application, when the simulation time of a previous test case relative to the test case exceeds a preset redundancy threshold, the monitoring priority is configured as the highest priority.

[0010] In a possible implementation of the first aspect of the present application, the monitoring module monitors the non-jumping time of the read-write control signal and the non-jumping time of the data request signal of the interface module based on the configured monitoring priority, timeout time, read-write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case, including: determining whether the non-jumping time of the read-write control signal of the interface module reaches the configured read-write control signal threshold ratio of the configured timeout time, and if so, determining to end the simulation of the test case; determining whether the non-jumping time of the data request signal of the interface module reaches the configured data request signal threshold ratio of the configured timeout time, and if so, determining to end the simulation of the test case.

[0011] In a possible implementation manner of the first aspect of the present application, the read-write control signal threshold ratio and the data request signal threshold ratio are configured based on simulation verification customization requirements.

[0012] In a possible implementation of the first aspect of the present application, the simulation end verification method also includes: monitoring the simulation waveform output by the interface module through the monitoring module, and when it is detected that the size of the simulation waveform is greater than a preset maximum value, determining to end the simulation of the test case, and then feeding back the position where the detected size of the simulation waveform is greater than the preset maximum value.

[0013] In a possible implementation of the first aspect of the present application, the simulation end verification method also includes: comparing the simulation time of the test case with the global maximum simulation end time through the monitoring module, and when it is detected that the simulation time of the test case reaches the global maximum simulation end time, determining to end the simulation of the test case, and then feeding back an error that the simulation time of the test case detected reaches the global maximum simulation end time, wherein the global maximum simulation end time is independent of the timeout time and independent of the test case.

[0014] In a possible implementation of the first aspect of the present application, the timeout period is determined independently of the number of packets sent and the packet length associated with the test case, and the number of packets sent and the packet length associated with the test case can be modified through the test case library.

[0015] In a possible implementation manner of the first aspect of the present application, the timeout period is determined based on the number of packets sent and the packet length associated with the test case.

[0016] In a possible implementation of the first aspect of the present application, the operation of the monitoring module is independent of the operation of the sequence generator, the operation of the test case library, the operation of the reference model, the operation of the interface module, and the operation of the monitoring module.

[0017] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0018] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A flowchart of a simulation end verification method provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of a simulation verification platform provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0025] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0026] Figure 1 A flowchart of a simulation end verification method provided in an embodiment of the present application. Figure 1 As shown, the simulation end verification method includes the following steps.

[0027] Step S101: Initialize the simulation end verification platform, and then instantiate the top layer, the design to be tested, and the interface module, wherein the simulation end verification platform includes a sequence generator, a test case library, a reference model, a detection module, and a monitoring module, the sequence generator is used to generate stimuli to be input to the design to be tested, the test case library is used to provide test cases that are simultaneously sent to the design to be tested and the reference model, and the detection module is used to compare the output of the reference model with the output of the design to be tested through the interface module to generate a detection result.

[0028] Step S103: configure the monitoring module's monitoring enable signal, monitoring priority, timeout period, read / write control signal threshold ratio, and data request signal threshold ratio, wherein the timeout period is a preset simulation end time associated with the test case.

[0029] Step S105: When the configured monitoring work enable signal is enabled, the monitoring module monitors the read-write control signal retention time and the data request signal retention time of the interface module based on the configured monitoring priority, timeout period, read-write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case.

[0030] Figure 1 The simulation end verification method shown is applied to the development process of network chips, and can be used in conjunction with a large number of verifications and simulations to verify various functions and characteristics of the chip. Generally, a large number of test cases (TC) need to be input into the design under test (DUT), and simulation verification is performed based on methodologies such as Universal Verification Methodology (UVM), and different test cases may have different numbers of packets sent, packet lengths, etc., and different test cases may also require different processing times after being input into the design under test. Figure 1 The simulation end verification method shown can meet the needs of any number of test cases and cope with the increasingly complex chip simulation verification work. By increasing the reusability of the module and reducing the debugging time of the constructed case, it can not only ensure the execution of all test cases, but also flexibly adapt to the customized needs of chip simulation verification personnel, effectively reducing redundant reserved simulation time, which is conducive to shortening the debugging time of chip verification personnel, shortening the chip verification cycle, and improving chip development efficiency. The following is a detailed description.

[0031] refer to Figure 1, in step S101, the simulation end verification platform is initialized, and then the top layer, the design to be tested, and the interface module are instantiated. Wherein, the simulation end verification platform includes a sequence generator, a test case library, a reference model, a detection module, and a monitoring module. The sequence generator is used to generate a stimulus input to the design to be tested, the test case library is used to provide a test case that is simultaneously sent to the design to be tested and the reference model, and the detection module is used to compare the output of the reference model with the output of the design to be tested through the interface module to generate a detection result. Here, the test case library is used to store, manage and maintain various test cases. Chip simulation verification personnel use various tools such as artificial intelligence models, random algorithms, etc. to develop various test cases. These test cases may each have different information such as the number of packets sent and the length of the packet. Different test cases can also be used to test different parts of the design to be tested, requiring different processing delays. In order to achieve the best chip simulation verification effect, it is necessary to ensure that all test cases are executed, so that the output of each test case can be compared with the output of the reference model in the detection module, and then determine whether there are errors or areas that can be improved in the design to be tested. Here, the reference model is generally a model that meets the expectations of chip design and is described in code, such as logical behavior, to provide a reference basis. In some embodiments, a systematic programming language or similar tools, such as systemverilog (SV), can be used to construct some underlying general simulation end models, and then called through the UVM tool to simplify the simulation end model, which is conducive to the transplantation of reference models and verification environments and improves the overall efficiency of the system. After initializing the simulation end verification platform, the top layer, the design to be tested, and the interface module are instantiated. Here, the interface module can be understood as a part of the design to be tested, or provided separately, and is not specifically limited here. The interface module is used to provide an intervention operation space for subsequent monitoring operations of the monitoring module. After step S101, execute step S103.

[0032] Continue to refer Figure 1, in step S103, the monitoring work enable signal, monitoring priority, timeout time, read / write control signal threshold ratio, and data request signal threshold ratio of the monitoring module are configured, wherein the timeout time is the preset simulation end time associated with the test case. Here, the monitoring work enable signal is used to enable or disable the monitoring module, so that the monitoring module can be selectively disabled according to the needs of certain test cases, so that the test case can control the end of the simulation by itself, which is conducive to adapting to complex and changeable customized simulation verification requirements. The monitoring priority is used to compare the test case priority associated with the test case, so that the test case priority of certain test cases can be set when adding test cases to the test case library. In this way, by comparing the monitoring priority and the test case priority, the monitoring module can be selectively enabled for certain test cases so that the monitoring module controls the end of the simulation, and the monitoring module can be selectively disabled for other test cases so that the test case can control the end of the simulation by itself, which is conducive to adapting to complex and changeable customized simulation verification requirements. The timeout time is the preset simulation end time associated with the test case. Here, different test cases may have different associated simulation end times, and these preset simulation end times can be set by chip simulation verification personnel when generating development test cases, and can be based on any appropriate reference factors, such as the number of packets sent and the packet length of the test case, or can be based on the application environment requirements of the chip, such as communication protocol specifications, product parameters, etc. Generally, when chip simulation verification personnel develop test cases and set the simulation end time associated with the preset test cases, they will reserve some redundant simulation time to ensure that the test cases are executed. The read-write control signal threshold ratio is used to monitor a specific signal, that is, to monitor the read-write control signal of the interface module, so as to provide a basis for judging whether to end the simulation. The data request signal threshold ratio is used to monitor a specific signal, that is, to monitor the data request signal of the interface module, so as to provide a basis for judging whether to end the simulation. The read-write control signal threshold ratio and the data request signal threshold ratio can be set by the chip simulation verification personnel according to customized requirements, and are used to configure the monitoring module to apply a specific threshold ratio control to the signal of interest. The signals of interest are divided into two types: read / write control signals and data request signals, and may be, for example, an ACK signal within the design under test, a ready signal, or other internal signals of the design under test, etc. After step S103 , step S105 is executed.

[0033] Continue to refer Figure 1, in step S105, when the configured monitoring work enable signal is enabled, the monitoring module monitors the read-write control signal of the interface module and the data request signal based on the configured monitoring priority, timeout, read-write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case. In this way, the monitoring module can be enabled or disabled through the configured monitoring work enable signal. When the configured monitoring work enable signal is enabled, it means that the monitoring module is enabled, and then, the monitoring module monitors and controls the signal of interest based on the pre-configured parameters, that is, the configured monitoring priority, timeout, read-write control signal threshold ratio, and data request signal threshold ratio, that is, monitors the read-write control signal of the interface module and the data request signal based on the pre-configured parameters, that is, the read-write control signal of the interface module and the data request signal, so as to determine whether to end the simulation of the test case. For example, assuming that the read-write control signal threshold ratio is configured to 90%, then when the read-write control signal of interest remains unchanged for a period of time that reaches 90% of the corresponding timeout period, it can be determined that the simulation should be terminated early. Here, when the concerned signal, that is, the read-write control signal and the data request signal of the interface module, remain unchanged for a long time, and the unchanged time reaches a certain value, this means that the corresponding test case should have been executed inside the design to be tested. Therefore, if the simulation verification is continued, it is redundant simulation time. At this time, in order to shorten the redundant simulation time, the monitoring module determines that the simulation should be terminated early and the loop should be jumped out. In this way, the monitoring module is used to manage the simulation end conditions and determine whether to end the simulation early, instead of the verification personnel setting the simulation end time for each test case separately. Specifically, the verification platform is initialized, including instantiating the top layer, the design to be tested, and the interface module; then the simulation end time of the monitoring module is configured; the control signals such as data reading and writing, data request, etc. processed by the interface module are monitored by the monitoring module, and it can be detected whether there is a control signal that does not jump for a long time. If the time for which the control signal remains unchanged meets the pre-configured conditions, the environment component calls the monitoring module to end the simulation of the corresponding test case. In this way, the test case can modify the number of packets and the packet length at will, and monitor the simulation end time through a unified monitoring module, that is, the simulation ends whenever the control signal does not jump for a long enough time. In addition, the monitoring module is provided separately from other modules and components, which can improve the reusability of the module and facilitate transplantation. It can be conveniently transplanted to other verification environments, effectively reducing the simulation time of the test case.

[0034] In conclusion, Figure 1The simulation end verification method shown, monitors the non-jumping time of the concerned signal of the interface module through the monitoring module, and combines the various parameters that can be flexibly configured, when the time for the control signal to remain unchanged meets the pre-configured conditions, the simulation is terminated, without waiting for the simulation time of the test case to reach the simulation end time associated with the preset test case, so it can be unaffected by the redundant simulation time reserved when developing the test case, when the number of test cases is large and the chip simulation verification work is complicated, it can also ensure that all test cases are executed, and it can flexibly adapt to the customized needs of chip simulation verification personnel, effectively reducing the redundant reserved simulation time, which is conducive to shortening the debugging time of chip verification personnel, shortening the chip verification cycle, and improving chip development efficiency. In addition, because the non-jumping time of the concerned signal of the interface module is monitored by the monitoring module, so as to determine whether to end the simulation, the simulation end condition can be decoupled from the information such as the number of packets and the package field of the test case in some cases, that is, the test case library can modify the information such as the number of packets and the length of the packet at will, and no longer pay attention to the simulation end condition, which is conducive to reducing the difficulty of test case development. In addition, taking into account the customized needs of certain test cases, by providing configurable monitoring enable signals and monitoring priorities, the monitoring module can be selectively disabled according to the needs of certain test cases, allowing the test cases to control the end of the simulation by themselves. It is also possible to selectively enable the monitoring module for certain test cases by comparing the monitoring priority and the test case priority, so that the monitoring module controls the end of the simulation, and selectively disable the monitoring module for other test cases so that the test cases can control the end of the simulation by themselves, which is conducive to adapting to complex and changeable customized simulation verification needs.

[0035] Figure 2 A schematic diagram of a simulation verification platform provided in an embodiment of the present application. Figure 2 As shown, the simulation verification platform includes multiple different modules and components for providing simulation verification for the design to be tested 290 and can be used as a reference Figure 1 The simulation end verification method shown in the figure effectively reduces the redundant simulation time of the test case, enhances the reusability of the components during verification, and improves the chip development efficiency. Figure 2 As shown, the simulation end verification platform includes a sequence generator 201, a test case library 203, a reference model 205, a detection module 207, and a monitoring module 209. In addition, an interface module 292 is connected to the design to be tested 290. Figure 2The simulation verification platform shown can apply the following simulation end verification method: initialize the simulation end verification platform, and then instantiate the top layer, the design to be tested 290 and the interface module 292, wherein the simulation end verification platform includes a sequence generator 201, a test case library 203, a reference model 205, a detection module 207, and a monitoring module 209, the sequence generator 201 is used to generate stimuli to be input to the design to be tested 290, the test case library 203 is used to provide test cases that are simultaneously sent to the design to be tested 290 and the reference model 205, and the detection module 207 is used to compare the output of the reference model 205 with the design to be tested 290 after The output of the interface module 292 generates a detection result; the monitoring work enable signal, monitoring priority, timeout period, read-write control signal threshold ratio, and data request signal threshold ratio of the monitoring module 209 are configured, wherein the timeout period is the preset simulation end time associated with the test case; when the configured monitoring work enable signal is enabled, the monitoring module 209 monitors the read-write control signal holding time without jumping and the data request signal holding time without jumping of the interface module 292 based on the configured monitoring priority, timeout period, read-write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case.

[0036] Figure 2The simulation verification platform shown monitors the non-changing time of the concerned signal of the interface module 292 through the monitoring module 209, and combines various parameters that can be flexibly configured. When the time for which the control signal remains non-changing meets the pre-configured conditions, the simulation is ended without waiting until the simulation time of the test case reaches the preset simulation end time associated with the test case. Therefore, it is not affected by the redundant simulation time reserved when developing the test case. When the number of test cases is large and the chip simulation verification work is complicated, it can ensure that all test cases are executed and completed, and it can flexibly adapt to the customized needs of chip simulation verification personnel, effectively reducing redundant reserved simulation time, which is beneficial to shorten the debugging time of chip verification personnel, shorten the chip verification cycle, and improve chip development efficiency. In addition, because the monitoring module 209 is used to monitor the non-jumping time of the concerned signal of the interface module 292, so as to determine whether to end the simulation, the simulation end condition can be decoupled from the number of packets and the package field of the test case in some cases, that is, the test case library 203 can modify the number of packets and the packet length and other information at will, and no longer pay attention to the simulation end condition, which is conducive to reducing the difficulty of developing test cases. In addition, considering the customized requirements of some test cases, by providing configurable monitoring work enable signals and monitoring priorities, the monitoring module 209 can be selectively disabled according to the requirements of some test cases, so that the test cases can control the end of the simulation by themselves, and the monitoring module 209 can be selectively enabled for some test cases by comparing the monitoring priority and the test case priority, so that the monitoring module 209 controls the end of the simulation, and the monitoring module 209 can be selectively disabled for other test cases so that the test cases can control the end of the simulation by themselves, which is conducive to adapting to the complex and changeable customized requirements of simulation verification.

[0037] refer to Figure 1 and Figure 2 In a possible implementation, the simulation end verification method further includes: when the configured monitoring work enable signal is disabled, the monitoring module does not monitor the interface module, and when the simulation time of the test case reaches the timeout period, the simulation of the test case ends. In this way, the monitoring work enable signal is used to enable or disable the monitoring module, so that the monitoring module can be selectively disabled according to the needs of certain test cases, so that the test case can control the end of the simulation by itself, which is conducive to adapting to complex and changeable simulation verification customization needs.

[0038] In a possible implementation, the monitoring module monitors the read-write control signal of the interface module and the data request signal based on the configured monitoring priority, timeout, read-write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case, including: obtaining the test case priority from the monitored signal of the interface module through the monitoring module, and then comparing the test case priority and the monitoring priority. When the test case priority is higher than the monitoring priority, the monitoring module terminates monitoring the interface module, and when the simulation time of the test case reaches the timeout, the simulation of the test case ends. In this way, the monitoring priority is used to compare the test case priority associated with the test case, so that the test case priority of some test cases can be set when adding test cases to the test case library. In this way, by comparing the monitoring priority and the test case priority, the monitoring module can be selectively enabled for some test cases so that the monitoring module controls the end of the simulation, and the monitoring module can be selectively disabled for other test cases so that the test case can control the end of the simulation by itself, which is conducive to adapting to complex and changeable simulation verification customization requirements.

[0039] In some embodiments, the test case priority is configured by the test case library or the design to be tested, and the test case priority corresponds to the test case. This is conducive to adapting to complex and changeable simulation verification customization requirements.

[0040] In some embodiments, when the simulation time of the previous test case relative to the test case exceeds the preset redundancy threshold, the monitoring priority is configured as the highest priority. In this way, when the simulation time of the previous test case is redundant, that is, exceeds the preset redundancy threshold, by configuring the monitoring priority as the highest priority, it means that the monitoring priority is higher than the test case priority, and then the monitoring module is enabled, so that the simulation can be terminated first when the preset conditions are met, thereby solving the problem of redundant simulation time caused by the previous test case and improving the chip simulation verification efficiency as a whole.

[0041] In a possible implementation, the monitoring module monitors the read-write control signal holding time and the data request signal holding time of the interface module based on the configured monitoring priority, timeout period, read-write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case, including: determining whether the read-write control signal holding time of the interface module reaches the configured read-write control signal threshold ratio of the configured timeout period, and if so, determining to end the simulation of the test case; determining whether the data request signal holding time of the interface module reaches the configured data request signal threshold ratio of the configured timeout period, and if so, determining to end the simulation of the test case. In this way, the timeout period is the preset simulation end time associated with the test case. Here, different test cases may have different associated simulation end times, and these preset simulation end times can be set by chip simulation verification personnel when generating development test cases, and can be based on any appropriate reference factors, such as the number of packets sent and the packet length of the test case, or can be based on the application environment requirements of the chip, such as communication protocol specifications, product parameters, etc. Generally, when chip simulation verification personnel develop test cases and set the simulation end time associated with the preset test cases, they will reserve some redundant simulation time to ensure that the test cases are executed. The read-write control signal threshold ratio is used to monitor a specific signal, that is, to monitor the read-write control signal of the interface module, so as to provide a basis for judging whether to end the simulation. The data request signal threshold ratio is used to monitor a specific signal, that is, to monitor the data request signal of the interface module, so as to provide a basis for judging whether to end the simulation. The read-write control signal threshold ratio and the data request signal threshold ratio can be set by the chip simulation verification personnel according to customized requirements, and are used to configure the monitoring module to apply a specific threshold ratio control to the signal of interest. The signals of interest are divided into two types: read-write control signals and data request signals, which can be, for example, an ACK signal inside the design to be tested, a ready-to-receive signal, or other internal signals of the design to be tested. The monitoring module monitors and controls the signals of interest based on various pre-configured parameters, namely, the configured monitoring priority, timeout time, read-write control signal threshold ratio, and data request signal threshold ratio, namely, monitors the read-write control signal of the interface module to maintain a non-jump time and the data request signal to maintain a non-jump time, thereby determining whether to end the simulation of the test case. For example, assuming that the read-write control signal threshold ratio is configured to 90%, then when the read-write control signal of interest maintains a non-jump time that reaches 90% of the corresponding timeout time, it can be determined that the simulation is terminated in advance.Here, when the concerned signal, that is, the read / write control signal and data request signal of the interface module, remains unchanged for a long time, and the unchanged time reaches a certain value, it means that the corresponding test case should have been executed inside the design to be tested. Therefore, if the simulation verification is continued, it is a redundant simulation time. At this time, in order to shorten the redundant simulation time, the monitoring module determines that the simulation should be ended in advance and the loop should be jumped out. In this way, the monitoring module is used to manage the simulation end conditions and determine whether to end the simulation in advance, instead of the verification personnel setting the simulation end time for each test case separately. Specifically, the verification platform is initialized, including instantiating the top layer, the design to be tested, and the interface module; then the simulation end time of the monitoring module is configured; the control signals such as data read / write and data request processed by the interface module are monitored by the monitoring module, and it can be detected whether a certain control signal does not jump for a long time. If the control signal remains unchanged for a time that meets the pre-configured conditions, the environment component calls the monitoring module to end the simulation of the corresponding test case. In this way, the test case can modify the number of packets and the length of the packet at will, and monitor the end time of the simulation through a unified monitoring module, that is, the simulation ends when the control signal does not jump for a long enough time. In addition, the monitoring module is provided separately from other modules and components, which can improve the reusability of the module and facilitate its transplantation. It can be easily transplanted to other verification environments, effectively reducing the simulation time of the test case.

[0042] In some embodiments, the read-write control signal threshold ratio and the data request signal threshold ratio are configured based on the customized requirements of simulation verification. In this way, it is conducive to meeting the customized requirements of simulation verification. For example, a 90% ratio can be set for a concerned control signal and an 80% ratio can be set for another concerned control signal. By setting the corresponding ratio, the simulation end time can be controlled more flexibly, and corresponding configurations can be provided for different test cases, thereby better improving the overall chip simulation verification efficiency. For example, if some test cases are more important, a higher ratio can be set to ensure the execution effect of these test cases.

[0043] In a possible implementation, the simulation end verification method further includes: monitoring the simulation waveform output by the interface module through the monitoring module, and when it is detected that the size of the simulation waveform is greater than a preset maximum value, determining to end the simulation of the test case, and then feeding back the position where the size of the detected simulation waveform is greater than the preset maximum value. In this way, on the basis of monitoring the non-jump time of the control signal of concern, an additional judgment mechanism for terminating the simulation in advance is provided, that is, the simulation waveform is monitored, and when the size of the simulation waveform is greater than the preset maximum value, for example, the voltage waveform exceeds the maximum amplitude allowed in the design, these mean that an error may have occurred during the processing of the test case, so the simulation can be ended in advance, and the position where the error occurred can be fed back to facilitate the verification personnel to locate it. In this way, it is beneficial to further shorten the chip verification cycle and improve the efficiency of chip development.

[0044] In a possible implementation, the simulation end verification method further includes: comparing the simulation time of the test case with the global maximum simulation end time through the monitoring module, and when it is detected that the simulation time of the test case reaches the global maximum simulation end time, determining to end the simulation of the test case, and then feeding back the error that the simulation time of the test case detected reaches the global maximum simulation end time, wherein the global maximum simulation end time is independent of the timeout time and independent of the test case. In this way, by setting the global maximum simulation end time, it is beneficial to better control the overall verification process from a global perspective, and it is beneficial to further shorten the chip verification cycle and improve chip development efficiency.

[0045] In a possible implementation, the timeout period is determined independently of the number of packets and the packet length associated with the test case, and the number of packets and the packet length associated with the test case can be modified by the test case library. In this way, because the time for which the concerned signal of the interface module remains unchanged is monitored by the monitoring module to determine whether to end the simulation, the simulation end condition can be decoupled from the number of packets and the packet field of the test case in some cases, that is, the test case library can modify the number of packets and the packet length at will, and no longer pay attention to the simulation end condition, which is conducive to reducing the difficulty of test case development.

[0046] In a possible implementation, the timeout period is determined based on the number of packets and the packet length associated with the test case. In this way, the development requirements of diversified test cases and the customized requirements of chip simulation verification can be met.

[0047] In a possible implementation, the operation of the monitoring module is independent of the operation of the sequence generator, the operation of the test case library, the operation of the reference model, the operation of the interface module, and the operation of the monitoring module. In this way, the independence of the monitoring module is ensured, and the monitoring module is provided separately from other modules and components, which can improve the reusability of the module and facilitate transplantation. It can be conveniently transplanted to other verification environments, effectively reducing the simulation time of test cases.

[0048] Figure 3 3 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0049] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0050] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0051] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0052] The bus 340 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0053] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0054] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0055] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0056] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0057] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A simulation end verification method, characterized in that: The simulation end verification method comprises: Initialize the simulation end verification platform, and then instantiate the top layer, the design to be tested, and the interface module, wherein the simulation end verification platform includes a sequence generator, a test case library, a reference model, a detection module, and a monitoring module, wherein the sequence generator is used to generate a stimulus input to the design to be tested, the test case library is used to provide a test case that is simultaneously sent to the design to be tested and the reference model, and the detection module is used to compare the output of the reference model with the output of the design to be tested through the interface module to generate a detection result; Configure the monitoring module's monitoring enable signal, monitoring priority, timeout period, read / write control signal threshold ratio, and data request signal threshold ratio, wherein the timeout period is a preset simulation end time associated with the test case; When the configured monitoring work enable signal is enabled, the read / write control signal holding time and the data request signal holding time of the interface module are monitored based on the configured monitoring priority, timeout time, read / write control signal threshold ratio, and data request signal threshold ratio, so as to determine whether to end the simulation of the test case, including: The monitoring module obtains the test case priority from the monitored signal of the interface module, and then compares the test case priority with the monitoring priority. When the test case priority is higher than the monitoring priority, the monitoring module stops monitoring the interface module, and when the simulation time of the test case reaches the timeout time, the simulation of the test case ends. Determine whether the read / write control signal of the interface module remains unchanged for a period of time equal to a configured read / write control signal threshold ratio of a configured timeout period, and if so, determine to end the simulation of the test case. Determine whether the non-transition time of the data request signal of the interface module reaches a configured data request signal threshold ratio of the configured timeout time, and if so, determine to end the simulation of the test case.

2. The simulation end verification method according to claim 1, characterized in that: The simulation end verification method also includes: When the configured monitoring work enable signal is disabled, the monitoring module does not monitor the interface module, and when the simulation time of the test case reaches the timeout period, the simulation of the test case ends.

3. The simulation end verification method according to claim 1, characterized in that: The test case priority is configured by the test case library or the design to be tested, and the test case priority corresponds to the test case.

4. The simulation end verification method according to claim 1, characterized in that: When the simulation time of a previous test case relative to the test case exceeds a preset redundancy threshold, the monitoring priority is configured as the highest priority.

5. The simulation end verification method according to claim 1, characterized in that: The read / write control signal threshold ratio and the data request signal threshold ratio are configured based on simulation verification customization requirements.

6. The simulation end verification method according to claim 1, characterized in that: The simulation end verification method also includes: The monitoring module monitors the simulation waveform output by the interface module. When it is detected that the size of the simulation waveform is greater than a preset maximum value, it is determined to end the simulation of the test case, and then the position where the size of the detected simulation waveform is greater than the preset maximum value is fed back.

7. The simulation end verification method according to claim 1, characterized in that: The simulation end verification method also includes: Through the monitoring module, the simulation time of the test case is compared with the global maximum simulation end time. When it is detected that the simulation time of the test case reaches the global maximum simulation end time, it is determined to end the simulation of the test case, and then, the error of the simulation time of the test case reaching the global maximum simulation end time is fed back, wherein the global maximum simulation end time is independent of the timeout time and independent of the test case.

8. The simulation end verification method according to claim 1, characterized in that: The timeout period is determined independently of the number of packets sent and the packet length associated with the test case, and the number of packets sent and the packet length associated with the test case can be modified through the test case library.

9. The simulation end verification method according to claim 1, characterized in that: The timeout period is determined based on the number of packets sent and the packet length associated with the test case.

10. The simulation end verification method according to claim 1, characterized in that: The operation of the monitoring module is independent of the operation of the sequence generator, the operation of the test case library, the operation of the reference model, the operation of the interface module and the operation of the monitoring module.

11. An electronic device, characterized in that: The electronic device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 10 when executing the computer program.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 10.

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