An asynchronous FIFO based on event-driven circuit and data processing method thereof
By designing an asynchronous FIFO based on an event-driven circuit, using the handshake signal driving circuit of request and response, the adaptation problem of asynchronous FIFO to the event-driven circuit is solved, and efficient data processing and energy savings are achieved.
Patent Information
- Application Number
- CN202411816914.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2044-12-11
AI Technical Summary
The existing asynchronous FIFO driven based on clock signals is not suitable for event-driven circuit designs and cannot effectively adapt to communication between asynchronous FIFO and event-driven circuits.
Design an asynchronous FIFO based on event-driven circuit, and operates through a request and reply handshake signal driving circuit, including a dual-port RAM module, a write pointer self-increase module, a read pointer self-increase module, a Gray code conversion module, a full and read empty judgment module, a two-stage register and a write/read control path.
The adaptation of asynchronous FIFO to event-driven circuits is realized, which reduces the circuit dynamic power consumption and saves energy, and solves the problem of mismatch in data processing speeds of asynchronous FIFO in event-driven circuits.
Smart Images
Figure CN119294323B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to an asynchronous FIFO based on an event-driven circuit and a data processing method thereof. Background Art
[0002] As the scale of integrated circuits continues to expand, multiple clocks will inevitably be generated, thus introducing different clock domains. Communication between different clock domains requires cross-clock domain processing. FIFO (first in first out) is a first-in-first-out data storage circuit, usually composed of a dual-port RAM and an additional control circuit. Asynchronous FIFO is one of the commonly used methods for cross-clock domain processing of multi-bit signals; at the same time, asynchronous FIFO can also be used as a data buffer to solve the problem of data transmission rate mismatch between two circuits. It has a wide range of uses in digital signal processing, large-capacity storage, and remote communication.
[0003] Current large-scale integrated circuits are all globally asynchronous and locally synchronous, and the driving signals in the circuits are all stable pulse signals provided by the clock. However, there is no clock signal in the event-driven circuit, and the circuit modules at the front and back stages communicate and drive the circuit to work through the handshake of the event pulse signal of request and response. Therefore, the existing asynchronous FIFO driven by the clock signal is not suitable for the circuit design based on the event-driven type. In view of this, the present invention proposes an asynchronous FIFO design method based on the event-driven circuit design to solve the adaptation problem of the asynchronous FIFO to the event-driven circuit. Summary of the invention
[0004] In view of the problems existing in the above-mentioned background technology, the purpose of the present invention is to provide an asynchronous FIFO based on an event-driven circuit and a data processing method thereof. The circuit does not rely on a clock signal, but works through a request and response handshake signal driving circuit, thereby solving the adaptation problem of the asynchronous FIFO to the event-driven circuit.
[0005] In order to achieve the above object, the present invention adopts the following technical solution:
[0006] An asynchronous FIFO based on an event-driven circuit, comprising:
[0007] Dual-port RAM module for storing data;
[0008] The write pointer auto-increment module is used to update the write address after each write operation is completed;
[0009] The read pointer auto-increment module is used to update the read address after each read operation is completed;
[0010] Gray code conversion module for write pointer / read pointer;
[0011] A full judgment module is used to judge whether the FIFO is full;
[0012] The read empty judgment module is used to judge whether the FIFO is read empty;
[0013] Two-level registers for sampling write pointer / read pointer Gray code;
[0014] A write / read control path, used to drive the two-stage register to transmit the write pointer / read pointer Gray code, wherein the start signal of the write / read control path is a write / read request event;
[0015] In the asynchronous FIFO, the access signal between modules is a "request-response" handshake signal, and the modules are driven by a "request-response" event-driven circuit.
[0016] Furthermore, the write / read control path includes a click asynchronous control unit, which is a core component of the write / read control path.
[0017] The present invention further provides a data processing method of an asynchronous FIFO based on an event-driven circuit, comprising the following steps:
[0018] The write / read control path starts working after receiving the write / read request event signal, generates a pulse signal to drive the register to sample, and transmits data to the write full or read empty judgment module to judge whether the FIFO is full or read empty; after completing a data write or data read, the write / read control path generates a corresponding write / read response signal and sends it to the access module in the external circuit module; when the external circuit module accessing the FIFO receives the write / read response signal, the current write operation or read operation is completed, and the next read / write operation is performed;
[0019] When performing a write operation, the input data and the write request event signal are bound together and input into the FIFO;
[0020] When a read operation is performed, only the read request event is input into the FIFO;
[0021] When the FIFO is full, the full signal, which is an output signal indicating whether the FIFO is full, is set to a high level. After a data is read out, the full signal is set to a low level. When the external module detects that the full signal is at a low level, a write operation is performed.
[0022] After the FIFO is initialized and read empty, the output signal empty, which indicates whether the FIFO is empty, is set to a high level. After writing a data, the empty signal is set to a low level. When the external module detects that the empty signal is at a low level, it performs a read operation.
[0023] When the FIFO is empty, the read pointer will catch up with the write pointer. When the FIFO is full, the write pointer will circle around and catch up with the read pointer.
[0024] Furthermore, when the Verilog language is used to implement the judgment of whether the FIFO is full or empty, the FIFO is judged to be full or empty by extending one pointer bit and then converting the pointer into Gray code. The judgment condition is: when the FIFO is empty, the write pointer Gray code after the extended conversion is equal to the read pointer Gray code; when the FIFO is full, the highest two bits of the read pointer Gray code and the write pointer Gray code after the extended conversion are opposite, and the other low bits are the same.
[0025] Furthermore, in order to reduce the probability of metastable state when sampling the write pointer and the read pointer, when judging whether the FIFO is full or empty, the read pointer and the write pointer converted into Gray code are respectively pulsed twice and then compared.
[0026] Compared with the shortcomings and deficiencies of the prior art, the present invention has the following beneficial effects:
[0027] (1) The asynchronous FIFO based on the event-driven circuit proposed by the present invention does not rely on the clock signal in the circuit, but works by driving the circuit through the handshake signal of request and response, thus solving the adaptation problem of the asynchronous FIFO to the event-driven circuit;
[0028] (2) Since the present invention adopts an event-driven circuit design method, there is no clock pulse signal that jumps all the time in the circuit. The circuit starts working only when the request event signal arrives, and the circuit remains static at other times, which greatly reduces the dynamic power consumption of the circuit and saves energy. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a schematic diagram of the structure of an asynchronous FIFO based on an event-driven circuit provided by an embodiment of the present invention;
[0030] Figure 2 is a schematic diagram of the structure of a click asynchronous control unit provided in an embodiment of the present invention;
[0031] Figure 3 is a schematic diagram of the structure of a write control path provided by an embodiment of the present invention;
[0032] Figure 4 It is a structural diagram of a read control path provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0034] An asynchronous FIFO based on an event-driven circuit, whose structure is as follows Figure 1 As shown, including:
[0035] Dual-port RAM module for storing data;
[0036] The write pointer auto-increment module is used to update the write address after each write operation is completed;
[0037] The read pointer auto-increment module is used to update the read address after each read operation is completed;
[0038] Gray code conversion module for write pointer / read pointer;
[0039] A full judgment module is used to judge whether the FIFO is full;
[0040] The read empty judgment module is used to judge whether the FIFO is read empty;
[0041] Two-level registers for sampling write pointer / read pointer Gray code;
[0042] The write / read control path is used to drive the two-level register to transmit the write pointer / read pointer Gray code. The start signal of the write / read control path is the write / read request event.
[0043] The access signal between each module is a "request-response" handshake signal, and each module is driven by a "request-response" event-driven circuit.
[0044] Combine the following Figure 1 The data processing method of an asynchronous FIFO based on an event-driven circuit is described. The asynchronous FIFO based on an event-driven circuit of the present invention can be used as a data buffer to deal with the problem of data processing speed mismatch between the front and rear modules in the event-driven circuit. Among them, the dual-port RAM module is the core module in the FIFO. As a data storage area, it undertakes the task of storing data. When implemented in Verilog language, the dual-port RAM module can be defined as a reg-type register group.
[0045] wr is the abbreviation of write, and rd is the abbreviation of read. wr_data is the input data, which is the data written once in the dual-port RAM module. wr_req is an input signal, which indicates a write request event. When a write operation is performed, the input data wr_data and the write request event wr_req signal are bound together and input into the FIFO. rd_data is the output data, which is the data read once from the dual-port RAM module. rd_req is an input signal, which indicates a read request event. When a read operation is performed, only the read request event rd_req is input into the FIFO. wr_ptr is a write pointer, which indicates the address of this write operation. rd_ptr is a read pointer, which indicates the address of this read operation. Since the present invention adopts an event-driven circuit design, the read request event rd_req and the write request event wr_req will only come when the read operation and the write operation are required, and will not come at other times. Therefore, the present invention only uses the two signals of the read request event rd_req and the write request event wr_req to control the completion of the read operation and the write operation, without the need for the read enable signal and the write enable signal and the read-write clock signal to cooperate to control the occurrence of the read operation and the write operation as in the circuit design driven by the clock signal. rd_ptr_g is the value of the read pointer rd_ptr after the gray code conversion, and the values of rd_ptr_g after passing through the two-level registers are rd_ptr_g0 and rd_ptr_g1 respectively; wr_ptr_g is the value of the write pointer wr_ptr after the gray code conversion, and the values of wr_ptr_g after passing through the two-level registers are wr_ptr_g0 and wr_ptr_g1 respectively.
[0046] The full signal is an output signal, indicating whether the FIFO is full. When the FIFO is full, the output signal full signal is set to a high level. When the full signal is high, the FIFO cannot be written, and can only be read. When a data is read out, the full signal is set to a low level. The external module can only write when it detects that the full signal is low.
[0047] The empty signal is an output signal, indicating whether the FIFO is empty. After the FIFO is initialized and the FIFO is read empty, the output signal empty signal is set to a high level. When the empty signal is high, the FIFO cannot be read, only written. After a data is written, the empty signal is set to a low level. The external module can only perform a read operation when it detects that the empty signal is low.
[0048] By comparing the size relationship between the read pointer rd_ptr and the write pointer wr_ptr, we can determine whether the FIFO is full or empty. When the FIFO is full or empty, the read pointer rd_ptr is equal to the write pointer wr_ptr. After completing a write operation, the write pointer wr_ptr will increase by 1. Similarly, after completing a read operation, the read pointer rd_ptr will increase by 1. Therefore, when the FIFO is empty, the read pointer rd_ptr will catch up with the write pointer wr_ptr, and when the FIFO is full, the write pointer wr_ptr will catch up with the read pointer after a circle (after the address increases to the maximum value and then increases by 1, it will return to the minimum address value). When using the Verilog language to implement, the pointer bit can be extended by one bit and then converted into Gray code to determine whether the FIFO is full or empty. The judgment condition at this time is: when the FIFO is empty, the extended converted write pointer Gray code is equal to the read pointer Gray code; when the FIFO is full, the extended converted read pointer Gray code and the write pointer Gray code have the highest two bits opposite, and the rest of the low bits are the same. In order to reduce the probability of metastable state when sampling the write pointer and the read pointer, it is necessary to perform a size comparison operation on the read pointer and the write pointer converted into Gray code after two beats. Because the Gray codes of two adjacent read and write pointers are only one bit different, converting the pointer into Gray code and then beating it twice before sampling can greatly reduce the probability of metastable state.
[0049] The function of the write / read control path is to replace the clock signal in the traditional clock-driven circuit to drive the two-stage register to work. Its core component is the click asynchronous control unit, and its structure is as follows: Figure 2 As shown, inR is the external input "request" signal, inA is the external output "response" signal, outR is the external output "request" signal, outA is the external input "response" signal, and the fire signal is output to the outside as the drive signal of the register. The working process of the click asynchronous control unit is as follows: initially, inR, inA, outR, outA, and fire signals are all low level. When inR is received, the fire signal is pulled to a high level through the XOR gate and the AND gate. At this time, the rising edge of the fire signal is output to the outside to reach the register connected to it, and on the other hand, it drives the trigger inside click to output a high level, so outR and inA also become high levels. At this time, because inR and inA are both high levels, the XOR gate outputs a low level; outR and outA are one high and one low, and the XOR gate also outputs a low level, so the fire signal is restored to a low level after passing through the AND gate. After receiving outA from the next level circuit, the entire click returns to its initial state to wait for the next inR. The structures of the write control path and the read control path are shown as follows. Figure 3 and 4As shown, the write request event wr_req and the read request event rd_req are the start signals of the write control path and the read control path respectively. After receiving the write / read request event signal, the write / read control path starts the click asynchronous control unit to generate a pulse signal to drive the register for sampling, and transmits the data to the write full or read empty judgment module to judge whether the FIFO is full or read empty; after completing a data write or data read, the write / read control path generates a corresponding write response signal wr_ack or read response signal rd_ack and sends it to the access module in the external circuit module; when the external circuit module accessing the FIFO receives the write / read response signal, the current write operation or read operation is completed, and the next read / write operation is performed.
[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A data processing method of an asynchronous FIFO based on an event-driven circuit, characterized in that: The asynchronous FIFO based on the event-driven circuit comprises: Dual-port RAM module for storing data; The write pointer auto-increment module is used to update the write address after each write operation is completed; The read pointer auto-increment module is used to update the read address after each read operation is completed; Gray code conversion module for write pointer / read pointer; A full judgment module is used to judge whether the FIFO is full; The read empty judgment module is used to judge whether the FIFO is read empty; Two-level registers for sampling write pointer / read pointer Gray code; A write / read control path, used to drive the two-stage register to transmit the write pointer / read pointer Gray code, wherein the start signal of the write / read control path is a write / read request event; In the asynchronous FIFO, the access signal between modules is a "request-response" handshake signal, and the modules are driven by a "request-response" event-driven circuit; The data processing method comprises the following steps: The write / read control path starts working after receiving the write / read request event signal, generates a pulse signal to drive the register to sample, and transmits data to the write full or read empty judgment module to judge whether the FIFO is full or read empty; after completing a data write or data read, the write / read control path generates a corresponding write / read response signal and sends it to the access module in the external circuit module; when the external circuit module accessing the FIFO receives the write / read response signal, the current write operation or read operation is completed, and the next read / write operation is performed; When performing a write operation, the input data and the write request event signal are bound together and input into the FIFO; When a read operation is performed, only the read request event is input into the FIFO; When the FIFO is full, the full signal, which is an output signal indicating whether the FIFO is full, is set to a high level. After a data is read out, the full signal is set to a low level. When the external module detects that the full signal is at a low level, a write operation is performed. After the FIFO is initialized and read empty, the output signal empty, which indicates whether the FIFO is empty, is set to a high level. After writing a data, the empty signal is set to a low level. When the external module detects that the empty signal is at a low level, it performs a read operation. When the FIFO is empty, the read pointer will catch up with the write pointer. When the FIFO is full, the write pointer will circle around and catch up with the read pointer.
2. The data processing method of the asynchronous FIFO based on the event-driven circuit according to claim 1, characterized in that: The write / read control path includes a click asynchronous control unit.
3. The data processing method of the asynchronous FIFO based on the event-driven circuit according to claim 1, characterized in that: When using Verilog language to implement the judgment of whether the FIFO is full or empty, the FIFO is judged to be full or empty by extending one pointer bit and then converting the pointer into Gray code. The judgment condition is: when the FIFO is empty, the write pointer Gray code after the extended conversion is equal to the read pointer Gray code; when the FIFO is full, the highest two bits of the read pointer Gray code after the extended conversion are opposite to the write pointer Gray code, and the other low bits are the same.
4. The data processing method of the asynchronous FIFO based on the event-driven circuit as claimed in claim 3, characterized in that: When judging whether the FIFO is full or empty, the read pointer and the write pointer converted into Gray code are respectively clocked twice and then compared.