Low-latency virtual EMIF software design method, device, medium and system

Abstract

The invention discloses a low-delay virtual EMIF software design method, device, medium and system, and belongs to the field of spaceflight measurement and control, the method comprises the following steps: a PS unit and a PL unit of a ZYNQ chip are connected by adopting an AXI bus, and the PL unit and an FPGA chip are interconnected by adopting a discrete line; a virtual EMIF read-write control module in the PL unit is used for converting an AXI bus time sequence into a virtual EMIF bus time sequence, and output virtual EMIF bus related signals are connected through an inter-chip connecting line between the PL unit and the FPGA chip in a discrete line mode. The invention provides a solution which is simple and reliable and can reduce data receiving and transmitting transmission delay and improve the real-time performance of system data transmission.

Description

Technical Field

[0001] The present invention relates to the field of aerospace measurement and control, and more specifically, to a low-latency virtual EMIF software design method, device, medium and system. Background Art

[0002] ZYNQ is a chip based on ARM architecture, integrating processor (PS unit) and programmable logic (PL unit), with high programmability and flexibility, which can adapt to different application requirements. In recent years, ZYNQ+FPGA has been increasingly used in hardware design in the field of aerospace measurement and control.

[0003] On the one hand, ZYNQ receives instructions from the host computer through the network port and sends them to the FPGA for processing; on the other hand, it reads the instructions from the FPGA and returns information such as results or status, and reports them through the network port.

[0004] In traditional designs, the PS unit implements the transmission and reception of instructions with the FPGA through the PL unit, which is connected to the FPGA through the GTX bus or SPI bus. The PS unit implements the write FPGA operation. First, the PS unit writes the instruction to the PL unit through the AXI-Bram_Ctrl method; then the PL unit encodes the PS write instruction, writes it into the local FIFO of the PL unit, reads it when the FIFO is not empty, and sends it to the FPGA through the GTX bus or SPI bus; finally, the received data packet is decoded and parsed in the FPGA unit, the relevant instructions are obtained, and written into the corresponding address unit. The PS unit implements the read FPGA operation. Since the AXI-Bram_Ctrl read operation needs to return the read result to the PS unit within one clock cycle of the read operation, a PS unit read FPGA operation needs to be split into two steps to execute. First, the PS unit read instruction is sent to the FPGA unit as a write operation; secondly, the FPGA unit decodes and analyzes the received data packet. For the PS unit read FPGA operation, the FPGA actively sends it to the PL unit through the GTX bus or SPI bus. The PL unit decodes and analyzes the data packet received from the FPGA and writes it to the corresponding AXI-Bram address unit. Finally, the PS unit initiates a second data read operation to read the data in the address unit corresponding to the AXI-Bram, indirectly realizing the PS unit reading the data in the FPGA unit. In the above method, since the PS reads and writes the FPGA through the two-level transfer method between the PL and the FPGA, the delay of a 32-bit instruction read and write operation will reach the us level, which becomes inapplicable for occasions with high real-time requirements. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a low-latency virtual EMIF software design method, device, medium and system, which solves the problem of low real-time performance and high latency in the reading and writing FPGA operations of the ZYNQ chip PS unit in the existing measurement and control system without increasing the complexity of the software.

[0006] The object of the present invention is achieved through the following solutions:

[0007] A low-latency virtual EMIF software design system includes a ZYNQ chip PS unit, a ZYNQ chip PL unit and an FPGA chip, wherein the ZYNQ chip PS unit and the PL unit are connected by an AXI bus, and the PL unit and the FPGA chip are interconnected by discrete lines;

[0008] A virtual EMIF read-write control module is built into the PL unit, and the virtual EMIF read-write control module is used to convert the AXI bus timing into the EMIF bus timing; and the virtual EMIF read-write control module is used to output the chip select EMIF_ce_n, write enable EMIF_awe_n, read enable EMIF_aoe_n, address bus EMIF_a, and bidirectional data bus EMIF_d signals related to the virtual EMIF bus; and the ZYNQ chip PL unit and the FPGA chip are connected through the inter-chip connection lines in the form of discrete lines.

[0009] Furthermore, the chip select EMIF_ce_n uses 1 bit, the write enable EMIF_awe_n uses 1 bit, the read enable EMIF_aoe_n uses 1 bit, the address bus EMIF_a uses 24 bits, and the bidirectional data bus EMIF_d uses 32 bits, which requires a total of 59 bits, that is, the PL unit and the FPGA require 59 discrete lines for interconnection. When the interconnection lines between the PL unit and the FPGA are insufficient, the address bus EMIF_a and the bidirectional data bus EMIF_d can be reduced.

[0010] A low-latency virtual EMIF software design method, based on a low-latency virtual EMIF software design system described in Example 1, comprises the following steps:

[0011] The write data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed; monitors whether the AXI write address Valid is valid, otherwise continues to monitor; if yes, then enters the AXI write data Valid validity judgment flow;

[0012] In the AXI write data Valid judgment process, if not, continue to judge; if yes, enter the write data setting Setup cycle process; in the write data setting Setup cycle process, monitor whether the set Setup cycle maximum value is reached, otherwise continue to monitor; if yes, enter the write data setting Strobe cycle process; in the write data setting Strobe cycle process, monitor whether the set Strobe cycle maximum value is reached, otherwise continue to monitor; if yes, enter the write data setting Hold cycle process; in the write data setting Hold cycle process, monitor whether the set Hold cycle maximum value is reached, otherwise continue to monitor; if yes, return to the initial state.

[0013] A low-latency virtual EMIF software design method, based on the low-latency virtual EMIF software design system as described above, comprises the steps of:

[0014] The read data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed; monitor whether the AXI read address Valid is valid, otherwise continue to monitor; if yes, enter the read data setting Setup cycle flow; in the read data setting Setup cycle flow, monitor whether the set Setup cycle maximum value is reached, otherwise continue to monitor; if yes, enter the read data setting Strobe cycle flow; in the read data setting Strobe cycle flow, monitor whether the set Strobe cycle maximum value is reached, otherwise continue to monitor; if yes, enter the read data setting Hold cycle flow; in the read data setting Hold cycle flow, monitor whether the set Hold cycle maximum value is reached, otherwise continue to monitor; if yes, enter the read data Ready whether valid judgment flow; in the read data Ready whether valid judgment flow, otherwise continue to judge; if yes, return to the initial state.

[0015] A low-latency virtual EMIF software design device comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, any of the above methods is executed.

[0016] A computer-readable storage medium stores a computer program, wherein the computer program executes any of the above methods when loaded by a processor.

[0017] The beneficial effects of the present invention include:

[0018] (1) The present invention reduces the data transmission delay and improves the real-time performance of system data transmission. The present invention reduces the ZYNQ chip PS unit reading and writing FPGA unit operation delay from the original us level to the current 100ns level through a virtual EMIF bus.

[0019] (2) The present invention reduces the complexity of the internal program implementation of the PS unit and FPGA unit of the ZYNQ chip. The present invention replaces the traditional design of reading and writing using PL-side encoding and FPGA-side decoding through a virtual EMIF bus. The PS reads the FPGA operation no longer needs to use a two-read indirect access method, so that the ZYNQ chip PS unit has the ability to directly read and write the FPGA unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 A schematic diagram of a low-latency virtual EMIF software design method of the present invention;

[0022] Figure 2 for Figure 1 Implement the schematic diagram;

[0023] Figure 3 for Figure 2 Virtual EMIF read / write control module write data processing flow chart;

[0024] Figure 4 for Figure 2 Virtual EMIF read / write control module read data processing flow chart. DETAILED DESCRIPTION

[0025] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0026] Especially for the occasions where the real-time requirements for reading and writing FPGA instructions by the ZYNQ chip PS unit in the system are high, a low-latency virtual EMIF software design method is designed.

[0027] like Figure 1 As shown, the present invention provides a low-latency virtual EMIF software design method, including: ZYNQ chip PS unit + ZYNQ chip PL unit + FPGA chip composition. The ZYNQ chip PS unit and the PL unit are connected by an AXI bus, and the PL unit and the FPGA chip are interconnected by discrete lines.

[0028] like Figure 2As shown in the figure, the PS unit is the main control unit of the system and is responsible for actively initiating read and write access operations to the FPGA. A virtual EMIF read and write control module is built into the PL unit. On the one hand, this module is responsible for converting the timing of the AXI bus from the PS unit to the timing of the EMIF bus of the PL unit; on the other hand, it outputs the chip select EMIF_ce_n, write enable EMIF_awe_n, read enable EMIF_aoe_n, address bus EMIF_a, and bidirectional data bus EMIF_d related to the virtual EMIF bus; and connects the inter-chip connection between the ZYNQ chip PL unit and the FPGA chip in a discrete line manner.

[0029] Figure 2 In the example, the chip select EMIF_ce_n uses 1 bit, the write enable EMIF_awe_n uses 1 bit, the read enable EMIF_aoe_n uses 1 bit, the address bus EMIF_a uses 24 bits, and the bidirectional data bus EMIF_d uses 32 bits, which requires a total of 59 bits, that is, the PL unit and the FPGA require 59 discrete lines for interconnection. When the interconnection lines between the PL unit and the FPGA are insufficient, the address bus EMIF_a and the bidirectional data bus EMIF_d can be reduced.

[0030] like Figure 3 As shown, the write data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed. Monitor whether the AXI write address Valid is valid. If so, transfer to the AXI write data Valid validity judgment flow. In the AXI write data Valid validity judgment flow, if yes, transfer to the write data setting Setup cycle flow. In the write data setting Setup cycle flow, monitor whether the set Setup cycle maximum value is reached. If yes, transfer to the write data setting Strobe cycle flow. In the write data setting Strobe cycle flow, monitor whether the set Strobe cycle maximum value is reached. If yes, transfer to the write data setting Hold cycle flow. In the write data setting Hold cycle flow, monitor whether the set Hold cycle maximum value is reached. If yes, return to the initial state.

[0031] like Figure 4As shown, the read data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed. Monitor whether the AXI read address Valid is valid. If so, enter the read data setting Setup cycle flow. In the read data setting Setup cycle flow, monitor whether the set Setup cycle maximum value is reached. If so, enter the read data setting Strobe cycle flow. In the read data setting Strobe cycle flow, monitor whether the set Strobe cycle maximum value is reached. If so, enter the read data setting Hold cycle flow. In the read data setting Hold cycle flow, monitor whether the set Hold cycle maximum value is reached. If so, enter the read data Ready validity determination flow. In the read data Ready validity determination flow, if so, return to the initial state.

[0032] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0033] In other embodiments, including but not limited to the following embodiments:

[0034] Example 1

[0035] A low-latency virtual EMIF software design system includes a ZYNQ chip PS unit, a ZYNQ chip PL unit and an FPGA chip, wherein the ZYNQ chip PS unit and the PL unit are connected by an AXI bus, and the PL unit and the FPGA chip are interconnected by discrete lines;

[0036] A virtual EMIF read-write control module is built into the PL unit, and the virtual EMIF read-write control module is used to convert the AXI bus timing into the EMIF bus timing; and the virtual EMIF read-write control module is used to output the chip select EMIF_ce_n, write enable EMIF_awe_n, read enable EMIF_aoe_n, address bus EMIF_a, and bidirectional data bus EMIF_d signals related to the virtual EMIF bus; and the ZYNQ chip PL unit and the FPGA chip are connected through the inter-chip connection lines in the form of discrete lines.

[0037] Example 2

[0038] On the basis of Example 1, the chip select EMIF_ce_n uses 1 bit, the write enable EMIF_awe_n uses 1 bit, the read enable EMIF_aoe_n uses 1 bit, the address bus EMIF_a uses 24 bits, and the bidirectional data bus EMIF_d uses 32 bits, which requires a total of 59 bits, that is, the PL unit and the FPGA require 59 discrete lines for interconnection. When the interconnection lines between the PL unit and the FPGA are insufficient, the address bus EMIF_a and the bidirectional data bus EMIF_d can be reduced.

[0039] Example 3

[0040] A low-latency virtual EMIF software design method, based on a low-latency virtual EMIF software design system described in Example 1, comprises the following steps:

[0041] The write data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed; monitors whether the AXI write address Valid is valid, otherwise continues to monitor; if yes, then enters the AXI write data Valid validity judgment flow;

[0042] In the AXI write data Valid judgment process, if not, continue to judge; if yes, enter the write data setting Setup cycle process; in the write data setting Setup cycle process, monitor whether the set Setup cycle maximum value is reached, otherwise continue to monitor; if yes, enter the write data setting Strobe cycle process; in the write data setting Strobe cycle process, monitor whether the set Strobe cycle maximum value is reached, otherwise continue to monitor; if yes, enter the write data setting Hold cycle process; in the write data setting Hold cycle process, monitor whether the set Hold cycle maximum value is reached, otherwise continue to monitor; if yes, return to the initial state.

[0043] Example 4

[0044] A low-latency virtual EMIF software design method, based on a low-latency virtual EMIF software design system described in Example 1, comprises the following steps:

[0045] The read data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed; monitor whether the AXI read address Valid is valid, otherwise continue to monitor; if yes, enter the read data setting Setup cycle flow; in the read data setting Setup cycle flow, monitor whether the set Setup cycle maximum value is reached, otherwise continue to monitor; if yes, enter the read data setting Strobe cycle flow; in the read data setting Strobe cycle flow, monitor whether the set Strobe cycle maximum value is reached, otherwise continue to monitor; if yes, enter the read data setting Hold cycle flow; in the read data setting Hold cycle flow, monitor whether the set Hold cycle maximum value is reached, otherwise continue to monitor; if yes, enter the read data Ready whether valid judgment flow; in the read data Ready whether valid judgment flow, otherwise continue to judge; if yes, return to the initial state.

[0046] Example 5

[0047] A low-latency virtual EMIF software design device includes a processor and a memory, wherein a computer program is stored in the memory. When the computer program is loaded by the processor, the method described in any one of Embodiments 3 to 4 is executed.

[0048] Example 6

[0049] A computer-readable storage medium stores a computer program in the readable storage medium. The computer program is loaded by a processor and executes the method described in any one of Embodiments 3 to 4.

[0050] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0051] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.

[0052] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

Claims

1. A low-latency virtual EMIF software design system, characterized in that: It includes a ZYNQ chip PS unit, a ZYNQ chip PL unit and an FPGA chip. The ZYNQ chip PS unit and the PL unit are connected by an AXI bus, and the PL unit and the FPGA chip are interconnected by discrete lines. A virtual EMIF read-write control module is built into the PL unit, and the virtual EMIF read-write control module is used to convert the AXI bus timing into the EMIF bus timing; and the virtual EMIF read-write control module is used to output the chip select EMIF_ce_n, write enable EMIF_awe_n, read enable EMIF_aoe_n, address bus EMIF_a, and bidirectional data bus EMIF_d signals related to the virtual EMIF bus; and the ZYNQ chip PL unit and the FPGA chip are connected through the inter-chip connection lines in the form of discrete lines.

2. The low-latency virtual EMIF software design system according to claim 1, characterized in that: The chip select EMIF_ce_n uses 1 bit, the write enable EMIF_awe_n uses 1 bit, the read enable EMIF_aoe_n uses 1 bit, the address bus EMIF_a uses 24 bits, and the bidirectional data bus EMIF_d uses 32 bits, which requires a total of 59 bits, that is, the PL unit and the FPGA require 59 discrete lines for interconnection. When the interconnection lines between the PL unit and the FPGA are insufficient, the address bus EMIF_a and the bidirectional data bus EMIF_d can be reduced.

3. A low-latency virtual EMIF software design method, characterized in that: A low-latency virtual EMIF software design system based on claim 1 comprises the following steps: The write data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed; Monitor whether the AXI write address Valid is valid, otherwise continue monitoring; if it is, transfer to the AXI write data Valid validity judgment process; In the AXI write data Valid judgment process, if not, continue to judge; if yes, enter the write data setting Setup cycle process; in the write data setting Setup cycle process, monitor whether the set Setup cycle maximum value is reached, otherwise continue to monitor; if yes, enter the write data setting Strobe cycle process; in the write data setting Strobe cycle process, monitor whether the set Strobe cycle maximum value is reached, otherwise continue to monitor; if yes, enter the write data setting Hold cycle process; in the write data setting Hold cycle process, monitor whether the set Hold cycle maximum value is reached, otherwise continue to monitor; if yes, return to the initial state.

4. A low-latency virtual EMIF software design method, characterized in that: A low-latency virtual EMIF software design system based on claim 1 comprises the following steps: The read data processing flow of the virtual EMIF read / write control module in the PL unit enters the initial state after the power-on reset is completed; Monitor whether the AXI read address Valid is valid, otherwise continue monitoring; if yes, enter the read data setting Setup cycle process; in the read data setting Setup cycle process, monitor whether the set Setup cycle maximum value is reached, otherwise continue monitoring; if yes, enter the read data setting Strobe cycle process; in the read data setting Strobe cycle process, monitor whether the set Strobe cycle maximum value is reached, otherwise continue monitoring; if yes, enter the read data setting Hold cycle process; in the read data setting Hold cycle process, monitor whether the set Hold cycle maximum value is reached, otherwise continue monitoring; if yes, enter the read data Ready whether valid judgment process; in the read data Ready whether valid judgment process, otherwise continue judging; if yes, return to the initial state.

5. A low-latency virtual EMIF software design device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 3 to 4 is executed.

6. A computer-readable storage medium, characterized in that: A computer program is stored in the readable storage medium, and the computer program is loaded by a processor to execute the method according to any one of claims 3 to 4.

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