A quantum logic gate construction method, a dicke2 quantum state preparation method, and related devices

Abstract

The application discloses a quantum logic gate construction method, a Dicke2 quantum state preparation method and related devices. The quantum state preparation method comprises the following steps: determining a quantum bit used for preparing a Dicke2 quantum state; and applying a plurality of disentanglement quantum logic gates to the quantum bit with an initial state of the Dicke2 quantum state to obtain a disentanglement quantum circuit, wherein the action relationship between the disentanglement quantum logic gate and the quantum bit in a later layer action time sequence is determined according to the action relationship between the disentanglement quantum logic gate and the quantum bit in a previous layer action time sequence; determining an inverse circuit of the disentanglement quantum circuit as a target quantum circuit; and running the target quantum circuit to prepare the Dicke2 quantum state. Compared with the prior art, the Dicke2 quantum state preparation method provided by the application only needs a layer for the depth of the circuit, so that a bit pair logarithmic preparation scheme of the Dicke2 quantum state can be realized, and the running time of a quantum computer can be effectively compressed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and in particular to a quantum logic gate construction method, a Dicke2 quantum state preparation method and related devices. BACKGROUND

[0002] Quantum computing is a new computing mode that regulates quantum information units according to quantum mechanics. Unlike classical computing, quantum computing follows the laws of quantum mechanics, which is a new computing mode that can break through the bottleneck of classical computing power. When a device processes and computes quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers have the ability to process mathematical problems more efficiently than ordinary computers, for example, they can accelerate the time to break RSA keys from hundreds of years to hours, so they have become a key technology under research.

[0003] Dicke2 quantum state is a uniform quantum state with only two states and the rest are states. In mathematics, chemistry and finance, there are many times when Dicke2 quantum states are needed to prepare initial states to solve corresponding problems. How to efficiently prepare Dicke2 quantum states in quantum computing has become a technical problem to be solved. SUMMARY

[0004] The purpose of the present application is to provide a quantum logic gate construction method, a Dicke2 quantum state preparation method and related devices to solve the technical problems in the prior art, and to achieve efficient preparation of Dicke2 quantum states in quantum computing.

[0005] In a first aspect, the present application provides a disentangling quantum logic gate construction method, which comprises:

[0006] A first H gate, a parametric RY gate and a second H gate acting on each quantum bit in turn are obtained; wherein the angle parameter of the parametric RY gate of two quantum bits is opposite in value;

[0007] A first controlled rotation gate is constructed at the first evolution time sequence and the second evolution time sequence on two quantum bits, the control bits of the two first controlled rotation gates are the same quantum bit, wherein the first evolution time sequence is the time sequence between the first H gate and the parametric RY gate, and the second evolution time sequence is the time sequence between the parametric RY gate and the second H gate.

[0008] In a second aspect, the present application provides a Dicke2 quantum state preparation method, which comprises:

[0009] Determining quantum bits for preparing Dicke2 quantum states;

[0010] A plurality of disentangling quantum logic gates are applied to the quantum bits in an initial state of a Dicke2 quantum state to obtain a disentangling quantum circuit, wherein the disentangling quantum logic gates are constructed by the method described above, and wherein the action relationship between the disentangling quantum logic gates and the quantum bits in a later action sequence is determined by the action relationship between the disentangling quantum logic gates and the quantum bits in a previous action sequence.

[0011] An inverse circuit of the disentangling quantum circuit is determined as a target quantum circuit.

[0012] The target quantum circuit is run to prepare the Dicke2 quantum state.

[0013] The Dicke2 quantum state preparation method described above, wherein preferably, the action relationship between the disentangling quantum logic gates and the quantum bits in a later action sequence is determined by the action relationship between the disentangling quantum logic gates and the quantum bits in a previous action sequence, comprises:

[0014] In each action sequence, the quantum bits are re-grouped to form a plurality of quantum bit pairs, each of which includes a first bit quantum bit and a second bit quantum bit, and the first bit quantum bit is lower than the second bit quantum bit.

[0015] In the first action sequence, the quantum bits from the lowest bit to the highest bit are sequentially grouped, each two quantum bits form a quantum bit pair, and each quantum bit pair is applied to a disentangling quantum logic gate.

[0016] In other action sequences, a plurality of quantum bits are re-grouped according to the action relationship between the disentangling quantum logic gates and the quantum bits in a previous action sequence to form a quantum bit set, the quantum bits in the quantum bit set come from the first bit quantum bit or the second bit quantum bit in the quantum bit pair in each previous action sequence that is not evolved into a state, and the quantum bits in the quantum bit set are sequentially grouped from the lowest bit to the highest bit, each two quantum bits form a quantum bit pair, and each quantum bit pair is applied to a disentangling quantum logic gate.

[0017] The Dicke2 quantum state preparation method described above, wherein preferably, in the first action sequence, the quantum bits from the lowest bit to the highest bit are sequentially grouped, each two adjacent quantum bits form a quantum bit pair, and each quantum bit pair is applied to a disentangling quantum logic gate.

[0018] ​In other layer action timing, a plurality of quantum bits are re-grouped according to the action relationship of the disentanglement quantum logic gate and the quantum bit in the previous layer action timing, to form a quantum bit set, the quantum bits in the quantum bit set come from the quantum bit not evolved into state of the first bit quantum bit or the second bit quantum bit in each previous layer action timing, the quantum bits in the quantum bit set are sequentially grouped from low bit to high bit, every two adjacent two quantum bits form a quantum bit pair, and each quantum bit pair acts on a disentanglement quantum logic gate.

[0019] The preparation method of the Dicke 2 quantum state as described above, preferably, the disentanglement quantum circuit further comprises a second controlled rotation gate acting on each disentanglement quantum gate, the control bit of the second controlled rotation gate is the target bit of the first controlled rotation gate, and the target bit of the second controlled rotation gate is the control bit of the first controlled rotation gate.

[0020] The preparation method of the Dicke 2 quantum state as described above, preferably, the first controlled rotation gate is a controlled Z gate, and the second controlled rotation gate is a controlled X gate.

[0021] The preparation method of the Dicke 2 quantum state as described above, preferably, the target quantum circuit further comprises an H gate acting on all quantum bits, and the H gate is located after the multi-layer action timing of the entanglement quantum logic gate on the quantum bits.

[0022] In a third aspect, the present application provides a Dicke 2 quantum state preparation device, the device comprising:

[0023] An acquisition module is configured to determine quantum bits for preparing a Dicke 2 quantum state.

[0024] A disentanglement quantum circuit construction module is configured to construct a disentanglement quantum circuit, a plurality of disentanglement quantum logic gates acting on quantum bits in an initial state of a Dicke 2 quantum state to obtain a disentanglement quantum circuit, wherein the action relationship of the disentanglement quantum logic gate and the quantum bit in a next layer action timing is determined by the action relationship of the disentanglement quantum logic gate and the quantum bit in a previous layer action timing.

[0025] A target quantum circuit construction module is configured to determine the inverse circuit of the disentanglement quantum circuit as a target quantum circuit.

[0026] A running module is configured to run the target quantum circuit to prepare the Dicke 2 quantum state.

[0027] In a fourth aspect, the present application provides a storage medium, wherein the storage medium stores a computer program, and the computer program is configured to implement the method as described above when the computer program is executed.

[0028] In a fifth aspect, the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the method as described above.

[0029] Compared with the prior art, the Dicke2 quantum state preparation method provided by the present application only needs to compress the depth of the circuit to layer, so that the bit pair logarithmic preparation scheme of the Dicke2 quantum state can be realized, and the running time of the quantum computer can be effectively compressed. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a network block diagram of a quantum circuit construction system provided by an embodiment of the present application;

[0031] Figure 2 is a flowchart of a disentangled quantum logic gate preparation method provided by an embodiment of the present application;

[0032] Figure 3 is a structural diagram of a disentangled quantum logic gate provided by an embodiment of the present application;

[0033] Figure 4 is a flowchart of a Dicke2 quantum state preparation method provided by an embodiment of the present application;

[0034] Figure 5 is a structural diagram of a disentangled quantum circuit provided by an embodiment of the present application;

[0035] Figure 6 is a structural diagram of a target quantum circuit provided by an embodiment of the present application;

[0036] Figure 7 is a structural diagram of another disentangled quantum circuit provided by an embodiment of the present application;

[0037] Figure 8 is a structural diagram of another target quantum circuit provided by an embodiment of the present application;

[0038] Figure 9 is a structural diagram of a Dicke2 quantum state preparation device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be explained as a limitation of the present application.

[0040] Structure of a quantum circuit construction system

[0041] Figure 1 is a network block diagram of a quantum circuit construction system provided by an embodiment of the present application. The quantum circuit construction system can include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and can also include additional storage, classical processors, quantum processors, and other devices not shown.

[0042] The network 110 is a medium for providing communication links between various devices and computers connected together in the quantum circuit construction system, including but not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof, and the connection mode can use wired, wireless communication links, or optical fiber cables, etc.

[0043] The server 120 and the client 140 are conventional data processing systems that can contain data and have application programs or software tools that perform conventional computing processes. The client 140 can be a personal computer or a network computer, so the data can also be provided by the server 120. The wireless device 130 can be a smartphone, a tablet, a notebook computer, a smart wearable device, etc. The storage unit 150 can include a database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0044] The classical processing system 160 (quantum processing system 170) can include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data), which can be boot files, operating system images, and application programs 162 (application programs 173), which can be used to implement quantum algorithms compiled according to the quantum circuit construction method provided by the embodiments of the present application.

[0045] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0046] It should be noted that a real quantum computer is a hybrid structure, which includes at least Figure 1 two parts: the classical processing system 160, responsible for performing classical computation and control; the quantum processing system 170, responsible for running quantum programs and thus implementing quantum computation.

[0047] The classical processing system 160 and the quantum processing system 170 can be integrated in one device or distributed in two different devices. For example, a first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, and storage and network services required by quantum applications are also provided. A user develops a quantum application through the quantum application development tools and services thereon, and sends the quantum program to a second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, parses the code of the quantum program through the quantum computer operating system, and compiles it into instructions that can be recognized and executed by the quantum computer control system, and the quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0048] In the classical processing system 160 based on a silicon chip, the units of the classical processor 161 are CMOS tubes, and such computing units are not limited by time and coherence, that is, such computing units are not limited by the use time and are available at any time. In addition, in the silicon chip, the number of such computing units is also sufficient, and the number of computing units in a classical processor is currently thousands or even tens of thousands. The number of computing units is sufficient and the computing logic of the CMOS tube is fixed, for example: AND logic. When operating with CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the effect of operation.

[0049] Unlike such logic units in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and also limited by coherence time, that is, the quantum bit is limited by the use time and is not available at any time. It is a key problem of quantum computing to fully use the quantum bit within the available use time of the quantum bit. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of the quantum computer, and each quantum bit realizes computing functions through logic functions configured on demand, and given the limited number of quantum bits and the diversified logic functions in the field of quantum computing, for example: Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. When quantum computing, a limited number of quantum bits are combined with a variety of logic functions to achieve the effect of operation.

[0050] Based on these differences, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit's use) is crucial to improving the computational performance of quantum computers and requires specialized design. The aforementioned design considerations for qubits are technical issues that ordinary computing devices do not need to address.

[0051] [Methods for Constructing Unentangled Quantum Logic Gates]

[0052] In the embodiments provided by this invention, a de-entangled quantum logic gate is provided. This entangled quantum logic gate is used to realize controlled rotation operations between two entangled qubits, where the quantum states of the two qubits are... state and Transitions between states.

[0053] Reference Figure 2 As shown, the present invention also provides a method for constructing a de-entangled quantum logic gate, wherein the constructed de-entangled quantum logic gate refers to... Figure 3 As shown, the construction method includes:

[0054] S101: Determine two qubits and obtain the first H gate, the parametric RY gate, and the second H gate that are sequentially applied to each qubit; wherein, the angle parameter of the parametric RY gate of the two qubits takes the opposite value, and the absolute value of the angle parameter of the parametric RY gate is jointly determined by the quantum state amplitude value of each qubit.

[0055] S102: A first controlled rotation gate is constructed at both the first and second evolution timings on the two qubits. Preferably, the first controlled rotation gate is a controlled Z gate, and the control bits of the two first controlled rotation gates are on the same qubit. The first evolution timing is the timing between the first H gate and the parametric RY gate, and the second evolution timing is the timing between the parametric RY gate and the second H gate.

[0056] [Dicke2 quantum state preparation method]

[0057] Dicke2 has only two quantum states. The rest are states The embodiments provided in this invention assume that the initial state of a certain unentangled quantum circuit is the Dicke2 quantum state to be prepared; then, by unentanglement processing the Dicke2 quantum state, the target quantum state can be evolved to a uniform quantum state. The above steps are classical processing procedures for quantum circuits of the state, which can be implemented using a quantum simulator.

[0058] Furthermore, the inverse circuit of the aforementioned deentangled quantum circuit can be constructed to obtain the target quantum circuit, and the target quantum circuit can be run and applied to the initial state. The Dicke 2 quantum state is prepared on the quantum bits, so that the preparation of the Dicke 2 quantum state is realized on a real quantum chip.

[0059] In an implementable embodiment, referring to FIG. 1, Figure 4 As shown in FIG. 1, the present application provides a method for preparing a Dicke 2 quantum state, comprising the following steps:

[0060] Step S201: determining quantum bits for preparing a Dicke 2 quantum state.

[0061] The number of quantum bits corresponding to the Dicke 2 quantum state can be predetermined, can be determined according to the number of quantum bits supported by a quantum device, and is generally less than or equal to the number of quantum bits supported by the quantum device. When the quantum device supports a large number of quantum bits, the number of quantum bits required for preparation can be selected as appropriate.

[0062] Step S202: applying a plurality of disentanglement quantum logic gates to the quantum bits in an initial state of a Dicke 2 quantum state to obtain a disentanglement quantum circuit, the disentanglement quantum circuit being used to evolve the Dicke 2 quantum state into a state of The disentanglement quantum logic gates are constructed by the method described above, wherein the action relationship between the disentanglement quantum logic gates and the quantum bits in a later action time sequence is determined by the action relationship between the disentanglement quantum logic gates and the quantum bits in an earlier action time sequence.

[0063] In the disentanglement quantum circuit, each disentanglement quantum logic gate acts on two preset quantum bits, which can be two quantum bits at adjacent positions or two quantum bits at spaced positions, and can be determined according to the setting of the circuit, without being limited herein. Along the action time sequence, the plurality of disentanglement quantum logic gates are distributed in multiple layers, each layer of disentanglement quantum logic gates includes at least one disentanglement quantum logic gate, and the disentanglement quantum logic gates in the same layer of disentanglement quantum logic gates act on the same action time sequence.

[0064] In the disentanglement quantum circuit, the disentanglement quantum logic gates play a role of disentangling two quantum bits. After the disentanglement quantum circuit acts on the two quantum bits, the disentangling of the two quantum bits is completed. After each quantum bit of a target quantum state passes through the action time sequence of each layer of disentanglement quantum logic gates, part of the quantum bits are disentangled with each other, until after passing through all the action time sequences, a state of is obtained.

[0065] Step S203: determining the inverse circuit of the disentanglement quantum circuit as the target quantum circuit. The target quantum circuit has target quantum logic gates, which are determined based on the disentanglement quantum logic gates, wherein the action relationship between the target quantum logic gate and the quantum bit in the previous layer action timing is determined by the action relationship between the target quantum logic gate and the quantum bit in the next layer action timing.

[0066] The number of target quantum logic gates of the target quantum circuit is the same as the number of disentanglement quantum logic gates of the disentanglement quantum circuit, and the execution timing of the plurality of target quantum logic gates is opposite to that of the plurality of disentanglement quantum logic gates.

[0067] The target quantum circuit is obtained by inverse deduction of the disentanglement quantum circuit. In the target quantum circuit, each target quantum logic gate acts on two preset quantum bits, which can be two quantum bits at adjacent positions or two quantum bits at spaced positions. Since the Dicke2 state is a symmetric quantum state, two quantum bits can be freely set. At the same time, the maximum parallel executable quantum gate pair needs to be satisfied, so as to efficiently complete disentanglement. Along the action timing, the plurality of target quantum logic gates are distributed in multiple layers, each layer of target quantum logic gates includes at least one target quantum logic gate, and the target quantum logic gates in the same layer of target quantum logic gates act on the same action timing.

[0068] In the target quantum circuit, the target quantum logic gate functions to generate a preset entangled state between two quantum bits, and the initial state is After each quantum bit of the state passes through a layer of target quantum logic gates, part of the quantum bits are entangled with each other, and after passing through all the action timings, the Dicke2 quantum state is obtained.

[0069] Step S204: running the target quantum circuit to prepare the Dicke2 quantum state. In specific preparation, the target quantum circuit is first obtained, and then the corresponding quantum operation of the target quantum circuit is run on the quantum chip to prepare the Dicke2 quantum state.

[0070] Based on the Dicke2 quantum state preparation method provided in the above embodiment, the depth of the circuit only needs to be layer, so that the bit pair logarithmic preparation scheme of the Dicke2 quantum state is realized, and the running time of the quantum computer can be effectively compressed.

[0071] Further, the specific method for determining the action relationship between the disentanglement quantum logic gate and the quantum bit in the next layer action timing from the action relationship between the disentanglement quantum logic gate and the quantum bit in the previous layer action timing is as follows:

[0072] Each quantum bit in the disentanglement quantum circuit needs to be uniquely identified, so each quantum bit is assigned a unique number to distinguish different quantum bits. In the embodiments provided by the present application, the quantum bits in the disentanglement quantum circuit are sequentially numbered from the lowest bit to the highest bit. For example, as shown in FIG. 1, the disentanglement quantum circuit has eight quantum bits, and the numbers of the eight quantum bits are sequentially arranged from 1 to 8. The first quantum bit is located at the top of the diagram, which is the lowest bit quantum bit. The eighth quantum bit is located at the bottom of the diagram, which is the highest bit quantum bit. Figure 5

[0073] In each layer of action timing, the quantum bits are re-grouped to form a plurality of quantum bit pairs. Each quantum bit pair includes a first bit quantum bit and a second bit quantum bit. The first bit quantum bit is at a lower bit than the second bit quantum bit. In each layer of action timing, each quantum bit pair is acted on by a disentanglement quantum logic gate.

[0074] In the first layer of action timing, the quantum bits from the lowest bit to the highest bit are sequentially grouped. Every two quantum bits form a quantum bit pair. The two quantum bits can be two quantum bits at adjacent positions or two quantum bits at spaced positions. Preferably, every two adjacent quantum bits form a quantum bit pair. Each quantum bit pair is acted on by a disentanglement quantum logic gate, so as to disentangle the two quantum bits. After the disentanglement quantum logic gate acts on the two quantum bits, the disentanglement of the two quantum bits is completed. The first bit quantum bit or the second bit quantum bit is evolved into a state.

[0075] In other layers of action timing, a plurality of quantum bits are re-grouped according to the action relationship between the disentanglement quantum logic gate and the quantum bits in the previous layer of action timing to form a quantum bit set. The quantum bits in the quantum bit set come from the first bit quantum bit or the second bit quantum bit that is not evolved into a state in each quantum bit pair in the previous layer of action timing. The quantum bits in the quantum bit set are sequentially grouped from the lowest bit to the highest bit. Every two quantum bits form a quantum bit pair. The two quantum bits can be two quantum bits at adjacent positions or two quantum bits at spaced positions. Preferably, every two adjacent quantum bits form a quantum bit pair. Each quantum bit pair is acted on by a disentanglement quantum logic gate.

[0076] After each quantum bit of the target quantum state passes through a layer of disentanglement quantum logic gate, part of the quantum bits are disentangled with each other. After passing through all the action timings, the initial approximate state is obtained.

[0077] ​​​​The deentanglement quantum circuit provided by this invention can directly deentangle the first layer. The number of qubits, half the number of qubits remaining after the second layer of deentanglement. By continuing in this way, all entanglement can eventually be completed, and the depth of the line only needs to be... layer.

[0078] In one feasible implementation, refer to Figure 5 As shown, an example of a deentangled quantum circuit with 8 qubits will be used for illustration:

[0079] In the first layer of the interaction sequence, every two adjacent qubits are grouped into four qubit pairs, namely [1,2], [3,4], [5,6], and [7,8]. Each qubit pair is subjected to a deentangled quantum logic gate, which limits the second qubit in the qubit pair to approximately The state, that is, the state after the qubits 2, 4, 6 and 7 are acted upon, is approximately state.

[0080] After the first layer of interaction, the amplitude approximately exists on qubits 1, 3, 5, and 7. In the second layer of interaction, the remaining qubits are regrouped, this time into pairs of [1,3] and [5,7]. Each pair is subjected to a deentanglement quantum logic gate, constraining the second qubit in the pair to evolve into approximately... The state, that is, the state after the 3rd and 7th qubits are acted upon, is approximately state.

[0081] After the second layer of interaction, the amplitude exists only on qubits 1 and 5. At this point, in the third layer of interaction, only the deentanglement quantum logic gate needs to be applied to qubits 1 and 5 to completely collapse the quantum states on qubits 1 and 5. state.

[0082] For n qubits, let's first assume they are powers of 2, that is... Where m is a positive integer, in the first layer of the action sequence, each qubit is grouped, and the qubit pairs are: [1,2],[3,4],[5,6]......[2 m -1,2 m ].

[0083] The second qubit in a bounded qubit pair is evolved into an approximation After the first layer of interaction, the remaining qubits with amplitude are qubits 1, 3, and so on up to 2. m-1th qubit, in the second layer action timing, re-grouping the remaining qubits, obtaining the following qubit pairs: [1, 3], [5, 7]... [2 m -3, 2 m -1].

[0084] This is until the last layer, only two qubits are left to be grouped, a total of 2n-1 pairs of qubits are needed to be paired layer.

[0085] When considering n qubits are not the exponential of 2, in the first layer action timing, the highest bit qubit is not grouped, in the second layer action timing, the highest bit qubit is included in the range of grouping.

[0086] The following takes 7 qubits as an example:

[0087] Referring to Fig. 1, in the first layer action timing, the qubit pairs are three: [1, 2], [3, 4], [5, 6], and the remaining 7th qubit is not grouped. Figure 7 In the second layer action timing, the 7th qubit is included in the range of grouping, and the qubit pairs are two: [1, 3], [5, 7].

[0088] In the third layer action timing, the qubit pair is [1, 5].

[0089] In the embodiments provided by the present application, the specific method for determining the action relationship between the target quantum logic gate and the qubits in the previous layer action timing of the target quantum circuit from the action relationship between the target quantum logic gate and the qubits in the subsequent layer action timing is as follows:

[0090] Each qubit in the target quantum circuit needs to be uniquely identified, so each qubit is assigned a unique number to distinguish different qubits, in the embodiments provided by the present application, the qubits in the target quantum circuit are numbered from the lowest bit to the highest bit, for example, referring to Fig. 1, the target quantum circuit has 8 qubits, and the numbers of the 8 qubits are arranged in sequence from 1 to 8, the 1st qubit is located at the uppermost position in the figure, which is the lowest bit qubit, and the 8th qubit is located at the lowermost position in the figure, which is the highest bit qubit, which is the same as the number of the disentanglement quantum circuit.

[0091] Figure 6

[0092] ​​In each layer of action timing, the quantum bits are re-grouped to form a plurality of quantum bit pairs, the quantum bits included in different quantum bit pairs are different, each quantum bit pair includes a first bit quantum bit and a second bit quantum bit, the first bit quantum bit is lower than the second bit quantum bit, and each quantum bit pair is subjected to a target quantum logic gate in each layer of action timing.

[0093] In the last layer of action timing, the quantum bits from the lowest bit to the highest bit are sequentially grouped, each two adjacent quantum bits form a quantum bit pair, and each two adjacent quantum bits form a quantum bit pair, and each two adjacent quantum bits from the lowest bit to the highest bit are subjected to a target quantum logic gate in the last layer of action timing. Since the target quantum circuit is obtained by inversely deducing the disentanglement quantum circuit, in the last layer of action timing, the quantum bit pair subjected to the target quantum logic gate is the same as the quantum bit pair subjected to the disentanglement quantum logic gate in the first layer of action timing of the disentanglement quantum circuit.

[0094] In other layers of action timing, a plurality of quantum bits are re-grouped to form a quantum bit set according to the action relationship between the target quantum logic gate and the quantum bits in the next layer of action timing, and the quantum bits in the quantum bit set are sequentially grouped from low bits to high bits to form quantum bit pairs. Here, it can be deduced from the disentanglement quantum circuit, for example, in the second-to-last layer of action timing, the quantum bit pair subjected to the target quantum logic gate is the same as the quantum bit pair subjected to the disentanglement quantum logic gate in the second layer of action timing of the disentanglement quantum circuit, and the quantum bit pairs of all action timings of the target quantum circuit are obtained by analogy.

[0095] After the initial state quantum bits pass through each layer of target quantum logic gates, some of the quantum bits are entangled with each other, and after passing through all the action timings, the Dicke2 quantum state is obtained.

[0096] In a feasible implementation, refer to Figure 6 As shown in the figure, a target quantum circuit with 8-bit quantum bits is taken as an example for description:

[0097] In the last layer of action timing, each two adjacent quantum bits are grouped to form four quantum bit pairs, namely [1, 2], [3, 4], [5, 6] and [7, 8], and each quantum bit pair is subjected to a target quantum logic gate.

[0098] In the second-to-last layer of action timing, the quantum bit pairs are two, namely [1, 3] and [5, 7], and each quantum bit pair is subjected to a conjugate transpose matrix of a unitary matrix (target quantum logic gate).

[0099] In the first layer of the interaction sequence, the target quantum logic gate is applied to qubits 1 and 5.

[0100] For n qubits, let's first assume they are powers of 2, that is... Where m is a positive integer, in the last layer of the action sequence, each qubit is grouped, and the qubit pairs are: [1,2],[3,4],[5,6]......[2 m -1,2 m ].

[0101] In the penultimate engagement sequence, the qubits are rearranged to obtain the following qubit pairs: [1,3],[5,6]......[2 m -3,2 m -1].

[0102] Applying this logic to the first layer of timing, only two qubits remain to be grouped, requiring a total of pairing operations. One layer is sufficient.

[0103] When considering n qubits that are not exponents of 2, the highest-order qubits are not grouped in the last layer of the operational sequence.

[0104] The following example uses 7 qubits:

[0105] Reference Figure 8 As shown, in the last layer of the timing sequence, there are three qubit pairs: [1,2], [3,4], [5,6], and the remaining qubit number 7 is not grouped.

[0106] In the penultimate layer of the timing sequence, qubit 7 is included in the grouping range, and the qubit pair is two: [1,3], [5,7].

[0107] In the first layer of the interaction sequence, the qubit pair is [1,5].

[0108] The quantum state preparation method provided in the above embodiments only requires a certain depth of circuit. This allows for the logarithmic preparation of Dicke2 quantum states, effectively reducing the runtime of quantum computers.

[0109] Furthermore, the deentangled quantum circuit also includes a second controlled rotation gate acting after each deentangled quantum gate. The control bit of the second controlled rotation gate is the target bit of the first controlled rotation gate, and the target bit of the second controlled rotation gate is the control bit of the first controlled rotation gate. Preferably, the second controlled rotation gate is a controlled X gate. Figure 5For example, the control bits of the first controlled rotation gate are the 1st, 3rd, 5th and 7th qubits, and the target bits are the 2nd, 4th, 6th and 8th qubits, and the control bits of the second controlled rotation gate are the 2nd, 4th, 6th and 8th qubits, and the target bits are the 1st, 3rd, 5th and 7th qubits.

[0110] First, we assume that we have qubits in the state:

[0111]

[0112] The first step is to apply the disentangling quantum logic gate on the [1,2], [3,4], [5,6]......[2 m -1,2 m ] qubits, and then apply the second controlled rotation gate on the [1,2], [3,4], [5,6]......[2 m -1,2 m ] qubits, and the quantum state becomes:

[0113]

[0114] Thus, the quantum state preparation of the layer as the final circuit is completed.

[0115] In the embodiments provided by the present application, the target quantum circuit further comprises an H gate acting on all qubits, wherein the H gate is located after the multi-layer action timing sequence of the entangling quantum logic gate on the qubits.

[0116] Structure of the Dicke2 quantum state preparation device

[0117] As shown in Figure 9 , the preparation device comprises:

[0118] The acquisition module is configured to determine the qubits for preparing the Dicke2 quantum state.

[0119] The disentangling quantum circuit construction module is configured to construct a disentangling quantum circuit, and a plurality of disentangling quantum logic gates act on the qubits in the initial state of the Dicke2 quantum state to obtain the disentangling quantum circuit, wherein the action relationship between the disentangling quantum logic gate and the qubit in the next layer action timing sequence is determined by the action relationship between the disentangling quantum logic gate and the qubit in the previous layer action timing sequence.

[0120] The disentangling quantum logic gate is determined based on the disentangling quantum logic gate construction method, the plurality of disentangling quantum logic gates act on the qubits in the initial state of the Dicke2 quantum state to obtain the disentangling quantum circuit, and the disentangling quantum circuit is used to evolve the Dicke2 quantum state into the state.

[0121] a target quantum circuit construction module configured to determine an inverse circuit of the disentangling quantum circuit as the target quantum circuit.

[0122] wherein the inverse circuit of the disentangling quantum circuit is the target quantum circuit, the target quantum circuit has the same number of target quantum logic gates as the disentangling quantum circuit has disentangling quantum logic gates, and the execution timing of the target quantum logic gates is opposite to that of the disentangling quantum logic gates, and the target quantum logic gates are applied to the quantum bits in the initial state of Dicke2 quantum state.

[0123] a running module configured to run the target quantum circuit to prepare the Dicke2 quantum state.

[0124] wherein the running module is a quantum system capable of running a quantum circuit, and an exemplary quantum hardware including a quantum processor and a quantum control system connected in communication is a system, wherein the quantum processor is a quantum chip, and the quantum control system is configured to provide an analog signal for implementing a quantum logic gate in the quantum circuit, and the analog signal is applied to the quantum chip to implement the running of the quantum circuit.

[0125] Structure of storage medium

[0126] The embodiment of the present application further provides a storage medium, and the storage medium stores a computer program, wherein the computer program is set to implement the steps in any of the method embodiments when running.

[0127] Specifically, in the embodiment, the storage medium can be set to store a computer program for implementing the following steps:

[0128] Step S201: determining quantum bits for preparing a Dicke2 quantum state.

[0129] Step S202: applying a plurality of disentangling quantum logic gates to the quantum bits in the initial state of the Dicke2 quantum state to obtain a disentangling quantum circuit, wherein the disentangling quantum logic gates are constructed by using the disentangling quantum logic gate construction method, and wherein the action relationship between the disentangling quantum logic gates and the quantum bits in the next layer of action timing is determined by the action relationship between the disentangling quantum logic gates and the quantum bits in the previous layer of action timing.

[0130] Step S203: determining an inverse circuit of the disentangling quantum circuit as the target quantum circuit.

[0131] Step S204: running the target quantum circuit to prepare the Dicke2 quantum state.

[0132] Structure of electronic device

[0133] The embodiment of the present application also provides an electronic device, comprising a memory and a processor, the memory storing a computer program, and the processor is configured to run the computer program to realize the steps in any of the method embodiments.

[0134] Specifically, the electronic device can further comprise a transmission device connected with the processor and an input-output device connected with the processor.

[0135] Specifically, in the embodiment, the processor can be configured to realize the following steps through the computer program:

[0136] Step S201: determining a quantum bit for preparing a Dicke2 quantum state.

[0137] Step S202: a plurality of disentangling quantum logic gates are applied to the quantum bit with the initial state of the Dicke2 quantum state to obtain a disentangling quantum circuit, the disentangling quantum logic gates are constructed by using the disentangling quantum logic gate construction method, and the action relationship between the disentangling quantum logic gates and the quantum bit in the next layer of action time sequence is determined by the action relationship between the disentangling quantum logic gates and the quantum bit in the previous layer of action time sequence.

[0138] Step S203: determining an inverse circuit of the disentangling quantum circuit as a target quantum circuit.

[0139] Step S204: running the target quantum circuit to prepare the Dicke2 quantum state.

[0140] The above detailed description of the structure, features and effects of the present application is based on the embodiments shown in the drawings. The above description is only the preferred embodiment of the present application, but the present application is not limited by the drawings. Any changes or modifications made in accordance with the concept of the present application, or equivalent embodiments with equivalent changes, shall be within the scope of the present application.

Claims

1. A method for constructing a disentangling quantum logic gate, the method comprising: The method comprises: ​ obtaining a first H gate, a parametric RY gate and a second H gate acting on each qubit in turn; wherein the angle parameter of the parametric RY gate of two qubits is opposite in value; A first controlled rotation gate is constructed at the first evolution time sequence and the second evolution time sequence on two qubits, and the control bits of the two first controlled rotation gates are the same qubit, wherein the first evolution time sequence is the time sequence between the first H gate and the parametric RY gate, and the second evolution time sequence is the time sequence between the parametric RY gate and the second H gate.

2. A method for preparing a Dicke 2 quantum state, said Dicke 2 quantum state being a homogeneous quantum state with only two states and the rest of states, characterized in that, The method comprises: determining a qubit for preparing a Dicke2 quantum state; a plurality of disentangling quantum logic gates act on the qubit whose initial state is the Dicke2 quantum state to obtain a disentangling quantum circuit, wherein the disentangling quantum logic gate is constructed by the method of claim 1, wherein the action relationship between the disentangling quantum logic gate and the qubit in the next layer of action time sequence is determined by the action relationship between the disentangling quantum logic gate and the qubit in the previous layer of action time sequence; determining the inverse circuit of the disentangling quantum circuit as a target quantum circuit; running the target quantum circuit to prepare the Dicke2 quantum state.

3. The method of claim 2, wherein: The action relationship between the disentangling quantum logic gate and the qubit in the next layer of action time sequence is determined by the action relationship between the disentangling quantum logic gate and the qubit in the previous layer of action time sequence, comprising: In each layer of action time sequence, the qubits are re-grouped to form a plurality of qubit pairs, each of which includes a first bit qubit and a second bit qubit, and the first bit qubit is lower than the second bit qubit; In the first layer of action time sequence, the qubits from the lowest bit to the highest bit are sequentially grouped, and each two qubits form a qubit pair, and each qubit pair acts on a disentangling quantum logic gate; In other layer action timing, according to the action relationship of the disentangling quantum logic gate and the quantum bit in the previous layer action timing, a plurality of quantum bits are reorganized to form a quantum bit set, and the quantum bits in the quantum bit set come from the quantum bit in the quantum bit pair in each previous layer action timing, which is not evolved into The first bit quantum bit or the second bit quantum bit in the state, and the quantum bits in the quantum bit set are sequentially grouped from low to high, and each two quantum bits form a quantum bit pair, and each quantum bit pair acts on a disentangling quantum logic gate.

4. The method of claim 3, wherein: In the first layer of action time sequence, the qubits from the lowest bit to the highest bit are sequentially grouped, and each two adjacent qubits form a qubit pair, and each qubit pair acts on a disentangling quantum logic gate; In other layer action timing, according to the action relationship of the disentangling quantum logic gate and the quantum bit in the previous layer action timing, a plurality of quantum bits are reorganized to form a quantum bit set, and the quantum bits in the quantum bit set come from the quantum bit in the quantum bit pair in each previous layer action timing, which is not evolved into The first bit quantum bit or the second bit quantum bit in the state, and the quantum bits in the quantum bit set are sequentially grouped from low to high, and each two adjacent two quantum bits form a quantum bit pair, and each quantum bit pair acts on a disentangling quantum logic gate.

5. The method of claim 2, wherein: The disentangling quantum circuit further comprises a second controlled rotation gate acting after each disentangling quantum logic gate, the control bit of the second controlled rotation gate is the target bit of the first controlled rotation gate, and the target bit of the second controlled rotation gate is the control bit of the first controlled rotation gate.

6. The method of claim 5, wherein: The first controlled rotation gate is a controlled Z gate, and the second controlled rotation gate is a controlled X gate.

7. The method of claim 2, wherein: The target quantum circuit further comprises an H gate acting on all qubits, wherein the H gate is located after the multiple layers of entangling quantum logic gates acting on the qubits.

8. A Dicke 2 quantum state preparation apparatus, the Dicke 2 quantum state being a uniform quantum state with only two states and the rest of the states states, characterized in that, The device comprises: an acquisition module for determining a qubit for preparing a Dicke2 quantum state; The disentanglement quantum circuit construction module is configured to construct a disentanglement quantum circuit, a plurality of disentanglement quantum logic gates acting on quantum bits in an initial state of a Dicke2 quantum state to obtain the disentanglement quantum circuit, wherein the disentanglement quantum logic gates are constructed by using the method in claim 1, and an action relationship between the disentanglement quantum logic gates and the quantum bits in a next layer action timing sequence is determined by an action relationship between the disentanglement quantum logic gates and the quantum bits in a previous layer action timing sequence; The target quantum circuit construction module is configured to determine an inverse circuit of the disentanglement quantum circuit as a target quantum circuit. The running module is configured to run the target quantum circuit to prepare the Dicke2 quantum state.

9. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to implement the method in any one of claims 1 to 7 when running. 10.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to run the computer program to implement the method in any one of claims 1 to 7.

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