Wafer failure analysis method and device, computer equipment and storage medium

Abstract

The invention relates to a wafer failure analysis method and device, computer equipment and a storage medium, and the method comprises the steps: obtaining a failure bitmap of a to-be-detected wafer; based on the defect linetype corresponding to each atomic item in the failure bitmap, detecting the failure bitmap to obtain a linear defect detection result; the defect line type comprises a solid line type defect and a dotted line type defect; and further, outputting failure information of the wafer to be detected according to each detection result. Through the wafer failure analysis method and device, the problem that comprehensive and accurate failure analysis cannot be carried out on the wafer based on different defect categories is solved, comprehensive and accurate failure analysis on the wafer based on different defect categories is realized, and the accuracy of a failure analysis result is improved.

Description

[0001] This application is a divisional application with an application date of June 26, 2024, application number 202410834663.7, and invention name “Wafer failure analysis method, device, computer equipment and storage medium”. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a method, apparatus, computer device and storage medium for analyzing failure of a wafer. Background Art

[0003] With the rapid development of semiconductor technology, chips are widely used in various fields, such as the Internet of Things, information communication, consumer electronics, and medical equipment. As the core component of electronic equipment, the performance and reliability of chips affect the performance and stability of the overall equipment. Wafers are silicon wafers used to make silicon semiconductor integrated circuits. Chips are usually manufactured on the surface of semiconductor wafers, so it is crucial to perform failure analysis on them during the production process of wafers.

[0004] In related technologies, the wafer surface is usually divided into multiple regions, and the failure severity of each region is calculated for defect analysis. However, the above method cannot perform comprehensive and accurate failure analysis on the wafer based on different defect categories, resulting in inaccurate failure analysis results.

[0005] Currently, no effective solution has been proposed to address the problem in related technologies that it is impossible to conduct comprehensive and accurate failure analysis on wafers based on different defect categories. Summary of the invention

[0006] In this embodiment, a wafer failure analysis method, apparatus, computer equipment and storage medium are provided to solve the problem in the related art that a comprehensive failure analysis of the wafer cannot be performed, resulting in inaccurate failure analysis results.

[0007] In a first aspect, a wafer failure analysis method is provided in this embodiment, the method comprising:

[0008] Obtaining a failure bitmap of the wafer to be inspected;

[0009] Determine a corresponding detection order according to a plurality of preset defect categories; the defect categories are different defect pixel point combinations in the failure bitmap;

[0010] Based on the detection order corresponding to each defect category, the failure bitmap is detected to obtain multiple detection results;

[0011] According to each of the detection results, the failure information of the wafer to be detected is output.

[0012] In some embodiments, determining the corresponding inspection order according to the preset multiple defect categories includes:

[0013] Determine a defect detection unit corresponding to each defect category; the defect detection unit is a minimum pixel point combination for analyzing whether there is a defect in the failure bitmap under each defect category;

[0014] Based on the detection conflict relationship between the defect detection units, the detection order corresponding to each defect category is determined.

[0015] In some embodiments, the detecting the failure bitmap based on the detection order corresponding to each defect category includes:

[0016] Performing detection based on the detection order corresponding to each defect category, and after completing the detection of the current defect category, removing the detected defective pixels of the current defect category from the failure bitmap;

[0017] The next defect category is detected based on the failure bitmap after defective pixels are eliminated.

[0018] In some embodiments, the defect categories include linear defects, cluster defects, random defects, and bit defects; and the detection of the failure bitmap based on the detection sequence corresponding to each defect category includes:

[0019] Detecting the failure bitmap in the order of detecting linear defects, clustered defects, and random defects;

[0020] After detecting a linear defect or a cluster defect, removing corresponding defective pixels from the failure bitmap;

[0021] It is determined whether the remaining defective pixels in the failure bitmap are random defects. If they are random defects, the detection is terminated; otherwise, the bit defect detection is continued.

[0022] In some embodiments, the defect type is a linear defect; and the detecting the failure bitmap includes:

[0023] Taking each row of pixels and / or each column of pixels in the failure bitmap as an atomic item;

[0024] The failure bitmap is detected based on the defect line type corresponding to each of the atomic items; the defect line type includes a solid line defect and a dotted line defect.

[0025] In some embodiments, the detecting the failure bitmap further includes:

[0026] The line defects include at least one defect subcategory, the defect subcategory consisting of at least one atomic item in each row and / or column;

[0027] After the defect line type corresponding to each of the atomic items is obtained, the line type defects in the failure bitmap are obtained based on the detection priority of the at least one defect subcategory.

[0028] In some embodiments, the defect subclassification and the detecting of the failure bitmap further include:

[0029] After obtaining the defect line type corresponding to each of the atomic items, recording the intersection point information of each row of pixels and each column of pixels;

[0030] After obtaining the detection result of the current defect subcategory, the pixel points that are not intersection points in the detection result of the current defect subcategory are eliminated based on the intersection point information, and then the detection of the next defect subcategory is continued.

[0031] In some embodiments, the defect type is a cluster defect; and the detecting the failure bitmap includes:

[0032] Determine the connection relationship definition between different defective pixels;

[0033] Selecting a plurality of first defective pixel point combinations that meet the connection relationship definition from the failure bitmap;

[0034] Determining whether the number of defective pixels in each of the first defective pixel combinations exceeds a preset threshold;

[0035] According to the judgment result, it is determined whether the first defective pixel combination belongs to the cluster defect.

[0036] In some embodiments, the defect category is a random defect; and the detecting the failure bitmap includes:

[0037] Determine the ratio of the number of defective pixels to the number of all pixels in the failure bitmap;

[0038] Determining whether the ratio exceeds a preset threshold range;

[0039] According to the judgment result, it is determined whether the failure bitmap has the random defect.

[0040] In some embodiments, the defect category is a bit defect; and the detecting the failure bitmap includes:

[0041] Acquire multiple second defective pixel point combinations corresponding to the bit defect;

[0042] Based on the definition information of the second defective pixel combination, semantic segmentation detection is performed on the failure bitmap.

[0043] In some embodiments, outputting failure information of the wafer to be inspected according to each of the inspection results includes:

[0044] Determining multiple current defect categories of the wafer to be inspected according to each of the inspection results;

[0045] Determine the defect point location information corresponding to each of the current defect categories;

[0046] Each of the current defect categories and the corresponding defect point location information is used as failure information of the wafer to be inspected.

[0047] In a second aspect, a wafer failure analysis device is provided in this embodiment, the device comprising: an acquisition module, a setting module, an analysis module and an output module;

[0048] The acquisition module is used to acquire the failure bitmap of the wafer to be detected;

[0049] The setting module is used to determine the corresponding detection order according to a plurality of preset defect categories; the defect categories are different defect pixel point combinations in the failure bitmap;

[0050] The analysis module is used to detect the failure bitmap based on the detection order corresponding to each defect category to obtain multiple detection results;

[0051] The output module is used to output the failure information of the wafer to be inspected according to each of the inspection results.

[0052] In a third aspect, a computer device is provided in this embodiment, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the wafer failure analysis method described in the first aspect is implemented.

[0053] In a fourth aspect, a storage medium is provided in this embodiment, on which a computer program is stored, and when the program is executed by a processor, the wafer failure analysis method described in the first aspect is implemented.

[0054] Compared with the related art, the wafer failure analysis method, apparatus, computer equipment and storage medium provided in the present embodiment obtain a failure bitmap of the wafer to be inspected; determine the corresponding inspection sequence according to multiple preset defect categories, wherein the defect category is a different combination of defect pixels in the failure bitmap; inspect the failure bitmap based on the inspection sequence corresponding to each defect category to obtain multiple inspection results; further, output the failure information of the wafer to be inspected according to each inspection result, thereby solving the problem that a comprehensive and accurate failure analysis of the wafer cannot be performed based on different defect categories, and realizing a comprehensive and accurate failure analysis of the wafer based on different defect categories, thereby improving the accuracy of the failure analysis results.

[0055] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0057] Figure 1 It is a hardware structure block diagram of a terminal device of a wafer failure analysis method provided by an embodiment of the present application;

[0058] Figure 2 is a flow chart of a wafer failure analysis method provided by an embodiment of the present application;

[0059] Figure 3 is a schematic diagram of different defect line types provided by an embodiment of the present application;

[0060] Figure 4 is a schematic diagram of multiple defect subcategories corresponding to linear defects provided in an embodiment of the present application;

[0061] Figure 5 is a schematic diagram related to cluster defects provided by an embodiment of the present application;

[0062] Figure 6 is a schematic diagram of multiple defect subcategories corresponding to bit defects provided by an embodiment of the present application;

[0063] Figure 7 It is a flow chart of a wafer failure analysis method provided by an embodiment of the present application;

[0064] Figure 8 It is a flow chart of a wafer failure analysis method provided by a preferred embodiment of the present application;

[0065] Fig. 9It is a structural block diagram of a wafer failure analysis device provided in one embodiment of the present application.

[0066] In the figure: 102, processor; 104, memory; 106, transmission device; 108, input and output device; 10, acquisition module; 20, setting module; 30, analysis module; 40, output module. DETAILED DESCRIPTION

[0067] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0068] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not represent quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. Usually, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0069] The method embodiment provided in this embodiment can be executed in a terminal, a computer or a similar computing device. For example, running on a terminal, Figure 1 FIG. 1 is a hardware structure diagram of a terminal of the wafer failure analysis method of this embodiment. Figure 1 As shown, the terminal may include one or more ( Figure 1Only one is shown in the figure) processor 102 and memory 104 for storing data, wherein processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA. The above terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0070] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the failure analysis method of the wafer in the present embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0071] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by the communication provider of the terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet wirelessly.

[0072] In this embodiment, a wafer failure analysis method is provided. Figure 2 is a flow chart of the wafer failure analysis method of this embodiment, such as Figure 2 As shown, the process includes the following steps:

[0073] Step S210, obtaining a failure bitmap of the wafer to be inspected;

[0074] Step S220, determining a corresponding detection order according to a plurality of preset defect categories; the defect categories are different defect pixel point combinations in the failure bitmap;

[0075] Step S230, based on the detection order corresponding to each defect category, the failure bitmap is detected to obtain multiple detection results;

[0076] Step S240: outputting failure information of the wafer to be inspected according to each inspection result.

[0077] Specifically, a failure bitmap of the wafer to be inspected is obtained, and the failure bitmap contains defect point information of the wafer to be inspected. Normal points and defect points in the failure bitmap are usually distinguished by using pixels of different colors.

[0078] Before performing failure analysis on the wafer to be inspected, multiple defect categories that need to be inspected are determined. The defect categories include but are not limited to linear defects, clustered defects, random defects, and bit defects, and each defect category includes at least one defect subcategory, such as linear defects including global defects, extensive defects, cross-shaped defects, single-line defects, etc. Based on this, the defect detection unit corresponding to each defect category is analyzed and determined. The defect detection unit refers to the minimum pixel combination used to analyze whether there is a defect in the failure bitmap under each defect category, and the defect detection unit corresponding to each defect category is adjusted according to different failure analysis requirements. For example, clustered defects determine the corresponding minimum pixel combination based on the preset connection relationship definition of defective pixels and the number threshold of defective pixels.

[0079] Furthermore, based on the detection conflict relationship between the defect detection units, the detection order corresponding to each defect category is determined. In this embodiment, the detection conflict relationship refers to the inclusion, overlap, and other relationships between the defect detection units corresponding to different defect categories when the failure bitmap is detected based on different defect categories, so as to avoid the mutual influence of defect detections of different categories and improve the accuracy of detection.

[0080] Where each defect category contains multiple defect subcategories, the defect detection unit corresponding to each defect subcategory is determined, and the corresponding detection order is determined based on the detection conflict relationship between the defect detection units. For example, for multiple defect subcategories under line defects, the detection order is global defect, extensive defect, multi-line defect, double-line defect, cross-shaped defect, and single-line defect.

[0081] Based on the above detection sequence, the failure bitmap is detected to obtain multiple detection results. According to each detection result, multiple current defect categories of the wafer to be detected are determined, and then the defect point location information corresponding to each current defect category is determined, and each current defect category and the corresponding defect point location information are used as the failure information of the wafer to be detected. Among them, when the detection result is a global defect or a widespread defect, that is, all the pixels of the failure bitmap are defective points or contain defective pixels exceeding the threshold, the subsequent detection of other defect categories is stopped, and the current detection result is output as the failure analysis result of the wafer to be detected; if subsequent detection is required, after obtaining the detection result corresponding to each defect category, the defective pixel points corresponding to the current defect category in the failure bitmap are eliminated, and the intermediate state diagram during the defect detection process is recorded.

[0082] In order to view the failure analysis results intuitively and flexibly, when each test result is obtained, a test result image corresponding to each test result can be generated as the failure information of the wafer to be tested. The test result image is associated with the defect category to which it belongs and contains the corresponding defect point location information.

[0083] After that, the failure information of the wafer to be inspected is output to the visualization interface for display. In the visualization interface, the user can retrieve the corresponding failure bitmap and all its inspection result images by inputting image query information, such as image path, and then use the multiple selection box to select the defect category to be displayed, and adjust the configuration parameters, that is, the threshold and other parameter information under different defect categories, to retrieve the inspection result image that meets the screening conditions for display, and update the display content of the inspection result image at the same time. In addition, another tab page can be called to display the intermediate state diagram generated during the failure analysis process, so that users can locate and analyze the location of defect detection problem points.

[0084] In existing wafer failure analysis methods, the wafer surface is usually divided into multiple regions, and the failure severity of each region is calculated for defect analysis. However, the above method cannot perform comprehensive and accurate failure analysis on the wafer based on different defect categories, resulting in inaccurate failure analysis results.

[0085] Compared with the prior art, this embodiment obtains the failure bitmap of the wafer to be inspected; determines the corresponding detection order according to multiple preset defect categories, where the defect category is a combination of different defect pixels in the failure bitmap; detects the failure bitmap based on the detection order corresponding to each defect category to obtain multiple detection results; further, outputs the failure information of the wafer to be inspected according to each detection result. Based on this, by performing multi-category defect detection on the failure bitmap according to a reasonable detection order, the failure analysis result of the wafer is obtained, which solves the problem of not being able to perform a comprehensive and accurate failure analysis on the wafer based on different defect categories, and realizes a comprehensive and accurate failure analysis of the wafer based on different defect categories, thereby improving the accuracy of the failure analysis result.

[0086] In some embodiments, determining the corresponding inspection order according to the preset multiple defect categories in step S220 includes the following steps:

[0087] Step S221, determining a defect detection unit corresponding to each defect category; the defect detection unit is a minimum pixel point combination for analyzing whether a failure bitmap has a defect under each defect category;

[0088] Step S222: determining the detection order corresponding to each defect category based on the detection conflict relationship between each defect detection unit.

[0089] Specifically, the defect detection unit corresponding to each defect category is analyzed, and the defect detection unit is used to analyze whether there is a minimum pixel combination of defects in the failure bitmap under each defect category. For example, clustering defects determine the corresponding minimum pixel combination based on the preset connection relationship definition of defective pixels and the number threshold of defective pixels.

[0090] It should be noted that the preset multiple defect categories include but are not limited to linear defects, cluster defects, random defects and bit defects, and each defect category includes at least one defect subcategory, for example, linear defects include global defects, extensive defects, cross defects, single line defects, etc. In the case where each defect category contains multiple defect subcategories, the defect detection unit corresponding to each defect subcategory is determined, and the corresponding detection order is determined based on the detection conflict relationship between the defect detection units.

[0091] Furthermore, it is determined whether there is a detection conflict relationship between the defect detection units, and the detection order corresponding to each defect category is determined according to the judgment result of the detection conflict relationship, such as detecting the failure bitmap in the order of linear defects, cluster defects, random defects and bit defects. The detection conflict relationship refers to the inclusion, overlap and other relationships between the defect detection units corresponding to different defect categories when detecting the failure bitmap based on different defect categories.

[0092] Through this embodiment, the defect detection unit corresponding to each defect category is determined, and based on the detection conflict relationship between the defect detection units, the detection order corresponding to each defect category is determined to avoid mutual influence of defect detections of different categories and improve the detection accuracy.

[0093] In some embodiments, the step S230 of detecting the failure bitmap based on the detection order corresponding to each defect category includes:

[0094] Step S231, performing detection based on the detection order corresponding to each defect category, and after completing the detection of the current defect category, removing the detected defective pixels of the current defect category from the failure bitmap;

[0095] Step S232 : the next defect category is detected based on the failure bitmap after defective pixels are eliminated.

[0096] Specifically, detection is performed based on the detection order corresponding to each defect category. After the detection result corresponding to each defect category is obtained, the defective pixels obtained based on the current defect category detection are determined, and the defective pixels of the current defect category detected are eliminated from the failure bitmap.

[0097] Furthermore, based on the failure bitmap after defective pixels are removed, the next defect category detection is performed, and the defect detection of each category is completed in this way. For example, when clustering defects on the failure bitmap, it is detected that there are clustered defects in the failure bitmap, the defective pixels corresponding to the clustered defects are obtained from the current detection results, and the defective pixels are removed from the failure bitmap, and then the detection is performed based on the failure bitmap after the defective pixels are removed.

[0098] Through this embodiment, defective pixels detected in the previous sequence are promptly eliminated during the detection process to avoid affecting subsequent detections, thereby improving the accuracy of various defect detections.

[0099] In some embodiments, the defect categories include linear defects, cluster defects, random defects, and bit defects; the step S230 of detecting the failure bitmap based on the detection order corresponding to each defect category includes:

[0100] The failure bitmap is inspected in the order of linear defects, cluster defects, and random defects;

[0101] After detecting linear defects or cluster defects, the corresponding defective pixels are removed from the failure bitmap;

[0102] Determine whether the remaining defective pixels in the failure bitmap are random defects. If they are random defects, end the detection; otherwise, continue the bit defect detection.

[0103] In this embodiment, the detection order is the detection order of linear defects, cluster defects, and random defects, and the failure bitmap is detected according to the detection order. First, the failure bitmap of the wafer to be detected is input, and the failure bitmap of the wafer to be detected is subjected to linear defect detection, and the defective pixels detected by the linear defect are eliminated from the failure bitmap, and the failure bitmap after eliminating some defective pixels is subjected to cluster defect detection through the segmentation model. If a cluster defect is detected, the defective pixels detected by the cluster defect are further eliminated from the failure bitmap.

[0104] Afterwards, determine whether the remaining defective pixels in the failure bitmap are random defects. If there are random defects, merge the current detection results; if there are no random defects, use the segmentation model to perform bit defect detection on the current failure bitmap, and merge all detection results after the bit defect detection is completed.

[0105] Through this embodiment, the failure bitmap is detected in the order of linear defects, clustered defects, and random defects, and the defective pixels detected in the previous order are promptly eliminated during the detection process to avoid affecting subsequent detections, thereby improving the accuracy of various defect detections.

[0106] In some embodiments, the defect type is a linear defect; the step S230 of detecting the failure bitmap includes the following steps:

[0107] Taking each row of pixels and / or each column of pixels in the invalid bitmap as an atomic item;

[0108] The failure bitmap is detected based on the defect line type corresponding to each atomic item; the defect line type includes solid line defect and dotted line defect.

[0109] In this embodiment, each row of pixels and / or each column of pixels in the failure bitmap is regarded as an atomic item, and the directions of the rows and columns are regarded as the X-axis and the Y-axis respectively, and the defect line type corresponding to each atomic item is determined. The defect line type includes a solid line defect and a dotted line defect, such as Figure 3 As shown, Figure 3 The α defect in is a solid line defect, and the β defect is a dotted line defect; specifically, a solid line defect means that the number of all pixels on the atomic item is the same as the length of each row / column; a dotted line defect means that the proportion of all pixels on the atomic item in the length of each row / column exceeds a certain proportion. In terms of demand setting, dotted line defects may include solid line defects or be in parallel with solid line defects (that is, the proportion setting must be within 100%). Users can choose to detect solid line defects first and then dotted line defects, or detect dotted line defects first and then determine solid line defects from dotted line defects according to their needs. Because different line types are represented by different colors during visualization, it will only affect the difference in display style.

[0110] In some of the embodiments, detecting the failure bitmap further includes:

[0111] Linear defects include at least one defect subcategory, and the defect subcategory consists of at least one atomic item in each row and / or column;

[0112] After the defect line type corresponding to each atomic item is obtained, the line type defect in the failure bitmap is obtained based on the detection priority of at least one defect subcategory.

[0113] Furthermore, after determining the defect line type corresponding to each atomic item, the target atomic item belonging to the solid line defect or the dotted line defect is determined, and it is analyzed whether the atomic item adjacent to or perpendicular to the target atomic item has defects, and the defect subcategory to which the target atomic item belongs is determined according to the analysis result. Among them, the defect subcategories corresponding to the line defect include multi-line defects, double-line defects, cross-shaped defects and single-line defects. It is worth noting that the defect subcategories can also include global defects and widespread defects. When global defects or widespread defects are detected, the defect subcategories such as multi-line defects, double-line defects, cross-shaped defects and single-line defects are not detected.

[0114] Specifically, global defects refer to all pixels in the failure bitmap as defective points, such as Figure 4 As shown in A1 in FIG. 1 ; extensive defects refer to the number of defective pixels in the failure bitmap exceeding the preset number threshold, such as Figure 4 A2 in FIG. 1 shows a multi-line defect; a multi-line defect refers to three or more consecutive target atomic items, for example, three consecutive lateral atomic items of solid line defects (such as Figure 4 A3 in ), three consecutive lateral atomic terms containing dotted and solid defects (such as Figure 4 A4 in), vertical atomic terms of three consecutive solid line defects (such as Figure 4 A5 in ), three consecutive vertical atomic items containing dotted and solid defects (such as Figure 4 A6 in ); double line defects refer to two consecutive target atomic items, specifically including two consecutive vertical atomic items of solid line defects (such as Figure 4 A7 in the figure), the lateral atomic terms of two consecutive dotted line defects (such as Figure 4 A8 in ), the lateral atomic terms of two consecutive solid line defects (such as Figure 4 A9 in ), vertical atomic terms of two consecutive dotted defects (such as Figure 4 A10 in ); a cross defect refers to two mutually perpendicular target atomic items, and the ratio of the number of defective pixels in each target atomic item to its height or width exceeds a preset threshold, specifically including the cross atomic items of two dotted line defects (such as Figure 4 A11 in), the cross-atomic term of two solid line defects (such as Figure 4A12 in ); a single-line defect refers to a single target atomic item, specifically including a vertical atomic item of a single dotted line defect (such as Figure 4 A13 in), vertical atomic terms of single solid line defects (such as Figure 4 A14 in), the lateral atomic term of a single dotted line defect (such as Figure 4 A15 in), the lateral atomic term of a single solid line defect (such as Figure 4 in A16).

[0115] Through this embodiment, each row of pixels and / or each column of pixels in the failure bitmap is taken as an atomic item, and the failure bitmap is detected based on the defect line type corresponding to each atomic item; the defect line type includes solid line defects and dotted line defects, so each row of pixels and / or each column of pixels is detected as an atomic item to ensure the accuracy and comprehensiveness of line defect detection.

[0116] In some embodiments, the defect subclass detects a failure bitmap and further includes:

[0117] After obtaining the defect line type corresponding to each atomic item, the intersection point information of each row of pixels and each column of pixels is recorded;

[0118] After obtaining the detection result of the current defect subcategory, the non-intersection pixel points in the detection result of the current defect subcategory are eliminated based on the intersection point information, and then the detection of the next defect subcategory is continued.

[0119] Specifically, this scheme is to perform defect line type detection corresponding to the atomic items of each row and column separately, and the defect atomic items have detection priority settings, such as detection according to the priority of multi-line defects, double-line defects, cross-shaped defects and single-line defects. If the corresponding pixels are not eliminated after the detection of multi-line defects has been completed, it will cause the detection of subsequent defect subcategories, and deleting all the pixels of the detected multi-line defects will cause the damage to the defect line type of the atomic items in each row or column that have been determined. Therefore, when detecting the defect line type corresponding to each atomic item, the intersection point information of the intersecting atomic items will be recorded. For example, after the detection of multi-line defects is completed, the corresponding pixel point information is saved, and the non-intersection point pixels are deleted based on the intersection point information to ensure the accuracy of subsequent defect subcategory detection.

[0120] In some embodiments, the defect type is a cluster defect; the step S230 of detecting the failure bitmap includes the following steps:

[0121] Determine the connection relationship definition between different defective pixels;

[0122] Selecting a plurality of first defective pixel point combinations that meet the connection relationship definition from the failure bitmap;

[0123] Determining whether the number of defective pixels in each first defective pixel combination exceeds a preset threshold;

[0124] According to the judgment result, it is determined whether the first defective pixel combination belongs to a cluster defect.

[0125] Specifically, when detecting cluster defects, the connection relationship definition between different defective pixels is pre-set. In this embodiment, the connection relationship between points includes but is not limited to the connection relationship of four-connected domains and the connection relationship of eight-connected domains. Among them, the connection relationship of the four-connected domain refers to the existence of adjacent defective pixels in the upper, lower, left or right position of the current defective pixel; the connection relationship of the eight-connected domain refers to the existence of adjacent defective pixels in the upper, lower, left, right, upper left, lower left, upper right or lower right position of the current defective pixel.

[0126] As for the connection relationship judgment of multiple defective pixels, it is usually considered that two defective pixels with common connection defective pixels belong to the same defective pixel combination, that is, belong to the same cluster. For example, if defective pixel a and defective pixel c have no connection relationship, defective pixel a and defective pixel b have a connection relationship, and defective pixel c and defective pixel b have a connection relationship, then defective pixels a, b and c are considered to belong to the same cluster.

[0127] Furthermore, based on the definition of the connection relationship between different defective pixels, the current failure bitmap is detected through the segmentation model to obtain multiple first defective pixel combinations that meet the definition of the connection relationship. It is determined whether the number of defective pixels in each first defective pixel combination exceeds a preset threshold. If the number of defective pixels in the first defective pixel combination exceeds the preset threshold, the first defective pixel combination belongs to a cluster defect. The segmentation model includes but is not limited to the instance segmentation model YOLOv5 and the mask region-based convolutional neural network (Mask R-CNN).

[0128] For example, Figure 5 As shown, the threshold of the number of defective pixels is preset to 10. Figure 5 B1 and Figure 5 In B1 and B2, they all constitute the first defective pixel combination, and the number of defective pixels in B1 is 8, and the number of defective pixels in B2 is 12. Then B1 does not belong to a cluster defect, and B2 is a cluster defect.

[0129] Through this embodiment, the connection relationship definition between different defective pixel points is determined, and multiple first defective pixel point combinations that meet the connection relationship definition are selected from the failure bitmap, and it is determined whether the number of defective pixel points in each first defective pixel point combination exceeds a preset threshold. Then, based on the judgment result, it is determined whether the first defective pixel point combination belongs to a cluster defect, so that detection is performed based on the pre-defined defect point connection relationship and defect point number threshold to ensure the accuracy of cluster defect detection.

[0130] In some embodiments, the defect type is a random defect; the step S230 of detecting the failure bitmap includes the following steps:

[0131] Determine the ratio of the number of defective pixels to the total number of pixels in the failure bitmap;

[0132] Determine whether the ratio exceeds a preset threshold range;

[0133] Based on the judgment result, it is determined whether the failure bitmap has random defects.

[0134] Specifically, when detecting random defects, the number of defective pixels in the current failure bitmap is obtained, the ratio of the number of defective pixels in the failure bitmap to the number of all pixels is calculated, and it is determined whether the ratio exceeds a preset threshold range.

[0135] Furthermore, if the above ratio exceeds the preset threshold range, it indicates that there are no random defects in the current failure bitmap and subsequent detection is required, such as bit defect detection; if the ratio is within the preset threshold range, it is determined that there are random defects in the current failure bitmap and subsequent detection is stopped.

[0136] Through this embodiment, the ratio of the number of defective pixels in the failure bitmap to the total number of pixels is determined, and it is judged whether the ratio exceeds a preset threshold range. Based on the judgment result, it is determined whether there are random defects in the failure bitmap, so as to judge whether there are random defects in the failure bitmap and achieve accurate random defect detection.

[0137] In some embodiments, the defect type is a bit defect; the step S230 of detecting the failure bitmap includes the following steps:

[0138] Obtain multiple second defective pixel point combinations corresponding to the bit defect;

[0139] Based on the definition information of the second defective pixel combination, semantic segmentation detection is performed on the failure bitmap.

[0140] Specifically, a plurality of second defective pixel point combinations corresponding to the preset position defects, each second defective pixel point combination includes a square grid defect (such as Figure 6 C1 in), triangular defects (such as Figure 6C2 in), horizontal two-grid defects (such as Figure 6 C3 in), vertical two-grid defects (such as Figure 6 C4 in) and single-cell defects (such as Figure 6 C5 in ).

[0141] Furthermore, shape information of the defective pixels in each second defective pixel combination and quantity information of the defective pixels are obtained, and the shape information and quantity information are used as definition information of the second defective pixel combination. Based on the definition information of different second defective pixel combinations, semantic segmentation detection is performed on the failure bitmap to detect whether there is a matching second defective pixel combination in the current failure bitmap.

[0142] In this embodiment, semantic segmentation detection can use convolutional neural network U-net, segmentation network (Segmentation Network, SegNet) and fully convolutional neural network (Fully Convolutional Networks, FCN) and the like.

[0143] Through this embodiment, multiple second defective pixel point combinations corresponding to the bit defects are obtained, and based on the definition information of the second defective pixel point combinations, semantic segmentation detection is performed on the failure bitmap to improve the accuracy of bit detection and ensure the integrity of the failure bitmap detection.

[0144] In some embodiments, outputting failure information of the wafer to be inspected according to each inspection result in step S240 includes the following steps:

[0145] Step S241, determining multiple current defect categories of the wafer to be inspected according to each inspection result;

[0146] Step S242, determining the defect point location information corresponding to each current defect category;

[0147] Step S243, taking each current defect category and the corresponding defect point location information as failure information of the wafer to be inspected.

[0148] Specifically, according to each detection result, multiple current defect categories of the wafer to be detected are determined, and the defect point location information corresponding to each current defect category is obtained, and each current defect category and the corresponding defect point location information are used as the failure information of the wafer to be detected.

[0149] It should be noted that when obtaining each test result, a test result image corresponding to each test result can be generated as the failure information of the wafer to be tested. The test result image is associated with the defect category to which it belongs and contains the corresponding defect point location information, so that users can view the failure analysis results intuitively and flexibly in the future.

[0150] Through this embodiment, based on each detection result, multiple current defect categories of the wafer to be detected are determined, and the defect point location information corresponding to each current defect category is determined, and each current defect category and the corresponding defect point location information are used as the failure information of the wafer to be detected, so that the failure analysis results of the wafer to be detected can be visually fed back to the user, which is convenient for locating and analyzing the location of the defect detection problem points.

[0151] The present embodiment is described and illustrated by means of specific examples below.

[0152] Figure 7 FIG. 1 is a flow chart of the wafer failure analysis method of this embodiment. Figure 7 As shown, the wafer failure analysis method specifically includes the following steps:

[0153] A first failure bitmap of a wafer to be inspected is input, and linear defect detection is performed on the first failure bitmap of the wafer to be inspected to obtain a first detection result. Defective pixel points corresponding to the first detection result are eliminated in the first failure bitmap to obtain a second failure bitmap. Cluster defect detection is performed on the second failure bitmap of the wafer to be inspected through a segmentation model to obtain a second detection result. Defective pixel points corresponding to the second detection result are eliminated in the second failure bitmap to obtain a third failure bitmap.

[0154] Further, it is determined whether the third failure bitmap has random defects. If the third failure bitmap has random defects, the various test results are merged, that is, the first test result, the second test result and the third test result corresponding to the random defects are merged, and the merged result is output.

[0155] If there are no random defects in the third failure bitmap, the third failure bitmap is subjected to bit defect detection through the segmentation model to obtain a fourth detection result, and the defective pixels corresponding to the fourth detection result are eliminated in the third failure bitmap to obtain a fourth failure bitmap, and then the various detection results are merged, that is, the first detection result, the second detection result and the fourth detection result corresponding to the bit defect are merged, and the merged result is output.

[0156] The present embodiment is described and illustrated below through preferred embodiments.

[0157] Figure 8 Flow chart of the wafer failure analysis method of the preferred embodiment, as shown in FIG. Figure 8 As shown, the wafer failure analysis method includes the following steps:

[0158] Step S810, obtaining a failure bitmap of the wafer to be inspected;

[0159] Step S820, determining a defect detection unit corresponding to each defect category; the defect detection unit is a minimum pixel point combination for analyzing whether a failure bitmap has a defect under each defect category;

[0160] Step S830, determining the detection order corresponding to each defect category based on the detection conflict relationship between each defect detection unit;

[0161] Step S840, based on the detection order corresponding to each defect category, the failure bitmap is detected to obtain multiple detection results;

[0162] Step S850, determining multiple current defect categories of the wafer to be inspected according to each inspection result;

[0163] Step S860, determining the defect point location information corresponding to each current defect category;

[0164] Step S870: taking each current defect type and the corresponding defect point location information as failure information of the wafer to be inspected.

[0165] In this embodiment, the multiple defect categories include linear defects, cluster defects, random defects and bit defects. According to the detection order of linear defects, cluster defects, random defects and bit defects, the failure bitmap is detected in sequence to obtain corresponding multiple detection results. Among them, linear defects include global defects, extensive defects, multi-line defects, double-line defects, cross-shaped defects and single-line defects, and bit defects include square grid defects, triangle defects, horizontal two-grid defects, vertical two-grid defects and single-grid defects.

[0166] Specifically, firstly, the failure bitmap is detected whether there is a global defect, that is, whether all the pixels in the image are defective points. If all the pixels are defective points, the subsequent detection is stopped and the current detection result is output. If the failure bitmap does not have a global defect, the failure bitmap is detected whether there is a widespread defect, that is, whether the ratio of the defective pixel to all the pixels in the image exceeds a preset threshold. If the ratio of the defective pixel to all the pixels exceeds the preset threshold, the subsequent detection is stopped and the current detection result is output. If the failure bitmap does not have a widespread defect, the failure bitmap is detected in turn whether there are multi-line defects, double-line defects, cross-shaped defects and single-line defects to obtain the corresponding detection results, and the currently detected defective pixels are eliminated in the failure bitmap.

[0167] Afterwards, the current failure bitmap is traversed to perform cluster defect detection, the detection results are recorded, and the currently detected defective pixels are eliminated in the failure bitmap. On the basis of completing the cluster defect detection, it is determined whether there are random defects in the failure bitmap. If there are random defects in the failure bitmap, the subsequent detection is stopped, and all the results obtained by the defect detection are merged and output; if there are no random defects in the failure bitmap, the segmentation model is used to further detect whether there are bit defects in the failure bitmap, and the corresponding detection results are obtained, and all the results obtained by the defect detection are merged and output. Through this embodiment, the failure bitmap of the wafer to be inspected is obtained, and the defect detection unit corresponding to each defect category is determined, wherein the defect detection unit is the minimum pixel combination for analyzing whether there are defects in the failure bitmap under each defect category, and based on the detection conflict relationship between the defect detection units, the detection order corresponding to each defect category is determined.

[0168] Furthermore, based on the detection order corresponding to each defect category, the failure bitmap is detected to obtain multiple detection results, and multiple current defect categories of the wafer to be detected are determined according to each detection result. The defect point location information corresponding to each current defect category is determined, and each current defect category and the corresponding defect point location information are used as the failure information of the wafer to be detected, which solves the problem that it is impossible to perform a comprehensive and accurate failure analysis on the wafer based on different defect categories, realizes a comprehensive and accurate failure analysis on the wafer based on different defect categories, and improves the accuracy of the failure analysis results.

[0169] It should be noted that the steps shown in the above process or the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0170] In this embodiment, a wafer failure analysis device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. The terms "module", "unit", "subunit", etc. used below can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0171] Fig. 9 is a structural block diagram of the wafer failure analysis device of this embodiment, such as Fig. 9 As shown, the device includes: an acquisition module 10, a setting module 20, an analysis module 30 and an output module 40;

[0172] An acquisition module 10 is used to acquire a failure bitmap of a wafer to be inspected;

[0173] A setting module 20 is used to determine a corresponding detection order according to a plurality of preset defect categories; the defect category is a combination of different defective pixels in the failure bitmap;

[0174] An analysis module 30, configured to detect the failure bitmap based on the detection sequence corresponding to each defect category to obtain multiple detection results;

[0175] The output module 40 is used to output failure information of the wafer to be inspected according to each inspection result.

[0176] Through the device provided in this embodiment, a failure bitmap of a wafer to be inspected is obtained; according to a plurality of preset defect categories, a corresponding inspection sequence is determined, wherein the defect category is a different combination of defect pixels in the failure bitmap; based on the inspection sequence corresponding to each defect category, the failure bitmap is inspected to obtain a plurality of inspection results; further, according to each inspection result, failure information of the wafer to be inspected is output, which solves the problem that a comprehensive and accurate failure analysis of the wafer based on different defect categories cannot be performed, realizes a comprehensive and accurate failure analysis of the wafer based on different defect categories, and improves the accuracy of the failure analysis results.

[0177] In some of the embodiments, the setting module 20 is also used to determine the defect detection unit corresponding to each defect category; the defect detection unit is the minimum pixel combination used to analyze whether there is a defect in the failure bitmap under each defect category; based on the detection conflict relationship between the defect detection units, the detection order corresponding to each defect category is determined.

[0178] In some of the embodiments, the setting module 20 is also used to perform detection based on the detection order corresponding to each defect category. After completing the detection of the current defect category, the defective pixels of the current defect category detected are eliminated from the failure bitmap; the detection of the next defect category is performed based on the failure bitmap after the defective pixels are eliminated.

[0179] In some of the embodiments, the setting module 20 is also used to detect the failure bitmap in the order of linear defects, clustered defects, and random defects; after detecting linear defects or clustered defects, the corresponding defective pixels in the failure bitmap are removed; and it is determined whether the remaining defective pixels in the failure bitmap are random defects. If they are random defects, the detection is terminated, otherwise the bit defect detection continues.

[0180] In some of the embodiments, the analysis module 30 is further used to treat each row of pixels and / or each column of pixels in the failure bitmap as an atomic item; based on the defect line type corresponding to each atomic item, the failure bitmap is detected; the defect line type includes a solid line defect and a dashed line defect.

[0181] In some of the embodiments, the analysis module 30 is also used to determine the connection relationship definition between different defective pixel points; select multiple first defective pixel point combinations that meet the connection relationship definition from the failure bitmap; determine whether the number of defective pixels in each first defective pixel point combination exceeds a preset threshold; and determine whether the first defective pixel point combination belongs to a cluster defect based on the judgment result.

[0182] In some of the embodiments, the analysis module 30 is further used to determine the ratio of the number of defective pixels in the failure bitmap to the total number of pixels; determine whether the ratio exceeds a preset threshold range; and determine whether there are random defects in the failure bitmap based on the determination result.

[0183] In some of the embodiments, the analysis module 30 is further used to obtain a plurality of second defective pixel point combinations corresponding to the bit defects; and perform semantic segmentation detection on the failure bitmap based on definition information of the second defective pixel point combinations.

[0184] In some of the embodiments, the output module 40 is also used to determine multiple current defect categories of the wafer to be inspected based on each detection result; determine the defect point location information corresponding to each current defect category; and use each current defect category and the corresponding defect point location information as failure information of the wafer to be inspected.

[0185] It should be noted that the above modules can be functional modules or program modules, and can be implemented by software or hardware. For modules implemented by hardware, the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0186] In this embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0187] Optionally, the computer device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0188] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0189] S1, obtaining a failure bitmap of the wafer to be tested;

[0190] S2, determining a corresponding detection order according to a plurality of preset defect categories; the defect categories are different defect pixel point combinations in the failure bitmap;

[0191] S3, based on the detection order corresponding to each defect category, the failure bitmap is detected to obtain multiple detection results;

[0192] S4, outputting failure information of the wafer to be inspected according to each inspection result.

[0193] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0194] In addition, in combination with the wafer failure analysis method provided in the above embodiments, a storage medium may be provided in this embodiment to implement the method. The storage medium stores a computer program; when the computer program is executed by a processor, any wafer failure analysis method in the above embodiments is implemented.

[0195] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0196] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0197] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0198] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A wafer failure analysis method, characterized in that: The method comprises: Obtaining a failure bitmap of the wafer to be inspected; Taking each row of pixels and / or each column of pixels in the failure bitmap as an atomic item; Based on the defect line type corresponding to each of the atomic items, the failure bitmap is detected to obtain the detection result of the line defect; the defect line type includes a solid line defect and a dotted line defect; According to each of the detection results, the failure information of the wafer to be detected is output.

2. The wafer failure analysis method according to claim 1, characterized in that: The method further comprises: Determine, according to a plurality of preset defect subcategories of linear defects, a defect detection unit corresponding to each defect subcategory, and determine a corresponding detection order based on a detection conflict relationship between the defect detection units; The failure bitmap is detected according to the detection sequence.

3. The wafer failure analysis method according to claim 1 or 2, characterized in that: The detecting the failure bitmap further includes: The line-type defects include at least one defect subcategory, the defect subcategory consisting of at least one atomic item in each row and / or column; After the defect line type corresponding to each of the atomic items is obtained, the line type defects in the failure bitmap are obtained based on the detection priority of the at least one defect subcategory.

4. The wafer failure analysis method according to claim 3, characterized in that: The detecting the failure bitmap further includes: After determining the defect line type corresponding to each of the atomic items, determining a target atomic item that is a solid line defect or a dotted line defect; Analyze whether there are defects in the atomic items adjacent to or perpendicular to the target atomic item, and determine the defect subcategory to which the target atomic item belongs based on the analysis result.

5. The wafer failure analysis method according to claim 3, characterized in that: The detecting the failure bitmap further includes: After obtaining the defect line type corresponding to each of the atomic items, recording the intersection point information of each row of pixels and each column of pixels; After obtaining the detection result of the current defect subcategory, the pixel points that are not intersection points in the detection result of the current defect subcategory are eliminated based on the intersection point information, and then the detection of the next defect subcategory is continued.

6. The wafer failure analysis method according to claim 1, characterized in that: The solid line defect means that the number of all pixels on the atomic item is the same as the length of each row / column; the dotted line defect means that the proportion of the number of all pixels on the atomic item in the length of each row / column exceeds a preset ratio.

7. The wafer failure analysis method according to claim 1, characterized in that: Outputting the failure information of the wafer to be inspected according to each of the inspection results includes: Determining a plurality of current defect subcategories of the wafer to be inspected according to each of the inspection results; Determine defect point location information corresponding to each of the current defect subcategories; Each of the current defect subcategories and the corresponding defect point location information is used as failure information of the wafer to be inspected.

8. A wafer failure analysis device, characterized in that: The device comprises: an acquisition module, an analysis module and an output module; The acquisition module is used to acquire the failure bitmap of the wafer to be detected; The analysis module is used to take each row of pixels and / or each column of pixels in the failure bitmap as an atomic item; The analysis module is further used to detect the failure bitmap based on the defect line type corresponding to each of the atomic items to obtain the detection result of the line defect; the defect line type includes a solid line defect and a dotted line defect; The output module is used to output the failure information of the wafer to be inspected according to each of the inspection results.

9. The wafer failure analysis device according to claim 8, characterized in that: The device also includes a setting module; The setting module is used to determine the defect detection unit corresponding to each defect subcategory according to the preset defect subcategories of multiple linear defects, and determine the corresponding detection order based on the detection conflict relationship between the defect detection units; The analysis module is used to detect the failure bitmap according to the detection sequence.

10. A computer device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps of the wafer failure analysis method according to any one of claims 1 to 7.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the wafer failure analysis method according to any one of claims 1 to 7 are implemented.

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