Sensing, storage and computing integrated visual system based on optoelectronic synaptic devices and memristor devices

Abstract

The present invention discloses a sensing, storage and computing integrated visual system based on photoelectric synaptic devices and memristor devices, belonging to the field of intelligent vision and brain-like computing; the visual system includes: an image sensing module based on photoelectric synaptic devices: using a matrix to arrange photoelectric synaptic devices to convert the two-dimensional image information of the image to be tested into a two-dimensional electrical signal, and preprocessing; and also includes an image recognition module based on an array memristor device: receiving the preprocessed two-dimensional electrical signal, using a memristor array structure, first standardizing the two-dimensional electrical signal to obtain an image feature matrix, and then inputting the feature matrix into a multi-layer convolutional neural network, the multi-layer convolutional neural network performs multiple matrix operations on the input feature matrix, further extracts image feature information, and finally outputs an image recognition result. The visual system can be widely used in the field of image sensing and recognition, and has the characteristics of enhancing fuzzy images and high recognition rate.

Description

Technical Field

[0001] The present invention belongs to the field of intelligent vision and brain-like computing, and specifically relates to a sensing, storage and computing integrated visual system based on photoelectric synaptic devices and memristor devices. Background Art

[0002] At present, fields such as autonomous driving and bionic robots are in a stage of rapid development. Computer vision technology, as a key technical node in this field, is receiving widespread attention. Traditional computer vision technology mainly adopts the von Neumann architecture, which is divided into three modules: sensing, storage, and information processing. It is highly compatible with current mature computer technology. However, due to the limitations of transmission bandwidth and memory performance, the transmission delay and storage delay between sensors, memory and processors greatly limit the performance ceiling of the system. With the rapid development of artificial intelligence technology, the data throughput of intelligent systems has shown explosive growth, and the computing power bottleneck caused by transmission delay and storage delay cannot be ignored. On the other hand, with the further application of micro robots, small drones and other equipment, computer vision systems also urgently need to develop in the direction of low power consumption, lightweight and miniaturization.

[0003] As an emerging intelligent sensing technology, the "sensing, storage and computing integration" technology has attracted great attention from the industry. Inspired by the human visual system, this technology breaks the limitations of the von Neumann architecture, integrates the three functions of sensing, storage and computing, and forms a more efficient and intelligent computing architecture. In the "sensing, storage and computing integration" technology, the perception unit can perform simple pre-processing and storage functions on the data while collecting data; the computing unit can further perform in-depth computing and processing on the data, and store the calculated data in real time, realizing data processing and storage with almost zero delay. However, the "sensing, storage and computing integration" technology is a bionic study of biological neural behavior. Its data transmission and logical operations rely on new devices with synaptic and neuron characteristics, which are difficult to be fully compatible with the current traditional silicon-based logic gate circuits. Therefore, a sensing, storage and computing integrated visual system based on photoelectric synaptic devices and memristor devices is proposed. Summary of the invention

[0004] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a sensing, storage and computing integrated visual system based on photoelectric synapse devices and memristor devices, which solves the problems in the prior art.

[0005] The purpose of the present invention can be achieved through the following technical solutions:

[0006] The sensor-storage-computing integrated visual system based on optoelectronic synaptic devices and memristor devices includes:

[0007] Image sensing module based on photoelectric synapse devices: Matrix-arranged photoelectric synapse devices are used to convert the two-dimensional image information of the image to be measured into a two-dimensional electrical signal and perform preprocessing;

[0008] And, an image recognition module based on array memristor devices: receiving the preprocessed two-dimensional electrical signal, using the memristor array structure, first standardizing the two-dimensional electrical signal to obtain an image feature matrix, and then inputting the feature matrix into a multi-layer convolutional neural network. The multi-layer convolutional neural network performs multiple matrix operations on the input feature matrix to further extract image feature information and finally output image recognition results.

[0009] Furthermore, the preprocessing includes: enhancing image contrast and reducing noise.

[0010] Furthermore, the image sensing module based on photoelectric synapse devices includes: 784 photoelectric synapse devices distributed in a 28×28 array.

[0011] Furthermore, the photoelectric synapse device comprises, from top to bottom, a top electrode, a semiconductor middle layer and a bottom electrode;

[0012] The top electrode is Ag; the semiconductor middle layer is a double-layer structure: Ti3C2MXene-CsPbBr3QDs; and the bottom electrode is a transparent FTO material.

[0013] Furthermore, the preparation process of the Ti3C2MXene-CsPbBr3QDs includes: superimposing a layer of two-dimensional Ti3C2MXene material on the CsPbBr3QDs layer.

[0014] Furthermore, the image recognition module based on array memristor devices includes an array memristor device constructed by multiple memristor devices; wherein every two memristor devices are connected as a unit in a current differential circuit manner, and multiple units are arranged in an array to form the entire array structure.

[0015] Furthermore, the connection method of the current differential circuit is: after the two memristor devices are connected in series, the two ends are connected to the positive word line and the negative word line respectively, and the middle node is connected to the bit line; when the array memristor device works normally, the voltage values ​​of the positive word line and the negative word line are set to be opposite, and the bit line voltage is 0.

[0016] Furthermore, the memristor device comprises, from top to bottom, a top electrode, a middle layer and a bottom electrode;

[0017] The top electrode is Ag; the middle layer is a double-layer structure: MAPbI3-Ti3C2, and the bottom electrode is FTO material.

[0018] Furthermore, the preparation process of the MAPbI3-Ti3C2 includes: superimposing a layer of two-dimensional Ti3C2MXene material under MAPbI3.

[0019] Furthermore, the multi-layer convolutional neural network includes:

[0020] Input layer: receives a 28×28 feature matrix as the input of the entire multi-layer convolutional neural network;

[0021] First convolutional layer: A 5×5 matrix is ​​used as a convolution kernel. A total of 10 convolution kernels are used to perform convolution operations on the feature matrix of the input layer, and 10 24×24 matrices are obtained as the output feature matrix of the first convolutional layer.

[0022] First pooling layer: Perform a 2×2 maximum pooling operation on the output feature matrix of the first convolutional layer to obtain 10 12×12 matrices as the output feature matrix of the first pooling layer;

[0023] Second convolutional layer: Use 10 5×5 matrices as a convolution kernel, and use a total of 20 such convolution kernels to perform convolution operations on the 10 feature matrices output by the first pooling layer, and obtain 20 8×8 matrices as the output feature matrices of the second convolutional layer;

[0024] Second pooling layer: Perform a 2×2 maximum pooling operation on the output feature matrix of the second convolutional layer to obtain 20 4×4 matrices as the output feature matrix of the second pooling layer;

[0025] Linear layer: extract each element of the 20 4×4 matrices output by the second pooling layer to obtain a total of 320 vectors;

[0026] Output layer: Contains 10 output neurons, each of which is fully connected to the 320 vectors of the linear layer, and outputs 10 numerical values ​​representing the probability of recognizing the image as a number from 0 to 9.

[0027] Beneficial effects of the present invention:

[0028] 1. The sensing, storage and computing integrated visual system based on photoelectric synaptic devices and memristor devices proposed in the present invention adopts a new photoelectric synaptic device based on perovskite materials in the image sensing module, and integrates three functions of sensing, storage and processing in a single chip, which not only realizes the conversion of image optical information into electrical signals, but also realizes image noise reduction and short-term storage functions, which is conducive to promoting the development of lightweight and intelligent visual sensing technology.

[0029] 2. The sensing, storage and computing integrated visual system based on optoelectronic synaptic devices and memristor devices proposed in the present invention adopts a new type of memristor device in the image recognition module and constructs an array device using a current differential circuit, thereby improving the accuracy and flexibility of the array unit conductivity modulation, realizing multi-layer convolutional neural networks running on the chip, effectively improving the on-chip computing power, and realizing deep processing and recognition functions of the image; at the same time, due to the non-volatile storage characteristics of the memristor device, real-time storage and access of on-chip network weight information can be achieved, effectively eliminating the data transmission delay and power consumption between the computing unit and the storage unit, and has good application prospects in the fields of storage and computing integration and image recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 Shown is a schematic diagram of the structure of the visual system of the present invention;

[0032] Figure 2 FIG. 1 is a schematic diagram of the hardware structure of the image sensing module of the present invention;

[0033] Figure 3 Shown is a structural diagram of the optoelectronic synapse device of the present invention;

[0034] Figure 4 Shown is the response current curve of the photoelectric synaptic device of the present invention under light stimulation of different intensities;

[0035] Figure 5 The figure shows a handwritten digital image with noise detected by the image sensing module of the present invention;

[0036] Figure 6 The image shown is the image output by the image sensing module of the present invention;

[0037] Figure 7 FIG. 1 is a schematic diagram of the hardware structure of the image recognition module of the present invention;

[0038] Figure 8 for Figure 7 The enlarged schematic diagram of point A in the middle;

[0039] Fig. 9 Shown is a structural diagram of the memristor device of the present invention;

[0040] Fig.10 The figure shows the conductivity change curve of the memristor device of the present invention under multiple continuous pulse stimulations;

[0041] Fig.11 Shown is a schematic diagram of the network structure of a multi-layer convolutional neural network in the present invention;

[0042] Fig.12 Shown is a comparison chart of recognition rates of handwritten digit recognition of the present invention;

[0043] Fig.13 Shown are clear digital images used for the control group. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The present invention designs a sensing, storage and computing integrated intelligent visual system based on photoelectric synaptic devices and memristor devices, uses the photoelectric synaptic devices arranged in a matrix to convert image information into electrical signals and perform noise reduction processing, inputs the processed electrical signals into a hardware multi-layer convolutional neural network based on array memristor devices for digital recognition, and finally outputs the recognition results. The sensing, storage and computing integrated intelligent visual system based on photoelectric memristor devices can be widely used in the field of image sensing and recognition, and has the characteristics of enhancing fuzzy images and high recognition rate.

[0046] like Figure 1 As shown, the sensing, storage and computing integrated visual system based on the optoelectronic synaptic device and the memristor device includes:

[0047] Image sensing module based on photoelectric synaptic devices: Matrix-arranged photoelectric synaptic devices are used to convert the two-dimensional image information of the image to be measured into a two-dimensional electrical signal, and pre-process it, including: enhancing image contrast and reducing noise;

[0048] An image recognition module based on array memristor devices receives the preprocessed two-dimensional electrical signal, and uses the memristor array structure to first standardize the two-dimensional electrical signal to obtain a 28×28 image feature matrix, and then inputs the feature matrix into a multi-layer convolutional neural network. The multi-layer convolutional neural network performs multiple matrix operations on the input feature matrix to further extract image feature information and finally outputs the image recognition result.

[0049] like Figure 2As shown in FIG. 1 , the image sensing module based on the photoelectric synapse device includes: 784 photoelectric synapse devices distributed in a 28×28 array. Under the illumination condition, the different grayscales of each pixel of the image will be converted into different amplitudes of light intensity, which will be irradiated onto the photosynapse array. Each synapse device in the photosynapse array will generate different magnitudes of response current to different amplitudes of light intensity, thereby converting the optical signal of the image into a 28×28 two-dimensional electrical signal.

[0050] like Figure 3 As shown, each photoelectric synaptic device includes, from top to bottom, a top electrode, a semiconductor middle layer, and a bottom electrode. In this embodiment, the top electrode is Ag; the semiconductor middle layer is a CsPbBr3QDs-Ti3C2MXene double-layer structure, where CsPbBr3QDs is an inorganic perovskite quantum dot material with good photoelectric properties. A layer of two-dimensional Ti3C2MXene material is superimposed under this material, which can further improve the photoelectric performance of the device and significantly improve the light response; the bottom electrode uses a transparent FTO material to facilitate receiving light stimulation.

[0051] The preparation process of the optoelectronic synapse device includes:

[0052] The FTO glass was ultrasonically cleaned with deionized water, acetone, and ethanol for 15 minutes in sequence, blown dry after cleaning, and placed in a UV ozone environment for 15 minutes for surface activation;

[0053] The prepared Ti3C2MXene dispersion was spin-coated on the FTO glass surface in two steps, and the rotation speed and time of the two-step spin coating were 500rpm, 30s, 2000rpm, 60s respectively. After spin coating, the Ti3C2MXene film was annealed and dried at 80℃ for 15 minutes to obtain a Ti3C2MXene film.

[0054] The prepared CsPbBr3QDs solution was spin-coated on the surface of the Ti3C2MXene film, and the spin-coating speed and time were 1000 rpm and 40 s respectively. After spin-coating, the film was annealed and dried at 85°C for 20 minutes to obtain a CsPbBr3QDs film;

[0055] Using thermal evaporation method, 100nm of Ag was deposited on the CsPbBr3QDs film as the top electrode.

[0056] like Figure 4 As shown, the photocurrent curve of the photoelectric synapse device under light stimulation of different intensities. Figure 4 It can be seen that the device can stimulate photocurrents of different sizes under stimulation of different light intensities, and as the light intensity increases, the response current amplitude increases exponentially.

[0057] Figure 5 and Figure 6 They are the original handwritten digital image with noise and the electrical signal output by the image sensing module. The pixel information of both images has been normalized. Figure 5 and Figure 6 It can be seen that based on the characteristic that the response current of the optical synaptic device increases exponentially with the light intensity, the converted electrical signal will show a higher contrast than the optical signal of the original image, and the intensity of the noise signal will be significantly weakened.

[0058] like Figure 7 and Figure 8 As shown, in the image recognition module based on array memristor devices, the array memristor device is specifically based on a plurality of memristor devices. Each of the two memristor devices is connected in a current differential circuit (such as Figure 8 As shown in the figure, the two memristors are connected as a unit, and multiple units are arranged in an array to form the entire array structure. The specific connection method of the current differential circuit is: after the two memristors are connected in series, the two ends are connected to the positive word line (WL+) and the negative word line (WL-), respectively, and the middle node is connected to the bit line (BL). When the array is working normally, the voltage values ​​of the positive word line and the negative word line are set to be opposite ( ), the bit line voltage is 0, then the bit line current is , that is, the equivalent conductivity of the unit is: ; The use of current differential circuit can effectively improve the flexibility and accuracy of conductivity regulation, which is conducive to improving the accuracy of subsequent neural network calculations.

[0059] like Fig. 9 As shown, the memristor device includes, from top to bottom, a top electrode, a semiconductor middle layer, and a bottom electrode. In this embodiment, the top electrode is Ag; the middle layer is a MAPbI3-Ti3C2MXene double-layer structure, wherein MAPbI3 (Methylammonium Lead Iodide) is "methylamine lead iodide", a perovskite material with good photoelectric properties. Due to the characteristics of a large number of iodine ions migrating inside, it is one of the ideal materials for the middle layer of the memristor device. A layer of two-dimensional Ti3C2Mxene material is superimposed under this material, which can effectively improve the cyclic resistance switching performance of the memristor device, improve the stability of the resistance value memory, improve the device performance, and extend the device life; the bottom electrode is FTO material.

[0060] The preparation process of the memristor device includes:

[0061] The FTO glass was ultrasonically cleaned with deionized water, acetone, and ethanol for 15 minutes in sequence, blown dry after cleaning, and placed in a UV ozone environment for 15 minutes for surface activation;

[0062] The prepared Ti3C2MXene dispersion was spin-coated on the FTO glass surface in two steps, and the rotation speed and time of the two-step spin coating were 500rpm, 30s, 2000rpm, 60s respectively. After spin coating, the Ti3C2MXene film was annealed and dried at 80℃ for 15 minutes to obtain a Ti3C2MXene film.

[0063] The prepared MAPbI3 solution was spin-coated on the Ti3C2MXene film at a speed of 4000rpm for 20s. 300μL of chlorobenzene was added as an anti-solvent at 10s to obtain a high-quality film. The film was annealed at 75℃ and 105℃ for 10 minutes respectively to obtain the final MAPbI3 film.

[0064] Using thermal evaporation method, 100nm of Ag was deposited on the CsPbBr3QDs film as the top electrode.

[0065] Fig.10 The figure shows the conductivity change curve of the memristor device under multiple continuous pulse stimulations. Fig.10 It can be seen from the graph that the memristor device has electrical synaptic characteristics. The conductivity value will change under the stimulation of multiple continuous electric pulses. By changing the number of electric pulses, pulse width and interval, the switching control between multiple conductivity values ​​can be achieved. At the same time, the memristor device has certain memory characteristics, and can maintain the current conductivity value unchanged for a certain period of time when the external voltage is removed.

[0066] like Fig.11 As shown, the multi-layer convolutional neural network includes:

[0067] Input layer: receives a 28×28 feature matrix as the input of the entire multi-layer convolutional neural network;

[0068] First convolutional layer: A 5×5 matrix is ​​used as a convolution kernel. A total of 10 such convolution kernels are used to perform convolution operations on the feature matrix of the input layer, and 10 24×24 matrices are obtained as the output feature matrix of the first convolutional layer.

[0069] First pooling layer: Perform a 2×2 maximum pooling operation on the output feature matrix of the first convolutional layer to obtain 10 12×12 matrices as the output feature matrix of the first pooling layer;

[0070] Second convolutional layer: Use 10 5×5 matrices as a convolution kernel, and use a total of 20 such convolution kernels to perform convolution operations on the 10 feature matrices output by the first pooling layer, and obtain 20 8×8 matrices as the output feature matrices of the second convolutional layer;

[0071] Second pooling layer: Perform a 2×2 maximum pooling operation on the output feature matrix of the second convolutional layer to obtain 20 4×4 matrices as the output feature matrix of the second pooling layer;

[0072] Linear layer: extract each element of the 20 4×4 matrices output by the second pooling layer to obtain a total of 320 vectors;

[0073] Output layer: Contains 10 output neurons, each of which is fully connected to the 320 vectors of the linear layer, and outputs 10 numerical values ​​representing the probability of recognizing the image as a number from 0 to 9.

[0074] In the convolution layer of a multi-layer convolutional neural network, all matrix convolution operations involved are performed in array memristor devices. The convolution operation between the feature matrix and the convolution kernel in a multi-layer convolutional neural network is actually a process of calculating the sum of the products of all corresponding elements of two 5×5 matrices and repeating it many times. The specific steps of each calculation are as follows:

[0075] First, an electric pulse signal is used to control the equivalent conductance value of each unit in the array memristor device. g i,j , so that they correspond to each weight value of the matrix in the convolution kernel ω i,j , to achieve the mapping from the weights in the convolution kernel to the conductance values ​​of the array memristor devices:

[0076]

[0077] The values ​​of the input matrix are then mapped to different voltage values ​​to form an input voltage matrix V Input , and split it column by column:

[0078]

[0079]

[0080] The split input matrix is ​​input into the word line end (WL) of the array memristor device column by column. V In,1 ) is input, according to Ohm's law and Kirchhoff's law, the output current that can be obtained at the bit line end (BL) of the array memristor device is I BL1 for:

[0081]

[0082] Here we read the current value of the first bit line, namely:

[0083]

[0084] Similar to the above steps, the remaining four columns of the input matrix ( V In,2 , V In,3 , V In,4 , V In,5 ) input the word line terminal in sequence, and read the current values ​​of the 2nd, 3rd, 4th, and 5th bit lines respectively:

[0085]

[0086] By adding all the read current values, we can get an element value of the output matrix, that is, I Output :

[0087]

[0088] By repeating the above steps multiple times, the complete convolution operation can be completed and the output feature matrix can be obtained.

[0089] Fig.12 The recognition rate curve of fuzzy handwritten digit recognition using the sensing, storage and computing integrated intelligent visual system constructed by the present invention is shown in FIG. Fig.12 The recognition rate curve of pure software recognition using clear pictures is also given as an ideal control group, as well as the recognition rate curve of using blurred pictures but without image denoising by the image perception module. Fig.13 The data sets used for handwritten digit recognition in the present invention are all based on the MNIST data set, wherein the control group for directly recognizing clear images uses the original MNIST data set, and the data set used for fuzzy image recognition is a new data set generated by artificially adding noise points to the images in the MNIST data set.

[0090] from Fig.12 It can be seen that the integrated sensing, storage and computing intelligent visual system constructed by the present invention can effectively reduce the noise of blurred images, enhance image contrast, and improve image recognition rate; the hardware multi-layer neural network based on array memristor devices can also obtain recognition effects similar to those of pure software operations, realizing the "integrated sensing, storage and computing" image recognition function.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0092] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A sensor-storage-computing integrated visual system based on optoelectronic synaptic devices and memristor devices, characterized in that: include: Image sensing module based on photoelectric synapse devices: Matrix-arranged photoelectric synapse devices are used to convert the two-dimensional image information of the image to be measured into a two-dimensional electrical signal and perform preprocessing; And, an image recognition module based on array memristor devices: receiving the preprocessed two-dimensional electrical signal, using the memristor array structure, first standardizing the two-dimensional electrical signal to obtain an image feature matrix, then inputting the feature matrix into a multi-layer convolutional neural network, the multi-layer convolutional neural network performs multiple matrix operations on the input feature matrix, further extracts image feature information, and finally outputs an image recognition result; The preprocessing includes: enhancing image contrast and reducing noise; The photoelectric synapse device comprises, from top to bottom, a top electrode, a semiconductor middle layer and a bottom electrode; The top electrode is Ag; the semiconductor middle layer is a double-layer structure: Ti3C2MXene-CsPbBr3 QDs; the bottom electrode is a transparent FTO material; The image recognition module based on array memristor devices includes an array memristor device constructed by a plurality of memristor devices; wherein every two memristor devices are connected as a unit in a current differential circuit manner, and a plurality of units are arranged in an array to form the entire array structure; The memristor device comprises, from top to bottom, a top electrode, a middle layer and a bottom electrode; The top electrode is Ag; the middle layer is a double-layer structure: MAPbI3-Ti3C2, and the bottom electrode is FTO material.

2. The sensing, storage and computing integrated visual system based on optoelectronic synaptic devices and memristor devices according to claim 1 is characterized in that: The image sensing module based on photoelectric synapse devices includes: 784 photoelectric synapse devices distributed in a 28×28 array.

3. The sensing, storage and computing integrated visual system based on optoelectronic synaptic devices and memristor devices according to claim 1 is characterized in that: The preparation process of the Ti3C2MXene-CsPbBr3 QDs includes: stacking a layer of two-dimensional Ti3C2MXene material on a CsPbBr3 QDs layer.

4. The sensing, storage and computing integrated visual system based on optoelectronic synaptic devices and memristor devices according to claim 1 is characterized in that: The connection mode of the current differential circuit is: after two memristor devices are connected in series, the two ends are connected to a positive word line and a negative word line respectively, and the middle node is connected to a bit line; when the array memristor device is working normally, the voltage values ​​of the positive word line and the negative word line are set to be opposite, and the bit line voltage is 0.

5. The sensing, storage and computing integrated visual system based on optoelectronic synaptic devices and memristor devices according to claim 1 is characterized in that: The preparation process of the MAPbI3-Ti3C2 includes: superimposing a layer of two-dimensional Ti3C2MXene material under MAPbI3.

6. The sensing, storage and computing integrated visual system based on optoelectronic synaptic devices and memristor devices according to claim 1 is characterized in that: The multi-layer convolutional neural network comprises: Input layer: receives a 28×28 feature matrix as the input of the entire multi-layer convolutional neural network; First convolutional layer: A 5×5 matrix is ​​used as a convolution kernel. A total of 10 convolution kernels are used to perform convolution operations on the feature matrix of the input layer, and 10 24×24 matrices are obtained as the output feature matrix of the first convolutional layer. First pooling layer: Perform a 2×2 maximum pooling operation on the output feature matrix of the first convolutional layer to obtain 10 12×12 matrices as the output feature matrix of the first pooling layer; Second convolution layer: Use 10 5×5 matrices as a convolution kernel, and use a total of 20 convolution kernels to perform convolution operations on the 10 feature matrices output by the first pooling layer, and obtain 20 8×8 matrices as the output feature matrices of the second convolution layer; Second pooling layer: Perform a 2×2 maximum pooling operation on the output feature matrix of the second convolutional layer to obtain 20 4×4 matrices as the output feature matrix of the second pooling layer; Linear layer: extract each element of the 20 4×4 matrices output by the second pooling layer to obtain a total of 320 vectors; Output layer: Contains 10 output neurons, each of which is fully connected to the 320 vectors of the linear layer, and outputs 10 numerical values ​​representing the probability of recognizing the image as a number from 0 to 9.

Images