Driving circuit, control method thereof and display panel

Abstract

The invention provides a driving circuit, a control method of the driving circuit and a display panel comprising the driving circuit. The driving circuit comprises a plurality of GOA driving units; a plurality of switching devices, wherein each switching device in the plurality of switching devices is respectively connected with one GOA driving unit in the plurality of GOA driving units in series; the array substrate comprises a plurality of GOA driving units, a plurality of switching devices, and a control line used for controlling conduction of each of the plurality of switching devices, each GOA driving unit in the plurality of GOA driving units is connected to a plurality of rows of grid lines, and one of the plurality of switching devices is connected in series between the GOA driving unit and each row of grid lines connected with the GOA driving unit.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a driving circuit, a control method of the driving circuit, and a display panel including the driving circuit. Background Art

[0002] The gate on array (GOA) driving technology is a technology that directly manufactures the gate driving circuit on the array substrate. The application of this technology can directly manufacture the gate driving circuit around the panel, thereby reducing the manufacturing process and reducing the product cost.

[0003] In the related art, one GOA driving unit corresponds to one row of gate lines, so the number of GOA driving units required is the same as the number of gate lines. As the number of pixels of the display panel continues to increase, more GOA driving units are required, which is not conducive to the narrow frame design of the display panel. Summary of the invention

[0004] In view of the above problems, the present disclosure proposes a driving circuit, a control method of the driving circuit and a display panel including the driving circuit, which reduces the number of required GOA driving units, thereby enabling a narrow frame design.

[0005] One aspect of the present disclosure provides a driving circuit, comprising: a plurality of array gate (Gateon Array, GOA) driving units; a plurality of switching devices, each of the plurality of switching devices is respectively connected in series with one of the plurality of GOA driving units; and a control line for controlling the conduction of each of the plurality of switching devices, wherein each of the plurality of GOA driving units is respectively connected to a plurality of rows of gate lines, and one of the plurality of switching devices is connected in series between the GOA driving unit and each row of gate lines connected to the GOA driving unit.

[0006] According to an embodiment of the present disclosure, each of the multiple GOA driving units is respectively connected to two rows of gate lines, the GOA driving unit is connected to one of the two rows of gate lines via a first switching device, and the GOA driving unit is connected to the other row of gate lines of the two rows of gate lines via a second switching device.

[0007] According to an embodiment of the present disclosure, the first switching device and the second switching device are thin film transistors (TFT) of the same type, and the control line includes a first control line and a second control line, and the first control line and the second control line are respectively connected to the first switching device and the second switching device to respectively control the conduction of the first switching device and the second switching device.

[0008] According to an embodiment of the present disclosure, the first switching device and the second switching device are TFTs of opposite types, and the control line includes a first control line connected to the first switching device and the second switching device to control conduction of the first switching device and the second switching device.

[0009] According to an embodiment of the present disclosure, each of the multiple GOA driving units is respectively connected to four rows of gate lines, and the GOA driving unit is respectively connected to each of the four rows of gate lines via a first switching device, a second switching device, a third switching device and a fourth switching device.

[0010] Another aspect of the present disclosure further provides a control method for a driving circuit, which is applied to the driving circuit according to the present disclosure, and the method includes: controlling multiple switching devices connected to a GOA driving unit so that the multiple switching devices are turned on successively in different time periods.

[0011] According to an embodiment of the present disclosure, each of the multiple GOA driving units is respectively connected to two rows of gate lines, the GOA driving unit is connected to one row of the two rows of gate lines via a first switching device, and the GOA driving unit is connected to the other row of the two rows of gate lines via a second switching device, and controlling the multiple switching devices connected to one GOA driving unit so that the multiple switching devices are turned on successively at different time periods includes: controlling the first switching device and the second switching device so that the first switching device and the second switching device are turned on successively at different time periods.

[0012] According to an embodiment of the present disclosure, the first switching device and the second switching device are TFTs of the same type, and the control line includes a first control line and a second control line, the first control line and the second control line are respectively connected to the first switching device and the second switching device, and controlling the first switching device and the second switching device so that the first switching device and the second switching device are successively turned on at different time periods includes: controlling the conduction of the first switching device and the second switching device by the first control line and the second control line, respectively, so that the first switching device and the second switching device are successively turned on at different time periods.

[0013] According to an embodiment of the present disclosure, the first switching device and the second switching device are TFTs of opposite types, and the control line includes a first control line, the first control line is connected to the first switching device and the second switching device, and controlling the first switching device and the second switching device so that the first switching device and the second switching device are successively turned on at different time periods includes: controlling the conduction of the first switching device and the second switching device by the first control line so that the first switching device and the second switching device are successively turned on at different time periods.

[0014] According to an embodiment of the present disclosure, each of the multiple GOA driving units is respectively connected to four rows of gate lines, and the GOA driving unit is respectively connected to each of the four rows of gate lines via a first switching device, a second switching device, a third switching device and a fourth switching device, and controlling the multiple switching devices connected to one GOA driving unit so that the multiple switching devices are successively turned on at different time periods includes: controlling the first switching device, the second switching device, the third switching device and the fourth switching device so that the first switching device, the second switching device, the third switching device and the fourth switching device are successively turned on at different time periods.

[0015] Another aspect of the present disclosure further provides a display panel including the driving circuit according to the present disclosure.

[0016] According to the driving circuit, the control method of the driving circuit and the display panel of each embodiment of the present disclosure, the number of required GOA driving units is significantly reduced while maintaining the conduction time of each row of gate lines, so that a narrow frame design can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed example embodiments with reference to the accompanying drawings. The embodiments as described in the present disclosure are shown in the figures of the accompanying drawings by way of example and not limitation. In the accompanying drawings, similar reference numerals indicate similar elements, and for the purpose of illustration, the drawings are not drawn to scale.

[0018] Figure 1 The driving scheme of GOA in the related art is schematically shown;

[0019] Figure 2 is a schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure;

[0020] Figure 3 Schematically shows Figure 2 The timing diagram of the driving circuit shown;

[0021] Figure 4 is another schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure;

[0022] Figure 5 Schematically shows Figure 4 The timing diagram of the driving circuit shown;

[0023] Figure 6 is a schematic diagram for explaining resolution adjustment of a driving circuit according to an embodiment of the present disclosure; and

[0024] Figure 7 is another schematic circuit diagram and timing diagram of a driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the construction or process steps described in the following description. The present disclosure can have other embodiments, and in the absence of conflict, the various embodiments of the present disclosure and the various features in the embodiments can be combined with each other.

[0026] As used herein, the term "and / or" includes any and all combinations of at least one of the associated listed items.

[0027] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used in the disclosure, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in the present disclosure, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of at least one other feature, whole, step, operation, element, component and / or its group is not excluded.

[0028] Figure 1 The driving scheme of the GOA in the related art is schematically shown.

[0029] like Figure 1 As shown, in the related art, one GOA driving unit corresponds to one row of gate lines, so the number of GOA driving units required is the same as the number of gate lines. As the number of pixels of the display panel continues to increase, more GOA driving units are required, which is not conducive to narrow frame design.

[0030] The embodiments of the present disclosure provide a driving circuit that can reduce the number of required GOA driving units, thereby enabling a narrow frame design.

[0031] According to the driving circuit of the embodiment of the present disclosure, one GOA driving unit corresponds to multiple rows of gate lines, and a switching device is connected in series between the GOA driving unit and each row of gate lines corresponding to the GOA driving unit.

[0032] Figure 2 is a schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure.

[0033] See also Figure 2 One GOA driving unit corresponds to two rows of gate lines, and a thin film transistor (TFT) used as a switching device is connected in series between the GOA driving unit and each row of gate lines corresponding to the GOA driving unit. Two control lines are connected to the two TFTs, respectively, to apply control signals S1 and S2 to the gates of the two TFTs, respectively. Figure 2 As shown, the GOA driving unit G12 is connected to the gate lines G1 and G2 respectively via two TFTs T1 and T2, the GOA driving unit G34 is connected to the gate lines G3 and G4 respectively via two TFTs T3 and T4, the control signal S1 is applied to the gates of TFTs T1 and T3, and the control signal S2 is applied to the gates of TFTs T2 and T4.

[0034] Figure 3 Schematically shows Figure 2 The timing diagram of the driving circuit is shown.

[0035] See also Figure 3The width of the output signal of a GOA driving unit connected to two rows of gate lines can cover the conduction time of the two rows of gate lines connected to the GOA driving unit, and the waveforms of the control signals S1 and S2 make the two rows of gate lines connected to one GOA driving unit turn on successively. For example, TFTTT1 to T4 are N-type TFTs. When the control signal S1 is at a high level, TFTT1 is turned on, so that the high-level signal applied to TFT T1 by the GOA driving unit G12 is applied to the gate line G1 via TFT T1. When the control signal S2 is at a high level, TFT T2 is turned on, so that the high-level signal applied to TFT T2 by the GOA driving unit G12 is applied to the gate line G2 via TFT T2, so that the high-level signal applied to the gate lines G1 and G2 corresponds to the turn-on time required for the gate lines G1 and G2 of each row; in addition, when the control signal S1 is at a high level, TFT T3 is turned on, so that the high-level signal applied to TFT T3 by the GOA driving unit G34 is applied to the gate line G3 via TFT T3. When the control signal S2 is at a high level, TFT T4 is turned on, so that the high-level signal applied to TFT T4 by the GOA driving unit G34 is applied to the gate line G3 via TFT T4 is applied to the gate line G4, so that the high level signal applied to the gate lines G3 and G4 corresponds to the turn-on time required for the gate lines G3 and G4 in each row.

[0036] It should be recognized that although Figure 2 TFTs T1 to T4 are shown as N-type TFTs, but the embodiments of the present disclosure are not limited thereto. The TFTs used may be P-type TFTs, and the high level / low level of the control signal only needs to be configured accordingly. Alternatively, the switch device may be implemented as other forms of controllable switch devices, which are not specifically limited by the present disclosure.

[0037] According to the driving circuit of the embodiment of the present disclosure, the number of required GOA driving units is significantly reduced while maintaining the on-time of each row of gate lines. Although the number of TFTs used as switching devices is increased, the overall occupied area can be reduced by about 40%.

[0038] Figure 4 is another schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure.

[0039] See also Figure 4 , one GOA driving unit corresponds to two rows of gate lines, and TFTs of opposite types are connected in series between the GOA driving unit and each row of gate lines corresponding to the GOA driving unit. One control line is connected to two TFTs of opposite types to apply a control signal S1 to the gates of the two TFTs. Figure 4As shown, the GOA driving unit G12 is connected to the gate lines G1 and G2 respectively via two TFTs T1 and T2 of opposite types, the GOA driving unit G34 is connected to the gate lines G3 and G4 respectively via two TFTs T3 and T4 of opposite types, and the control signal S1 is applied to the gates of TFTs T1 to T4.

[0040] Figure 5 Schematically shows Figure 4 The timing diagram of the driving circuit is shown.

[0041] See also Figure 5 The width of the output signal of a GOA driving unit connected to two rows of gate lines can cover the conduction time of the two rows of gate lines connected to the GOA driving unit, and the waveform of the control signal S1 makes the two rows of gate lines connected to one GOA driving unit turn on successively. For example, TFT T1 and T3 are N-type TFTs, TFT T2 and T4 are P-type TFTs, when the control signal S1 is at a high level, TFT T1 is turned on, so that the high-level signal applied to TFT T1 by the GOA driving unit G12 is applied to the gate line G1 via TFT T1, and when the control signal S1 is at a low level, TFT T2 is turned on, so that the high-level signal applied to TFT T2 by the GOA driving unit G12 is applied to the gate line G2 via TFT T2, so that the high-level signal applied to the gate lines G1 and G2 corresponds to the turn-on time required for the gate lines G1 and G2 of each row; in addition, when the control signal S1 is at a high level, TFT T3 is turned on, so that the high-level signal applied to TFT T3 by the GOA driving unit G34 is applied to the gate line G3 via TFT T3, and when the control signal S1 is at a low level, TFT T4 is turned on, so that the high-level signal applied to TFT T4 by the GOA driving unit G34 is applied to the gate line G3 via TFT T3. T4 is applied to the gate line G4, so that the high level signal applied to the gate lines G3 and G4 corresponds to the turn-on time required for the gate lines G3 and G4 in each row.

[0042] According to an embodiment of the present disclosure, since the GOA driving unit is connected to multiple rows of gate lines, the switching devices connected to each GOA driving unit can be turned on at the same time by changing the waveform of the control signal (for example, the control signal S1 and / or S2), so that the signal output by the GOA driving unit is simultaneously applied to each row of gate lines connected to the GOA driving unit.

[0043] Figure 6 It is a schematic diagram for explaining resolution adjustment of a driving circuit according to an embodiment of the present disclosure.

[0044] like Figure 6As shown, the display panel can be divided into a low-resolution area and a normal-resolution area. By appropriately changing the waveforms of the control signals S1 and S2, so that the control signal always maintains a high level (or a low level) in the portion corresponding to the low-resolution area, the signal output by each GOA driving unit can be simultaneously applied to each row of gate lines connected to the GOA driving unit.

[0045] For example, Figure 6 As shown, the control signal always maintains a high level in the portion corresponding to the low-resolution regions R1 and R3, and is controlled in the manner described in the above embodiment in the portion corresponding to the normal-resolution region R2. Figure 6 , the control signal is shown to always maintain a high level in the portion corresponding to the low-resolution area, but the present disclosure is not limited thereto. For example, when a P-type TFT is used as a switching device connected to the GOA driving unit, the control signal is always maintained at a low level in the portion corresponding to the low-resolution area, so that the signal output by each GOA driving unit is simultaneously applied to each row of gate lines connected to the GOA driving unit.

[0046] For example, see Figure 2 , Figure 3 and Figure 6 When the control signal S1 is at a high level, TFT T1 is turned on, so that the high level signal applied to TFT T1 by the GOA driving unit G12 is applied to the gate line G1 via TFT T1. At the same time, the control signal S2 is at a high level, and TFT T2 is turned on, so that the high level signal applied to TFT T2 by the GOA driving unit G12 is applied to the gate line G2 via TFT T2, so that the signals applied to the gate lines G1 and G2 are consistent with the output signal of the GOA driving unit G12 (that is, Figure 3 In addition, when the control signal S1 is at a high level, TFT T3 is turned on, so that the high-level signal applied to TFT T3 by the GOA driving unit G34 is applied to the gate line G3 via TFT T3, and at the same time, the control signal S2 is at a high level, and TFT T4 is turned on, so that the high-level signal applied to TFT T4 by the GOA driving unit G34 is applied to the gate line G4 via TFT T4, so that the signal applied to the gate lines G3 and G4 is the same as the output signal of the GOA driving unit G34 (that is, Figure 3The control method is the same as that of the signal at point B shown in the figure. Based on this control method, two rows (or more rows) of pixel units connected to the gate lines G1 and G2 simultaneously obtain data signals provided via data lines (not shown in the figure), so the two rows (or more rows) of pixel units connected to the gate lines G1 and G2 simultaneously display the same content. Based on the same principle, two rows (or more rows) of pixel units connected to the gate lines G3 and G4 simultaneously obtain data signals provided via data lines, so the two rows (or more rows) of pixel units connected to the gate lines G3 and G4 simultaneously display the same content, and so on. That is to say, in the low-resolution area of ​​the display panel, more than one row of pixel units simultaneously display the same content, so the resolution (i.e., vertical resolution) of this area is reduced.

[0047] It should be recognized that although Figure 6 The figure shows that the upper and lower regions R1 and R3 of the display panel are divided into low-resolution regions, but the present disclosure is not limited thereto. The low-resolution regions can be divided arbitrarily as needed, and the present disclosure does not limit the division method of the low-resolution regions.

[0048] Figure 7 is another schematic circuit diagram and timing diagram of a driving circuit according to an embodiment of the present disclosure.

[0049] See also Figure 7 ,exist Figure 7 The left side shows another schematic circuit diagram of a driving circuit according to an embodiment of the present disclosure. According to this embodiment, one GOA driving unit corresponds to four rows of gate lines, and a TFT used as a switching device is connected in series between the GOA driving unit and each row of gate lines corresponding to the GOA driving unit. Four control lines are respectively connected to the four TFTs to apply control signals S1 to S4 to the gates of the four TFTs respectively. Figure 7 As shown on the left, GOA driving units G1-4 are connected to gate lines G1 to G4 via a group of four TFTs, respectively, and GOA driving units G5-8 are connected to gate lines G5 to G8 via another group of four TFTs, respectively, and control signals S1 to S4 are applied to the gates of each group of four TFTs.

[0050] Figure 7 The right side schematically shows Figure 7Timing diagram of the driving circuit shown on the left. According to this embodiment, the width of the output signal of a GOA driving unit connected to four rows of gate lines can cover the conduction time of the four rows of gate lines connected to the GOA driving unit, and the waveforms of the control signals S1 to S4 make the four rows of gate lines connected to one GOA driving unit conduct successively. For example, a group of four TFTs connected to the GOA driving units G1~4 are N-type TFTs. When the control signal S1 is at a high level, the first TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G1~4 is applied to the gate line G1. When the control signal S2 is at a high level, the second TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G1~4 is applied to the gate line G2. When the control signal S3 is at a high level, the third TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G1~4 is applied to the gate line G3. When the control signal S4 is at a high level, the fourth TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G1~4 is applied to the gate line G4, so that the high-level signal applied to the gate lines G1 to G4 corresponds to the turn-on time required for each row of gate lines G1 to G4. A group of four TFTs connected to the GOA driving units G5~8 are N-type TFTs. When the control signal S1 is at a high level, the first TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G5~8 is applied to the gate line G5. When the control signal S2 is at a high level, the second TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G5~8 is applied to the gate line G6. When the control signal S3 is at a high level, the third TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G5~8 is applied to the gate line G7. When the control signal S4 is at a high level, the fourth TFT in a group of four TFTs is turned on, so that the output signal of the GOA driving units G5~8 is applied to the gate line G8, so that the high-level signal applied to the gate lines G5 to G8 corresponds to the turn-on time required for each row of gate lines G5 to G8.

[0051] It should be recognized that although Figure 7 In the figure, each TFT is shown as an N-type TFT, but the embodiments of the present disclosure are not limited thereto, and the adopted TFT may be a P-type TFT, and it is only necessary to configure the high level / low level of the control signal accordingly.

[0052] It should be appreciated that, although in the above embodiments of the present disclosure, the number of switching devices connected to one GOA driving unit is described as two or four, that is, one GOA driving unit corresponds to two or four rows of gate lines, the present disclosure is not limited thereto. As required, one GOA driving unit can be set to correspond to three or more rows of gate lines, which is not limited in the present disclosure.

[0053] According to the driving circuit of the embodiment of the present disclosure, the number of required GOA driving units is significantly reduced while maintaining the on-time of each row of gate lines, so that a narrow frame design can be achieved.

[0054] In the present disclosure, the terms first, second, third, etc. may be used to describe various elements, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0055] In the present disclosure, reference to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" throughout the present disclosure does not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0056] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrations of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A driving circuit, comprising: Multiple GOA drive units; A plurality of switch devices, each of the plurality of switch devices is respectively connected in series with one of the plurality of GOA drive units; as well as a control line for controlling conduction of each of the plurality of switching devices, Each of the plurality of GOA driving units is respectively connected to a plurality of rows of gate lines, and one of the plurality of switching devices is connected in series between the GOA driving unit and each row of gate lines connected to the GOA driving unit.

2. The driving circuit according to claim 1, wherein: Each of the plurality of GOA driving units is connected to two rows of gate lines respectively. The GOA driving unit is connected to one of the two rows of gate lines via a first switching device, and The GOA driving unit is connected to the other row of the two rows of gate lines via a second switching device.

3. The driving circuit according to claim 2, wherein: The first switching device and the second switching device are TFTs of the same type, and The control line includes a first control line and a second control line, and the first control line and the second control line are respectively connected to the first switching device and the second switching device to control conduction of the first switching device and the second switching device, respectively.

4. The driving circuit according to claim 2, wherein: The first switching device and the second switching device are TFTs of opposite types, and The control line includes a first control line connected to the first switching device and the second switching device to control conduction of the first switching device and the second switching device.

5. The driving circuit according to claim 1, wherein: Each of the plurality of GOA driving units is respectively connected to four rows of gate lines, and the GOA driving unit is respectively connected to each of the four rows of gate lines via a first switching device, a second switching device, a third switching device, and a fourth switching device.

6. A control method for a drive circuit, wherein the drive circuit is the drive circuit according to claim 1, the method comprising: A plurality of switch devices connected to a GOA driving unit are controlled so that the plurality of switch devices are turned on successively in different time periods.

7. The control method according to claim 6, wherein: Each of the plurality of GOA driving units is connected to two rows of gate lines respectively, the GOA driving unit is connected to one of the two rows of gate lines via a first switching device, and the GOA driving unit is connected to the other of the two rows of gate lines via a second switching device, Controlling a plurality of switch devices connected to a GOA driving unit so that the plurality of switch devices are turned on successively in different time periods comprises: The first switching device and the second switching device are controlled so that the first switching device and the second switching device are turned on successively in different time periods.

8. The control method according to claim 7, wherein: The first switching device and the second switching device are TFTs of the same type, and the control line includes a first control line and a second control line, the first control line and the second control line are connected to the first switching device and the second switching device, respectively, Controlling the first switching device and the second switching device so that the first switching device and the second switching device are turned on successively in different time periods includes: The first control line and the second control line are used to control the conduction of the first switch device and the second switch device, respectively, so that the first switch device and the second switch device are turned on successively in different time periods.

9. The control method according to claim 7, wherein: The first switching device and the second switching device are TFTs of opposite types, and the control line includes a first control line connected to the first switching device and the second switching device, Controlling the first switching device and the second switching device so that the first switching device and the second switching device are turned on successively in different time periods includes: The first control line controls the conduction of the first switching device and the second switching device, so that the first switching device and the second switching device are successively turned on in different time periods.

10. The control method according to claim 6, wherein: Each of the plurality of GOA driving units is respectively connected to four rows of gate lines, and the GOA driving unit is respectively connected to each of the four rows of gate lines via a first switching device, a second switching device, a third switching device, and a fourth switching device, Controlling a plurality of switch devices connected to a GOA driving unit so that the plurality of switch devices are turned on successively in different time periods comprises: The first switching device, the second switching device, the third switching device and the fourth switching device are controlled so that the first switching device, the second switching device, the third switching device and the fourth switching device are turned on successively in different time periods.

11. A display panel comprising the driving circuit according to any one of claims 1 to 5.

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