A display driving chip, a display driving method, a display device and an electronic equipment

Abstract

This application relates to a display driver chip, a display driving method, a display device, and an electronic device, and pertains to the field of image processing technology. The chip includes: a power supply terminal and multiple output terminals; the power supply terminal receives a power supply voltage; the multiple output terminals include a first output terminal and a second output terminal; the first output terminal outputs a first display driving voltage during a first time period and a second display driving voltage during a second time period, the first display driving voltage being equal to the power supply voltage; the second output terminal maintains the output of a third display driving voltage during the first time period, a first switching time period, and the second time period, the first switching time period being located between the first and second time periods; wherein the second display driving voltage is within a preset voltage range, and the maximum value of the preset voltage range is less than the third display driving voltage. This reduces the power consumption of the display driver chip.

Description

Technical Field

[0001] This application relates to the field of image processing technology, and in particular to a display driver chip, a display driver method, a display device, and an electronic device. Background Technology

[0002] A display screen includes pixel circuits, which are typically driven by a display driver IC (DDIC). Approximately one-quarter of the total power consumption is at the display driver chip level. As users spend increasingly more time using the device, reducing the power consumption of the display driver chip is becoming increasingly important. Organic light-emitting diode (OLED) displays contain a red-green-blue-green (RGBG) pixel circuit. The display driver chip consumes significant power during the process of driving the RGBG pixel circuits. Summary of the Invention

[0003] This application provides a display driver chip, a display driving method, a display device, and an electronic device, which solves the problem of high power consumption of the display driver chip in the prior art during the process of driving the RGBG pixel circuit display.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a display driver chip is provided, comprising a power supply terminal and multiple output terminals. The power supply terminal is used to receive a power supply voltage. The multiple output terminals include a first output terminal and a second output terminal. The first output terminal is used to output a first display driving voltage during a first time period and a second display driving voltage during a second time period, wherein the first display driving voltage is equal to the power supply voltage. The second output terminal is used to continuously output a third display driving voltage during the first time period, a first switching time period, and the second time period, wherein the first switching time period is located between the first time period and the second time period. The second display driving voltage is located within a preset voltage range, and the maximum value of the preset voltage range is less than the third display driving voltage.

[0006] In the above technical solution, the display driver chip can obtain multiple voltages based on the power supply voltage at the power supply terminal. These multiple voltages include voltages within a preset voltage range. The second display driving voltage is typically one of these multiple voltages within the preset voltage range. If both the first and second display driving voltages are obtained from the power supply voltage, interference will occur during the switch from the first to the second display driving voltage. This technical solution uses a voltage equal to the power supply voltage as the first display driving voltage. That is, the first display driving voltage may not be obtained from the power supply voltage, but can be the power supply voltage itself. When the first output terminal outputs a dynamic voltage, the interference on the values ​​of the multiple voltages obtained from the power supply voltage is mitigated. The third display driving voltage output by the second output terminal can be either obtained from the power supply voltage or the power supply voltage itself, and the third display driving voltage output by the second output terminal will not be affected by interference. Compared to the case where additional current is needed to stabilize the second output terminal voltage due to interference, this technical solution eliminates the need for additional stabilization of the second output terminal voltage, thus reducing power consumption. Furthermore, compared to situations where the second output voltage needs to recover (re-establish) due to interference, this technical solution eliminates the need to wait for the second output voltage to recover, thereby improving the driving capability of the display driver chip and accelerating the voltage output process. Additionally, this technical solution reduces power consumption not through additional power consumption or circuit area, but by reducing power consumption through the output power supply voltage, thus saving circuit area and minimizing power consumption.

[0007] In one possible implementation of the first aspect, the multiple output terminals further include a third output terminal. This third output terminal is used to output a fourth display driving voltage in a first time period and a first display driving voltage in a second time period. The fourth display driving voltage is located within a preset voltage range. The fourth display driving voltage output by the third output terminal in the first time period differs in magnitude from the second display driving voltage output by the first output terminal in the second time period. In the above possible implementations, if both the first and fourth display driving voltages are obtained from the power supply voltage, interference will occur between the multiple voltage values ​​obtained from the power supply voltage during the switching process from the first to the fourth display driving voltage. In this technical solution, the first display driving voltage may not be obtained from the power supply voltage, but may be the power supply voltage itself. When the first output terminal outputs a dynamic voltage, the interference from the multiple voltage values ​​obtained from the power supply voltage is mitigated. The third display driving voltage output by the second output terminal will not be affected by interference. For multiple output terminals, power consumption can be reduced and the voltage output process can be accelerated.

[0008] In one possible implementation of the first aspect, the first output terminal is specifically used to output a first display driving voltage in a first time period, a second display driving voltage in a second time period, a first display driving voltage in a third time period, and a second display driving voltage in a fourth time period. The second output terminal is specifically used to maintain the output of a third display driving voltage throughout the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, and the fourth time period, where the second switching time period is located between the second and third time periods, and the third switching time period is located between the third and fourth time periods. In the above possible implementations, when driving the color display of multiple sub-pixels in the third and fourth time periods, the first display driving voltage may not be a voltage obtained from the power supply voltage, but may be the power supply voltage itself. When the first output terminal outputs dynamic voltages, interference to the values ​​of multiple voltages obtained from the power supply voltage is mitigated. For the case of driving multiple sub-pixels, power consumption can be reduced and the voltage output process can be accelerated.

[0009] In one possible implementation of the first aspect, the first output terminal is specifically used to output a first display driving voltage in a first time period, a second display driving voltage in a second time period, a third time period, a fourth time period, an nth time period, and a (n+1)th time period, where n is an odd number greater than or equal to 5. The second output terminal is specifically used to maintain the output of a third display driving voltage during the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period, and the (n+1)th time period, where the fourth switching time period is located between the fourth time period and the nth time period, and the nth switching time period is located between the nth time period and the (n+1)th time period. In the above possible implementations, when driving the color display of multiple sub-pixels in multiple time periods, the first display driving voltage may not be a voltage obtained from the power supply voltage, but may be the power supply voltage itself. When the first output terminal outputs dynamic voltages, interference to the values ​​of multiple voltages obtained from the power supply voltage is mitigated. For driving multiple sub-pixels, power consumption can be reduced and the voltage output process can be accelerated.

[0010] In one possible implementation of the first aspect, the chip further includes a first display channel circuit, a first display switch, and a first power switch. The output terminal of the first display channel circuit is coupled to a first terminal of the first display switch, and the second terminal of the first display switch is coupled to the first output terminal. The power supply terminal is coupled to the first terminal of the first power switch, and the second terminal of the first power switch is coupled to the first output terminal. In the above possible implementation, the first display channel circuit is coupled to the first output terminal via the first display switch, and the power supply terminal is coupled to the first output terminal via the first power switch. The first output terminal can output the voltage provided by the first display channel circuit, or it can output the power supply voltage received by the power supply terminal. When the first output terminal needs to output a voltage to drive the sub-pixels to emit light, the first display switch can be turned on and the first power switch turned off, causing the first display channel circuit to output voltage to the first output terminal. When the first output terminal needs to output a voltage to drive the sub-pixels not to emit light, the first display switch can be turned off and the first power switch turned on, causing the power supply terminal to output power supply voltage to the first output terminal. It can be seen that when the first output terminal outputs a dynamic voltage, the voltage is switched by turning the first display switch and the first power switch on and off, rather than by switching the voltage internally within the first display channel circuit. In this way, the interference on the voltage output of the display channel circuit adjacent to the first display channel circuit is alleviated.

[0011] In one possible implementation of the first aspect, the chip further includes multiple display channel circuits, multiple display switches, and multiple power switches. The output terminal of the m-th display channel circuit is coupled to the first terminal of the m-th display switch, and the second terminal of the m-th display switch is coupled to the m-th output terminal. The power supply terminal is coupled to the first terminal of the m-th power switch, and the second terminal of the m-th power switch is coupled to the m-th output terminal. The m-th display channel circuit can be any one of the multiple display channel circuits, the m-th display switch can be any one of the multiple display switches, the m-th power switch can be any one of the multiple power switches, and the m-th output terminal can be any one of the multiple output terminals. In the above possible implementation, the m-th display channel circuit is coupled to the m-th output terminal via the m-th display switch, and the power supply terminal is coupled to the m-th output terminal via the m-th power switch. The m-th output terminal can output the voltage provided by the m-th display channel circuit, or output the power supply voltage received by the power supply terminal. When the m-th output terminal needs to output a voltage for driving sub-pixels to emit light, the m-th display channel circuit can output voltage to the m-th output terminal by turning on the m-th display switch and turning off the m-th power switch. When the m-th output terminal needs to output a voltage to drive the sub-pixels to not emit light, the power supply terminal can output a power voltage to the output terminal by turning off the m-th display switch and turning on the m-th power switch. It can be seen that when the m-th output terminal outputs a dynamic voltage, the voltage is switched by turning the m-th display switch and the m-th power switch on and off, rather than by switching the voltage internally within the m-th display channel circuit. In this way, interference to the voltage output of the display channel circuit adjacent to the m-th display channel circuit is mitigated.

[0012] In one possible implementation of the first aspect, the chip further includes multiple drive enhancement circuits, with the k-th drive enhancement circuit coupled to the control terminal of the k-th display switch. The k-th drive enhancement circuit can be any one of the multiple drive enhancement circuits, and the k-th display switch can be any one of the multiple display switches. In the above possible implementation, the ideal waveform for the control waveform that controls the display switch to turn on or off is a square wave; however, in practice, this control waveform may be unstable. The drive enhancement circuit can stabilize the control waveform of the display switch it is coupled to. By setting one drive enhancement circuit for each display switch, high-speed switching of multiple display switches can be achieved.

[0013] In one possible implementation of the first aspect, the third display driving voltage is equal to the power supply voltage. In the aforementioned possible implementations, the third display driving voltage can be provided by the power supply, which can further reduce the power consumption of the display channel circuit.

[0014] In one possible implementation of the first aspect, the power supply terminal is used to connect to a power source. In the aforementioned possible implementation, the power supply terminal is connected to a power source, and the power supply voltage can be used as the voltage to drive the sub-pixels to not emit light. The power supply voltage has a robust power network and low path impedance, which can reduce the additional power consumption caused by the dynamic voltage output of the display channel circuitry.

[0015] Secondly, a display driver chip is provided, comprising a power supply terminal, a first output terminal, a first display channel circuit, a first display switch, and a first power switch. The power supply terminal receives a power supply voltage. The output terminal of the first display channel circuit is coupled to a first terminal of the first display switch, and a second terminal of the first display switch is coupled to the first output terminal. The power supply terminal is coupled to a first terminal of the first power switch, and a second terminal of the first power switch is coupled to the first output terminal. In the above possible implementations, the first display channel circuit is coupled to the first output terminal via the first display switch, and the power supply terminal is coupled to the first output terminal via the first power switch. The first output terminal can output the voltage provided by the first display channel circuit, or it can output the power supply voltage received by the power supply terminal. When the first output terminal needs to output a voltage for driving sub-pixels to emit light, the first display switch can be turned on and the first power switch turned off, causing the first display channel circuit to output voltage to the first output terminal. When the first output terminal needs to output a voltage for driving sub-pixels not to emit light, the first display switch can be turned off and the first power switch turned on, causing the power supply terminal to output power supply voltage to the first output terminal. As can be seen, when the first output terminal outputs a dynamic voltage, the voltage is switched by turning the first display switch and the first power switch on and off, rather than by switching the voltage internally within the first display channel circuit. Compared to situations where additional current is needed to stabilize the voltage due to interference, this technical solution does not require additional stabilization voltage, thus reducing power consumption. Furthermore, compared to situations where voltage recovery (re-establishment) is required due to interference, this technical solution does not require waiting for voltage recovery, which can improve the driving capability of the display driver chip and accelerate the voltage output process. Additionally, this technical solution does not require additional power consumption or circuit area to reduce power consumption; instead, it can reduce power consumption by outputting the power supply voltage, saving circuit area and minimizing power consumption.

[0016] In one possible implementation of the second aspect, the chip further includes multiple output terminals, multiple display channel circuits, multiple display switches, and multiple power switches. The output terminal of the m-th display channel circuit is coupled to the first terminal of the m-th display switch, and the second terminal of the m-th display switch is coupled to the m-th output terminal. The power supply terminal is coupled to the first terminal of the m-th power switch, and the second terminal of the m-th power switch is coupled to the m-th output terminal. The m-th display channel circuit can be any one of the multiple display channel circuits, the m-th display switch can be any one of the multiple display switches, the m-th power switch can be any one of the multiple power switches, and the m-th output terminal can be any one of the multiple output terminals. In the above possible implementation, the m-th display channel circuit is coupled to the m-th output terminal via the m-th display switch, and the power supply terminal is coupled to the output terminal via the m-th power switch. The m-th output terminal can output the voltage provided by the m-th display channel circuit, or output the power supply voltage received by the power supply terminal. When the m-th output terminal needs to output a voltage to drive the sub-pixel to emit light, the m-th display switch can be turned on and the m-th power switch can be turned off, causing the m-th display channel circuit to output voltage to the m-th output terminal. When the m-th output terminal needs to output a voltage to drive the sub-pixel to not emit light, the m-th display switch can be turned off and the m-th power switch can be turned on, causing the power supply terminal to output power voltage to the first output terminal. The power supply voltage at the power supply terminal can replace the voltage provided by the m-th display channel circuit. It can be seen that when the m-th output terminal outputs a dynamic voltage, the voltage is switched by turning the m-th display switch and the m-th power switch on and off, rather than by switching the voltage internally within the m-th display channel circuit. In this way, the interference on the voltage output by the display channel circuit adjacent to the m-th display channel circuit is mitigated.

[0017] In one possible implementation of the second aspect, the chip further includes multiple drive enhancement circuits. The k-th drive enhancement circuit is coupled to the control terminal of the k-th display switch. The k-th drive enhancement circuit can be any one of the multiple drive enhancement circuits, and the k-th display switch can be any one of the multiple display switches. In the above possible implementations, the ideal waveform for the control waveform that turns the display switch on or off is a square wave; however, in practice, this control waveform may be unstable. The drive enhancement circuit can stabilize the control waveform of its coupled display switch. By setting one drive enhancement circuit for each display switch, high-speed switching of multiple display switches can be achieved.

[0018] In one possible implementation of the second aspect, the power supply terminal is used to connect to a power source. In the aforementioned possible implementations, the power supply terminal is connected to a power source, and the power supply voltage can be used as the voltage to drive the sub-pixels to not emit light. The power supply voltage has a robust power network and low path impedance, which can reduce the additional power consumption caused by the dynamic voltage output of the display channel circuitry.

[0019] Thirdly, a display driving method is provided, which is applied to a display driving chip, the display driving chip including a power supply terminal and multiple output terminals. The power supply terminal is used to receive a power supply voltage. The multiple output terminals include a first output terminal and a second output terminal. The method includes: outputting a first display driving voltage through the first output terminal in a first time period, and outputting a second display driving voltage in a second time period, the first display driving voltage being equal to the power supply voltage; and maintaining the output of a third display driving voltage through the second output terminal in the first time period, a first switching time period, and the second time period, the first switching time period being located between the first time period and the second time period. The second display driving voltage is located within a preset voltage range, and the maximum value of the preset voltage range is less than the third display driving voltage.

[0020] In one possible implementation of the third aspect, the method further includes: outputting a fourth display driving voltage through a third output terminal in a first time period, and outputting a first display driving voltage in a second time period, wherein the fourth display driving voltage is within a preset voltage range. The magnitude of the fourth display driving voltage output by the third output terminal in the first time period is different from the magnitude of the second display driving voltage output by the first output terminal in the second time period.

[0021] In one possible implementation of the third aspect, outputting a first display driving voltage through a first output terminal in a first time period and a second display driving voltage through a second time period includes: outputting the first display driving voltage through the first output terminal in the first time period, outputting the second display driving voltage through the second time period, outputting the first display driving voltage through the first output terminal in a third time period, and outputting the second display driving voltage through a fourth time period. Maintaining the output of a third display driving voltage through a second output terminal in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, and the fourth time period includes: maintaining the output of a third display driving voltage through the second output terminal in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, and the fourth time period, wherein the second switching time period is located between the second time period and the third time period, and the third switching time period is located between the third time period and the fourth time period.

[0022] In one possible implementation of the third aspect, outputting a first display driving voltage through a first output terminal in a first time period and a second display driving voltage in a second time period includes: outputting the first display driving voltage in the first time period, the second display driving voltage in the second time period, the first display driving voltage in the third time period, the second display driving voltage in the fourth time period, the first display driving voltage in the nth time period, and the second display driving voltage in the (n+1)th time period, where n is an odd number greater than or equal to 5. Maintaining the output of a third display driving voltage through a second output terminal in the first time period, the first switching time period, and the second time period includes: maintaining the output of a third display driving voltage through the second output terminal in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period, and the (n+1)th time period, where the fourth switching time period is located between the fourth time period and the nth time period, and the nth switching time period is located between the nth time period and the (n+1)th time period.

[0023] In one possible implementation of the third aspect, the third display driving voltage is equal to the power supply voltage.

[0024] Fourthly, a display device is provided, comprising a display screen and a display driver chip provided by the first aspect, or any possible implementation of the first aspect, or the second aspect, or any possible implementation of the second aspect. The display screen includes a plurality of pixel channels. The j-th pixel channel is coupled to a j-th output terminal, the j-th pixel channel being any one of the plurality of pixel channels, and the j-th output terminal being any one of the plurality of output terminals of the display driver chip.

[0025] Fifthly, an electronic device is provided, comprising a circuit board and a display device provided in the fourth aspect, wherein a display driver chip in the display device is disposed on the circuit board.

[0026] In another aspect, this application provides a computer-readable storage medium storing program code that can be invoked by a processor to execute the method provided by the third aspect or any possible implementation thereof.

[0027] In another aspect, this application provides a computer program product that, when run on a computer, causes the computer to perform the method provided by the third aspect or any possible implementation thereof.

[0028] It is understood that any of the display driving methods, devices, equipment, computer storage media or computer program products provided above all use the corresponding display driving chips provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects of the corresponding chips provided above, and will not be repeated here. Attached Figure Description

[0029] Figure 1 A schematic diagram of a first display device provided in an embodiment of this application;

[0030] Figure 2 A schematic diagram illustrating the principle of driving sub-pixels to emit light, provided for an embodiment of this application;

[0031] Figure 3 A voltage waveform for driving sub-pixel emission is provided in an embodiment of this application. Figure 1 ;

[0032] Figure 4 A voltage waveform for driving sub-pixel emission is provided in an embodiment of this application. Figure 2 ;

[0033] Figure 5 A voltage waveform for driving sub-pixel emission is provided in an embodiment of this application. Figure 3 ;

[0034] Figure 6 A schematic diagram of an electronic device provided in an embodiment of this application;

[0035] Figure 7 A schematic diagram of a second display device provided in an embodiment of this application;

[0036] Figure 8 A schematic diagram of a second display driver chip provided in an embodiment of this application. Figure 1 ;

[0037] Figure 9 A schematic diagram of a second display driver chip provided in an embodiment of this application. Figure 2 ;

[0038] Figure 10 A voltage waveform for driving sub-pixel emission is provided in an embodiment of this application. Figure 4 ;

[0039] Figure 11 A voltage waveform for driving sub-pixel emission is provided in an embodiment of this application. Figure 5 ;

[0040] Figure 12 A voltage waveform for driving sub-pixel emission is provided in an embodiment of this application. Figure 6 ;

[0041] Figure 13 This is a schematic diagram of a display driving method provided in an embodiment of this application. Detailed Implementation

[0042] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0043] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0044] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0045] First, some basic concepts involved in the embodiments of this application will be explained:

[0046] Organic light-emitting diode (OLED) displays are a display technology that uses organic light-emitting materials as the pixel light source. Each pixel in an OLED display consists of three sub-pixels: red (R), green (G), and blue (B). Each sub-pixel contains an OLED element. When current flows through it, the OLED element emits light of the corresponding color. The brightness and color of each OLED element can be controlled individually. Each sub-pixel may also include a resistive-capacitive (RC) load. OLED elements exhibit a certain delay in responding to voltage changes; the RC load can slow down the rise and fall rates of the signal, resulting in a more ideal voltage change curve for the OLED element. The RC load can also control the current to the OLED element, maintaining the consistency of its brightness and color. Therefore, the RC load can improve the stability of the display.

[0047] The red-green-blue-green (RGBG) pixel circuit is a pixel circuit that uses an RGBG pixel arrangement. Each pixel includes one red sub-pixel, one blue sub-pixel, and two green sub-pixels. This provides greater color depth and smoother color transitions. By adjusting the brightness combination of these four colors, countless colors can be generated, creating a rich and varied visual effect.

[0048] A display driver IC (DDIC) is an integrated circuit chip specifically designed to control and drive a display screen. Its main function is to convert the data to be displayed into electrical signals, ensuring that the image indicated by the displayed data is clearly and accurately presented on the screen.

[0049] In one possible implementation, such as Figure 1 As shown, the first display device 1100A includes a first display screen 100A and a first display driver IC (DDIC) 200A. For example, the first display screen 100A may be an OLED display screen.

[0050] The first display screen 100A may include a first pixel circuit 110A. The first pixel circuit 110A may include multiple channels, such as a first channel 11A, a second channel 12A, a third channel 13A, a fourth channel 14A, and more channels not shown. Each of the multiple channels may include multiple sub-pixels. Taking the first pixel circuit 110A as an RGBG pixel circuit as an example, the first channel 11A may include at least four sub-pixels: B, R, B, R; the second channel 12A may include at least four sub-pixels: G, G, G, G; the third channel 13A may include at least four sub-pixels: R, B, R, B; and the fourth channel 14A may include at least four sub-pixels: G, G, G, G. One sub-pixel B, one sub-pixel R, and two sub-pixels G can constitute a single pixel. For example, the first row of sub-pixels B in the first channel 11A, the first row of sub-pixels G in the second channel 12A, the first row of sub-pixels R in the third channel 13A, and the first row of sub-pixels G in the fourth channel 14A can constitute a single pixel. The first display driver chip 200A may include a first power supply terminal, multiple output terminals, a first gamma circuit 210A, and multiple driving channel circuits. The multiple output terminals may include a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, and more output terminals not shown. The multiple driving channel circuits may include a first driving channel circuit 221A, a second driving channel circuit 222A, a third driving channel circuit 223A, a fourth driving channel circuit 224A, and more driving channel circuits not shown.

[0051] The first power supply terminal and multiple drive channel circuits of the first display driver chip 200A are coupled to the first gamma circuit 210A. The multiple drive channel circuits of the first display driver chip 200A are coupled one-to-one with multiple output terminals; the specific coupling method can be found in [reference needed]. Figure 1 Multiple sub-pixels in each channel of the first pixel circuit 110A can be coupled to the same output terminal of the first display driver chip 200A. Furthermore, the multiple channels of the first pixel circuit 110A correspond one-to-one with the multiple output terminals of the first display driver chip 200A. For details on the correspondence, please refer to [reference needed]. Figure 1 For example, sub-pixels B in the first row, R in the second row, B in the third row, and R in the fourth row of the first channel 11A are all coupled to the first output terminal of the first display driver chip 200A. Sub-pixels G in the first row, G in the second row, G in the third row, and G in the fourth row of the second channel 12A are all coupled to the second output terminal of the first display driver chip 200A. Sub-pixels in the same row of multiple channels of the first pixel circuit 110A can be coupled to the same clock signal line. Figure 1 (Not shown in the image). For example, sub-pixels B in the first row of the first channel 11A, G in the first row of the second channel 12A, R in the first row of the third channel 13A, and G in the first row of the fourth channel 14A can be coupled to the first clock signal line. Sub-pixels R in the second row of the first channel 11A, G in the second row of the second channel 12A, B in the second row of the third channel 13A, and G in the second row of the fourth channel 14A can be coupled to the second clock signal line.

[0052] In one example, the first power supply terminal of the first display driver chip 200A is used to connect to a power supply, thereby receiving the power supply voltage from the power supply. The first gamma circuit 210A receives the power supply voltage through the first power supply terminal and converts it into multiple voltages of different magnitudes. For example, these multiple voltages, from largest to smallest, can be: Vgmp', Vdata1', Vdata2', ..., Vdataq', Vgsp'. The maximum voltage provided by the first gamma circuit 210A (e.g., Vgmp') is less than the power supply voltage. The first gamma circuit 210A can output multiple voltages to each drive channel circuit. The drive channel circuit is used to input multiple voltages and output a single voltage derived from those multiple voltages. Each drive channel circuit can provide one of the multiple voltages to the corresponding channel of that output terminal through its corresponding output terminal. For example, the first gamma circuit 210A can output Vgmp', Vdata1', Vdata2', ..., Vdataq', Vgsp' to the first drive channel circuit 221A. The first driving channel circuit 221A can obtain Vgmp from Vgmp', Vdata1 from Vdata1', Vdata2 from Vdata2', Vdataq from Vdataq', and Vgsp from Vgsp'. The first driving channel circuit 221A can provide one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp to the sub-pixels in the first channel 11A through its first output terminal. The maximum voltage output by the driving channel circuit (e.g., Vgmp) is less than the power supply voltage. When Vgmp is applied to the sub-pixel, the sub-pixel does not emit light; when Vdata1, Vdata2, ..., Vdataq, and Vgsp are applied to the sub-pixel sequentially, the brightness of the sub-pixel changes from small to large.

[0053] like Figure 2As shown, the first driving channel circuit 221A can output Vgmp in the first driving period, Vdata in the second driving period, Vgmp in the third driving period, and Vdata in the fourth driving period through its first output terminal. Here, Vdata is any one of Vdata1, Vdata2, ..., Vdataq. The first channel 11A receives Vgmp in the first driving period. With the cooperation of the clock signal line, Vgmp is applied to the first row sub-pixel B, and the first row sub-pixel B does not emit light. The first channel 11A receives Vdata in the second driving period. With the cooperation of the clock signal line, Vdata is applied to the second row sub-pixel R, and the second row sub-pixel R emits light. The first channel 11A receives Vgmp in the third driving period. With the cooperation of the clock signal line, Vgmp is applied to the third row sub-pixel B, and the third row sub-pixel B does not emit light. The first channel 11A receives Vdata in the fourth driving period. With the cooperation of the clock signal line, Vdata is applied to the fourth row sub-pixel R, and the fourth row sub-pixel R emits light.

[0054] like Figure 3 As shown, with Figure 2 The principle is the same as shown, when the voltage waveforms of multiple output terminals are Figure 3 When the voltage waveform is displayed, the second row of sub-pixels R in the first channel 11A illuminates, the fourth row of sub-pixels R in the first channel 11A illuminates, the first row of sub-pixels R in the third channel 13A illuminates, and the third row of sub-pixels R in the third channel 13A illuminates; the remaining sub-pixels do not illuminate. At this time, the image on the first display screen 100A is red.

[0055] like Figure 4 As shown, with Figure 2 The principle is the same as shown, when the voltage waveforms of multiple output terminals are Figure 4 When the voltage waveform is displayed, the first row of sub-pixels B in the first channel 11A illuminates, the third row of sub-pixels B in the first channel 11A illuminates, the second row of sub-pixels B in the third channel 13A illuminates, and the fourth row of sub-pixels B in the third channel 13A illuminates, while the remaining sub-pixels do not illuminate. At this time, the image on the first display screen 100A is blue.

[0056] like Figure 5 As shown, with Figure 2 The principle is the same as shown, when the voltage waveforms of multiple output terminals are Figure 5 When the voltage waveform is displayed, the first row of sub-pixels G in the second channel 12A illuminates, the third row of sub-pixels G in the second channel 12A illuminates, the first row of sub-pixels G in the fourth channel 14A illuminates, and the third row of sub-pixels G in the fourth channel 14A illuminates; the remaining sub-pixels do not illuminate. At this time, the image on the first display screen 100A is green.

[0057] from Figures 3-5As can be seen, the output terminal can output dynamic voltage. Dynamic voltage refers to voltages of varying magnitudes. Outputting dynamic voltage means that the output terminal does not consistently output the same voltage level, but rather outputs different voltage levels at different driving periods. This dynamic voltage is based on the different voltage levels converted from the data to be displayed, rather than being caused by interference. For example, Figure 3 The voltage output from the first output terminal switches from Vgmp to Vdata, or from Vdata to Vgmp. When the output terminal outputs a dynamic voltage, its adjacent output terminals, which should ideally maintain the same voltage, may experience voltage disturbances. For example, Figure 3 During the time interval between the voltage output of the first output terminal switching from Vgmp to Vdata, or from Vdata to Vgmp, the Vgmp output of the adjacent second output terminal is pulled low. The second output terminal should maintain the output of Vgmp, but the actual voltage waveform exhibits a dip.

[0058] The aforementioned interference is a gamma disturbance introduced by the first gamma circuit 210A. The first gamma circuit 210A outputs multiple voltages to both the first drive channel circuit 221A (using these voltages as its input) and the second drive channel circuit 222A (using these voltages as its input). When outputting a dynamic voltage, the first drive channel circuit 221A switches voltages based on the multiple voltages provided by the first gamma circuit 210A, causing interference with the voltage supplied by the first gamma circuit 210A to the first drive channel circuit 221A. When the voltage output by the first gamma circuit 210A is interfered with, the input voltage of the second drive channel circuit 222A is also interfered with; therefore, the voltage output by the second drive channel circuit 222A is also affected.

[0059] When the voltage is disturbed, a large current needs to be drawn from the power supply voltage for voltage stabilization, which results in significant power consumption. Furthermore, the first gamma circuit 210A has numerous traces, and the impedance and parasitic capacitance introduced by these traces limit its driving capability, thereby limiting the driving capability of the drive channel circuit and the output voltage process. This slows down the voltage re-establishment (voltage recovery) process. Additionally, reducing gamma disturbances requires enhancing the performance of the first gamma circuit 210A through additional power consumption or circuit area, leading to significant power consumption and wasted circuit area. Therefore, this implementation suffers from conversion efficiency and thermal power consumption issues when outputting dynamic voltages, which consume a lot of power and cannot provide an optimal low-power solution.

[0060] In another possible implementation, the aforementioned Vgmp can be provided by a low dropout regulator (LDO). However, LDOs have insufficient driving force, and the voltage re-establishment process is particularly slow when the LDO is disturbed.

[0061] This application provides an electronic device. For example... Figure 6 As shown, electronic device 1000B may include a circuit board ( Figure 6 (Not shown in the image) and a second display device 1100B. The second display device 1100B may include a coupled second display screen 100B and a second display driver chip 200B. The second display driver chip 200B may be disposed on a circuit board.

[0062] like Figure 7 As shown, the second display screen 100B may include a second pixel circuit 110B. The second pixel circuit 110B may include multiple pixel channels, such as a first pixel channel 11B, a second pixel channel 12B, a third pixel channel 13B, a fourth pixel channel 14B, and more pixel channels not shown. Each of the multiple pixel channels may include multiple sub-pixels. Taking the second pixel circuit 110B as an RGBG pixel circuit as an example, the first pixel channel 11B may include at least four sub-pixels: B, R, B, R; the second pixel channel 12B may include at least four sub-pixels: G, G, G, G; the third pixel channel 13B may include at least four sub-pixels: R, B, R, B; and the fourth pixel channel 14B may include at least four sub-pixels: G, G, G, G. One sub-pixel B, one sub-pixel R, and two sub-pixels G can constitute a single pixel. For example, the first row of sub-pixels B in the first pixel channel 11B, the first row of sub-pixels G in the second pixel channel 12B, the first row of sub-pixels R in the third pixel channel 13B, and the first row of sub-pixels G in the fourth pixel channel 14B can be considered as a single pixel.

[0063] The second display driver chip 200B may include a second power supply terminal, multiple output terminals, multiple display switches, multiple power switches, a second gamma circuit 210B, and multiple display channel circuits. The multiple output terminals may include a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, and more output terminals not shown. The multiple display switches may include a first display switch S1B, a second display switch S2B, a third display switch S3B, a fourth display switch S4B, and more display switches not shown. The multiple power switches may include a first power switch K1B, a second power switch K2B, a third power switch K3B, a fourth power switch K4B, and more power switches not shown. The multiple display channel circuits may include a first display channel circuit 221B, a second display channel circuit 222B, a third display channel circuit 223B, a fourth display channel circuit 224B, and more display channel circuits not shown.

[0064] The second power supply terminal and multiple display channel circuits of the second display driver chip 200B are coupled to the second gamma circuit 210B. The multiple display channel circuits of the second display driver chip 200B are coupled one-to-one with the first terminals of multiple display switches, and the second terminals of the multiple display switches are coupled one-to-one with multiple output terminals. The second power supply terminal is coupled to the first terminals of multiple power switches, and the second terminals of the multiple power switches are coupled one-to-one with multiple output terminals. For example, the output terminal of the first display channel circuit 221B is coupled to the first terminal of the first display switch S1B, and the second terminal of the first display switch S1B is coupled to the first output terminal. The second power supply terminal is coupled to the first terminal of the first power switch K1B, and the second terminal of the first power switch K1B is coupled to the first output terminal. As another example, the output terminal of the m-th display channel circuit is coupled to the first terminal of the m-th display switch, and the second terminal of the m-th display switch is coupled to the m-th output terminal. The power supply terminal is coupled to the first terminal of the m-th power switch, and the second terminal of the m-th power switch is coupled to the m-th output terminal. The m-th display channel circuit is any one of the multiple display channel circuits, the m-th display switch is any one of the multiple display switches, the m-th power switch is any one of the multiple power switches, and the m-th output terminal is any one of the multiple output terminals.

[0065] Multiple pixel channels of the second pixel circuit 110B are coupled one-to-one with multiple output terminals of the second display driver chip 200B. For example, the j-th pixel channel is coupled to the j-th output terminal, where the j-th pixel channel is any one of the multiple pixel channels, and the j-th output terminal is any one of the multiple output terminals of the display driver chip. Optionally, multiple sub-pixels in each pixel channel of the second pixel circuit 110B can be coupled to the same output terminal of the second display driver chip 200B, and the multiple pixel channels of the second pixel circuit 110B correspond one-to-one with the multiple output terminals of the second display driver chip 200B. For example, the first row of sub-pixels B, the second row of sub-pixels R, the third row of sub-pixels B, and the fourth row of sub-pixels R in the first pixel channel 11B are all coupled to the first output terminal of the second display driver chip 200B. The first row of sub-pixels G, the second row of sub-pixels G, the third row of sub-pixels G, and the fourth row of sub-pixels G in the second pixel channel 12B are all coupled to the second output terminal of the second display driver chip 200B.

[0066] In the second pixel circuit 110B, sub-pixels located in the same row of multiple pixel channels can be coupled to the same clock signal line. Figure 7 (Not shown in the image). For example, sub-pixel B in the first row of the first pixel channel 11B, sub-pixel G in the first row of the second pixel channel 12B, sub-pixel R in the first row of the third pixel channel 13B, and sub-pixel G in the first row of the fourth pixel channel 14B can be coupled to the third clock signal line. Sub-pixel R in the second row of the first pixel channel 11B, sub-pixel G in the second row of the second pixel channel 12B, sub-pixel B in the second row of the third pixel channel 13B, and sub-pixel G in the second row of the fourth pixel channel 14B can be coupled to the fourth clock signal line.

[0067] In one example, the following combination Figure 8 Possible implementations of the multiple display channel circuits and the second pixel circuit 110B in the second display driver chip 200B will be described. Figure 8 Multiple power switches are not shown.

[0068] The second power supply terminal of the second display driver chip 200B is used to connect to a power supply, thereby receiving the power supply voltage from the power supply. The second gamma circuit 210B receives the power supply voltage through the second power supply terminal and converts the power supply voltage into multiple voltages of different magnitudes. For example, the second gamma circuit 210B may include multiple resistors, and multiple voltages are obtained by resistor voltage division. These multiple voltages, from largest to smallest, can be: Vgmp', Vdata1', Vdata2', ..., Vdataq', Vgsp'. Among them, the maximum voltage provided by the second gamma circuit 210B (such as Vgmp') is less than the power supply voltage. The second gamma circuit 210B can output multiple voltages to each display channel circuit.

[0069] The display channel circuit is used to input multiple voltages and output a single voltage derived from those multiple voltages. Each display channel circuit can, when its corresponding display switch is turned on, provide one of the multiple voltages to the corresponding pixel channel through its corresponding output terminal. For example, each display channel circuit may include a multiplexer (MUX) and a channel operational amplifier (CH-OP). The i-th input terminal of the multiplexer is coupled to the i-th voltage output terminal of the second gamma circuit 210B. The i-th input terminal of the multiplexer is any one of the multiple input terminals of the multiplexer. The i-th voltage output terminal of the second gamma circuit 210B is any one of the multiple voltage output terminals of the second gamma circuit 210B. The output terminal of the multiplexer is coupled to the first input terminal of the channel operational amplifier, and both the second input terminal and the output terminal of the channel operational amplifier are coupled to the first terminal of the first display switch S1B.

[0070] The first voltage output terminal of the second gamma circuit 210B can be used to output Vgmp' to the first input terminal of the multiplexer of the first display channel circuit 221B. The second voltage output terminal of the second gamma circuit 210B can be used to output Vdata1' to the second input terminal of the multiplexer of the first display channel circuit 221B. The third voltage output terminal of the second gamma circuit 210B can be used to output Vdata2' to the third input terminal of the multiplexer of the first display channel circuit 221B. ... The q+1 voltage output terminal of the second gamma circuit 210B can be used to output Vdataq' to the q+1 input terminal of the multiplexer of the first display channel circuit 221B. The q+2 voltage output terminal of the second gamma circuit 210B can be used to output Vgsp' to the q+2 input terminal of the multiplexer of the first display channel circuit 221B. The first display channel circuit 221B can obtain Vgmp from Vgmp', Vdata1 from Vdata1', Vdata2 from Vdata2', Vdataq from Vdataq', and Vgsp from Vgsp'.

[0071] The first display channel can supply one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp to the sub-pixels in the first pixel channel 11B through the first output terminal when the first display switch S1B is on and the first power switch K1B is off. The maximum voltage output by the display channel circuit (e.g., Vgmp) is less than the power supply voltage. The second power supply terminal can supply power voltage to the first pixel channel 11B through the first output terminal when the first power switch K1B is on and the first display switch S1B is off. Each sub-pixel can include an RC load, which includes a resistor R and a capacitor C. The first end of the resistor R is coupled to the first output terminal, the second end of the resistor R is coupled to the first end of the capacitor C, and the second end of the capacitor C is grounded.

[0072] In this embodiment, the display channel circuit is coupled to the output terminal via a display switch, and the second power supply terminal is coupled to the output terminal via a power switch. The output terminal can output the voltage of the display channel circuit, or output the power supply voltage received by the second power supply terminal. When the output terminal needs to output a voltage (e.g., Vdata) to drive the sub-pixel to emit light, the display channel circuit can output the voltage to the output terminal by switching the display switch and the power switch on and off. When the output terminal needs to output a voltage (e.g., Vgmp) to drive the sub-pixel not to emit light, the second power supply terminal can output the power supply voltage to the output terminal by switching the display switch and the power switch on and off. If the power supply voltage is greater than Vgmp, the power supply voltage can also drive the sub-pixel not to emit light, so the power supply voltage can replace Vgmp output by the display channel circuit. It can be seen that when the output terminal outputs a dynamic voltage, it does not switch the voltage based on the multiple voltages provided by the second gamma circuit 210B, but switches the voltage by switching the display switch and the power switch on and off. In this way, the interference on the voltage provided by the second gamma circuit 210B to the display channel circuit is mitigated, and the interference on the voltage output by the display channel circuit adjacent to this display channel circuit is mitigated. In this way, the interference on the final output voltage is mitigated.

[0073] In one possible implementation, such as Figure 9 As shown, the multiple display switches can be metal-oxide-semiconductor field-effect transistors (MOSFETs). The second display driver chip 200B also includes multiple drive enhancement (buffer) circuits, such as a first drive enhancement circuit 231B, a second drive enhancement circuit 232B, a third drive enhancement circuit 233B, and a fourth drive enhancement circuit 234B. In some examples, the k-th drive enhancement circuit is coupled to the control terminal of the k-th display switch. The k-th drive enhancement circuit is any one of the multiple drive enhancement circuits, and the k-th display switch is any one of the multiple display switches. For example, the first drive enhancement circuit 231B is coupled to the control terminal of the first display switch S1B, the second drive enhancement circuit 232B is coupled to the control terminal of the second display switch S2B, the third drive enhancement circuit 233B is coupled to the control terminal of the third display switch S3B, and the fourth drive enhancement circuit 234B is coupled to the control terminal of the fourth display switch S4B. Exemplarily, the drive enhancement circuit is used to stabilize the control waveform of the display switch to which it is coupled.

[0074] In this embodiment, the ideal control waveform for turning the display switches on or off is a square wave; however, in practice, this control waveform may be unstable. A drive enhancement circuit can stabilize the control waveform of its coupled display switches. By providing a drive enhancement circuit for each display switch, high-speed switching of multiple display switches can be achieved.

[0075] In one possible implementation, the power supply voltage at the second power supply terminal can be used instead of the maximum voltage (e.g., Vgmp) provided by the display channel circuit.

[0076] In some examples, such as Figure 10 As shown, the example of the second display driver chip 200B driving the second display screen 100B to display a red image is introduced.

[0077] For example, in the first time period T1, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the second time period T2, the first display switch S1B is turned on, and the first power switch K1B is turned off. A first output terminal is used to output a first display driving voltage in the first time period T1 and a second display driving voltage in the second time period T2. The first display driving voltage is used to drive the sub-pixels to not emit light. For example, the first display driving voltage is equal to the power supply voltage received by the second power supply terminal. Optionally, the second power supply terminal is used to connect to a power source. The second power supply terminal is used to receive an analog power supply voltage (AVDD). Since AVDD is greater than the maximum voltage (e.g., Vgmp) provided by the display channel circuit, AVDD can be used to drive the sub-pixels to not emit light, and AVDD can replace the maximum voltage Vgmp provided by the display channel circuit. In this embodiment, the second power supply terminal is connected to a power source, and the power supply voltage can be used as the voltage to drive the sub-pixels to not emit light through the second power supply terminal. The power supply voltage has a robust power network and low path impedance, which can reduce the additional power consumption caused by the dynamic voltage output by the display channel circuit. Furthermore, the second display driving voltage is used to drive the sub-pixels to emit light. For example, the second display driving voltage is located within a preset voltage range. The maximum value of the preset voltage range is less than the first display driving voltage. For example, the preset voltage range is between Vgsp and Vgmp (the preset voltage range does not include Vgsp and Vgmp). For example, if Vgsp is 0.2V, AVDD is 8V, and Vgmp = AVDD - Vgsp = 7.8V, the preset voltage range can be between 0.2V and 7.8V.

[0078] During the first time period T1, the first switching time period Tz1, and the second time period T2, the second power switch K2B is turned on, and the second display switch S2B is turned off. The first switching time period Tz1 is located between the first time period T1 and the second time period T2. The second output terminal is used to maintain the output of the third display driving voltage during the first time period T1, the first switching time period Tz1, and the second time period T2. The third display driving voltage is used to drive the sub-pixels to not emit light. For example, the third display driving voltage is equal to the power supply voltage received by the second power supply terminal. The maximum value of the preset voltage range is also less than the third display driving voltage.

[0079] Alternatively, during the first time period T1, the first switching time period Tz1, and the second time period T2, the second display switch S2B is turned on, and the second power switch K2B is turned off. The second output terminal maintains an output third display drive voltage equal to the maximum voltage (e.g., Vgmp) provided by the second display channel circuit 222B during the first time period T1, the first switching time period Tz1, and the second time period T2. That is, the third display drive voltage is less than the power supply voltage received by the second power supply terminal. The maximum value of the preset voltage range is also less than the third display drive voltage.

[0080] For example, in the first time period T1, the first power switch K1B is turned on and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the second time period T2, the first display switch S1B is turned on and the first power switch K1B is turned off. In the third time period T3, the first power switch K1B is turned on and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the fourth time period T4, the first display switch S1B is turned on and the first power switch K1B is turned off. The first output terminal is specifically used to output a first display driving voltage in the first time period T1, a second display driving voltage in the second time period T2, a first display driving voltage in the third time period T3, and a second display driving voltage in the fourth time period T4. The second display driving voltage output by the first output terminal in the first time period T1 can be Vdata12, and the second display driving voltage output by the first output terminal in the fourth time period T4 can be Vdata14. Vdata12 and Vdata14 are preset voltage values ​​within a preset voltage range. For example, Vdata12 and Vdata14 are one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp, respectively. Vdata12 and Vdata14 can be the same voltage value or different voltage values.

[0081] During the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, and the fourth time period T4, the second power switch K2B is turned on, and the second display switch S2B is turned off. The second switching time period Tz2 is located between the second time period T2 and the third time period T3, and the third switching time period Tz3 is located between the third time period T3 and the fourth time period T4. The second output terminal is specifically used to maintain the output of the third display drive voltage during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, and the fourth time period T4. The third display drive voltage is equal to the power supply voltage (e.g., AVDD) received by the second power supply terminal. Alternatively, during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, and the fourth time period T4, the second display switch S2B is turned on, and the second power switch K2B is turned off. The third display drive voltage is equal to the maximum voltage (e.g., Vgmp) provided by the second display channel circuit 222B.

[0082] For example, in the first time period T1, the first power switch K1B is on and the first display switch S1B is off (optionally, S1B is off first, and K1B is on later). In the second time period T2, the first display switch S1B is on and the first power switch K1B is off. In the third time period T3, the first power switch K1B is on and the first display switch S1B is off (optionally, S1B is off first, and K1B is on later). In the fourth time period T4, the first display switch S1B is on and the first power switch K1B is off. In the nth time period Tn, the first power switch K1B is on and the first display switch S1B is off (optionally, S1B is off first, and K1B is on later). In the (n+1)th time period Tn+1, the first display switch S1B is on and the first power switch K1B is off. n is an odd number greater than or equal to 5. The first output terminal is specifically used to output a first display driving voltage in a first time period T1, a second display driving voltage in a second time period T2, a first display driving voltage in a third time period T3, a second display driving voltage in a fourth time period T4, a first display driving voltage in a nth time period Tn, and a second display driving voltage in a (n+1)th time period Tn+1. Specifically, the second display driving voltage output by the first output terminal in the first time period T1 can be Vdata12, the second display driving voltage output by the first output terminal in the fourth time period T4 can be Vdata14, and the second display driving voltage output by the first output terminal in the (n+1)th time period Tn+1 can be Vdata1(n+1). Vdata12, Vdata14, and Vdata1(n+1) are preset voltage values ​​within a preset voltage range. For example, Vdata12, Vdata14, and Vdata1(n+1) are one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp, respectively. Vdata12, Vdata14, and Vdata1(n+1) can be the same voltage value, or at least two of them can be different voltage values.

[0083] During the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, and the third switching time period Tn+1, the second power switch K2B is turned on, and the second display switch S2B is turned off. The fourth switching time period Tz4 is located between the fourth time period T4 and the nth time period Tn, and the nth switching time period Tzn is located between the nth time period Tn and the (n+1)th time period Tn+1. The second output terminal is specifically used to maintain the output of the third display drive voltage during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn, and the (n+1)th time period Tn+1. The third display drive voltage is equal to the power supply voltage (e.g., AVDD) received by the second power supply terminal. Alternatively, during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn, and the (n+1)th time period Tn+1, the second display switch S2B is turned on, and the second power switch K2B is turned off. The third display drive voltage is equal to the maximum voltage (e.g., Vgmp) provided by the second display channel circuit 222B.

[0084] For example, the first display channel circuit 221B outputs the second display driving voltage only when the first display switch S1B is turned on. In this embodiment, the first display channel circuit 221B outputs voltage only when the first display switch S1B is turned on, further reducing the power consumption of the first display channel circuit 221B. Alternatively, the first display channel outputs the maximum voltage (e.g., Vgmp) that the first display channel circuit 221B can provide when both the first display switch S1B and the first power switch K1B are turned on. In this embodiment, the first display channel circuit 221B continuously outputs the second display driving voltage, and the first display channel circuit 221B is in a static output mode. In this way, interference of the output voltage of the first display channel circuit 221B to the power supply voltage at the power supply terminal can be avoided, and the design complexity of the first display channel circuit 221B can also be reduced.

[0085] For example, in the first time period T1, the third display switch S3B is on and the third power switch K3B is off. In the second time period T2, the third power switch K3B is on and the third display switch S3B is off. In the third time period T3, the third display switch S3B is on and the third power switch K3B is off. In the fourth time period T4, the third power switch K3B is on and the third display switch S3B is off. In the nth time period Tn, the third display switch S3B is on and the third power switch K3B is off. In the (n+1)th time period Tn+1, the third power switch K3B is on and the third display switch S3B is off. n is an odd number greater than or equal to 5. The third output terminal is specifically used to output the fourth display driving voltage in the first time period T1, the first display driving voltage in the second time period T2, the fourth display driving voltage in the third time period T3, the first display driving voltage in the fourth time period T4, the fourth display driving voltage in the nth time period Tn, and the first display driving voltage in the (n+1)th time period Tn+1. The fourth display driving voltage is located within the aforementioned preset voltage range. The fourth display driving voltage output by the third output terminal in the first time period T1 can be Vdata31, the fourth display driving voltage output by the third output terminal in the third time period T3 can be Vdata33, and the fourth display driving voltage output by the third output terminal in the nth time period Tn can be Vdata3n. Vdata31, Vdata33, and Vdata3n are preset voltage values ​​within the preset voltage range. For example, Vdata31, Vdata33, and Vdata3n are one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp, respectively. Vdata12, Vdata14, Vdata1(n+1), Vdata31, Vdata33, and Vdata3n can be the same voltage value, or at least two of them can be different voltage values.

[0086] During the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn, and the (n+1)th time period Tn+1, the fourth power switch K4B is turned on, and the fourth display switch S4B is turned off. The fourth output terminal is specifically used to maintain the output of the third display drive voltage during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn, and the (n+1)th time period Tn+1. The third display drive voltage is equal to the power supply voltage (e.g., AVDD) received by the second power supply terminal. Alternatively, during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn, and the (n+1)th time period Tn+1, the fourth display switch S4B is turned on, and the fourth power switch K4B is turned off. The third display drive voltage is equal to the maximum voltage (e.g., Vgmp) provided by the fourth display channel circuit 224B.

[0087] In other examples, the second display driver chip 200B can be used to drive the second display screen 100B to display a blue image, and the voltage waveforms of multiple output terminals are shown in the figure. Figure 11 As shown. Figure 11 The principle behind the voltage waveform diagram shown can be found by referring to... Figure 10 The principle of the voltage waveform diagram shown is not described again in this embodiment of the application. For example, Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34, and Vdata3(n+1) are preset voltage values ​​within a preset voltage range. For instance, Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34, and Vdata3(n+1) are one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp, respectively. Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34, and Vdata3(n+1) can be the same voltage value, or at least two of them can be different voltage values.

[0088] In some other examples, the second display driver chip 200B can be used to drive the second display screen 100B to display a green image, and the voltage waveforms of multiple output terminals are shown in the figure. Figure 12 As shown. Figure 12 The principle behind the voltage waveform diagram shown can be found by referring to... Figure 10The principle of the voltage waveform diagram shown is not described again in this embodiment. For example, Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, and Vdata4n are preset voltage values ​​within a preset voltage range. For instance, Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, and Vdata4n are one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp, respectively. Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, and Vdata4n can be the same voltage value, or at least two of them can be different voltage values.

[0089] In this embodiment, when the voltage output from the first output terminal is not a fixed value, a voltage equal to the power supply voltage received from the second power supply terminal is used as the first display driving voltage. That is, the first display driving voltage and the second display driving voltage have different sources. Figures 3-5 Compared to the illustrated implementation, the power supply voltage at the second power supply terminal can be used instead of the maximum voltage provided by the display channel circuit. When the first output terminal outputs a dynamic voltage, it no longer switches voltages based on multiple voltages provided by the second gamma circuit 210B. Interference on the voltage supplied by the second gamma circuit 210B to the first display channel circuit 221B is mitigated, and interference on the voltage output by the second display channel circuit 222B is also mitigated. Thus, interference on the final output voltage of the second output terminal is mitigated. Therefore, there is no need to draw a large current from the power supply voltage for voltage stabilization, reducing power consumption. Furthermore, the problem of impedance and parasitic capacitance limiting the driving capability of the second gamma circuit 210B can be alleviated, thereby improving the driving capability of the second display driver chip 200B and accelerating the voltage output process. Also, there is no need to enhance the performance of the second gamma circuit 210B through additional power consumption or circuit area to eliminate voltage interference, thereby reducing power consumption and circuit area waste.

[0090] based on Figures 6-12 The provided second display driver chip 200B, in this application embodiment, also provides a display driving method applied to the second display driver chip 200B. For example... Figure 13 As shown, the method may include at least:

[0091] S100: A first display driving voltage is output through the first output terminal during a first time period T1, and a second display driving voltage is output during a second time period T2. For example, the first display driving voltage is equal to the power supply voltage received by the second power supply terminal.

[0092] S200: The third display driving voltage is maintained at the output terminal during the first time period T1, the first switching time period Tz1, and the second time period T2. For example, the first switching time period Tz1 is located between the first time period T1 and the second time period T2. The second display driving voltage is within a preset voltage range, and the maximum value of the preset voltage range is less than the third display driving voltage.

[0093] In one possible implementation, S100 may specifically include: outputting a first display driving voltage through a first output terminal in a first time period T1, outputting a second display driving voltage in a second time period T2, outputting the first display driving voltage in a third time period T3, and outputting the second display driving voltage in a fourth time period T4.

[0094] S200 may specifically include: maintaining the output of a third display driving voltage through the second output terminal during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3 and the fourth time period T4, wherein the second switching time period Tz2 is located between the second time period T2 and the third time period T3, and the third switching time period Tz3 is located between the third time period T3 and the fourth time period T4.

[0095] In one possible implementation, S100 may specifically include: outputting a first display driving voltage through a first output terminal in a first time period T1, outputting a second display driving voltage in a second time period T2, outputting a first display driving voltage in a third time period T3, outputting a second display driving voltage in a fourth time period T4, outputting a first display driving voltage in a nth time period Tn, and outputting a second display driving voltage in a (n+1)th time period Tn+1, where n is an odd number greater than or equal to 5.

[0096] Specifically, S200 may include: maintaining the output of a third display driving voltage through the second output terminal during the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn, and the (n+1)th time period Tn+1, wherein the fourth switching time period Tz4 is located between the fourth time period T4 and the nth time period Tn, and the nth switching time period Tzn is located between the nth time period Tn and the (n+1)th time period Tn+1.

[0097] In one possible implementation, the third display driving voltage is equal to the power supply voltage received at the power supply terminal.

[0098] It is understood that the above display driving method can be applied to the aforementioned second display driver chip 200B. Since the effects of the chip have been described in detail in the aforementioned chip embodiment, they will not be repeated here.

[0099] This application also provides a computer-readable storage medium storing program code. When the medium is run on a device (e.g., a microcontroller, chip, computer, or processor), the program code can be invoked to execute one or more steps in the above method embodiments.

[0100] Based on this understanding, this application also provides a computer program product containing instructions. The technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or its processor to execute all or part of the steps of the methods of the various embodiments of this application.

[0101] In the several embodiments provided in this application, it should be understood that the disclosed chips, devices, equipment, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms.

[0102] In addition, the functional modules in the various embodiments of this application can be integrated into one device, or each module can exist physically separately, or two or more modules can be integrated into one device.

[0103] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display driver chip, characterized in that, The display driver chip includes a power supply terminal and multiple output terminals; the multiple output terminals include a first output terminal and a second output terminal. The power supply terminal is used to receive the power supply voltage; The first output terminal is used to output a first display driving voltage in a first time period and a second display driving voltage in a second time period, wherein the first display driving voltage is equal to the power supply voltage; The second output terminal is used to maintain the output of the third display driving voltage during the first time period, the first switching time period, and the second time period, wherein the first switching time period is located between the first time period and the second time period; The second display driving voltage is located within a preset voltage range, and the maximum value of the preset voltage range is less than the third display driving voltage.

2. The display driver chip according to claim 1, characterized in that, The plurality of output terminals also includes a third output terminal; The third output terminal is used to output a fourth display driving voltage during the first time period and output the first display driving voltage during the second time period, wherein the fourth display driving voltage is located within the preset voltage range; The fourth display driving voltage output by the third output terminal during the first time period is different from the second display driving voltage output by the first output terminal during the second time period.

3. The display driver chip according to claim 1 or 2, characterized in that, The first output terminal is specifically used to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in the third time period, and output the second display driving voltage in the fourth time period; The second output terminal is specifically used to maintain the output of the third display driving voltage during the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, and the fourth time period. The second switching time period is located between the second time period and the third time period, and the third switching time period is located between the third time period and the fourth time period.

4. The display driver chip according to claim 1 or 2, characterized in that, The first output terminal is specifically used to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in the third time period, output the second display driving voltage in the fourth time period, output the first display driving voltage in the nth time period, and output the second display driving voltage in the n+1th time period, where n is an odd number greater than or equal to 5; The second output terminal is specifically used to maintain the output of the third display driving voltage during the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period, and the n+1th time period. The fourth switching time period is located between the fourth time period and the nth time period, and the nth switching time period is located between the nth time period and the n+1th time period.

5. The display driver chip according to claim 1 or 2, characterized in that, The chip also includes a first display channel circuit, a first display switch, and a first power switch; The output terminal of the first display channel circuit is coupled to the first terminal of the first display switch, and the second terminal of the first display switch is coupled to the first output terminal. The power supply terminal is coupled to the first terminal of the first power switch, and the second terminal of the first power switch is coupled to the first output terminal.

6. The display driver chip according to claim 5, characterized in that, The chip also includes multiple display channel circuits, multiple display switches, and multiple power switches; The output terminal of the m-th display channel circuit is coupled to the first terminal of the m-th display switch, and the second terminal of the m-th display switch is coupled to the m-th output terminal; the power supply terminal is coupled to the first terminal of the m-th power switch, and the second terminal of the m-th power switch is coupled to the m-th output terminal. The m-th display channel circuit is any one of the plurality of display channel circuits, the m-th display switch is any one of the plurality of display switches, the m-th power switch is any one of the plurality of power switches, and the m-th output terminal is any one of the plurality of output terminals.

7. The display driver chip according to claim 6, characterized in that, The chip also includes multiple drive enhancement circuits. The k-th drive enhancement circuit is coupled to the control terminal of the k-th display switch; the k-th drive enhancement circuit is any one of the plurality of drive enhancement circuits, and the k-th display switch is any one of the plurality of display switches.

8. The display driver chip according to claim 1 or 2, characterized in that, The third display driving voltage is equal to the power supply voltage.

9. The display driver chip according to claim 1 or 2, characterized in that, The power supply terminal is used to connect to a power source.

10. A display driving method, characterized in that, The display driving method is applied to a display driving chip, the display driving chip including a power supply terminal and multiple output terminals; the power supply terminal is used to receive a power supply voltage; the multiple output terminals include a first output terminal and a second output terminal; the method includes: A first display driving voltage is output through the first output terminal during a first time period, and a second display driving voltage is output during a second time period. The first display driving voltage is equal to the power supply voltage. The third display driving voltage is maintained at the second output terminal during the first time period, the first switching time period, and the second time period, wherein the first switching time period is located between the first time period and the second time period. The second display driving voltage is located within a preset voltage range, and the maximum value of the preset voltage range is less than the third display driving voltage.

11. The display driving method according to claim 10, characterized in that, The plurality of output terminals also includes a third output terminal, and the method further includes: The fourth display driving voltage is output through the third output terminal during the first time period, and the first display driving voltage is output during the second time period. The fourth display driving voltage is located within the preset voltage range. The fourth display driving voltage output by the third output terminal during the first time period is different from the second display driving voltage output by the first output terminal during the second time period.

12. The display driving method according to claim 10 or 11, characterized in that, The step of outputting a first display driving voltage through the first output terminal in a first time period and outputting a second display driving voltage in a second time period includes: The first display driving voltage is output through the first output terminal in the first time period, the second display driving voltage is output in the second time period, the first display driving voltage is output in the third time period, and the second display driving voltage is output in the fourth time period; The step of maintaining the output of the third display driving voltage through the second output terminal during the first time period, the first switching time period, and the second time period includes: The third display driving voltage is maintained at the second output terminal during the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, and the fourth time period. The second switching time period is located between the second time period and the third time period, and the third switching time period is located between the third time period and the fourth time period.

13. The display driving method according to claim 10 or 11, characterized in that, The step of outputting a first display driving voltage through the first output terminal in a first time period and outputting a second display driving voltage in a second time period includes: The first display driving voltage is output through the first output terminal in the first time period, the second display driving voltage is output in the second time period, the first display driving voltage is output in the third time period, the second display driving voltage is output in the fourth time period, the first display driving voltage is output in the nth time period, and the second display driving voltage is output in the n+1th time period, where n is an odd number greater than or equal to 5. The step of maintaining the output of the third display driving voltage through the second output terminal during the first time period, the first switching time period, and the second time period includes: The third display driving voltage is maintained at the second output terminal during the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period, and the n+1th time period. The fourth switching time period is located between the fourth time period and the nth time period, and the nth switching time period is located between the nth time period and the n+1th time period.

14. The display driving method according to claim 10 or 11, characterized in that, The third display driving voltage is equal to the power supply voltage.

15. A display device, characterized in that, The display device includes a display screen and a display driver chip as described in any one of claims 1-9; the display screen includes a plurality of pixel channels; The j-th pixel channel is coupled to the j-th output terminal, wherein the j-th pixel channel is any one of the multiple pixel channels, and the j-th output terminal is any one of the multiple output terminals of the display driver chip.

16. An electronic device, characterized in that, The electronic device includes a circuit board and a display device as described in claim 15, wherein a display driver chip in the display device is disposed on the circuit board.

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