Method for forming silicide connection layer and semiconductor device

Abstract

The present application discloses a method for forming a silicide connection layer and a semiconductor device. The method comprises: providing a semiconductor structure, wherein the material of the semiconductor structure comprises silicon; forming a protective layer on the semiconductor structure and forming a metal layer on the protective layer; performing an annealing process so that metal particles in the metal layer pass through the protective layer and react with silicon in the semiconductor structure to form an intermediate layer; removing the remaining part of the metal layer while the protective layer protects the intermediate layer; performing an annealing process again so that the intermediate layer continues to react with silicon in the semiconductor structure to form a silicide connection layer, and removing the protective layer. In the present application, in the process of removing the remaining part of the metal layer, the intermediate layer is not damaged due to the protection of the protective layer, which is beneficial to improving the performance of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a silicide connection layer and a semiconductor device. Background Art

[0002] In the integrated circuit process, the formation process of the silicide connection layer is the key link between the front-end process and the back-end process. In the existing process, the formation process of the silicide connection layer includes: the lithography step of the barrier layer, the etching step of the barrier layer, the metal ion implantation or deposition step, the first rapid thermal annealing (RTA) step, the residual metal removal (Strip) step, and the second rapid thermal annealing step.

[0003] However, in the residual metal removal step, the HPM solution and the APM solution will also oxidize part of the metal silicide when removing the unreacted metal. The oxidized metal silicide will be removed in the subsequent process, so that the formed silicide connection layer such as Figure 1 As shown in the figure, recesses appear. The loss of metal silicide in this process is generally 50 angstroms to 100 angstroms. This not only makes it impossible for the formed silicide connection layer to reduce the contact resistance well, thereby affecting the electrical properties of the semiconductor device and reducing the sensitivity of the semiconductor device; it also affects the reliability of the semiconductor device, making it unable to work normally, thereby reducing the yield. Summary of the invention

[0004] In view of the above problems, the purpose of the present application is to provide a method for forming a silicide connection layer and a semiconductor device, by improving the formation process of the silicide connection layer so that metal silicide will not be lost in the residual metal removal step.

[0005] According to a first aspect of the present invention, there is provided a method for forming a silicide connection layer, comprising:

[0006] A semiconductor structure is provided, wherein the material of the semiconductor structure includes silicon;

[0007] forming a protective layer on the semiconductor structure and forming a metal layer on the protective layer;

[0008] performing an annealing process so that metal particles in the metal layer pass through the protective layer and react with silicon in the semiconductor structure to form an intermediate layer;

[0009] removing the remaining portion of the metal layer while the protective layer protects the intermediate layer;

[0010] The annealing process is performed again to allow the intermediate layer to continue to react with silicon in the semiconductor structure to form a silicide connection layer, and the protection layer is removed.

[0011] Optionally, the metal layer is made of nickel.

[0012] Optionally, the protective layer is made of hafnium silicate or hafnium dioxide, and the protective layer is removed after the silicide connection layer is formed.

[0013] Optionally, the forming method further comprises:

[0014] After forming a metal layer on the protective layer, forming an isolation layer on the metal layer;

[0015] And after forming the intermediate layer and before removing the remaining portion of the metal layer, the isolation layer is removed.

[0016] Optionally, the isolation layer is made of titanium nitride, and removing the isolation layer and the remaining portion of the metal layer includes: removing the remaining portion of the metal layer and the isolation layer using a dry etching process and using an etching gas of hydrogen bromide gas or pure chlorine gas.

[0017] Optionally, removing the protective layer includes: removing the protective layer by a dry etching process, wherein the etching gases used are boron trichloride gas and chlorine gas.

[0018] Optionally, the formation method further comprises: before forming the protection layer on the semiconductor structure, injecting inert element particles into the semiconductor structure to break up the crystal lattice of the semiconductor structure.

[0019] Optionally, the inert element particles are xenon atoms.

[0020] Optionally, the semiconductor structure includes a gate structure disposed on a substrate and doped regions disposed in the substrate and located on both sides of the gate structure, the gate structure includes a stacked gate dielectric layer and a gate conductor layer and an isolation structure covering the sidewalls of the gate dielectric layer and the sidewalls and surface of the gate conductor layer;

[0021] The forming method further comprises: forming a barrier layer on the substrate, wherein the barrier layer has openings on the isolation structure and the doping region, and the protection layer covers the barrier layer and the surface of the doping region and the surface of the isolation structure.

[0022] According to a second aspect of the present invention, there is provided a semiconductor device, the semiconductor device comprising a silicide connection layer, the silicide connection layer being formed by any one of the forming methods described in the first aspect.

[0023] The unexpected technical effects of this application are:

[0024] The present application provides a method for forming a silicide connection layer, comprising: providing a semiconductor structure, wherein the material of the semiconductor structure includes silicon; forming a protective layer on the semiconductor structure and forming a metal layer on the protective layer; performing an annealing process so that metal particles in the metal layer pass through the protective layer and react with silicon in the semiconductor structure to form an intermediate layer; removing the remaining portion of the metal layer while the protective layer protects the intermediate layer; performing an annealing process again so that the intermediate layer continues to react with silicon in the semiconductor structure to form a silicide connection layer, and then removing the protective layer. Therefore, the intermediate protective layer will not be lost in the process of removing the remaining portion of the metal layer, and the silicide connection layer finally formed has a higher quality, and thus the performance and yield of the semiconductor device will not be reduced due to the poor quality of the silicide connection layer.

[0025] Furthermore, the metal layer is made of nickel. Since nickel atoms are small and highly diffusible, they can easily diffuse through the protective layer during the annealing process, so the presence of the protective layer does not substantially affect the reaction between the metal particles in the metal layer and the silicon in the semiconductor structure.

[0026] Furthermore, the material of the protective layer is hafnium silicate or hafnium dioxide. The protective layer of hafnium silicate or hafnium dioxide not only protects the intermediate layer from being lost during the removal of the remaining part of the metal layer, but also reduces the interface energy of the silicide, inhibits the agglomeration effect of nickel silicide, and delays the generation of byproduct NiSi2 in the silicide connection layer, thereby improving the thermal stability of the silicide connection layer.

[0027] Furthermore, there is an isolation layer on the metal layer, and the isolation layer is made of titanium nitride. A dry etching process is used to remove the remaining part of the metal layer and the isolation layer, and the etching gas used is hydrogen bromide gas or pure chlorine gas. Since hydrogen bromide gas and pure chlorine gas do not react with hafnium silicate and hafnium dioxide, the surface of the protective layer will not be damaged during the removal of the remaining part of the metal layer and the isolation layer, and the intermediate layer can be protected by the protective layer without loss.

[0028] Furthermore, a dry etching process is used to remove the protective layer, and the etching gases used are boron trichloride gas and chlorine gas. Since chlorine gas mixed with boron trichloride gas has a high selectivity for hafnium silicate or hafnium dioxide, the protective layer using hafnium silicate or hafnium dioxide is completely removed without damaging the silicide connection layer, thereby reducing the surface roughness of the silicide connection layer, enhancing the rectification characteristics of the semiconductor device, and being beneficial to improving the electrical properties of the semiconductor device.

[0029] Furthermore, before forming a protective layer on the semiconductor structure, inert element particles are injected into the semiconductor structure to break up the crystal lattice of the semiconductor structure. This makes it easier for the metal particles in the metal layer to diffuse in the semiconductor structure, thereby compensating for the reduction in the diffusion depth of the metal particles in the semiconductor structure caused by the protective layer, and the inert element particles will not cause material changes in the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0031] Figure 1 A cross-sectional view showing a silicide connection layer formed by a conventional process;

[0032] Figure 2a A cross-sectional view showing a process for forming a resist layer on a semiconductor structure in a conventional process;

[0033] Figure 2b A cross-sectional view showing a conventional process for forming a barrier layer on a semiconductor structure;

[0034] Figure 2c A cross-sectional view showing a conventional process for forming a metal layer on a semiconductor structure;

[0035] Figure 2d A cross-sectional view showing a conventional process for forming an intermediate layer in a semiconductor structure;

[0036] Figure 2e A cross-sectional view showing the remaining portion of the metal layer removed in a conventional process;

[0037] Figure 2f A cross-sectional view showing a conventional process for forming a silicide connection layer in a semiconductor structure;

[0038] Figure 3 A flow chart showing a method for forming a silicide connection layer according to an embodiment of the present application;

[0039] Figure 4a A cross-sectional view showing a process of forming a resist layer on a semiconductor structure according to an embodiment of the present application;

[0040] Figure 4b A cross-sectional view showing a barrier layer formed on a semiconductor structure according to an embodiment of the present application;

[0041] Figure 4c A cross-sectional view showing a protective layer formed on a semiconductor structure according to an embodiment of the present application;

[0042] Figure 4d A cross-sectional view showing a metal layer formed on a semiconductor structure according to an embodiment of the present application;

[0043] Figure 4e A cross-sectional view showing a method of forming an intermediate layer in a semiconductor structure according to an embodiment of the present application;

[0044] Figure 4f A cross-sectional view showing a remaining portion of a metal layer removed according to an embodiment of the present application;

[0045] Figure 4g A cross-sectional view showing a method of forming a silicide connection layer in a semiconductor structure according to an embodiment of the present application;

[0046] Figure 4h A cross-sectional view showing a protective layer removed according to an embodiment of the present application is shown.

[0047] Description of reference numerals: 110 - substrate; 120 - gate structure; 121 - gate dielectric layer; 122 - gate conductor layer; 123 - isolation structure; 123a - inner silicon nitride layer; 123b - middle silicon oxide layer; 123c - outer silicon nitride layer; 130 - doping region; 140 - initial barrier layer; 150 - resist layer; 160 - metal layer; 170 - middle layer; 180 - defect region; 190 - silicide Connecting layer; substrate-210; 220-gate structure; 221-gate dielectric layer; 222-gate conductor layer; 223-isolation structure; 223a-inner silicon nitride layer; 223b-middle silicon oxide layer; 223c-outer silicon nitride layer; 230-doped region; 240-initial blocking layer; 250-resist layer; 260-protective layer; 270-metal layer; 280-middle layer; 290-silicide connecting layer. DETAILED DESCRIPTION

[0048] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0049] This application may be presented in a variety of forms, some examples of which are described below.

[0050] The formation process of the silicide connection layer in the existing process includes: a barrier layer photolithography step, a barrier layer etching step, a metal ion implantation or deposition step, a first rapid thermal annealing step, a residual metal removal step, and a second rapid thermal annealing step.

[0051] Figure 2a to Figure 2f The figure shows the schematic diagram of each step in the formation process of the silicide connection layer in the existing process. Figure 2a to Figure 2f The formation process of the silicide connection layer in the existing process is described.

[0052] Figure 2aIn the embodiment, the semiconductor device includes a gate structure 120 disposed on a substrate 110 and a doped region 130 disposed in the substrate 110 and located on both sides of the gate structure 120. The material of the substrate 110 includes silicon, and the doped region 130 is formed by injecting an N-type dopant or a P-type dopant into the substrate 110. The N-type dopant includes, for example, phosphorus and arsenic, and the P-type dopant includes, for example, boron. The doped region 130 is often used as a source region or a drain region. The gate structure 120 includes a gate dielectric layer 121 and a gate conductor layer 122 arranged in a stacked manner, and an isolation structure 123 covering the sidewalls of the gate dielectric layer 121 and the sidewalls and surface of the gate conductor layer 122. The material of the gate dielectric layer 121 is silicon oxide, and the material of the gate conductor layer 122 is polycrystalline silicon. The isolation structure 123 may be a composite layer composed of silicon oxide and silicon nitride. The isolation structure 123 shown in the figure includes an inner silicon nitride layer 123a, an intermediate silicon oxide layer 123b, and an outer silicon nitride layer 123c.

[0053] for Figure 2a In the semiconductor device shown in FIG. 1 , a silicide connection layer is formed on the surface of the doped region 130, and an isolation structure 123 exists on the surface of the gate structure 120. Therefore, a barrier layer with openings on the isolation structure 123 and the doped region 130 can be formed on the substrate 110. Figure 2a The initial barrier layer 140 is shown and a resist layer 150 is formed on the initial barrier layer 140. Then, the initial barrier layer 140 is etched through a photolithography step and an etching step to form a barrier layer with openings on the isolation structure 123 and the doped region 130. The material of the initial barrier layer 140 is silicon oxide. It should be noted that in this example, Figure 2a Only a part of the structure on the substrate 110 is shown, and a barrier layer formed after the initial barrier layer 140 is etched covers a part of the structure on the substrate 110 that is not shown.

[0054] In the semiconductor process, the photolithography step and the etching step are independent of each other. Photoresist (PR) can be divided into positive resist and negative resist according to the reaction mode. The exposed part of the positive resist is removed during development to form an opening area, and the exposed part of the negative resist is retained during development to form a shielding area. The following is an example of using positive resist for the resist layer 150. The mask includes a light-shielding area and a light-transmitting area. During the photolithography process, the resist layer 150 is exposed through the mask, and the exposed part of the resist layer 150 is removed during development, thereby forming an opening area in the resist layer 150 corresponding to the light-transmitting area of ​​the mask. In the etching step, the exposed portion of the initial barrier layer 140 is removed through the opening area of ​​the resist layer 150, and due to the selectivity of the etchant, the etching stops at the surface of the isolation structure 123 and the doped region 130, so that the barrier layer formed corresponds to the light-transmitting area of ​​the mask and is opened on the isolation structure 123 and the doped region 130, and then the resist layer 150 is removed.

[0055] The above etching step can be performed by dry etching first and then wet etching. This is because dry etching is faster in the vertical downward direction. In order to avoid the initial barrier layer 140 on the isolation structure 123 surface and the doping region 130 surface (hereinafter also referred to as the first part) after being etched, the initial barrier layer 140 on the side wall of the isolation structure 123 (hereinafter also referred to as the second part) is still left, so the first part of the initial barrier layer 140 is first etched by dry etching and then the first part and the second part of the initial barrier layer 140 are etched by wet etching. After wet etching, the second part of the initial barrier layer 140 is completely etched away, and the first part of the initial barrier layer 140 still has a thickness of less than 10 angstroms. The remaining part of the first part of the initial barrier layer 140 can be etched away by performing a SiCoNi pre-cleaning process. It should be noted that the SiCoNi pre-cleaning process has a high selectivity, so it will not damage the silicon in the substrate 110, nor will it completely remove the isolation structure 123 and damage the gate conductor layer 122.

[0056] Figure 2c In the embodiment, a metal layer 160 is formed on the barrier layer and the substrate 110 in the area not blocked by the barrier layer, that is, a metal layer 160 covering the surface of the isolation structure 123, the surface of the doped region 130 and the surface of the barrier layer is formed. The metal layer 160 can be formed by physical vapor deposition (PVD). In some examples, an isolation layer (not shown in the figure) covering the metal layer 160 can be formed to prevent the metal layer 160 from being oxidized by contact with oxygen. The material of the metal layer 160 includes nickel. In some examples, the metal layer 160 is a nickel-platinum alloy layer, and the material of the isolation layer is titanium nitride.

[0057] Figure 2d In the process, the metal particles in the metal layer 160 react with the silicon in the substrate 110 by performing the first rapid thermal annealing step to generate the intermediate layer 170. The first rapid thermal annealing step is a low temperature annealing process, and the temperature of the low temperature annealing is, for example, 200°C-300°C, and the time of the low temperature annealing is, for example, 10s-20s. The material of the intermediate layer 170 generated by the first rapid thermal annealing step is a transition metal silicide generated by the reaction of the metal particles in the metal layer 160 and silicon. For example, when the metal particles are nickel, the transition metal silicide is Ni2Si.

[0058] Figure 2eIn the embodiment, the remaining portion of the metal layer 160 after the first rapid thermal annealing step is removed by performing a residual metal removal step. In the example where an isolation layer is present, the isolation layer is first removed and then the remaining portion of the metal layer 160 is removed. Specifically, an APM solution and an SPM solution are used to remove the isolation layer and the remaining portion of the metal layer 160, wherein the APM solution is a mixed solution composed of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and deionized water (H2O), and the formula is NH4OH:H2O2:H2O=1:1:5; the SPM solution is a mixed solution composed of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), and the formula is H2SO4:H2O2=4:1. Since the APM solution and the SPM solution contain hydrogen peroxide, when the remaining portion of the metal layer 160 is removed, the silicon in the intermediate layer 170 will also come into contact with the hydrogen peroxide and be oxidized to silicon oxide, so that there is Figure 2e The material shown is a defective region 180 of silicon oxide.

[0059] Figure 2f In the process, the intermediate layer 170 continues to react with the silicon in the substrate 110 by performing a second rapid thermal annealing step to generate a silicide connection layer 190. The second rapid thermal annealing step is a high temperature annealing process, and the temperature of the high temperature annealing is, for example, 480°C-550°C, and the time of the high temperature annealing is, for example, 25s-55s. The material of the silicide connection layer 190 generated by the second rapid thermal annealing step is a low-resistance metal silicide, that is, it has a lower resistance than the transition metal silicide, thereby reducing the contact resistance of the doped region 130. In the case where the metal particles in the metal layer 160 are nickel, the low-resistance metal silicide described here is NiSi.

[0060] After the silicide connection layer 190 is formed, an intermediate dielectric layer covering the defective region 180 and the barrier layer 140 is formed. Then, the intermediate dielectric layer is etched to form a connection hole and a metal material is filled in the connection hole to form a conductive plug. The function of the conductive plug is to connect the doped region 130 with the wiring on the surface of the intermediate dielectric layer. Therefore, the connection hole formed by etching the intermediate dielectric layer should expose the silicide connection layer 190. The material of the intermediate dielectric layer is silicon oxide. Therefore, in the process of etching the intermediate dielectric layer to form the connection hole, the defective region 180 will be removed, so that a groove appears on the surface of the silicide connection layer 190.

[0061] In the existing process described above, the formation of the defect area 180 in the residual metal removal step makes the finally formed silicide connection layer 190 thinner, which not only makes the formed silicide connection layer 190 unable to reduce the contact resistance well, thereby affecting the electrical properties of the semiconductor device and reducing the sensitivity of the semiconductor device; it also affects the reliability of the semiconductor device and makes the semiconductor device unable to work normally, thereby reducing the yield.

[0062] In view of this, an embodiment of the present application provides a method for forming a silicide connection layer, which improves the formation process of the silicide connection layer by adding a protective layer formation step and a removal step, so that metal silicide is not lost in the residual metal removal step.

[0063] Figure 3 FIG. 2 is a flow chart of a method for forming a silicide connection layer provided in an embodiment of the present application. Figure 3 As shown, the forming method includes:

[0064] Step S110, providing a semiconductor structure, wherein the material of the semiconductor structure includes silicon;

[0065] Step S120, forming a protective layer on the semiconductor structure and forming a metal layer on the protective layer;

[0066] Step S130, performing an annealing process to allow metal particles in the metal layer to pass through the protective layer and react with silicon in the semiconductor structure to form an intermediate layer;

[0067] Step S140, removing the remaining part of the metal layer while the protective layer protects the intermediate layer;

[0068] In step S150 , an annealing process is performed again to allow the intermediate layer to continue to react with silicon in the semiconductor structure to form a silicide connection layer, and the protective layer is removed.

[0069] It should be noted that the role of the protective layer is to protect the intermediate layer from being lost during the process of removing the remaining part of the metal layer. The protective layer can be removed after the remaining part of the metal layer is removed. Therefore, the removal of the protective layer in step S150 can be performed before or after the annealing process is performed again. The intermediate layer formed after the execution of step S130 is under the protective layer, and accordingly, the silicide connection layer formed after the execution of step S150 is also under the protective layer. Therefore, it is necessary to remove the protective layer to expose the silicide connection layer so that the silicide connection layer can be directly connected to the conductive plug later.

[0070] Figure 4a to Figure 4h Schematic diagram of various steps of forming a silicide connection layer on an exemplary semiconductor structure provided by an embodiment of the present application. The exemplary semiconductor structure is as follows Figure 4a The structure shown includes a gate structure 220 disposed on a substrate 210 and a doped region 230 disposed in the substrate 210 and located on both sides of the gate structure 220. The gate structure 220 includes a stacked gate dielectric layer 221 and a gate conductor layer 222 and an isolation structure 223 covering the sidewalls of the gate dielectric layer 221 and the sidewalls and surface of the gate conductor layer 222. The isolation structure 223 includes an inner silicon nitride layer 223a, an intermediate silicon oxide layer 223b and an outer silicon nitride layer 223c.

[0071] Combine the following Figure 3 as well as Figure 4a to Figure 4h The method for forming a silicide connection layer provided in an embodiment of the present application is described in detail.

[0072] The semiconductor structure provided in step S110 can be Figure 4a The gate structure 220 is shown as being disposed on a substrate 210 and a doped region 230 disposed in the substrate 210 and located on both sides of the gate structure 220. The gate structure 220 includes a gate dielectric layer 221 and a gate conductor layer 222 stacked and an isolation structure 223 covering the sidewalls of the gate dielectric layer 221 and the sidewalls and surface of the gate conductor layer 222. Figure 4a The semiconductor structure shown, the method for forming a silicide connection layer provided in the embodiment of the present application also includes: forming a barrier layer with openings on the isolation structure 223 and the doping region 230, the protective layer formed in step S120 covers the surface of the barrier layer and the surface of the doping region 230 and the surface of the isolation structure 223, so that the silicide connection layer is subsequently formed only on the surface of the doping region 230, which is not covered by the barrier layer 140 and where the isolation structure 223 does not exist.

[0073] The formation process of the barrier layer 240 is as follows: Figure 4a As shown, an initial barrier layer 240 is formed to cover the isolation structure 223 and the doped region 230, and a resist layer 250 is formed on the initial barrier layer 240. Then, a photolithography step and an etching step are performed through a mask including a light-shielding area and a light-transmitting area to etch away the portion of the initial barrier layer 240 on the isolation structure 223 and the doped region 230. The photolithography step and the etching step of the barrier layer formed with openings on the isolation structure 223 and the doped region 230 can refer to the above description of etching the barrier layer 140, which will not be repeated here.

[0074] The protective layer formed in step S120 may be formed by a physical vapor deposition process such as Figure 4c The protective layer 260 shown in FIG. 1 is a protective layer 260; the metal layer formed in step S120 can also be formed by a physical vapor deposition process such as Figure 4d Metal layer 270 is shown.

[0075] In some examples, before forming the protective layer 260 on the semiconductor structure, inert element particles may be injected into the semiconductor structure to break up the crystal lattice of the semiconductor structure, which makes it easier for the metal particles in the metal layer 270 to diffuse in the semiconductor structure during the execution of step S130, thereby compensating for the reduction in the diffusion depth of the metal particles in the semiconductor structure caused by the protective layer 260, and the inert element particles will not cause the material of the semiconductor structure to change. The inert element particles may be xenon (Xe) atoms, which have the advantage of large mass due to their large atomic number, and can better break up the crystal lattice of the semiconductor structure.

[0076] The material of the metal layer 270 formed above can be nickel, which can be achieved by depositing pure nickel on the protective layer 260. Nickel reacts with silicon to generate nickel silicide, and depositing pure nickel is conducive to reducing the resistance value of the silicide connection layer formed subsequently. Since nickel atoms are small in size and have high diffusivity, nickel atoms can easily diffuse through the protective layer 260 during the execution of step S130, so that the existence of the protective layer 260 can basically not affect the reaction between the metal particles in the metal layer 270 and the silicon in the semiconductor structure. In the case where inert element particles are injected into the semiconductor structure before the protective layer 260 is formed, nickel atoms can diffuse in the semiconductor structure without being affected by the protective layer 260.

[0077] Furthermore, the material of the protective layer 260 formed above can be hafnium silicate (HfSiO4) or hafnium dioxide. The protective layer 260 of hafnium silicate or hafnium dioxide not only protects the intermediate layer formed in step S130 from being lost during the execution of step S140, but also can reduce the interface energy of silicide, inhibit the agglomeration effect of nickel silicide, and delay the generation of byproduct NiSi2 in the silicide connection layer formed in step S150. In view of this, the protective layer 260 in step S150 is removed after the silicide connection layer is generated, so as to improve the thermal stability of the silicide connection layer.

[0078] The annealing process performed in step S130 is a low temperature annealing process, which is used for Figure 4e The intermediate layer 280 is generated as shown. When the material of the metal layer 270 is nickel, the material of the intermediate layer 280 is transition metal silicide Ni2Si. The conditions for low temperature annealing can refer to the above description of forming the intermediate layer 170, which will not be repeated here.

[0079] In the process of removing the remaining portion of the metal layer 270 in step S140, Figure 4f As shown, due to the existence of the protection layer 260 , the intermediate layer 280 below the protection layer 260 will not be damaged.

[0080] In some examples, after forming the metal layer 270 on the protective layer 260 in step S120, an isolation layer is also formed on the metal layer 270, and the above-mentioned removal of the remaining portion of the metal layer 270 is performed when the isolation layer is removed. When the material of the protective layer 260 is hafnium silicate or hafnium dioxide, the material of the isolation layer is titanium nitride, and the material of the metal layer 270 is nickel, a dry etching process can be used to remove the remaining portion of the metal layer 270 and the isolation layer, and the etching gas used is hydrogen bromide (HBr) gas or pure chlorine (Cl2), so the protective layer 260 made of hafnium silicate or hafnium dioxide will not be removed during the removal of the remaining portion of the metal layer 270, so that the protective layer 260 can well protect the intermediate layer 280 below. Here, the dry etching process is used to remove the remaining portion of the metal layer 270 and the isolation layer, which can remove the remaining portion of the metal layer 270 more quickly and more accurately.

[0081] The annealing process performed again in step S150 is a high temperature annealing process, which is used for Figure 4g The silicide connection layer 290 is generated as shown. When the material of the metal layer 270 is nickel, the material of the silicide connection layer 290 is low-resistance metal silicide NiSi. The conditions for high-temperature annealing can refer to the above description of forming the silicide connection layer 190, which will not be repeated here.

[0082] In step S150, when the material of the protective layer 260 is hafnium silicate or hafnium dioxide, a dry etching process such as Figure 4h As shown, the protective layer 260 is removed and the etching gas used includes boron trichloride (BCl3) gas and chlorine gas. It should be noted that pure chlorine gas will not react with hafnium silicate and hafnium dioxide, but when boron trichloride is mixed in chlorine gas, chlorine gas can react with hafnium silicate and hafnium dioxide. This is because boron trichloride can form an intermediate with oxygen atoms in hafnium silicate and hafnium dioxide, so that oxygen atoms in hafnium silicate and hafnium dioxide are more easily replaced by chlorine atoms in chlorine gas to form chloride. Since chlorine gas mixed with boron trichloride gas has a high selectivity for hafnium silicate or hafnium dioxide, the protective layer 260 using hafnium silicate or hafnium dioxide will not be damaged while completely removing the protective layer 260 using hafnium silicate or hafnium dioxide, thereby reducing the surface roughness of the silicide connection layer 290, reducing the sheet resistance corresponding to the silicide connection layer 290, enhancing the rectification characteristics of the semiconductor device, and being beneficial to improving the electrical properties of the semiconductor device.

[0083] Will Figure 4h and Figure 2fIn comparison, it can be seen that: compared with the existing process, the method for forming a silicide connection layer provided in the embodiment of the present application can form a silicide connection layer 290 with no thickness loss, thereby reducing the resistance of the semiconductor device and improving the reliability of the semiconductor device, thereby improving the operating speed and performance of the semiconductor device and improving the yield of the semiconductor device.

[0084] Will Figure 4a to Figure 4h The formation process of the silicide connection layer shown in FIG. Figure 2a to Figure 2f Compared with the formation process of the silicide connection layer shown in FIG. 1 , it can be seen that compared with the traditional process, the formation method of the silicide connection layer provided in the embodiment of the present application increases Figure 4c The steps of forming the protective layer 260 are shown in FIG. Figure 4h The removal step of the protection layer 260 shown in the figure does not involve the use of an additional photomask, and thus does not cause an increase in cost.

[0085] Corresponding to the method for forming a silicide connection layer provided in the above embodiments, another embodiment of the present application further provides a semiconductor device, which includes a silicide connection layer. The silicide connection layer is formed by any one of the methods for forming a silicide connection layer provided in the above embodiments, so that no grooves will exist on the surface due to thickness loss, thereby improving the operating speed and performance of the semiconductor device and improving the yield of the semiconductor device. Figure 4h The figure shows an exemplary semiconductor device provided in the embodiment of the present application, but it should be understood that Figure 4h It does not mean to limit the semiconductor device provided in the embodiments of the present application.

[0086] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A method for forming a silicide connection layer, comprising: A semiconductor structure is provided, wherein the material of the semiconductor structure includes silicon; forming a protective layer on the semiconductor structure and forming a metal layer on the protective layer; performing an annealing process so that metal particles in the metal layer pass through the protective layer and react with silicon in the semiconductor structure to form an intermediate layer; removing the remaining portion of the metal layer while the protective layer protects the intermediate layer; performing an annealing process again to allow the intermediate layer to continue to react with silicon in the semiconductor structure to form a silicide connection layer, and removing the protective layer; Wherein, the material of the metal layer is nickel, the material of the protective layer is hafnium silicate or hafnium dioxide, and the protective layer is removed after the silicide connection layer is formed.

2. The forming method according to claim 1, further comprising: After forming a metal layer on the protective layer, forming an isolation layer on the metal layer; And after forming the intermediate layer and before removing the remaining part of the metal layer, the isolation layer is removed.

3. The forming method according to claim 2, wherein: The isolation layer is made of titanium nitride, and removing the isolation layer and the remaining portion of the metal layer includes: removing the remaining portion of the metal layer and the isolation layer by a dry etching process, and using an etching gas of hydrogen bromide gas or pure chlorine gas.

4. The forming method according to claim 1, wherein: Removing the protective layer includes: removing the protective layer by a dry etching process, wherein the etching gases used are boron trichloride gas and chlorine gas.

5. The forming method according to claim 1, further comprising: Before forming a protection layer on the semiconductor structure, inert element particles are implanted into the semiconductor structure to break up the crystal lattice of the semiconductor structure.

6. The forming method according to claim 5, wherein: The inert element particles are xenon atoms.

7. The forming method according to claim 1, wherein: The semiconductor structure comprises a gate structure disposed on a substrate and doped regions disposed in the substrate and located on both sides of the gate structure, wherein the gate structure comprises a stacked gate dielectric layer and a gate conductor layer and an isolation structure covering the sidewalls of the gate dielectric layer and the sidewalls and surface of the gate conductor layer; The forming method further comprises: forming a barrier layer on the substrate, wherein the barrier layer has openings on the isolation structure and the doping region, and the protection layer covers the barrier layer and the surface of the doping region and the surface of the isolation structure.

8. A semiconductor device, comprising a silicide connection layer, wherein the silicide connection layer is formed by the formation method according to any one of claims 1 to 7.

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