Isolation structure of semiconductor element and manufacturing method thereof

Abstract

The invention discloses an isolation structure of a semiconductor element and a manufacturing method thereof. The isolation structure of the semiconductor element comprises a substrate, a first isolation structure and a second isolation structure. The substrate is provided with a first area and a second area, wherein a boundary is arranged between the first area and the second area. The first isolation structure is disposed in the first region of the substrate. The first isolation structure includes a dielectric liner and a first insulating layer. The second isolation structure is arranged in the second area of the substrate, the second isolation structure comprises a second insulating layer, and the first isolation structure and the second isolation structure are located on the two sides of the boundary respectively.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to an isolation structure of a semiconductor element and a manufacturing method thereof. Background Art

[0002] In advanced semiconductor technology, semiconductor components of different sizes can be manufactured on the same chip to reduce production costs, increase performance and reduce power consumption to meet the needs of various products.

[0003] For example, medium voltage components or high voltage components usually have larger sizes, while low voltage components have smaller sizes. However, when semiconductor components with different operating voltages and / or sizes are manufactured in different regions of the same chip, some problems may arise at the junctions of these regions. For example, the junctions of these regions may form a junction structure with a poor cross-sectional shape, which is easy to break and form contamination, or may cause tip discharge due to the presence of a sharp tip, causing leakage in the semiconductor component, or generate noise when the product is tested, interfering with the test results. Summary of the invention

[0004] An object of the present invention is to provide an isolation structure of a semiconductor element and a manufacturing method thereof to solve the above-mentioned problem.

[0005] According to one embodiment of the present invention, an isolation structure of a semiconductor element is provided, comprising a substrate, a first isolation structure and a second isolation structure. The substrate has a first region and a second region, wherein there is a junction between the first region and the second region. The first isolation structure is disposed in the first region of the substrate, wherein the first isolation structure comprises a dielectric liner and a first insulating layer. The second isolation structure is disposed in the second region of the substrate, wherein the second isolation structure comprises a second insulating layer, and the first isolation structure and the second isolation structure are respectively located on both sides of the junction.

[0006] According to another embodiment of the present invention, a method for manufacturing an isolation structure of a semiconductor element is provided, comprising the following steps: providing a substrate, wherein the substrate has a first region and a second region, and there is a junction between the first region and the second region; forming a first trench in the first region of the substrate; forming a dielectric lining in the first trench; forming a second trench in the second region of the substrate, wherein the first trench and the second trench are respectively located on both sides of the junction; and filling the first trench and the second trench with an insulating material to form a first insulating layer in the first trench and a second insulating layer in the second trench.

[0007] Compared to the prior art, the method of manufacturing an isolation structure of a semiconductor element of the present invention forms a dielectric lining in the first trench after forming a first trench in the first area and before forming a second trench in the second area, thereby improving the cross-sectional shape of the boundary structure between the first area and the second area, which is beneficial to reducing the probability of boundary structure fracture, tip discharge or noise generation during detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 It is a schematic diagram of the steps of manufacturing an isolation structure of a semiconductor element according to one embodiment of the present invention.

[0009] Explanation of symbols

[0010] 1: Isolation structure of semiconductor components

[0011] 10: Base

[0012] 10a: Top surface

[0013] 100: First Area

[0014] 110: First groove

[0015] 110a: side surface

[0016] 120: first isolation structure

[0017] 120a: side surface

[0018] 121: first insulating layer

[0019] 122: Dielectric lining

[0020] 124: Dielectric materials

[0021] 200: Second Area

[0022] 210: Second groove

[0023] 210a: side surface

[0024] 220: Fin structure

[0025] 230: Second isolation structure

[0026] 230a: side surface

[0027] 231: Second insulation layer

[0028] 310: first hard mask layer

[0029] 320: second hard mask layer

[0030] 330: Patterned mask layer

[0031] 331: Groove

[0032] 400: Junction structure

[0033] AA: Area

[0034] B: Junction

[0035] D1,D2: Depth

[0036] H1,H2: Height

[0037] S1,S2: Distance

[0038] W1,W2,W3,W4: Width

[0039] X,Y,Z: Direction DETAILED DESCRIPTION

[0040] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, back, bottom, top, etc., are only the directions with reference to the attached drawings. Therefore, the directional terms used are for illustration, not for limitation of the present invention. In addition, in the following embodiments, the same or similar elements will be marked with the same or similar numbers.

[0041] The description below regarding “a first feature is formed on or above a second feature” may refer to “the first feature is in direct contact with the second feature” or “there are other features between the first feature and the second feature” such that the first feature and the second feature are not in direct contact with each other.

[0042] The present invention uses the terms "first", "second", etc. to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish a certain element, region, layer, and / or section from another element, region, layer, and / or section, and they do not imply or represent any previous ordinal number of the element, nor do they represent the arrangement order of a certain element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, region, layer, and / or section discussed below may also be referred to as the second element, region, layer, and / or section. These terms in the claims may not be the same as those in the specification, but may be replaced by "first", "second", "third", etc. according to the order of the elements declared in the claims.

[0043] According to one embodiment of the present invention, a method for manufacturing an isolation structure of a semiconductor element is provided, comprising the following steps: providing a substrate, wherein the substrate has a first region and a second region, and there is a junction between the first region and the second region; forming a first trench in the first region of the substrate; forming a dielectric liner in the first trench; forming a second trench in the second region of the substrate, wherein the first trench and the second trench are respectively located on both sides of the junction; and filling the first trench and the second trench with an insulating material to form a first insulating layer in the first trench and a second insulating layer in the second trench.

[0044] Please refer to Figures 1 to 5 , which is a schematic diagram of the steps of manufacturing an isolation structure 1 of a semiconductor element according to an embodiment of the present invention, and is used to illustrate the aforementioned method of manufacturing the isolation structure of a semiconductor element. Figure 1 In the invention, a substrate 10 is provided, wherein the substrate 10 has a first region 100 and a second region 200, and a boundary B is provided between the first region 100 and the second region 200. The substrate 10 may be a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate or a silicon on insulator (SOI) substrate. The difference between the first region 100 and the second region 200 is that both regions may be provided with components having different operating voltages (not shown). The first region 100 may be, for example, a medium-high voltage component region, and the second region 200 may be, for example, a low-voltage component region. Generally speaking, taking a display chip as an example, the low-voltage component region includes, for example, a logic operation circuit, and its operating voltage is below 5 volts, and preferably within 1.5 volts. The operating voltage of the electronic components included in the medium-high voltage component region is greater than 5 volts, and is usually above 10 volts. For example, the driving components in the display chip require a higher voltage to drive the components therein, and these components belong to the medium-voltage components or high-voltage components of the present invention. In other words, the operating voltage of the first region 100 may be greater than the operating voltage of the second region 200 .

[0045] Next, a first hard mask layer 310 and a second hard mask layer 320 are sequentially formed on the substrate 10. The material of the first hard mask layer 310 may include an oxide such as silicon dioxide, and the material of the second hard mask layer 320 may include a nitride such as silicon nitride, but is not limited thereto. Next, a first trench 110 is formed in the first region 100 of the substrate 10. For example, the first hard mask layer 310 and the second hard mask layer 320 in the first region 100 may be patterned by photolithography, etching, or other manufacturing processes, and the first trench 110 is formed in the first region 100.

[0046] Then, if Figure 2As shown, the dielectric material 124 completely covers the substrate 10, wherein a portion of the dielectric material 124 is disposed on the second hard mask layer 320, and a portion of the dielectric material 124 is disposed in the first trench 110 as a dielectric liner 122. The dielectric material 124 may include oxide or nitride, and the oxide may be, for example, silicon dioxide, and the nitride may be, for example, silicon nitride, but is not limited thereto. In other words, the material of the dielectric liner 122 may include oxide or nitride.

[0047] Then, if Figure 3 As shown, a patterned mask layer 330 is formed on the substrate 10. The patterned mask layer 330 disposed on the second region 200 of the substrate 10 has a plurality of grooves 331. The material of the patterned mask layer 330 may include photoresist, oxide, nitride or a combination thereof, such as silicon dioxide, silicon nitride or silicon oxynitride. The method for forming the patterned mask layer 330 may include patterned transfer such as sidewall image transfer (SIT). Then, as Figure 4 As shown, the pattern of the patterned mask layer 330 can be transferred to the second region 200 of the substrate 10 by an etching process to form a plurality of second grooves 210 and a plurality of fin structures 220 in the second region 200 of the substrate 10, wherein the second grooves 210 surround the fin structures 220, the plurality of fin structures 220 are arranged at intervals along a first direction (e.g., direction X), and the fin structures 220 are extended along a second direction (e.g., direction Y) perpendicular to the first direction. Then, the patterned mask layer 330 can be removed. The aforementioned fin structures 220 are extended along the second direction, which means that the length of the fin structures 220 in the second direction is greater than the length of the fin structures 220 in the first direction.

[0048] like Figure 4 As shown, the first groove 110 and the second groove 210 are respectively located on both sides of the junction B. The inclination of the side surface 110a of the first groove 110 relative to the top surface 10a of the substrate 10 is smaller than the inclination of the side surface 210a of the second groove 210 relative to the top surface 10a of the substrate 10. Specifically, the top surface 10a of the substrate 10 extends along a horizontal direction (e.g., direction X), the side surface 110a of the first groove 110 has a first slope relative to the horizontal direction, and the side surface 210a of the second groove 210 has a second slope relative to the first direction, and the absolute value of the first slope is smaller than the absolute value of the second slope. The depth D1 of the first groove 110 is greater than the depth D2 of the second groove 210. The width W1 of the first groove 110 is greater than the width W2 of the second groove 210.

[0049] like Figure 4As shown, when the first groove 110 and the second groove 210 are completed, a junction structure 400 is defined between the first groove 110 and the second groove 210 directly adjacent to the junction B, and the junction structure 400 has a triangular cross-section, and the top of the junction structure 400 (not separately labeled) has a sharp shape, and the top surface of the junction structure 400 (not separately labeled) is aligned with the top surface of the portion other than the first groove 110 and the second groove 210 (not separately labeled). The left side surface of the junction structure 400 (i.e., the side surface 110a of the first groove 110) and the right side surface of the junction structure 400 (i.e., the side surface 210a of the second groove 210) are asymmetric and have different degrees of inclination. However, the present invention is not limited thereto. In other embodiments, the junction structure 400 may have a quadrilateral cross-section that is narrow at the top and wide at the bottom. According to an embodiment of the present invention, the distance S1 between the first trench 110 and the second trench 210 directly adjacent to the junction B (i.e., the width of the junction structure 400 (not separately labeled)) may be less than or equal to 50 nanometers (nm). In other words, the width of the junction structure 400 may be less than or equal to 50 nm. The present invention forms a dielectric liner 122 in the first trench 110 after forming the first trench 110 in the first region 100 and before forming the second trench 210 in the second region 200, so that the dielectric liner 122 is disposed on the left side surface of the junction structure 400 (i.e., the side surface 110a of the first trench 110), and the dielectric liner 122 is not disposed on the right side surface of the junction structure 400 (i.e., the side surface 210a of the second trench 210). The dielectric liner 122 can protect the interface structure 400 and improve the cross-sectional shape of the interface structure 400 , thereby reducing the possibility of contamination caused by the breakage of the interface structure 400 and reducing the probability of tip discharge or noise generated during detection of the interface structure 400 .

[0050] Then, if Figure 5 As shown, deposition, planarization and other manufacturing processes can be used to simultaneously fill the first trench 110 and the second trench 210 with insulating materials to form a first insulating layer 121 in the first trench 110 and a second insulating layer 231 in the second trench 210, and remove the dielectric material 124 located above the second hard mask layer 320. In this way, the manufacturing of the isolation structure 1 of the semiconductor element can be completed. The insulating material can include a dielectric material, such as an oxide, and the oxide can be, for example, silicon dioxide. In other words, the material of the first insulating layer 121 and the second insulating layer 231 can include a dielectric material, such as an oxide. The first insulating layer 121 and the second insulating layer 231 can be formed in the same step, that is, the material of the first insulating layer 121 and the material of the second insulating layer 231 can be the same. In addition, the insulating material can be different from the material of the dielectric liner 122.

[0051] The above-mentioned film layers, such as the first hard mask layer 310, the second hard mask layer 320, the dielectric material 124, the patterned mask layer 330, the first insulating layer 121 and the second insulating layer 231, can be formed by any suitable method, such as but not limited to molecular beam epitaxy (MBE), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), atomic layer deposition (ALD), etc.

[0052] Figure 5 A cross-sectional schematic diagram of an isolation structure 1 of a semiconductor device according to an embodiment of the present invention is shown, wherein the isolation structure 1 of the semiconductor device comprises a substrate 10, a first isolation structure 120, and a second isolation structure 230. The substrate 10 comprises a first region 100 and a second region 200, wherein a junction B is formed between the first region 100 and the second region 200. The first isolation structure 120 is disposed in the first region 100 of the substrate 10, wherein the first isolation structure 120 comprises a dielectric liner 122 and a first insulating layer 121. The second isolation structure 230 is disposed in the second region 200 of the substrate 10, wherein the second isolation structure 230 comprises a second insulating layer 231, and the first isolation structure 120 and the second isolation structure 230 are respectively located on both sides of the junction B. The isolation structure 1 of the semiconductor device may further comprise a fin structure 220 disposed in the second region 200, wherein the second isolation structure 230 surrounds the fin structure 220.

[0053] Figure 5 In the embodiment, there is a junction structure 400 between the first isolation structure 120 and the second isolation structure 230 directly adjacent to the junction B, and the top surface (not separately labeled) of the junction structure 400 is aligned with the top surfaces (not separately labeled) of the first isolation structure 120 and the second isolation structure 230. For details of the junction structure 400, please refer to the above and will not be repeated here. According to one embodiment of the present invention, the distance S2 between the first isolation structure 120 and the second isolation structure 230 directly adjacent to the junction B can be less than or equal to 50nm, and the distance S2 is equal to the distance S1 (see Figure 4 )equal.

[0054] Figure 5In the embodiment, the inclination degree of the side surface 120a of the first isolation structure 120 relative to the top surface 10a of the substrate 10 is smaller than the inclination degree of the side surface 230a of the second isolation structure 230 relative to the top surface 10a of the substrate 10. The inclination degree of the side surface 120a of the first isolation structure 120 is similar to the side surface 110a of the first trench 110 (see Figure 4 ), the inclination degree of the side surface 230a of the second isolation structure 230 is the same as the inclination degree of the side surface 210a of the second trench 210 (see Figure 4 ) have the same degree of inclination. The height H1 of the first isolation structure 120 is greater than the height H2 of the second isolation structure 230. The ratio of the height H1 to the height H2 may be 1.60 to 1.86, the height H1 may be 2400nm to 2600nm, the height H2 may be 1400nm to 1500nm, and according to one embodiment of the present invention, the height H1 may be 2500nm, and the height H2 may be 1450nm. The width W3 of the first isolation structure 120 is greater than the width W4 of the second isolation structure 230. The ratio of the width W3 to the width W4 may be 4 to 10, the width W3 may be 160nm to 200nm, and the width W4 may be 10nm to 40nm. According to one embodiment of the present invention, the width W3 may be 180nm, and the width W4 may be 20nm. Figure 5 In the figure, the top surface 10a of the substrate 10 can define a normal direction (e.g., direction Z), the first isolation structure 120 has different widths W3 in the normal direction, and the second isolation structure 230 has different widths W4 in the normal direction. The aforementioned ranges and values ​​refer to the largest of the different widths W3 and the largest of the different widths W4.

[0055] The first isolation structure 120 is used to define the setting area AA of the medium voltage component (not shown) or high voltage component (not shown) to be formed subsequently. Since the operating voltage of the medium voltage component and the high voltage component is higher, the first isolation structure 120 needs to be configured with a larger size (height H1 and width W3) to achieve a better isolation effect. The low voltage component (not shown) formed subsequently in the second area 200 has a lower operating voltage, so the size of the second isolation structure 230 is smaller than the size of the first isolation structure 120, and the density of the second isolation structure 230 is greater than the density of the first isolation structure 120. The left side surface (i.e., the side surface 110a of the left first trench 110) and the right side surface (i.e., the side surface 110a of the right first trench 110) of the region AA are substantially symmetrical and both are provided with a dielectric liner 122, while the left side surface (i.e., the side surface 110a of the right first trench 110) and the right side surface (i.e., the side surface 210a of the leftmost second trench 210) of the junction structure 400 are asymmetrical, and only the left side surface of the junction structure 400 is provided with a dielectric liner 122, and no dielectric liner 122 is provided on the right side surface of the junction structure 400. The left side surface and the right side surface (i.e., the side surfaces 210a of the left and right sides of the second trench 210) of the fin structure 220 are not provided with a dielectric liner 122 and directly contact the second insulating layer 231 of the second isolation structure 230.

[0056] In subsequent applications, the first hard mask layer 310, the second hard mask layer 320, a portion of the first isolation structure 120, and a portion of the second isolation structure 230 may be removed by a planarization process, so that the top surface (not separately labeled) of the first isolation structure 120, the top surface (not separately labeled) of the second isolation structure 230, and the top surface (not separately labeled) of the junction structure 400 are aligned with the top surface 10a of the substrate 10. In other words, compared to Figure 5 According to another embodiment of the semiconductor device isolation structure of the present invention, the first hard mask layer 310 and the second hard mask layer 320 may not be included.

[0057] Compared to the prior art, the method of manufacturing an isolation structure of a semiconductor element of the present invention forms a dielectric lining in the first trench after forming a first trench in the first area and before forming a second trench in the second area, thereby improving the cross-sectional shape of the boundary structure between the first area and the second area, which is beneficial to reducing the probability of boundary structure fracture, tip discharge or noise generation during detection.

[0058] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An isolation structure of a semiconductor element, comprising: A substrate having a first region and a second region, wherein the first region and the second region have a boundary therebetween; A first isolation structure disposed in the first region of the substrate, wherein the first isolation structure comprises a dielectric liner and a first insulating layer; and The second isolation structure is disposed in the second region of the substrate, wherein the second isolation structure includes a second insulating layer, and the first isolation structure and the second isolation structure are respectively located on two sides of the interface. 2 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein an inclination degree of a side surface of the first isolation structure relative to a top surface of the substrate is smaller than an inclination degree of a side surface of the second isolation structure relative to the top surface of the substrate. 3 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein a material of the dielectric liner comprises oxide or nitride. 4 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein a material of the dielectric liner is different from a material of the first insulating layer. 5 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein a material of the first insulating layer is the same as a material of the second insulating layer. 6 . The isolation structure of a semiconductor device as claimed in claim 5 , wherein a material of the first insulating layer comprises oxide. 7 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein a height of the first isolation structure is greater than a height of the second isolation structure. 8 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein a width of the first isolation structure is greater than a width of the second isolation structure. 9 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein a distance between the first isolation structure and the second isolation structure is less than or equal to 50 nanometers. 10 . The isolation structure of a semiconductor device as claimed in claim 1 , wherein an operating voltage of the first region is greater than an operating voltage of the second region.

11. The isolation structure of a semiconductor device as claimed in claim 1 , further comprising: The fin-shaped structure is disposed in the second region, wherein the second isolation structure surrounds the fin-shaped structure.

12. A method for manufacturing an isolation structure of a semiconductor device, comprising: Providing a substrate, wherein the substrate has a first region and a second region, and a boundary is formed between the first region and the second region; forming a first trench in the first region of the substrate; forming a dielectric liner in the first trench; forming a second trench in the second region of the substrate, wherein the first trench and the second trench are respectively located on two sides of the junction; as well as Insulating materials are filled into the first trench and the second trench to form a first insulating layer in the first trench and a second insulating layer in the second trench. 13 . The method of claim 12 , wherein an inclination degree of a side surface of the first trench relative to a top surface of the substrate is smaller than an inclination degree of a side surface of the second trench relative to the top surface of the substrate. The method of claim 12 , wherein a material of the dielectric liner comprises oxide or nitride.

15. The method of claim 12, wherein the dielectric liner is of a material different from the insulating material. The method of claim 12 , wherein the insulating material comprises an oxide. The method of claim 12 , wherein a depth of the first trench is greater than a depth of the second trench. The method of claim 12 , wherein a width of the first trench is greater than a width of the second trench.

19. The method of claim 12, wherein a distance between the first trench and the second trench is less than or equal to 50 nanometers.

20. The method of claim 12, wherein an operating voltage of the first region is greater than an operating voltage of the second region.

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