Semiconductor package structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor package structure and a preparation method thereof, comprising a substrate, a substrate-free redistribution layer and an isolation buffer layer, the substrate comprises an interconnection region and pads located in the periphery of the interconnection region; the substrate-free redistribution layer is embedded in the substrate and is used for electrically connecting at least two dies on the substrate, and the two dies are electrically connected to the substrate via corresponding pads; the isolation buffer layer is located between the outer wall of the substrate-free redistribution layer and the substrate, which can at least solve the problem of high-density interconnection of multi-chip, reduce the packaging cost, reduce the volume of the packaging structure, and improve the input / output bandwidth and power efficiency of the packaging structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor packaging technology, the number of chips in advanced packaging technology is constantly increasing. Generally, a silicon interposer is introduced to interconnect multiple chips.

[0003] However, Si interposers are expensive, and when applied to multi-chip interconnect packaging structures on organic substrates, they limit the input / output (I / O) bandwidth and power efficiency of the multi-chip interconnect packaging structures, making it difficult to meet the cost and performance requirements of high-density multi-chip interconnect packaging structures. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor packaging structure and its fabrication method, which can at least solve the problem of high-density interconnection of multiple chips, reduce packaging costs, reduce the volume of the packaging structure, and improve the input / output bandwidth and power efficiency of the packaging structure.

[0005] According to various embodiments of the present disclosure, one aspect provides a semiconductor packaging structure, including a substrate, a substrate-free redistribution layer, and an isolation buffer layer. The substrate includes an interconnect region and pads located around the interconnect region. The substrate-free redistribution layer is located within the interconnect region and is entirely embedded in the substrate, for electrically connecting at least two dies located on the substrate. The two dies are electrically connected to the substrate via corresponding pads. The isolation buffer layer is located between the outer wall of the substrate-free redistribution layer and the substrate.

[0006] In the semiconductor packaging structure described in the above embodiments, by embedding the entire substrate-free redistribution layer into the substrate, high-density interconnection between at least two dies is achieved directly using the multi-layer interconnection layers within the substrate-free redistribution layer. Compared to using Si interposers to achieve multi-chip interconnection, this effectively reduces packaging costs, decreases the volume of the packaging structure, increases chip interconnection density, and avoids an increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer. This effectively improves the input / output bandwidth and power efficiency of the packaging structure. By forming an isolation buffer layer between the outer wall of the substrate-free redistribution layer and the substrate, an airtight connection between the substrate-free redistribution layer and the substrate can be achieved, preventing external impurity particles or gases from entering the trench gaps and oxidizing or contaminating the dies. The isolation buffer layer can buffer the stress between the substrate-free redistribution layer and the substrate, preventing gaps and / or voids between the substrate-free redistribution layer and the substrate caused by thermal expansion and contraction.

[0007] In some embodiments, the top surface of the substrate-free redistribution layer is flush with the top surface of the substrate, avoiding the occurrence of poor soldering due to unevenness between the top surface of the substrate-free redistribution layer and the top surface of the substrate, which could cause die warping; and it also facilitates setting the conductive bumps of different dies to the same height, simplifying the conductive bump fabrication process.

[0008] In some embodiments, the redistribution layer includes an organic isolation layer and at least one interconnect layer for electrically connecting different dies; the interconnect layer is entirely embedded within the organic isolation layer. High-density interconnection between at least two dies is achieved directly using the multi-layer interconnect layers within the substrate-free redistribution layer, avoiding an increase in the semiconductor package size due to the introduction of the substrate-free redistribution layer.

[0009] In some embodiments, the redistribution layer further includes pads, which are correspondingly disposed with the interconnect layers. The pads are electrically connected to the corresponding interconnect layers. The top surfaces of the pads of the redistribution layer and the pads of the substrate are flush, which facilitates setting the conductive bumps of different dies to the same height, simplifies the conductive bump fabrication process, and can effectively avoid the phenomenon of cold solder joints caused by the warping of the dies due to the uneven bottom surfaces of the soldering of different dies.

[0010] In some embodiments, the coefficients of thermal expansion of the organic isolation layer, the isolation buffer layer, and the substrate are on the same order of magnitude, to avoid gaps between the organic isolation layer and the isolation buffer layer due to thermal expansion and contraction, which could lead to unstable die bonding.

[0011] In some embodiments, the semiconductor packaging structure further includes a molding layer that covers at least two dies and is located between different dies and between the dies and the substrate, thereby achieving hermetic encapsulation of the different dies and preventing external impurity particles or gases from entering the interior of the molding layer and oxidizing or contaminating the dies.

[0012] In some embodiments, the coefficients of thermal expansion of the molding layer and the isolation buffer layer are on the same order of magnitude to reduce the stress difference between the molding layer and the isolation buffer layer on the substrate or die; the coefficient of thermal expansion of the molding layer is smaller than that of the isolation buffer layer to reduce the stress of the molding layer on the die.

[0013] In some embodiments, the semiconductor packaging structure further includes an adhesive layer located between the bottom surface of the substrate-free redistribution layer and the substrate, to prevent the redistribution layer from moving and affecting the reliability and lifespan of the soldering; and to prevent the introduction of the adhesive layer from increasing the volume of the semiconductor packaging structure.

[0014] This disclosure also provides a method for manufacturing the semiconductor package structure described in the foregoing embodiments, comprising:

[0015] A substrate is provided, on which interconnect regions are included and pads are located on the periphery of the interconnect regions, and trenches are provided within the interconnect regions;

[0016] At least one substrate-free redistribution layer is fully embedded in the trench; the redistribution layer is used to electrically connect at least two dies located on the substrate, and the two dies are electrically connected to the substrate via corresponding pads.

[0017] An isolation buffer layer is formed, which is located between the outer wall of the substrate-free redistribution layer and the substrate.

[0018] In the semiconductor packaging structure fabrication method described in the above embodiments, by embedding the entire substrate-free redistribution layer into the trenches of the substrate interconnect region, high-density interconnection between at least two dies is achieved directly using the multilayer interconnect layers within the substrate-free redistribution layer. Compared to using Si interposers to achieve multi-chip interconnection, this effectively reduces packaging costs, increases chip interconnection density, and avoids an increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer. This effectively improves the input / output bandwidth and power efficiency of the packaging structure. By forming an isolation buffer layer between the outer wall of the substrate-free redistribution layer and the substrate, an airtight connection between the substrate-free redistribution layer and the substrate can be achieved, preventing external impurity particles or gases from entering the trench gaps and oxidizing or contaminating the dies. The isolation buffer layer can buffer the stress between the substrate-free redistribution layer and the substrate, preventing gaps and / or voids between the substrate-free redistribution layer and the substrate caused by thermal expansion and contraction.

[0019] In some embodiments, the method for fabricating a semiconductor package structure further includes the step of forming a substrate-free redistribution layer:

[0020] A substrate is provided, on which a sacrificial layer and an initial redistribution layer are sequentially formed, with the sacrificial layer located between the substrate and the initial redistribution layer;

[0021] The initial redistribution layer is cut along a direction perpendicular to the substrate to form at least one substrate-free redistribution layer.

[0022] In some embodiments, the method for fabricating a semiconductor package structure further includes the step of forming an initial redistribution layer:

[0023] A patterned mask layer is formed on the top surface of the sacrificial layer; the patterned mask layer has a groove defining at least one interconnect layer;

[0024] An interconnect layer is formed within the grooves of the patterned mask layer; the interconnect layer is used to electrically connect different dies.

[0025] Remove the patterned mask layer to form an organic isolation layer that covers the interconnect layer. The organic isolation layer and the interconnect layer are used together to form the initial redistribution layer.

[0026] In some embodiments, the redistribution layer is connected to the bottom surface of the trench via an adhesive layer; after the sacrificial layer and the initial redistribution layer are sequentially formed on the substrate, the method further includes:

[0027] An adhesive structure is formed on the top surface of the initial substrate-free redistribution layer. The adhesive structure includes a base frame and an adhesive material layer located between the base frame and the initial redistribution layer. The orthographic projection of the adhesive material layer on the top surface of the initial substrate-free redistribution layer at least completely covers the top surface of the initial substrate-free redistribution layer.

[0028] Remove the substrate and sacrificial layer;

[0029] During the process of cutting the initial redistribution layer, the adhesive structure is cut, and the adhesive material layer between the redistribution layer and the corresponding base frame is used to form the adhesive layer.

[0030] In some embodiments, after forming the isolation buffer layer, the method further includes:

[0031] A molding layer is formed, which covers at least two dies and is located between the different dies and between the dies and the substrate.

[0032] In some embodiments, before forming the isolation buffer layer and after forming the substrate-free redistribution layer, the method further includes:

[0033] At least two dies are bonded to the substrate and the redistribution layer, so that the dies are electrically connected to the corresponding pads on the substrate and the corresponding interconnects in the redistribution layer.

[0034] In some embodiments, the pads of the redistribution layer are flush with the top surface of the pads on the substrate; bonding at least two dies to both the substrate and the redistribution layer includes:

[0035] Form conductive bumps for bonding at least two bare dies, with the top surfaces of the conductive bumps flush;

[0036] At least two die input / output interfaces are bonded to corresponding conductive bumps. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 The diagram shows a cross-sectional view of the first semiconductor packaging structure provided in the related art.

[0039] Figure 2 The diagram shows a cross-sectional view of a second semiconductor packaging structure provided in the related art.

[0040] Figure 3The diagram shows a cross-sectional view of a third semiconductor packaging structure provided in the related technology.

[0041] Figure 4 The diagram shown is a cross-sectional view of a semiconductor packaging structure provided in this disclosure.

[0042] Figure 5 The diagram shown is a cross-sectional view of another semiconductor packaging structure provided in this disclosure.

[0043] Figure 6 The diagram shown is a flowchart illustrating a method for fabricating a semiconductor packaging structure provided in this disclosure.

[0044] Figure 7 The diagram shows a cross-sectional view of the structure obtained after forming a sacrificial layer and a mask layer on a substrate in a method for fabricating a semiconductor packaging structure provided in this disclosure.

[0045] Figure 8 Displayed as in Figure 7 A schematic cross-sectional view of the structure obtained after forming a patterned mask layer and an interconnect layer on the structure shown.

[0046] Figure 9 Displayed as in Figure 8 A schematic cross-sectional view of the structure obtained after removing the patterned mask layer and forming the organic isolation layer on the structure shown;

[0047] Figure 10 Displayed as in Figure 9 A schematic cross-sectional view of the structure obtained after forming an adhesive structure on the structure shown.

[0048] Figure 11 Displayed as in Figure 10 A schematic cross-sectional view of the structure obtained after removing the substrate and sacrificial layer from the structure shown.

[0049] Figure 12 Displayed as in Figure 11 A schematic diagram of the cross-section of the structure obtained after cutting the initial redistribution layer and adhesive material layer on the structure shown.

[0050] Figure 13 Displayed as based on Figure 12 The diagram shows a cross-sectional view of the structure obtained after obtaining the substrate-free redistribution layer from the structure shown.

[0051] Figure 14 The diagram shows a cross-sectional view of the structure obtained after all the substrate-free redistribution layers are embedded in the substrate trenches.

[0052] Figure 15 Displayed as in Figure 14 A schematic cross-sectional view of the structure obtained after forming an isolation buffer layer and a molding layer on the structure shown.

[0053] Explanation of reference numerals in the attached figures:

[0054] 100. Substrate; 10. First die; 20. Second die; 12. Conductor; 30. Silicon interposer; 40. Silicon bridge; 101. Substrate-free redistribution layer; 102. Isolation buffer layer; 1011. Organic isolation layer; 1012. Interconnect layer; 1013 / 1013'. Pad; 103. Molding layer; 104. Adhesive layer; 202. Mask layer; 203. Patterned mask layer; 101'. Initial redistribution layer; 300. Adhesive structure; 301. Frame; 302. Adhesive material layer; 105. Substrate; 106. Sacrificial layer; 107. Trench; 108. Conductive bump. Detailed Implementation

[0055] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0057] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0058] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0061] For example, please refer to Figure 1 After the first die 10 and the second die 20 to be packaged are soldered to corresponding positions on the top surface of the substrate 100, the first die 10 and the second die 20 are interconnected via wires 12 inside the substrate 100. For semiconductor packaging manufacturers, the substrate 100 is generally purchased directly, and they do not have the ability to form multiple wires 12 for connecting the first die 10 and the second die 20 within the substrate 100. Furthermore, the multi-chip high-density interconnect packaging structure has high requirements for the number of wires 12 and the complexity of wiring within the substrate 100, which increases the complexity and cost of the packaging process and makes it difficult to meet the cost and performance requirements of the multi-chip high-density interconnect packaging structure.

[0062] For example, please refer to Figure 2The silicon interposer 30 is a silicon substrate that serves as a conduit for transmitting electrical signals between multi-chip modules in advanced packaging. It enables interconnection between chips and with the packaging substrate, acting as a bridge between multiple dies, such as the first die 10 and the second die 20, and between the first die 10, the second die 20, and the substrate 100. While the silicon interposer 30 offers high fine-pitch wiring capabilities and reliable TSV (Through Silicon Via) technology, for high-density multi-chip interconnect packaging structures, it undoubtedly increases the size and cost of the interconnect packaging structure.

[0063] For example, please refer to Figure 3 In order to further reduce the size of the multi-chip interconnect package structure, a silicon bridge 40 embedded in the substrate 100 is used as a connection bridge between multiple dies, such as the first die 10 and the second die 20, and between the first die 10, the second die 20 and the substrate 100. However, the silicon bridge 40 cannot meet the wiring density requirements of the multi-chip high-density interconnect package structure, which limits the input / output bandwidth and power efficiency of the multi-chip interconnect package structure.

[0064] Based on the above-mentioned technical problems, this disclosure provides a semiconductor packaging structure and its fabrication method, which can at least solve the problem of high-density interconnection of multiple chips, reduce packaging costs, reduce the volume of the packaging structure, and improve the input / output bandwidth and power efficiency of the packaging structure.

[0065] For example, please refer to Figure 4 or Figure 5 A semiconductor package structure includes a substrate 100, a substrate-free redistribution layer 101, and an isolation buffer layer 102. The substrate 100 includes an interconnect region and pads 1013' located around the interconnect region. The substrate-free redistribution layer 101 is located within the interconnect region and is completely embedded in the substrate 100. It is used to electrically connect at least two dies located on the substrate 100. The two dies are electrically connected to the substrate 100 via corresponding pads 1013. The isolation buffer layer 102 is located between the outer wall of the substrate-free redistribution layer and the substrate 100.

[0066] As an example, please continue reading Figure 4 or Figure 5By embedding the entire substrate-free redistribution layer 101 into the substrate 100, high-density interconnections between at least two dies, such as the first die 10 and the second die 20, and between the first die 10, the second die 20, and the substrate 100 are achieved directly using the multilayer wiring layers within the substrate-free redistribution layer 101. This is a significant improvement over traditional methods using silicon substrates (Si). Interposer enables multi-chip interconnection, effectively reducing packaging costs, increasing chip interconnection density, and avoiding an increase in semiconductor package size due to the introduction of substrate-free redistribution layer 101. This effectively improves the input / output bandwidth and power efficiency of the package structure. By forming an isolation buffer layer 102 between the outer wall of substrate-free redistribution layer 101 and substrate 100, hermetic connection between substrate-free redistribution layer and substrate 100 can be achieved, preventing external impurities or gases from entering the trench gaps and oxidizing or contaminating the die. The isolation buffer layer 102 can buffer the stress between substrate-free redistribution layer 101 and substrate 100, preventing gaps and / or voids between substrate-free redistribution layer 101 and substrate 100 caused by thermal expansion and contraction.

[0067] As an example, please continue reading Figure 4 or Figure 5 The top surface of the substrate-free redistribution layer 101 is flush with the top surface of the substrate 100, which avoids the problem of bare die warping and poor soldering caused by unevenness between the top surface of the substrate-free redistribution layer and the top surface of the substrate 100. It also makes it easier to set the conductive bumps of different bare dies to be of equal height, simplifying the process of conductive bump preparation and reducing production costs.

[0068] As an example, please continue reading Figure 4 or Figure 5 An isolation buffer layer 102 can be provided to surround the outer wall of the substrate-free redistribution layer 101 in a circumferential direction, thereby reducing the mechanical coupling effect and thermal expansion coefficient (CTE) mismatch between the isolation buffer layer 102 and the substrate 100, thereby reducing stress concentration or cracking in certain areas of the package and improving the reliability of the package structure.

[0069] As an example, please continue reading Figure 4 or Figure 5 The substrate-free redistribution layer 101 includes an organic isolation layer 1011 and at least one interconnect layer 1012 for electrically connecting different dies, such as a first die 10 and a second die 20; the interconnect layer 1012 is entirely embedded within the organic isolation layer 1011. High-density interconnection between the first die 10 and the second die 20 is achieved directly using the multiple interconnect layers 1012 within the substrate-free redistribution layer 101, and the increase in semiconductor package size due to the introduction of the substrate-free redistribution layer 101 is avoided.

[0070] For example, please refer to Figure 5 The substrate-free redistribution layer 101 also includes pads 1013, which are correspondingly disposed with the interconnect layer 1012. The pads 1013 are electrically connected to the corresponding interconnect layer 1012. The top surfaces of the pads 1013 of the substrate-free redistribution layer 101 and the pads 1013' of the substrate 100 are flush, which facilitates setting the conductive bumps of different dies to the same height, simplifies the fabrication process of the conductive bumps, and reduces production costs. It can also effectively avoid the phenomenon of poor soldering caused by the uneven soldering bottom surfaces of different dies, which leads to die warping.

[0071] As an example, please continue reading Figure 4 or Figure 5 The substrate 100 is made of conventional PCB materials, often resin materials such as phenolic resin, epoxy resin, and polyester resin. Both the organic isolation layer 1011 and the isolation buffer layer 102 can be made of resin materials. Polyimide has gained widespread attention and application due to its unique comprehensive properties, including high temperature resistance, oxidation resistance, radiation resistance, corrosion resistance, damp heat resistance, high strength, and high modulus. Therefore, both the organic isolation layer 1011 and the isolation buffer layer 102 can be made of polyimide. Polyimide has an extremely low coefficient of thermal expansion, which is 2 × 10⁻⁶. -5 / ℃-3×10 -5 At / ℃, the coefficient of thermal expansion of thermoplastic polyimide is 3×10⁻⁶. -5 / ℃. The organic isolation layer 1011, the isolation buffer layer 102, and the substrate 100 are all made of resin. By setting the coefficients of thermal expansion of the organic isolation layer 1011, the isolation buffer layer 102, and the substrate 100 to be on the same order of magnitude, it is possible to avoid gaps between the organic isolation layer 1011 and the isolation buffer layer 102 due to thermal expansion and contraction, which would lead to unstable die bonding. It is also possible to make the stress of the organic isolation layer 1011, the isolation buffer layer 102, and the substrate 100 on the first die 10 and the second die 20 balanced, so as to avoid the performance and lifespan of the first die 10 and the second die 20 being reduced due to stress imbalance.

[0072] Furthermore, existing technologies use silicon interposers, while silicon's coefficient of thermal expansion is approximately 2.4 × 10⁻⁶ K between 300 K and 2500 K. -6 K -1 The silicon interposer and the substrate are made of significantly different materials, namely, a large difference in their coefficients of thermal expansion. This makes them prone to delamination under hot and cold environments, which can affect the performance of the packaging.

[0073] As an example, please continue reading Figure 4 or Figure 5The semiconductor packaging structure also includes a molding layer 103, which covers at least two dies, such as a first die 10 and a second die 20, and is located between the first die 10 and the second die 20, and between the first die 10, the second die 20 and the substrate 100, to achieve hermetic packaging of different dies and prevent external impurity particles or gases from entering the interior of the molding layer 103 and oxidizing or contaminating the dies.

[0074] As an example, please continue reading Figure 4 or Figure 5 The molding layer 103 and the isolation buffer layer 102 have thermal expansion coefficients on the same order of magnitude to reduce the stress difference between the molding layer 103 and the isolation buffer layer 102 on the first die 10 and the second die 20. The thermal expansion coefficient of the molding layer 103 can be set to be smaller than that of the isolation buffer layer 102. For example, the thermal expansion coefficient of the molding layer 103 can be set to be similar to that of the first die 10 and the second die 20 to reduce the stress exerted by the molding layer 103 on the first die 10 and the second die 20. The stress can be tensile stress or compressive stress. For example, if the volume of the molding layer 103 decreases due to a decrease in temperature, it will generate compressive stress on the first die 10 and the second die 20; conversely, if the volume of the molding layer 103 increases due to an increase in temperature, it will generate tensile stress on the first die 10 and the second die 20. By setting the coefficient of thermal expansion of the molding layer 103 to be similar to that of the first die 10 and the second die 20, the temperature change-volume change of the molding layer 103 and the first die 10 and the second die 20 are similar, thereby reducing the tensile or compressive stress of the molding layer 103 on the first die 10 and the second die 20, so as to improve the performance and reliability of the multi-chip interconnect package structure.

[0075] As an example, please continue reading Figure 4 or Figure 5 The semiconductor packaging structure also includes an adhesive layer 104, which is located between the bottom surface of the substrate-free redistribution layer 101 and the substrate 100. This adhesive layer 104 prevents the substrate-free redistribution layer 101 from shifting, thus affecting the reliability and lifespan of the soldering process. Furthermore, it prevents an increase in the volume of the semiconductor packaging structure due to the introduction of the adhesive layer 104. The adhesive layer 104 can be an ultra-thin film adhesive, achieving a stable connection between the substrate-free redistribution layer 101 and the substrate 100 while facilitating the stacking and thinning of the semiconductor packaging structure. Additionally, by adjusting the thickness of the adhesive layer 104, the embedding depth of the substrate-free redistribution layer 101 in the interconnect region can be adjusted, thereby making the top surface of the substrate-free redistribution layer 101 flush with the top surface of the substrate 100.

[0076] For example, please refer to Figure 6 A method for fabricating a semiconductor packaging structure includes the following steps:

[0077] Step S2: Provide a substrate, which includes interconnect regions and pads located around the interconnect regions, and the interconnect regions have trenches;

[0078] Step S4: Embed at least one substrate-free redistribution layer entirely into the trench; the redistribution layer is used to electrically connect at least two bare dies located on the substrate, and the two bare dies are electrically connected to the substrate via corresponding pads;

[0079] Step S6: Form an isolation buffer layer, which is located between the outer wall of the substrate-free redistribution layer and the substrate.

[0080] As an example, please continue reading Figure 6 By embedding the entire substrate-free redistribution layer into the trenches of the substrate interconnect region, high-density interconnection between at least two dies can be achieved directly using the multi-layer interconnection layers within the substrate-free redistribution layer. Compared to using Si interposers for multi-chip interconnection, this effectively reduces packaging costs, increases chip interconnection density, and avoids an increase in semiconductor package size due to the introduction of the substrate-free redistribution layer. This effectively improves the input / output bandwidth and power efficiency of the package structure. By forming an isolation buffer layer between the outer wall of the substrate-free redistribution layer and the substrate, a hermetically tight connection between the substrate-free redistribution layer and the substrate can be achieved, preventing external impurities or gases from entering the trench gaps and oxidizing or contaminating the dies. The isolation buffer layer can also buffer the stress between the substrate-free redistribution layer and the substrate, preventing gaps and / or voids between the substrate-free redistribution layer and the substrate caused by thermal expansion and contraction.

[0081] For example, please refer to Figure 6 The substrate 100 serves as a packaging substrate, on which various device elements (not shown) may be formed. Examples of device elements formed in or on the packaging substrate may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), etc.), diodes, resistors, capacitors, inductors, and / or other suitable device elements. Various processes may be performed to form the device elements, such as deposition, etching, implantation, photolithography, annealing, and / or other suitable processes. The packaging substrate may also have one or more circuit layers (not shown) for electrically connecting the device elements and subsequently attached semiconductor devices.

[0082] As an example, the method for fabricating a semiconductor package structure further includes the step of forming a substrate-free redistribution layer:

[0083] Step S31: A sacrificial layer and an initial redistribution layer are sequentially formed on the substrate, with the sacrificial layer located between the substrate and the initial redistribution layer;

[0084] Step S33: Cut the initial redistribution layer along a direction perpendicular to the substrate to form at least one substrate-free redistribution layer.

[0085] For example, please refer to Figures 7-9 Step S31 also includes the following step of forming the initial redistribution layer 101':

[0086] Step S311: A sacrificial layer 106 is formed on the top surface of the substrate 105;

[0087] Step S312: A patterned mask layer 203 is formed on the top surface of the sacrificial layer 106; the patterned mask layer 203 has a groove defining at least one interconnect layer 1012;

[0088] Step S313: An interconnect layer 1012 is formed in the groove of the patterned mask layer 203. The interconnect layer 1012 is used to electrically connect different dies.

[0089] Step S314: Remove the patterned mask layer 203 to form an organic isolation layer 1011 covering the interconnect layer 1012. The organic isolation layer 1011 and the interconnect layer 1012 are used to jointly constitute the initial redistribution layer 101'.

[0090] As an example, please continue reading Figures 7-9In step S311, the substrate 105 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. In step S312, a sacrificial layer 106 and a mask layer 202 can be sequentially stacked on the top surface of the substrate 105 using a deposition process. The material of the sacrificial layer 106 can be, but is not limited to, silicon oxide and / or silicon oxynitride. The sacrificial layer 106 facilitates the bonding and separation of the substrate 105 and the interconnect layer 1012, simplifying the fabrication process and reducing production costs. A photoresist material layer is coated on the top surface of the mask layer 202. After a series of steps such as exposure, development, photolithography, and etching, a patterned mask layer 203 is obtained. The patterned mask layer 203 has a groove (not shown) defining at least one interconnect layer 1012. The groove can extend along the thickness direction of the sacrificial substrate 200 and have at least one branch extending in a first direction parallel to the top surface of the sacrificial substrate 200. The groove can also have at least one branch extending in a second direction parallel to the top surface of the sacrificial substrate 200. The first direction and the second direction intersect. The deposition process may include, but is not limited to, at least one of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0091] It should be noted that, Figure 8 The grooves for forming interconnect layers 1012, as exemplarily provided, can be the final shape obtained after multiple pattern transfers. The number of pattern transfers depends on the number and / or quantity of interconnect layers 1012 to be formed, which is related to the density of multi-chip interconnects.

[0092] As an example, please continue reading Figure 8 In step S313, an interconnect layer 1012 can be formed in the groove of the patterned mask layer 203 using a deposition process. The interconnect layer 1012 can extend along the thickness direction of the sacrificial substrate 200 and have at least one branch extending in a first direction parallel to the top surface of the sacrificial substrate 200. The interconnect layer 1012 can also have at least one branch extending in a second direction parallel to the top surface of the sacrificial substrate 200. The material of the interconnect layer 1012 can be selected from copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy.

[0093] For example, please refer to Figure 9In step S314, a wet etching process can be used to remove the patterned mask layer 203; an organic isolation layer 1011 covering the interconnect layer 1012 can be formed using a vacuum forming process. The organic isolation layer 1011 and the interconnect layer 1012 are used together to form the initial redistribution layer 101'. The bottom portion of the interconnect layer 1012 can serve as a pad 1013'.

[0094] For example, please refer to Figures 10-11 The substrate-free redistribution layer 101 is connected to the bottom surface of the trench of the substrate via the adhesive layer 104; after the initial redistribution layer 101' is formed in step S31, and before the initial redistribution layer 101' is cut in a direction perpendicular to the substrate 105 in step S33, the method further includes:

[0095] Step S321: An adhesive structure 300 is formed on the top surface of the initial redistribution layer 101'. The adhesive structure 300 includes a base frame 301 and an adhesive material layer 302 located between the base frame 301 and the initial redistribution layer 101'. The orthographic projection of the adhesive material layer 302 on the top surface of the initial redistribution layer 101' at least completely covers the top surface of the initial redistribution layer 101'.

[0096] Step S322: Remove substrate 105 and sacrificial layer 106.

[0097] As an example, please continue reading Figures 10-11 In step S321, the top surface of the initial redistribution layer 101' is bonded to the substrate 301 using the adhesive material layer 302 to support subsequent cutting of the initial redistribution layer 101'. The adhesive material layer 302 is cut during the cutting of the initial redistribution layer 101', which can reduce the manufacturing process and reduce production costs. In step S322, the adhesive structure 300 can be flipped to the underside of the initial redistribution layer 101', and the substrate 105 and sacrificial layer 106 can be removed using etching and / or chemical mechanical polishing processes to expose the bottom surface of the pads 1013' inside the initial redistribution layer 101'.

[0098] For example, please refer to Figures 12-13 In step S33, during the cutting of the initial redistribution layer 101', the bonding structure 300 is cut, and the adhesive material layer 302 between the substrate-free redistribution layer 101 and the corresponding substrate 301 is used to form the bonding layer 104. The bonding layer 104 can be an ultra-thin film adhesive, which realizes a stable connection between the substrate-free redistribution layer 101 and the substrate 100, while facilitating the stacking and thinning of the semiconductor packaging structure.

[0099] For example, please refer to Figure 14At least one substrate-free redistribution layer 101 is fully embedded in the center of the trench 107. The substrate-free redistribution layer 101 is used to electrically connect at least two dies located on the substrate 100, and the two dies are electrically connected to the substrate 100 via corresponding pads 1013. For example, the first die 10 and the second die 20 are all bonded to the substrate 100 and the substrate-free redistribution layer 101, so that the first die 10 and the second die 20 are electrically connected to the corresponding pads 1013 on the substrate 100 and the corresponding interconnect layers 1012 in the substrate-free redistribution layer 101. High-density interconnection between the first die 10 and the second die 20 is achieved directly using the multilayer interconnect layers 1012 in the substrate-free redistribution layer 101, and the increase in the size of the semiconductor package structure due to the introduction of the substrate-free redistribution layer 101 is avoided.

[0100] For example, please refer to Figure 15 An isolation buffer layer 102 can be formed within the gaps of the trench 107. The isolation buffer layer 102 is located between the outer wall of the substrate-free redistribution layer 101 and the substrate 100, and can buffer the stress between the substrate-free redistribution layer 101 and the substrate 100, preventing gaps and / or voids from appearing between the substrate-free redistribution layer 101 and the substrate 100 due to thermal expansion and contraction. The isolation buffer layer 102 may include epoxy resin, resin, filler material, stress release agent (SRA), adhesion promoter, other suitable materials, or combinations thereof.

[0101] For example, please refer to Figure 15 The isolation buffer layer 102 in the trench 107 can circumferentially surround the outer wall of the substrate-free redistribution layer 101, reducing the mechanical coupling effect and thermal expansion coefficient (CTE) mismatch between the isolation buffer layer 102 and the substrate 100, thereby reducing stress concentration or cracking in certain areas of the package and improving the reliability of the package structure.

[0102] For example, please refer to Figure 15 The organic isolation layer 1011, the isolation buffer layer 102, and the substrate 100 can be configured to have thermal expansion coefficients on the same order of magnitude. This can prevent gaps from forming between the organic isolation layer 1011 and the isolation buffer layer 102 due to thermal expansion and contraction, which could lead to unstable die bonding. It can also ensure that the organic isolation layer 1011, the isolation buffer layer 102, and the substrate 100 exert stress evenly on the first die 10 and the second die 20, thus preventing stress imbalance from reducing the performance and lifespan of the first die 10 and the second die 20.

[0103] As an example, please continue reading Figure 15A molding layer 103 can be formed using a molding process. The molding layer 103 covers the outer surfaces of the first die 10 and the second die 20 and is located between the first die 10 and the second die 20, as well as between the first die 10, the second die 20 and the substrate 100, to achieve hermetic encapsulation of different dies and prevent external impurities or gases from entering the interior of the molding layer 103 and oxidizing or contaminating the dies.

[0104] As an example, please continue reading Figure 15 The thermal expansion coefficient of the molding layer 103 can be set to be similar to that of the first die 10 and the second die 20, so that the temperature change-volume change of the molding layer 103 and the first die 10 and the second die 20 are similar, thereby reducing the tensile or compressive stress of the molding layer 103 on the first die 10 and the second die 20, so as to improve the performance and reliability of the multi-chip interconnect package structure.

[0105] As an example, please continue reading Figure 15 The first die 10 and the second die 20 can be integrated circuit (IC) chips or dies, which may include a semiconductor substrate having multiple semiconductor devices (e.g., transistors, diodes, passive devices, etc.) thereon to form a functional integrated circuit. The functional integrated circuit may include processors, logic circuits, memory devices, analog circuits, digital circuits, mixed-signal circuits, etc. The top surface of the substrate 100 (the upper surface shown) can be used to receive and bond other packaged components. Multiple electrical connectors (not shown) may be disposed on the top surface of the substrate 100, enabling the first die 10 and the second die 20 to achieve electrical connection with an external electronic device, such as a printed circuit board (not shown).

[0106] As an example, please continue reading Figure 15 At least one of the first die 10 and the second die 20 can be a system-on-a-chip (SoC) or system-on-integrated circuit (SoIC) device or package, comprising two or more chips / dies with integrated functionality. Each first die 10 or second die 20 can be obtained, for example, by dicing a semiconductor wafer (on which several integrated circuit dies are formed) along a dicing track, dividing the semiconductor wafer into multiple individual semiconductor dies. As an example, please refer to [further details omitted]. Figure 15The molding layer 103 and the isolation buffer layer 102 have thermal expansion coefficients on the same order of magnitude to reduce the stress difference between the molding layer 103 and the isolation buffer layer 102 on the first die 10 and the second die 20. The thermal expansion coefficient of the molding layer 103 can be set to be smaller than that of the isolation buffer layer 102; for example, the thermal expansion coefficient of the molding layer 103 can be set to be similar to that of the first die 10 and the second die 20 to reduce the stress exerted by the molding layer 103 on the first die 10 and the second die 20. The stress can be tensile stress or compressive stress.

[0107] As an example, please continue reading Figure 15 The pads 1013' of the substrate-free redistribution layer 101 are flush with the top surface of the pads 1013 of the substrate 100. After at least one substrate-free redistribution layer 101 is fully embedded in the trench 107, at least two dies can be bonded to the substrate 100 and the redistribution layer. For example, conductive bumps 108 can be formed for bonding at least two dies, with the top surfaces of the conductive bumps 108 being flush. Then, the input / output interfaces of at least two dies are bonded to the corresponding conductive bumps 108 to simplify the bonding process and reduce production costs. This also effectively avoids the phenomenon of cold solder joints caused by die warping due to uneven soldering bottom surfaces of different dies. The conductive bumps 108 can be or include solder balls, such as tin-containing solder balls. The material of the conductive bump 108 may include copper, aluminum, gold, nickel, silver, palladium, or combinations thereof. The conductive bump 108 may be formed using at least one of the following processes: electroplating, electroless plating, placement, printing, physical vapor deposition (PVD), chemical vapor deposition (CVD), and photolithography.

[0108] In the semiconductor packaging structure fabrication method described in the above embodiments, by embedding the entire substrate-free redistribution layer 101 into the trenches of the interconnect region of the substrate 100, high-density interconnection between at least two dies is achieved directly using the multilayer interconnect layers 1012 within the substrate-free redistribution layer 101. Compared to using Si interposers to achieve multi-chip interconnection, this effectively reduces packaging costs, increases chip interconnection density, and avoids an increase in the volume of the semiconductor packaging structure due to the introduction of the substrate-free redistribution layer 101, thereby effectively improving the input / output bandwidth and power efficiency of the packaging structure. By forming an isolation buffer layer 102 between the outer wall of the substrate-free redistribution layer and the substrate 100, an airtight connection between the substrate-free redistribution layer and the substrate 100 can be achieved, preventing external impurity particles or gases from entering the trench gaps and oxidizing or contaminating the dies. The isolation buffer layer 102 can buffer the stress between the substrate-free redistribution layer 101 and the substrate 100, preventing gaps and / or voids between the substrate-free redistribution layer 101 and the substrate 100 caused by thermal expansion and contraction.

[0109] It should be understood that although the steps in the flowcharts shown in the accompanying figures are displayed sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, although at least some steps in the flowchart may include multiple steps or stages, these steps or stages are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0110] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above embodiments merely illustrate several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A semiconductor package structure, comprising: a substrate having an interconnection region and pads located at the periphery of the interconnection region; a substrateless redistribution layer embedded in the substrate and located in the interconnection region for electrically connecting at least two dies on the substrate, the two dies being electrically connected to the substrate via corresponding pads, respectively; an isolation buffer layer located between the outer sidewall of the substrateless redistribution layer and the substrate; and a molding layer covering the at least two dies and located between different dies and between the dies and the substrate; wherein the top surface of the substrateless redistribution layer is flush with the top surface of the substrate; the molding layer and the isolation buffer layer have thermal expansion coefficients in the same order of magnitude, and the thermal expansion coefficient of the molding layer is smaller than that of the isolation buffer layer. 2.The semiconductor package structure of claim 1, wherein the substrateless redistribution layer comprises an organic isolation layer and at least one interconnection layer for electrically connecting different dies; and the interconnection layer is embedded in the organic isolation layer. 3.The semiconductor package structure of claim 2, wherein the substrateless redistribution layer further comprises pads corresponding to the interconnection layer; and the pads are electrically connected to the corresponding interconnection layer, and the pads of the substrateless redistribution layer are flush with the top surface of the pads of the substrate. 4.The semiconductor package structure of claim 2, wherein the organic isolation layer, the isolation buffer layer and the substrate have thermal expansion coefficients in the same order of magnitude. 5.The semiconductor package structure of any one of claims 1-4, further comprising an adhesive layer located between the bottom surface of the substrateless redistribution layer and the substrate. 6.A method for manufacturing the semiconductor package structure of any one of claims 1-5, comprising: providing a substrate having an interconnection region and pads located at the periphery of the interconnection region, the interconnection region having a groove; embedding at least one substrateless redistribution layer in the groove; the substrateless redistribution layer being used for electrically connecting at least two dies on the substrate, the two dies being electrically connected to the substrate via corresponding pads, respectively; and forming an isolation buffer layer located between the outer sidewall of the substrateless redistribution layer and the substrate. 7.The method of claim 6, further comprising the following steps for forming the substrateless redistribution layer: providing a substrate, and sequentially forming a sacrificial layer and an initial redistribution layer on the substrate, the sacrificial layer being located between the substrate and the initial redistribution layer; and cutting the initial redistribution layer in a direction perpendicular to the substrate to form at least one substrateless redistribution layer. 8.The method of claim 7, further comprising the following steps for forming the initial redistribution layer: forming a patterned mask layer on the top surface of the sacrificial layer; the patterned mask layer having a recess for defining at least one interconnection layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ forming an interconnection layer in the groove of the patterned mask layer; the interconnection layer is used to electrically connect different dies; removing the patterned mask layer to form an organic isolation layer covering the interconnection layer, the organic isolation layer and the interconnection layer are used to jointly constitute an initial redistribution layer.

9. The method of claim 7, wherein the substrateless redistribution layer is connected to the bottom surface of the trench via an adhesive layer; after the substrate and the sacrificial layer are formed in sequence on the substrate, the method further comprises: forming an adhesive structure on the top surface of the initial substrateless redistribution layer, the adhesive structure comprises a base frame and an adhesive material layer between the base frame and the initial redistribution layer; the adhesive material layer covers at least the entire top surface of the initial substrateless redistribution layer in orthographic projection; removing the substrate and the sacrificial layer; during the cutting of the initial redistribution layer, the adhesive structure is cut, and the adhesive material layer between the substrateless redistribution layer and the corresponding base frame is used to constitute the adhesive layer.

10. The method of any one of claims 6-9, wherein after the isolation buffer layer is formed, the method further comprises: forming a molding layer covering the at least two dies and located between different dies and between the dies and the substrate.

11. The method of claim 10, wherein before the isolation buffer layer is formed and after the substrateless redistribution layer is formed, the method further comprises: bonding the at least two dies to the substrate and the substrateless redistribution layer, so that the dies are electrically connected to corresponding pads on the substrate and corresponding interconnection layers in the substrateless redistribution layer.

12. The method of claim 10, wherein the pads of the substrateless redistribution layer are flush with the top surface of the pads of the substrate; and the bonding of the at least two dies to the substrate and the substrateless redistribution layer comprises: forming conductive bumps for bonding the at least two dies, the top surface of the conductive bumps is flush; bonding input / output interfaces of the at least two dies to corresponding conductive bumps. ​ ​ ​ ​

Images