A bootstrap output stage driver circuit, chip and device for a direct current motor

Abstract

The application discloses a bootstrap output stage driving circuit, a chip and a device for a direct current motor, wherein the circuit comprises a power supply, a first diode, an under-voltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first driving circuit, a second driving circuit, a first capacitor, a first NMOS transistor, a second NMOS transistor and a first PMOS transistor. The circuit is an improved bootstrap circuit, and can realize circuit driving without using a charge pump and an oscillator. The circuit can not only solve the problem of large driving voltage swing of the direct current motor driving circuit in the prior art, but also can reduce cost, reduce circuit area and reduce circuit power consumption, and realize chip miniaturization.

Description

Technical Field

[0001] This application belongs to the field of electronic products, and in particular relates to a bootstrap output stage drive circuit, chip and device for DC motors. Background Technology

[0002] In recent years, the application fields of DC motors have become increasingly widespread. With the growing use of electric toys, electric toothbrushes, smart door locks, and other applications, the market has placed higher demands on DC motor drive circuits for smaller size, lower energy consumption, and longer service life. To address these needs, common solutions include reducing the fluctuation range of the internal drive voltage of the DC motor, minimizing the use of high-voltage transistors, and simplifying the circuit structure.

[0003] In existing technologies, a common approach is to generate the high-side drive logic level using a charge pump. However, this method results in a large swing in the gate voltage of the MOSFET driving the high-side voltage, leading to significant energy consumption. To handle this large swing, more high-voltage transistors must be used, resulting in a larger circuit area. To improve this situation, a bootstrap drive circuit is used. This allows the relative swing of the signal in most of the high-side drive circuitry to be within a relatively small range, ensuring that the energy consumed is only used for variations within the drive voltage swing range, without needing to adapt to the large swing of the power transistor's output voltage. However, traditional bootstrap drive circuits typically require an oscillator and an auxiliary charge pump to operate, resulting in higher costs, larger circuit areas, and difficulties in achieving chip miniaturization.

[0004] Therefore, how to solve the problems of large driving voltage swing, high power consumption and cost, large circuit area and difficulty in chip miniaturization of existing DC motor drive circuits is an important research issue. Summary of the Invention

[0005] The main technical problem solved by this invention is to provide a bootstrap output stage drive circuit, chip and device for DC motors, which solves the problems of large drive voltage swing, high power consumption and cost, large circuit area and difficulty in miniaturizing the chip in the prior art.

[0006] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is to provide a bootstrap output stage drive circuit, chip, and device for a DC motor, wherein the circuit includes:

[0007] In some embodiments, the circuit includes a power supply, a first diode, an undervoltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first driving circuit, a second driving circuit, a first capacitor, a first NMOS transistor, a second NMOS transistor, and a first PMOS transistor.

[0008] The positive terminal of the power supply is electrically connected to the anode of the first diode, the first connection terminal of the detection circuit, the first connection terminal of the logic circuit, and the first connection terminal of the second driving circuit; the negative terminal of the power supply is grounded and electrically connected to the fourth connection terminal of the detection circuit, the second connection terminal of the logic circuit, the second connection terminal of the second driving circuit, and the source of the second NMOS transistor.

[0009] The cathode of the first diode is electrically connected to the source of the first PMOS transistor, the first terminal of the undervoltage lockout circuit, the first terminal of the level conversion circuit, the first terminal of the first drive circuit, and the first terminal of the first capacitor.

[0010] The second connection terminal of the undervoltage lockout circuit is electrically connected to the gate of the first PMOS transistor, and the third connection terminal of the undervoltage lockout circuit is electrically connected to the second connection terminal of the level conversion circuit, the second connection terminal of the first driving circuit, the source of the first NMOS transistor, the drain of the second NMOS transistor, and the second connection terminal of the first capacitor.

[0011] The source of the first NMOS transistor also serves as the output terminal, used to power the load.

[0012] The second connection terminal of the detection circuit is electrically connected to the drain of the first PMOS transistor, and the third connection terminal of the detection circuit is electrically connected to the third connection terminal of the logic circuit.

[0013] The fourth connection terminal of the logic circuit is electrically connected to the third connection terminal of the second driving circuit, the fifth connection terminal of the logic circuit is used to input a reset signal, and the sixth connection terminal of the logic circuit is electrically connected to the third connection terminal of the level conversion circuit.

[0014] The fourth connection terminal of the level conversion circuit is electrically connected to the third connection terminal of the first driving circuit, the fourth connection terminal of the first driving circuit is electrically connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the first voltage.

[0015] The fourth connection terminal of the second driving circuit is electrically connected to the gate of the second NMOS transistor.

[0016] In some embodiments, the detection circuit includes a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a first NOT gate.

[0017] The first connection terminal of the first resistor serves as the first connection terminal of the detection circuit and is electrically connected to the first connection terminal of the first NOT gate.

[0018] The drain of the third NMOS transistor serves as the second connection terminal of the detection circuit, and is electrically connected to the gate of the third NMOS transistor and the gate of the fourth NMOS transistor, respectively.

[0019] The source of the third NMOS transistor serves as the fourth connection terminal of the detection circuit, and is electrically connected to the source of the fourth NMOS transistor and the second connection terminal of the first NOT gate, respectively.

[0020] The drain of the fourth NMOS transistor is electrically connected to the first terminal of the first resistor and the third terminal of the first NOT gate, respectively.

[0021] The fourth terminal of the first NOT gate serves as the third terminal of the detection circuit and is electrically connected to the third terminal of the logic circuit.

[0022] In some embodiments, the logic circuit includes a second NOT gate, a third NOT gate, and a first NAND gate.

[0023] The first terminal of the second NOT gate serves as the fifth terminal of the logic circuit; the second terminal of the second NOT gate serves as the sixth terminal of the logic circuit, and is electrically connected to the third terminal of the level conversion circuit and the first terminal of the third NOT gate, respectively; the third terminal of the second NOT gate is electrically connected to the third terminal of the third NOT gate and the third terminal of the first NAND gate, and serves as the first terminal of the logic circuit; the fourth terminal of the second NOT gate is electrically connected to the fourth terminal of the third NOT gate and the fourth terminal of the first NAND gate, and serves as the second terminal of the logic circuit.

[0024] The second terminal of the third NOT gate is electrically connected to the first terminal of the first NAND gate.

[0025] The second terminal of the first NAND gate serves as the third terminal of the logic circuit and is electrically connected to the third terminal of the detection circuit.

[0026] The fifth terminal of the first NAND gate serves as the fourth terminal of the logic circuit.

[0027] In some embodiments, the first driving circuit includes a first buffer, a first connection terminal of the first buffer serving as a first connection terminal of the first driving circuit, a second connection terminal of the first buffer serving as a second connection terminal of the first driving circuit, a third connection terminal of the first buffer serving as a third connection terminal of the first driving circuit, and a fourth connection terminal of the first buffer serving as a fourth connection terminal of the first driving circuit.

[0028] In some embodiments, the second driving circuit includes a second buffer, a first connection terminal of the second buffer serving as a first connection terminal of the second driving circuit, a second connection terminal of the second buffer serving as a second connection terminal of the second driving circuit, a third connection terminal of the second buffer serving as a third connection terminal of the second driving circuit, and a fourth connection terminal of the second buffer serving as a fourth connection terminal of the second driving circuit.

[0029] In some embodiments, the undervoltage lockout circuit includes a second resistor, a third resistor, a first amplifier, a second amplifier, a second NAND gate, a third NAND gate, and a fourth NOT gate.

[0030] The first connection terminal of the second resistor is connected to the second voltage. The second connection terminal of the second resistor is electrically connected to the first connection terminal of the third resistor, the inverting input terminal of the first amplifier, and the non-inverting input terminal of the second amplifier, respectively. The second connection terminal of the third resistor is grounded.

[0031] The non-inverting input of the first amplifier serves as the first connection terminal of the undervoltage lockout circuit; the output of the first amplifier is electrically connected to the first connection terminal of the second NAND gate.

[0032] The second terminal of the second NAND gate is electrically connected to the output terminal of the third NAND gate; the third terminal of the second NAND gate is electrically connected to the first terminal of the third NAND gate and the first terminal of the fourth NAND gate respectively; and the second terminal of the fourth NAND gate serves as the second terminal of the undervoltage lockout circuit.

[0033] The inverting input of the second amplifier serves as the third connection terminal of the undervoltage lockout circuit, and the output of the second amplifier is electrically connected to the second connection terminal of the third NAND gate.

[0034] In some embodiments, the level shifting circuit includes a fourth resistor, a second PMOS transistor, and a fifth NMOS transistor.

[0035] The first connection terminal of the fourth resistor serves as the first connection terminal of the level conversion circuit, and the second connection terminal of the fourth resistor is electrically connected to the source of the second PMOS transistor and also serves as the fourth connection terminal of the level conversion circuit.

[0036] The gate of the second PMOS transistor serves as the second connection terminal of the level conversion circuit, and the drain of the second PMOS transistor is electrically connected to the drain of the fifth NMOS transistor.

[0037] The source of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor serves as the third connection terminal of the level conversion circuit.

[0038] In some embodiments, the logic circuit includes a fifth NOT gate, a third buffer, and a fourth NAND gate.

[0039] The first connection terminal of the fifth NOT gate is electrically connected to the first connection terminal of the third buffer, and serves as the fifth connection terminal of the logic circuit.

[0040] The second terminal of the fifth NOT gate serves as the sixth terminal of the logic circuit and is electrically connected to the third terminal of the level conversion circuit.

[0041] The second connection terminal of the third buffer is electrically connected to the first connection terminal of the fourth NAND gate.

[0042] The third connection terminal of the third buffer is electrically connected to the third connection terminal of the fourth NAND gate, and serves as the first connection terminal of the logic circuit.

[0043] The fourth connection terminal of the third buffer is electrically connected to the fourth connection terminal of the fourth NAND gate, and serves as the second connection terminal of the logic circuit.

[0044] The second connection terminal of the fourth NAND gate serves as the third connection terminal of the logic circuit and is electrically connected to the third connection terminal of the detection circuit.

[0045] The fifth connection terminal of the fourth NAND gate serves as the fourth connection terminal of the logic circuit.

[0046] To address the aforementioned technical problems, this application also provides a bootstrap output stage driver chip for DC motors, including any of the bootstrap output stage driver circuits for DC motors described above.

[0047] To address the aforementioned technical problems, this application also provides a bootstrap output stage drive device for a DC motor, including the aforementioned bootstrap output stage drive chip for a DC motor.

[0048] Beneficial Effects: This application discloses a bootstrap output stage drive circuit, chip, and device for DC motors. The circuit includes: a power supply, a first diode, an undervoltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first drive circuit, a second drive circuit, a first capacitor, a first NMOS transistor, a second NMOS transistor, and a first PMOS transistor. The circuit of this application is an improved bootstrap circuit that eliminates the need for a charge pump and an oscillator to drive the circuit. This not only solves the problem of large drive voltage swing in existing DC motor drive circuits but also reduces cost, circuit area, and power consumption, enabling chip miniaturization. Attached Figure Description

[0049] Figure 1 A circuit diagram of one embodiment of the bootstrap output stage drive circuit for a DC motor according to this application is provided.

[0050] Figure 2 The timing diagram of the circuit in this application is provided;

[0051] Figure 3 A circuit diagram of one embodiment of the detection circuit in this application is provided;

[0052] Figure 4 A circuit diagram of one embodiment of the logic circuit in this application is provided;

[0053] Figure 5 A circuit diagram of another embodiment of the logic circuit in this application is provided;

[0054] Figure 6 A circuit diagram of one embodiment of the first driving circuit in this application is provided;

[0055] Figure 7 A circuit diagram of one embodiment of the second driving circuit in this application is provided;

[0056] Figure 8 A circuit diagram of one embodiment of the undervoltage lockout circuit in this application is provided;

[0057] Figure 9 A circuit diagram of one embodiment of the level conversion circuit in this application is provided. Detailed Implementation

[0058] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0059] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0060] Figure 1 A circuit diagram of a bootstrap output stage drive circuit for a DC motor is provided in this application, combined with... Figure 1 The circuit includes: a power supply 100, a first diode 110, an undervoltage lockout circuit 101, a detection circuit 104, a logic circuit 105, a level conversion circuit 102, a first driving circuit 103, a second driving circuit 106, a first capacitor 109, a first NMOS transistor 107, a second NMOS transistor 108, and a first PMOS transistor 111.

[0061] The positive terminal of the power supply 100 is electrically connected to the anode of the first diode 110, the first connection terminal of the detection circuit 104, the first connection terminal of the logic circuit 105, and the first connection terminal of the second driving circuit 106; the negative terminal of the power supply 100 is grounded and electrically connected to the fourth connection terminal of the detection circuit 104, the second connection terminal of the logic circuit 105, the second connection terminal of the second driving circuit 106, and the source of the second NMOS transistor 108.

[0062] The cathode of the first diode 110 is electrically connected to the source of the first PMOS transistor 111, the first connection terminal of the undervoltage lockout circuit 101, the first connection terminal of the level conversion circuit 102, the first connection terminal of the first drive circuit 103, and the first connection terminal of the first capacitor 109.

[0063] The second connection terminal of the undervoltage lockout circuit 101 is electrically connected to the gate of the first PMOS transistor 111, and the third connection terminal of the undervoltage lockout circuit 101 is electrically connected to the second connection terminal of the level conversion circuit 102, the second connection terminal of the first driving circuit 103, the source of the first NMOS transistor 107, the drain of the second NMOS transistor 108, and the second connection terminal of the first capacitor 109.

[0064] The source of the first NMOS transistor 107 also serves as an output terminal for powering a load (e.g., a DC motor); the second connection terminal of the detection circuit 104 is electrically connected to the drain of the first PMOS transistor 111, and the third connection terminal of the detection circuit 104 is electrically connected to the third connection terminal of the logic circuit 105; the fourth connection terminal of the logic circuit 105 is electrically connected to the third connection terminal of the second drive circuit 106, the fifth connection terminal of the logic circuit 105 is used to input a reset signal, and the sixth connection terminal of the logic circuit 105 is electrically connected to the third connection terminal of the level conversion circuit 102.

[0065] The fourth connection terminal of the level conversion circuit 102 is electrically connected to the third connection terminal of the first driving circuit 103. The fourth connection terminal of the first driving circuit 103 is electrically connected to the gate of the first NMOS transistor 107. The drain of the first NMOS transistor 107 is connected to a first voltage, which is the power supply voltage used to supply power to the load. The fourth connection terminal of the second driving circuit 106 is electrically connected to the gate of the second NMOS transistor 108.

[0066] Specifically, in combination Figure 2 To explain, Figure 2 IN represents the reset signal input to logic circuit 105, and also represents the start signal input from outside the circuit; UVLO represents the signal output by undervoltage lockout circuit 101, used to control the conduction and turn-off of the first PMOS transistor 111; Vc represents the voltage across the first capacitor 109; AH represents the high voltage threshold; VL represents the low voltage threshold; t0, t1, T+t0, and T+t1 represent different times, and T represents the oscillation period.

[0067] Specifically, when the reset signal IN is low, it indicates that there is no input signal to the circuit. The undervoltage lockout circuit 101 outputs a high voltage, i.e., UVLO is high. The first PMOS transistor 111 is cut off, and the circuit is in the off state. At this time, the voltage Vc across the first capacitor 109 is 0. At time t0, the reset signal IN changes from low to high, indicating that the circuit starts working. However, since the circuit is still in a low voltage state, the undervoltage lockout circuit 101 still outputs a high level, i.e., UVLO is high. The first PMOS transistor 111 is cut off, the detection circuit 104 outputs a low level, and the logic circuit 105 outputs a high level to the second drive circuit 106. The second drive circuit 106 controls the second NMOS transistor 108 to turn on. The logic circuit 105 outputs a low level to the level conversion circuit 102. At this time, the first drive circuit 103 controls the first NMOS transistor 107 to turn off. At this time, the power supply 100 starts charging the first capacitor 109.

[0068] Furthermore, when the circuit is working normally, the undervoltage lockout circuit 101 outputs a low level, the first PMOS transistor 111 is turned on, the detection circuit 104 outputs a high level, the logic circuit 105 outputs a low level to the second drive circuit 106, and the second drive circuit 106 outputs a low level to control the second NMOS transistor 108 to turn off; the logic circuit 105 outputs a high level to the level conversion circuit 102, at which time the first drive circuit 103 controls the first NMOS transistor 107 to turn on, and the voltage at the second connection terminal of the first capacitor 109 increases. Since the voltage across the capacitor cannot change abruptly, the voltage at the first connection terminal of the first capacitor 109 also increases accordingly. At time t1, when the voltage Vc across the first capacitor 109 reaches the high voltage threshold VH, the first capacitor 109 begins to discharge, supplying power to the undervoltage lockout circuit 101, the level conversion circuit, and the first drive circuit 103. The first diode 110 can act as a cutoff to prevent the first capacitor 109 from reverse charging the power supply 100. During the discharge process of the first capacitor 109, the voltage across the first capacitor 109 continuously decreases.

[0069] Furthermore, at time T+t0, when the voltage Vc across the first capacitor 109 drops to the low-voltage threshold VL, the undervoltage lockout circuit 101 outputs a high level, the first PMOS transistor 111 is turned off, the detection circuit 104 outputs a low level, and the logic circuit 105 outputs a high level to the second driving circuit 106. The second driving circuit 106 controls the second NMOS transistor 108 to turn on. The logic circuit 105 outputs a low level to the level conversion circuit 102. At this time, the first driving circuit 103 outputs a low level to control the first NMOS transistor 107 to turn off. Since the second connection terminal of the first capacitor 109 is grounded, the voltage of the first connection terminal of the first capacitor 109 is lower than that of the power supply 100, and the power supply 100 charges the first capacitor 109. This cycle repeats, and the circuit enters the normal operating mode, forming an adaptive circuit with an oscillation period of T.

[0070] The circuit of this application eliminates the use of an oscillator and forms an adaptive periodic signal. This adaptation is based on the difference between the high voltage threshold and the low voltage threshold. The frequency of the periodic signal can be adjusted by adjusting the difference between the two. The discharge speed of the first capacitor 109 depends entirely on the magnitude of the leakage current of the first NMOS transistor 107. Therefore, it can be well adapted to the continuous steady-state drive of the DC brushed motor, so that the charging time is a small proportion of an oscillation cycle and has little impact on the final drive current. The circuit of this application eliminates the need for a charge pump, thus reducing the use of high-voltage transistors and consequently lowering costs and circuit area. Furthermore, this circuit is an improved bootstrap circuit, enabling the drive circuit to operate without a charge pump and oscillator, achieving an adaptive oscillation cycle and further saving costs and power consumption, thus achieving chip miniaturization. In addition, since the swing range of the drive voltage in this application depends on the difference between the high-voltage threshold and the low-voltage threshold, while in the prior art the drive voltage swing range is 0–Vm, where Vm is the supply voltage, which can be tens of volts or even larger, resulting in a larger swing range, this application also solves the problem of large drive voltage swing in the prior art.

[0071] In some embodiments, combined with Figure 1 and Figure 3 The detection circuit 104 includes a third NMOS transistor 1040, a fourth NMOS transistor 1042, a first resistor 1041, and a first NOT gate 1043.

[0072] The first connection terminal of the first resistor 1041 serves as the first connection terminal 1044 of the detection circuit 104 and is electrically connected to the first connection terminal of the first NOT gate 1043.

[0073] The drain of the third NMOS transistor 1040 serves as the second connection terminal 1047 of the detection circuit 104, and is electrically connected to the gate of the third NMOS transistor 1040 and the gate of the fourth NMOS transistor 1042, respectively.

[0074] The source of the third NMOS transistor 1040 serves as the fourth connection terminal 1046 of the detection circuit 104, and is electrically connected to the source of the fourth NMOS transistor 1042 and the second connection terminal of the first NOT gate 1043, respectively.

[0075] The drain of the fourth NMOS transistor 1042 is electrically connected to the first connection terminal of the first resistor 1041 and the third connection terminal of the first NOT gate 1043, respectively; the fourth connection terminal of the first NOT gate 1043 serves as the third connection terminal 1045 of the detection circuit 104 and is electrically connected to the third connection terminal of the logic circuit 105.

[0076] Specifically, since the first connection terminal 1044 of the detection circuit 104 is electrically connected to the positive terminal of the power supply 100, the first connection terminal of the detection circuit 104 is connected to the power supply voltage and is at a high level; the second connection terminal 1047 of the detection circuit 104 is electrically connected to the drain of the first PMOS transistor 111, and the drain and gate of the third NMOS transistor 1040 and the gate of the fourth NMOS transistor 1042 are connected together and serve as the second connection terminal 1047 of the detection circuit 104. Therefore, the conduction and turn-off of the first PMOS transistor 111 affect the level of the input to the second connection terminal 1047 of the detection circuit 104.

[0077] When the first PMOS transistor 111 is turned on, the second connection terminal 1047 of the detection circuit 104 receives a high level, and both the third NMOS transistor 1040 and the fourth NMOS transistor 1042 are turned on. The third connection terminal (i.e., the input terminal) of the first NOT gate 1043 is grounded and receives a low level. The first NOT gate 1043 outputs a high level, and the fourth connection terminal (i.e., the output terminal) of the first NOT gate 1043 serves as the third connection terminal 1045 of the detection circuit 104. Therefore, the detection circuit 104 outputs a high level to the logic circuit 105. When the first PMOS transistor 111 is turned off, the second connection terminal 1047 of the detection circuit 104 receives a low level, and both the third NMOS transistor 1040 and the fourth NMOS transistor 1042 are turned off. The third connection terminal (i.e., the input terminal) of the first NOT gate 1043 is connected to the power supply 100 through the first resistor 1041, thus receiving a high level. The first NOT gate 1043 outputs a low level, thus the detection circuit 104 outputs a low level to the logic circuit 105. Therefore, the detection circuit 104 is used to detect whether there is a voltage input. When there is a voltage input to the detection circuit 104 (i.e., when the detection circuit 104 inputs a high level), the detection circuit 104 outputs a high level to the logic circuit 105; otherwise, it outputs a low level. The level output by the detection circuit 104 to the logic circuit 105 depends on the conduction and turn-off of the first PMOS transistor 111.

[0078] In some embodiments, combined with Figure 1 and Figure 4 The logic circuit 105 includes a second NOT gate 1050, a third NOT gate 1051, and a first NAND gate 1052.

[0079] The first connection terminal of the second NOT gate 1050 serves as the fifth connection terminal 1058 of the logic circuit 105, used to input a reset signal; the second connection terminal of the second NOT gate 1050 serves as the sixth connection terminal 1053 of the logic circuit 105, and is electrically connected to the third connection terminal of the level conversion circuit 102 and the first connection terminal of the third NOT gate 1051, respectively; the third connection terminal of the second NOT gate 1050 is electrically connected to the third connection terminal of the third NOT gate 1051 and the third connection terminal of the first NAND gate 1052, and serves as the first connection terminal 1055 of the logic circuit 105, used to connect to the positive terminal of the power supply 100; the fourth connection terminal of the second NOT gate 1050 is electrically connected to the fourth connection terminal of the third NOT gate 1051 and the fourth connection terminal of the first NAND gate 1052, and serves as the second connection terminal 1057 of the logic circuit 105, used to connect to the negative terminal of the power supply 100, i.e., grounded.

[0080] The second connection terminal of the third NOT gate 1051 is electrically connected to the first connection terminal of the first NAND gate 1052; the second connection terminal of the first NAND gate 1052 serves as the third connection terminal 1054 of the logic circuit 105 and is electrically connected to the third connection terminal of the detection circuit 104; the fifth connection terminal of the first NAND gate 1052 serves as the fourth connection terminal 1056 of the logic circuit 105 and is used to connect to the third connection terminal of the second driving circuit 106.

[0081] Specifically, since the first connection terminal of the second NOT gate 1050 serves as the fifth connection terminal 1058 of the logic circuit 105 and is used to input the reset signal IN; and the second connection terminal of the second NOT gate 1050 serves as the sixth connection terminal 1053 of the logic circuit 105 and is electrically connected to the third connection terminal of the level conversion circuit 102, the reset signal IN is output to the level conversion circuit 102 after being inverted by the second NOT gate 1050.

[0082] Specifically, when the reset signal IN is low, the second NOT gate 1050 outputs a high level to the level conversion circuit 102 and the third NOT gate 1051; the third NOT gate 1051 inverts the input high level and outputs a low level to the first NAND gate 1052. At this time, regardless of whether the signal input to the third connection terminal 1054 of the logic circuit 105 (i.e. the signal input by the detection circuit 104) is high or low, after the first NAND gate 1052 performs NAND logic operation, it outputs a high level to the second driving circuit 106.

[0083] Furthermore, when the reset signal IN is high, the second NOT gate 1050 outputs a low level to the level conversion circuit 102 and the third NOT gate 1051; the third NOT gate 1051 inverts the input low level and outputs a high level to the first NAND gate 1052. If the signal input from the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input from the detection circuit 104) is high, after the first NAND gate 1052 performs a NAND logic operation, it outputs a low level to the second driving circuit 106; if the signal input from the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input from the detection circuit 104) is low, after the first NAND gate 1052 performs a NAND logic operation, it outputs a high level to the second driving circuit 106. Therefore, the logic circuit 105 performs logic operations based on the input reset signal IN and the signal input by the detection circuit 104, and outputs different logic signals to the level conversion circuit 102 and the second driving circuit 106 respectively, so that the first NMOS transistor 107 and the second NMOS transistor 108 are in different working states, thereby affecting the charging and discharging state of the first capacitor 109 when the entire circuit is working.

[0084] In some embodiments, combined with Figure 1 and Figure 5 The logic circuit 105 includes a fifth NOT gate 1500, a third buffer 1510, and a fourth NAND gate 1511.

[0085] The first connection terminal of the fifth NOT gate 1500 is electrically connected to the first connection terminal of the third buffer 1510, and serves as the fifth connection terminal 1058 of the logic circuit 105 for inputting a reset signal; the second connection terminal of the fifth NOT gate 1500 serves as the sixth connection terminal 1053 of the logic circuit 105, and is electrically connected to the third connection terminal of the level conversion circuit 102; the second connection terminal of the third buffer 1510 is electrically connected to the first connection terminal of the fourth NAND gate 1511; the third connection terminal of the third buffer 1510 is electrically connected to the third connection terminal of the fourth NAND gate 1511, and serves as the first connection terminal of the logic circuit 105. Connection terminal 1055 is used to connect to the positive terminal of power supply 100; the fourth connection terminal of the third buffer 1510 is electrically connected to the fourth connection terminal of the fourth NAND gate 1511, and serves as the second connection terminal 1057 of logic circuit 105, used to connect to the negative terminal of power supply 100, i.e., ground; the second connection terminal of the fourth NAND gate 1511 serves as the third connection terminal 1054 of logic circuit 105, and is electrically connected to the third connection terminal of detection circuit 104; the fifth connection terminal of the fourth NAND gate 1511 serves as the fourth connection terminal 1056 of logic circuit 105, used to connect to the third connection terminal of second drive circuit 106.

[0086] Specifically, since the first connection terminal of the fifth NOT gate 1500 is electrically connected to the first connection terminal of the third buffer 1510, together they serve as the fifth connection terminal 1058 of the logic circuit 105, used to input the reset signal IN; and the second connection terminal of the fifth NOT gate 1500 serves as the sixth connection terminal 1053 of the logic circuit 105, and is electrically connected to the third connection terminal of the level conversion circuit 102; therefore, the reset signal IN is output to the level conversion circuit 102 after being inverted by the fifth NOT gate 1500.

[0087] Specifically, when the reset signal IN is low, the fifth NOT gate 1500 outputs a high level to the level conversion circuit 102 and the third buffer 1510; the third buffer 1510 outputs the low level input to the fourth NAND gate 1511. At this time, regardless of whether the signal input to the third connection terminal 1054 of the logic circuit 105 (i.e. the signal input by the detection circuit 104) is high or low, after the fourth NAND gate 1511 performs NAND logic operation, it outputs a high level to the third connection terminal of the second drive circuit 106.

[0088] Furthermore, when the reset signal IN is high, the fifth NOT gate 1500 outputs a low level to the level conversion circuit 102 and the third buffer 1510; the third buffer 1510 outputs the high level input to the fourth NAND gate 1511. If the signal input from the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input from the detection circuit 104) is high, after the fourth NAND gate 1511 performs a NAND logic operation, it outputs a low level to the second drive circuit 106; if the signal input from the third connection terminal 1054 of the logic circuit 105 (i.e., the signal input from the detection circuit 104) is low, after the fourth NAND gate 1511 performs a NAND logic operation, it outputs a high level to the second drive circuit.

[0089] In some embodiments, combined with Figure 1 and Figure 6 The first driving circuit 103 includes a first buffer 1030, a first connection terminal of the first buffer 1030 serving as the first connection terminal 1031 of the first driving circuit 103, a second connection terminal of the first buffer 1030 serving as the second connection terminal 1033 of the first driving circuit 103, a third connection terminal of the first buffer 1030 serving as the third connection terminal 1034 of the first driving circuit 103, and a fourth connection terminal of the first buffer 1030 serving as the fourth connection terminal 1032 of the first driving circuit 103.

[0090] Specifically, the third connection terminal 1034 of the first driving circuit 103 is electrically connected to the fourth connection terminal of the level conversion circuit 102, and is used to input the signal output by the level conversion circuit 102; the fourth connection terminal 1032 of the first driving circuit 103 is electrically connected to the gate of the first NMOS transistor 107, and is used to output a driving signal to the first NMOS transistor 107. The first buffer 1030 can improve the driving capability of the driving signal without changing the logic values ​​of the input signal and the output signal, that is, the input signal is the same as the output signal.

[0091] In some embodiments, combined with Figure 1 and Figure 7 The second driving circuit 106 includes a second buffer 1060, a first connection terminal of the second buffer 1060 serving as the first connection terminal 1061 of the second driving circuit 106, a second connection terminal of the second buffer 1060 serving as the second connection terminal 1063 of the second driving circuit 106, a third connection terminal of the second buffer 1060 serving as the third connection terminal 1064 of the second driving circuit 106, and a fourth connection terminal of the second buffer 1060 serving as the fourth connection terminal 1062 of the second driving circuit 106.

[0092] Specifically, the third connection terminal 1064 of the second driving circuit 106 is electrically connected to the fourth connection terminal of the logic circuit 105, and is used to input the signal output by the logic circuit 105; the fourth connection terminal 1062 of the second driving circuit 106 is electrically connected to the gate of the second NMOS transistor 108, and is used to output a driving signal to the second NMOS transistor 108. The second buffer 1060 can improve the driving capability of the driving signal without changing the logic values ​​of the input signal and the output signal, that is, the input signal is the same as the output signal.

[0093] In some embodiments, combined with Figure 1 and Figure 8 The undervoltage lockout circuit 101 includes a second resistor 1010, a third resistor 1011, a first amplifier 1012, a second amplifier 1013, a second NAND gate 1014, a third NAND gate 1015, and a fourth NOT gate 1016. The undervoltage lockout circuit 101 is used to detect the level of the circuit voltage and output a control signal to control the turn-on and turn-off of the first PMOS transistor 111. When the circuit voltage is low, the undervoltage lockout circuit 101 outputs a high level, turning off the first PMOS transistor 111, thereby reducing the circuit current consumption.

[0094] The first connection terminal of the second resistor 1010 is connected to the second voltage. The second connection terminal of the second resistor 1010 is electrically connected to the first connection terminal of the third resistor 1011, the inverting input terminal of the first amplifier 1012, and the non-inverting input terminal of the second amplifier 1013. The second connection terminal of the third resistor 1011 is grounded. The non-inverting input terminal of the first amplifier 1012 serves as the first connection terminal 1018 of the undervoltage lockout circuit 101. The output terminal of the first amplifier 1012 is electrically connected to the first connection terminal of the second NAND gate 1014.

[0095] The second terminal of the second NAND gate 1014 is electrically connected to the output terminal of the third NAND gate 1015; the third terminal (i.e., the output terminal) of the second NAND gate 1014 is electrically connected to the first terminal of the third NAND gate 1015 and the first terminal of the fourth NOT gate 1016, respectively; the second terminal of the fourth NOT gate 1016 serves as the second terminal 1017 of the undervoltage lockout circuit 101; the inverting input terminal of the second amplifier 1013 serves as the third terminal 1019 of the undervoltage lockout circuit 101, and the output terminal of the second amplifier 1013 is electrically connected to the second terminal of the third NAND gate 1015.

[0096] Specifically, the second voltage connected to the first connection terminal of the second resistor 1010 is the voltage Vc across the first capacitor 109. When the circuit is not in operation, since the voltage across the first capacitor 109 is 0, the inputs to the inverting input terminal of the first amplifier 1012 and the non-inverting input terminal of the second amplifier 1013 are both 0. The non-inverting input terminal of the first amplifier 1012 is electrically connected to the positive terminal of the power supply 100 through the first diode 110. Therefore, the output of the first amplifier 1012 is high, and the output of the second amplifier 1013 is low. At this time, the third NAND gate 1015 performs NAND logic and outputs a high level to the other input terminal of the second NAND gate 1014. The second NAND gate 1014 performs NAND logic and outputs a low level to the fourth NOT gate 1016. The fourth NOT gate 1016 inverts the input low level and outputs a high level, causing the first PMOS transistor 111 to turn off, and the circuit is in a shutdown protection state.

[0097] When the circuit starts working, the voltage across the first capacitor 109 continuously increases as the first capacitor 109 is charging. Consequently, the voltages at the inverting input of the first amplifier 1012 and the non-inverting input of the second amplifier 1013 also continuously increase. However, since it is in the initial charging stage, the voltage difference between the non-inverting and inverting inputs of the first amplifier 1012 is still significant, resulting in a high output voltage for the first amplifier 1012. The voltage difference between the non-inverting and inverting inputs of the second amplifier 1013 is not significant, resulting in a low output level for the second amplifier 1013. At this time, the third NAND gate 1015 performs a NAND logic operation and outputs a high level to the other input of the second NAND gate 1014. The second NAND gate 1014 performs a NAND logic operation and outputs a low level to the fourth NOT gate 1016. The fourth NOT gate 1016 inverts the low input level and outputs a high level, turning off the first PMOS transistor 111.

[0098] When the voltage across the first capacitor 109 reaches the high voltage threshold VH, the voltages input to the inverting input of the first amplifier 1012 and the non-inverting input of the second amplifier 1013 are also relatively high. Since the voltages input to the non-inverting and inverting inputs of the first amplifier 1012 are not significantly different, the first amplifier 1012 outputs a low voltage. At this time, the second NAND gate 1014 performs NAND logic and outputs a high level to the fourth NOT gate 1016. The fourth NOT gate 1016 inverts the input high level and outputs a low level, turning on the first PMOS transistor 111, and the circuit is in a stable operating state.

[0099] As the first capacitor 109 discharges, the voltage across it continuously decreases. When it reaches the low-voltage threshold VL, the voltage difference between the non-inverting and inverting inputs of the first amplifier 1012 becomes significant. Therefore, the first amplifier 1012 outputs a high level to one input of the second NAND gate 1014. The voltage difference between the non-inverting and inverting inputs of the second amplifier 1013 becomes negligible, resulting in a low output for the second amplifier 1013. At this point, the third NAND gate 1015 performs a NAND logic operation and outputs a high level to the other input of the second NAND gate 1014. The second NAND gate 1014 then performs a NAND logic operation and outputs a low level to the fourth NOT gate 1016. The fourth NOT gate 1016 inverts the low input level and outputs a high level, turning off the first PMOS transistor 111. Therefore, when the circuit voltage is low, the undervoltage lockout circuit 101 outputs a high level, turning off the first PMOS transistor 111, thereby reducing current consumption.

[0100] In some embodiments, combined with Figure 1 and Figure 9The level conversion circuit 102 includes a fourth resistor 1021, a second PMOS transistor 1022, and a fifth NMOS transistor 1023. The first connection terminal of the fourth resistor 1021 serves as the first connection terminal 1024 of the level conversion circuit 102, and the second connection terminal of the fourth resistor 1021 is electrically connected to the source of the second PMOS transistor 1022 and also serves as the fourth connection terminal 1027 of the level conversion circuit 102.

[0101] The gate of the second PMOS transistor 1022 serves as the second connection terminal 1025 of the level conversion circuit 102. The drain of the second PMOS transistor 1022 is electrically connected to the drain of the fifth NMOS transistor 1023. The source of the fifth NMOS transistor 1023 is grounded, and the gate of the fifth NMOS transistor 1023 serves as the third connection terminal 1026 of the level conversion circuit 102.

[0102] Specifically, the third connection terminal 1026 of the level conversion circuit 102 is electrically connected to the sixth connection terminal of the logic circuit 105, and is used to input the signal input by the logic circuit 105; the fourth connection terminal 1027 of the level conversion circuit 102 is electrically connected to the third connection terminal of the first driving circuit 103, and is used to output the signal to the first driving circuit 103; the first connection terminal 1024 of the level conversion circuit 102 is electrically connected to the positive terminal of the power supply 100 through the first diode 110, and is also electrically connected to the first connection terminal of the first capacitor 109; the second connection terminal 1025 of the level conversion circuit 102 is electrically connected to the drain of the second NMOS transistor 108 and the second connection terminal of the first capacitor 109, respectively.

[0103] Specifically, when the logic circuit 105 inputs a low level to the level conversion circuit 102, the fifth NMOS transistor 1023 is turned off, the second NMOS transistor 108 is turned on, and the second connection terminal of the first capacitor 109 is grounded. That is, the second connection terminal 1025 of the level conversion circuit 102 is at a low voltage, and the second PMOS transistor 1022 is turned on. At this time, the fourth connection terminal 1027 of the level conversion circuit 102 is grounded through the second PMOS transistor 1022 and the fifth NMOS transistor 1023. Therefore, the fourth connection terminal 1027 of the level conversion circuit 102 outputs a low voltage to the first driving circuit 103.

[0104] Furthermore, when a high level is input to the level conversion circuit 102 from the logic circuit 105, the fifth NMOS transistor 1023 is turned on, the second NMOS transistor 108 is turned off, and the second PMOS transistor 1022 is turned off. At this time, the fourth connection terminal 1027 of the level conversion circuit 102 outputs a high voltage to the first driving circuit 103. Therefore, the input voltage of the level conversion circuit 102 is related to the output voltage, and the fourth resistor 1021 can convert the input voltage from the logic circuit 105 into a suitable voltage for the first driving circuit 103. Therefore, the level conversion circuit is used for voltage conversion.

[0105] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0106] Based on the same inventive concept, this application also provides a bootstrap output stage driver chip for a DC motor, including any of the above-mentioned bootstrap output stage driver circuits for a DC motor.

[0107] The internal circuitry of the chip is described in the foregoing embodiment and will not be repeated here.

[0108] Based on the same inventive concept, this application also provides a bootstrap output stage drive device for a DC motor, including the above-mentioned bootstrap output stage drive chip for a DC motor.

[0109] In summary, this application discloses a bootstrap output stage drive circuit, chip, and device for a DC motor. The circuit includes: a power supply, a first diode, an undervoltage lockout circuit, a detection circuit, a logic circuit, a level conversion circuit, a first drive circuit, a second drive circuit, a first capacitor, a first NMOS transistor, a second NMOS transistor, and a first PMOS transistor. The circuit of this application is an improved bootstrap circuit that can drive the circuit without using a charge pump or an oscillator. It not only solves the problem of large drive voltage swing in existing DC motor drive circuits but also reduces cost, circuit area, and power consumption, achieving chip miniaturization.

[0110] The above description is merely an embodiment of the present invention and does not limit the scope of protection of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of protection of the present invention.

Claims

1. A bootstrap output stage drive circuit for a DC motor, characterized in that, include: Power supply, first diode, undervoltage lockout circuit, detection circuit, logic circuit, level conversion circuit, first drive circuit, second drive circuit, first capacitor, first NMOS transistor, second NMOS transistor, and first PMOS transistor; The positive terminal of the power supply is electrically connected to the anode of the first diode, the first connection terminal of the detection circuit, the first connection terminal of the logic circuit, and the first connection terminal of the second driving circuit; the negative terminal of the power supply is grounded and electrically connected to the fourth connection terminal of the detection circuit, the second connection terminal of the logic circuit, the second connection terminal of the second driving circuit, and the source of the second NMOS transistor. The cathode of the first diode is electrically connected to the source of the first PMOS transistor, the first connection terminal of the undervoltage lockout circuit, the first connection terminal of the level conversion circuit, the first connection terminal of the first driving circuit, and the first connection terminal of the first capacitor. The second connection terminal of the undervoltage lockout circuit is electrically connected to the gate of the first PMOS transistor, and the third connection terminal of the undervoltage lockout circuit is electrically connected to the second connection terminal of the level conversion circuit, the second connection terminal of the first driving circuit, the source of the first NMOS transistor, the drain of the second NMOS transistor, and the second connection terminal of the first capacitor, respectively. The source of the first NMOS transistor also serves as the output terminal, used to supply power to the load; The second connection terminal of the detection circuit is electrically connected to the drain of the first PMOS transistor, and the third connection terminal of the detection circuit is electrically connected to the third connection terminal of the logic circuit. The fourth connection terminal of the logic circuit is electrically connected to the third connection terminal of the second driving circuit, the fifth connection terminal of the logic circuit is used to input a reset signal, and the sixth connection terminal of the logic circuit is electrically connected to the third connection terminal of the level conversion circuit. The fourth connection terminal of the level conversion circuit is electrically connected to the third connection terminal of the first driving circuit, the fourth connection terminal of the first driving circuit is electrically connected to the gate of the first NMOS transistor, and the drain of the first NMOS transistor is connected to the first voltage. The fourth connection terminal of the second driving circuit is electrically connected to the gate of the second NMOS transistor.

2. The bootstrap output stage drive circuit for a DC motor according to claim 1, characterized in that, The detection circuit includes a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a first NOT gate; The first connection terminal of the first resistor serves as the first connection terminal of the detection circuit and is electrically connected to the first connection terminal of the first NOT gate. The drain of the third NMOS transistor serves as the second connection terminal of the detection circuit, and is electrically connected to the gate of the third NMOS transistor and the gate of the fourth NMOS transistor, respectively. The source of the third NMOS transistor serves as the fourth connection terminal of the detection circuit, and is electrically connected to the source of the fourth NMOS transistor and the second connection terminal of the first NOT gate, respectively. The drain of the fourth NMOS transistor is electrically connected to the first terminal of the first resistor and the third terminal of the first NOT gate, respectively. The fourth connection terminal of the first NOT gate serves as the third connection terminal of the detection circuit and is electrically connected to the third connection terminal of the logic circuit.

3. The bootstrap output stage drive circuit for a DC motor according to claim 1, characterized in that, The logic circuit includes a second NOT gate, a third NOT gate, and a first NAND gate; The first connection terminal of the second NOT gate serves as the fifth connection terminal of the logic circuit; the second connection terminal of the second NOT gate serves as the sixth connection terminal of the logic circuit, and is electrically connected to the third connection terminal of the level conversion circuit and the first connection terminal of the third NOT gate, respectively; the third connection terminal of the second NOT gate is electrically connected to the third connection terminal of the third NOT gate and the third connection terminal of the first NAND gate, and serves as the first connection terminal of the logic circuit; the fourth connection terminal of the second NOT gate is electrically connected to the fourth connection terminal of the third NOT gate and the fourth connection terminal of the first NAND gate, and serves as the second connection terminal of the logic circuit. The second connection terminal of the third NOT gate is electrically connected to the first connection terminal of the first NAND gate; The second connection terminal of the first NAND gate serves as the third connection terminal of the logic circuit and is electrically connected to the third connection terminal of the detection circuit. The fifth connection terminal of the first NAND gate serves as the fourth connection terminal of the logic circuit.

4. The bootstrap output stage drive circuit for a DC motor according to claim 1, characterized in that, The first driving circuit includes a first buffer, a first connection terminal of the first buffer serving as a first connection terminal of the first driving circuit, a second connection terminal of the first buffer serving as a second connection terminal of the first driving circuit, a third connection terminal of the first buffer serving as a third connection terminal of the first driving circuit, and a fourth connection terminal of the first buffer serving as a fourth connection terminal of the first driving circuit.

5. The bootstrap output stage drive circuit for a DC motor according to claim 1, characterized in that, The second driving circuit includes a second buffer, a first connection terminal of the second buffer serving as a first connection terminal of the second driving circuit, a second connection terminal of the second buffer serving as a second connection terminal of the second driving circuit, a third connection terminal of the second buffer serving as a third connection terminal of the second driving circuit, and a fourth connection terminal of the second buffer serving as a fourth connection terminal of the second driving circuit.

6. The bootstrap output stage drive circuit for a DC motor according to claim 1, characterized in that, The undervoltage lockout circuit includes a second resistor, a third resistor, a first amplifier, a second amplifier, a second NAND gate, a third NAND gate, and a fourth NOT gate; The first connection terminal of the second resistor is connected to a second voltage, and the second connection terminal of the second resistor is electrically connected to the first connection terminal of the third resistor, the inverting input terminal of the first amplifier, and the non-inverting input terminal of the second amplifier, respectively. The second connection terminal of the third resistor is grounded. The non-inverting input terminal of the first amplifier serves as the first connection terminal of the undervoltage lockout circuit; the output terminal of the first amplifier is electrically connected to the first connection terminal of the second NAND gate. The second terminal of the second NAND gate is electrically connected to the output terminal of the third NAND gate; the third terminal of the second NAND gate is electrically connected to the first terminal of the third NAND gate and the first terminal of the fourth NOT gate, respectively, and the second terminal of the fourth NOT gate serves as the second terminal of the undervoltage lockout circuit. The inverting input of the second amplifier serves as the third connection terminal of the undervoltage lockout circuit, and the output of the second amplifier is electrically connected to the second connection terminal of the third NAND gate.

7. The bootstrap output stage drive circuit for a DC motor according to claim 1, characterized in that, The level conversion circuit includes a fourth resistor, a second PMOS transistor, and a fifth NMOS transistor; The first connection terminal of the fourth resistor serves as the first connection terminal of the level conversion circuit, and the second connection terminal of the fourth resistor is electrically connected to the source of the second PMOS transistor and also serves as the fourth connection terminal of the level conversion circuit. The gate of the second PMOS transistor serves as the second connection terminal of the level conversion circuit, and the drain of the second PMOS transistor is electrically connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor is grounded, and the gate of the fifth NMOS transistor serves as the third connection terminal of the level conversion circuit.

8. The bootstrap output stage drive circuit for a DC motor according to claim 1, characterized in that, The logic circuit includes a fifth NOT gate, a third buffer, and a fourth NAND gate; The first connection terminal of the fifth NOT gate is electrically connected to the first connection terminal of the third buffer, and serves as the fifth connection terminal of the logic circuit. The second connection terminal of the fifth NOT gate serves as the sixth connection terminal of the logic circuit and is electrically connected to the third connection terminal of the level conversion circuit. The second connection terminal of the third buffer is electrically connected to the first connection terminal of the fourth NAND gate; The third connection terminal of the third buffer is electrically connected to the third connection terminal of the fourth NAND gate, and serves as the first connection terminal of the logic circuit. The fourth connection terminal of the third buffer is electrically connected to the fourth connection terminal of the fourth NAND gate, and serves as the second connection terminal of the logic circuit. The second connection terminal of the fourth NAND gate serves as the third connection terminal of the logic circuit and is electrically connected to the third connection terminal of the detection circuit. The fifth connection terminal of the fourth NAND gate serves as the fourth connection terminal of the logic circuit.

9. A bootstrap output stage driver chip for DC motors, characterized in that, Includes the bootstrap output stage drive circuit for a DC motor as described in any one of claims 1-8.

10. A bootstrap output stage drive device for a DC motor, characterized in that, Includes the bootstrap output stage driver chip for DC motors as described in claim 9.

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