A filter and filtering processing method

Abstract

The present application discloses a digital filter and a filtering processing method, wherein the digital filter includes a single-port random access memory, an operation module and a control module, wherein the control module writes a filtering parameter group corresponding to the current filtering task into the single-port random access memory; each filtering parameter group includes a filtering coefficient and an input sample; the control module reads sub-data groups from the single-port random access memory in a first-in-first-out order and distributes them to a computing unit in an idle state, wherein each sub-data group includes a filtering sub-coefficient and an input sub-sample, wherein the filtering sub-coefficient is a part of the filtering coefficient, and the input sub-sample is a part of the input sample; the control module is also used to obtain a corresponding output sample according to the final result of the computing unit participating in the current filtering task, and write the output sample into the single-port random access memory. The present application realizes a small-sized digital filter to meet the needs of a smaller nanometer-level digital filter.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit chips, and in particular to a filter and a filtering processing method. Background Art

[0002] Analog-to-digital conversion is the process of converting a continuous analog signal into a discrete digital signal. During this process, there may still be some noise components in the signal. Therefore, after analog-to-digital conversion, it is usually necessary to use a digital filter to further process these noises to improve the signal quality and signal-to-noise ratio.

[0003] Compared with analog filters, digital filters have the advantages of small area, flexibility, stability and high precision. However, the structure of digital filters is complex. Summary of the invention

[0004] The present application provides a filter and a filtering processing method, which can realize a small-sized digital filter to meet the demand for smaller nanometer-level digital filters.

[0005] In a first aspect, an embodiment of the present application provides a digital filter, comprising: a single-port random access memory, a calculation module and a control module, wherein the calculation module is connected between the single-port random access memory and the control module, the control module is also connected to the single-port random access memory, and the calculation module comprises a plurality of parallel calculation units;

[0006] The control module writes the filter parameter group corresponding to the current filter task into the single-port random access memory; each of the filter parameter groups includes a filter coefficient and an input sample;

[0007] The control module is further used to read sub-data groups from the single-port random access memory in a first-in first-out order and distribute them to the computing units in an idle state, each of the sub-data groups includes a filter sub-coefficient and an input sub-sample, the filter sub-coefficient is a part of the filter coefficient, and the input sub-sample is a part of the input sample;

[0008] The control module is further used to obtain corresponding output samples according to the final results of the calculation units participating in the current filtering task, and write the output samples into the single-port random access memory.

[0009] In some embodiments, the single-port random access memory includes a first storage block for storing the filter coefficients and a second storage block for storing the input samples;

[0010] The control module is further configured to write the filter coefficient corresponding to the current filter task into the first storage block, and write the input sample corresponding to the current filter task into the second storage block when switching from an idle state to a preloaded state.

[0011] In some embodiments, the computing unit includes a multiplier, a first adder, a first register, a second register and a third register, the first register and the second register are connected in parallel and between the single-port random access memory and the multiplier, the first adder is connected between the multiplier and the third register;

[0012] The control module is further configured to read at least two of the sub-data groups corresponding to the current filtering task from the single-port random access memory when switching from the pre-loading state to the data distribution state, and store the filter sub-coefficients in the read sub-data groups into the first register, and store the input sub-samples in the read sub-data groups into the second register;

[0013] The control module is further used to traverse and search for the computing unit in the idle state among the plurality of computing units, and send the sub-data group corresponding to the current filtering task to the multiplier of the computing unit in the idle state; one sub-data group corresponds to the multiplier of one computing unit in the idle state;

[0014] The multiplier substitutes the filter coefficient and the input sub-sample in the sub-data group into the following formula to obtain a corresponding product result;

[0015] W k =b k *x k ;

[0016] The first adder substitutes the multiplication result and the first accumulated value stored in the third register into the following formula to obtain an updated first accumulated value;

[0017] E k =W k +E k-1 ;

[0018] The third register stores the first accumulated value, and replaces the first accumulated value with the updated first accumulated value;

[0019] The control module is further configured to take the last updated first accumulated value read from the third register as the final result; the last updated first accumulated value is the sum of all the product results corresponding to all the sub-data groups corresponding to the current filtering task and the first preset initial value stored in the third register;

[0020] Among them, W k is the kth product result corresponding to the current filtering task, b k is the kth filter coefficient of the filter parameter group corresponding to the current filter task, x k is the kth input subsample of the filter parameter group corresponding to the current filter task, E k is the first accumulated value after the update, E k-1 is the first accumulated value stored in the third register, k is a positive integer, and E0 is the first preset initial value stored in the third register.

[0021] In some embodiments, the control module further includes a selector, a second adder and a fourth register, the selector is connected to a plurality of the third registers, and the second adder is connected between the selector and the fourth register;

[0022] The control module is further used for, when switching from the data distribution state to the data collection state, traversing and detecting whether the computing units participating in the current filtering task are in an idle state at the current moment, and passing the final result to the computing unit of the second adder to be cleared and marked as completed;

[0023] The selector reads the final result from the third register in the target computing unit until the final results in all the computing units participating in the current filtering task are read, and the target computing unit is the computing unit that is in the idle state at the current moment and participates in the current filtering task;

[0024] The second adder substitutes the final result and the second accumulated value stored in the fourth register into the following formula to obtain an updated second accumulated value;

[0025] Q k =E jk '+Q k-1 ;

[0026] The fourth register stores the second accumulated value, and replaces the second accumulated value with the updated second accumulated value;

[0027] The control module is further configured to use the last updated second accumulated value read from the fourth register as the output sample; the last updated second accumulated value is the sum of all the final results of all the calculation units participating in the current filtering task and the second preset initial value stored in the fourth register;

[0028] Among them, Q k is the updated second accumulated value, Q k-1 is the second accumulated value stored in the fourth register, E jk ' is the final result stored in the jth third register, j is a positive integer, and Q0 is the second preset initial value stored in the fourth register.

[0029] In some embodiments, the control module includes a plurality of control switches, the number of the control switches is the same as the number of the computing units, and the plurality of control switches are connected to the plurality of computing units in a one-to-one correspondence; the read and write ports of the single-port random access memory are connected to the corresponding computing units through the control switches:

[0030] The control module is also used to select the computing unit in the idle state that participates in the current filtering task, and output a selection signal to the control switch connected to the selected computing unit in the idle state to connect the read and write port with the selected computing unit.

[0031] In some embodiments, the control module accesses the single-port random access memory through software or direct memory access.

[0032] In some embodiments, the storage depth of the first storage block is the same as the number of the filter sub-coefficients corresponding to the current filtering task, and the storage depth of the second storage block is greater than or equal to the number of the filter sub-coefficients corresponding to the current filtering task.

[0033] In some embodiments, the number of the filter sub-coefficients corresponding to the current filtering task is the same as the order of the filter coefficients corresponding to the current filtering task.

[0034] In some embodiments, the digital filter is a finite impulse response filter.

[0035] In some embodiments, the filter coefficients include feedforward coefficients, the filter sub-coefficients include feedforward sub-coefficients, the input samples include a current input signal, the input sub-samples include an input sub-signal and a previous output sub-sample, and the output samples include a current output signal.

[0036] In some embodiments, the digital filter is an infinite impulse response filter.

[0037] In some embodiments, the filter coefficient includes a feedforward coefficient and a feedback coefficient, the filter sub-coefficient includes a feedforward sub-coefficient and a previous feedback sub-coefficient in the previous filter parameter group, the input sample includes an input signal and a previous input sample in the previous filter parameter group, the input sub-sample includes an input sub-signal and a previous output sub-sample, and the output sample includes a current output signal.

[0038] In some embodiments, the control module is also used to detect whether a preset value exists in the current sub-data group. If the preset value exists in the current sub-data group, it directly switches to detect whether the preset value exists in the next sub-data group. If the preset value does not exist in the current sub-data group, the current sub-data group is sent to the computing unit in an idle state.

[0039] In some embodiments, the single-port random access memory further includes a third storage block for storing the output samples, and a storage depth of the third storage block is greater than or equal to a first preset value.

[0040] In a second aspect, the present application further provides a filtering processing method, which is applied to a digital filter, wherein the digital filter comprises: a single-port random access memory, a calculation module and a control module, wherein the calculation module is connected between the single-port random access memory and the control module, and the control module is also connected to the single-port random access memory, and the calculation module comprises a plurality of parallel calculation units; the method comprises:

[0041] The control module writes the filter parameter group corresponding to the current filter task into the single-port random access memory; each of the filter parameter groups includes a filter coefficient and an input sample;

[0042] The control module reads sub-data groups from the single-port random access memory in a first-in first-out order and distributes the sub-data groups to the computing units in an idle state, each of the sub-data groups includes a filter sub-coefficient and an input sub-sample, the filter sub-coefficient is a part of the filter coefficient, and the input sub-sample is a part of the input sample;

[0043] The control module obtains corresponding output samples according to final results of the calculation units participating in the current filtering task, and writes the output samples into the single-port random access memory.

[0044] The embodiment of the present application provides a digital filter and a filtering processing method, wherein the digital filter includes a single-port random access memory, an operation module and a control module, wherein the control module writes a filtering parameter group corresponding to the current filtering task into the single-port random access memory; each filtering parameter group includes a filtering coefficient and an input sample; the control module reads sub-data groups from the single-port random access memory in a first-in-first-out order and distributes them to computing units in an idle state, wherein each sub-data group includes a filtering sub-coefficient and an input sub-sample, wherein the filtering sub-coefficient is a part of the filtering coefficient, and the input sub-sample is a part of the input sample; the control module is also used to obtain a corresponding output sample according to the final result of the computing unit participating in the current filtering task, and write the output sample into the single-port random access memory. The present application realizes a small-sized digital filter to meet the needs of a smaller nanometer-level digital filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a structural schematic diagram of a digital filter provided in an embodiment of the present application;

[0047] Figure 2 is a state diagram of a digital filter provided in an embodiment of the present application;

[0048] Figure 3 It is a circuit structure diagram of a digital filter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0050] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "one end" and "the other end" is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0051] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or it can be connected or can communicate with each other; it can be directly connected, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0052] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples, and the purpose is not to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In the above-mentioned embodiments, the description of each embodiment has its own emphasis, and for the parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0053] A digital signal is a discrete signal whose time and amplitude are both discrete, and is usually represented by binary values ​​0 and 1. Common digital signal types include pulse signals, sinusoidal signals, square wave signals, digital audio signals, etc. After the ADC (Akalog-to-Digital Converter) converts the analog signal into a digital signal, the digital signal will contain noise and interference signals. The digital filter can process the converted digital signal to remove unnecessary frequency components, that is, by filtering the input digital signal to reduce noise, extract useful information, etc., to improve the quality and accuracy of the signal.

[0054] In addition to FIR (Fikite Impulse Respokse Filter, finite impulse response filter), digital filters also include IIR (Ikfikite Impulse Respokse, infinite impulse response filter). In addition, there are other types of digital filters, such as adaptive filters, Wieker filters (Wiener filters), Kalman filters, linear predictors, etc. Digital filters are generally divided into full parallel structures, serial structures, and semi-parallel structures. Among them, the full parallel structure means that all multiplication operations are completed at one time through a large number of multipliers. The advantage is fast speed, but the disadvantage is that it occupies a large area. It is generally used on DSP (Digital Sigkal Processor) chips with a large number of multiplication resources. The serial structure means that one multiplier and one accumulator are used to complete all multiplication and addition operations through time-sharing multiplexing. The advantage is that it occupies a small area, but the disadvantage is that it is slow. It is generally used in scenarios where speed and real-time requirements are not high, such as through software programming, constantly calling the multiplication or addition operations of the MCU (Microcoktroller Ukit, microcontroller unit or micro control unit) to achieve filtering operations. The semi-parallel structure divides the multiplication and addition tasks and time-multiplexes the multiplier and the first adder to obtain the final result.

[0055] Digital filters are widely used to process noisy signals after analog-to-digital conversion. Digital filters can effectively remove or reduce these noises and improve signal quality. Digital filters can use dual-port RAM (Rakdom Access Memory, memory stick or random access memory) to implement filtering operations. Dual-port RAM has two independent read and write ports, allowing simultaneous read and write operations. Each read and write port can independently initiate read or write operations, thereby realizing parallel data processing. Dual-port RAM can output input samples and filter coefficients simultaneously for multiplication operations. However, due to the complex structure and design of dual-port RAM, dual-port RAM is often not supported in smaller nanometer-level process libraries.

[0056] The present application solves the above-mentioned problems through a digital filter and a filtering processing method in the following embodiments, thereby realizing a small-sized digital filter and meeting the demand for a smaller nanometer-level digital filter.

[0057] Reference Figure 1 As shown, the present application provides a digital filter 100, Figure 1 is a structural diagram of a digital filter 100 in an embodiment of the present application, such as Figure 1As shown, the digital filter 100 includes: a single-port random access memory 110, a calculation module 120 and a control module 130, wherein the calculation module 120 is connected between the single-port random access memory 110 and the control module 130, and the control module 130 is also connected to the single-port random access memory 110, and the calculation module 120 includes a plurality of parallel calculation units 121;

[0058] The control module 130 writes the filter parameter group corresponding to the current filter task into the single-port random access memory 110; each of the filter parameter groups includes a filter coefficient and an input sample;

[0059] The control module 130 is further configured to read sub-data groups from the single-port random access memory 110 in a first-in first-out order and distribute the sub-data groups to the computing unit 121 in an idle state, each of the sub-data groups comprising a filter sub-coefficient and an input sub-sample, the filter sub-coefficient being a part of the filter coefficient, and the input sub-sample being a part of the input sample;

[0060] The control module 130 is further configured to obtain corresponding output samples according to the final results of the calculation units 121 participating in the current filtering task, and write the output samples into the single-port random access memory 110 .

[0061] Specifically, a single-port random access memory 110 (Sikgle-Port RAM, hereinafter referred to as single-port RAM for the convenience of description) refers to a RAM with only one read-write port. It has only one set of data lines and address lines. The address lines are used to specify the address of the storage unit to be read or written, and the data lines are used to transmit data in the read-write operation. The read and write operations of the single-port RAM are performed through this read-write port. In short, this read-write port of the single-port RAM is input / output data multiplexing, and the single-port RAM can be used to store input samples, output samples and filter coefficients. The single-port RAM can only perform read operations or write operations at the same time, and cannot perform read operations and write operations at the same time.

[0062] The input sample is the data to be filtered, and the output sample refers to the data after filtering. Both the input sample and the output sample are binary data. The filter coefficient is usually a set of constants. The filter coefficient of this application is also expressed in binary. The filter coefficient determines the operating parameters of the filter, such as gradient, contrast and smoothness. Its size and distribution directly affect the filtering effect. The filter coefficient is a key parameter to achieve the signal processing effect. By reasonably selecting and adjusting the filter coefficient, the signal processing effect can be effectively improved.

[0063] In the present application, one filtering task corresponds to one output sample, that is, one filtering coefficient and one input sample correspond to one output sample at the same time. The digital filter 100 can filter multiple input samples in time-sharing to obtain multiple output samples corresponding to the filtered noise and interference signals, that is, the digital filter 100 can perform multiple filtering operations in time-sharing, and each filtering operation is performed by the digital filter 100 filtering an input sample according to a filtering coefficient to obtain a corresponding output sample.

[0064] After the control module 130 of the present application obtains the filter parameter group corresponding to the current filter task, the control module 130 can write the filter parameter group corresponding to the current filter task into the storage area of ​​the single-port RAM through the read-write port of the single-port RAM, and the control module 130 can read the sub-data groups in sequence from the storage area of ​​the single-port RAM in the order of FIFO. The number of filter sub-coefficients obtained each time is the same as the number of input sub-samples. A filter sub-coefficient and an input sub-sample constitute a sub-data group. Since at least two filter sub-coefficients of the same type are read in FIFO order, they can constitute a complete filter coefficient. Similarly, since at least two input sub-samples of the same type are read in FIFO order, they can constitute a complete filter coefficient. In this way, it is equivalent to splitting a filter coefficient in the filter parameter group corresponding to the current filter task into at least two filter sub-coefficients, and splitting an input sample in the filter parameter group corresponding to the current filter task into at least two input sub-samples. The control module 130 searches for some of the computing units 121 that are in an idle state (i.e., no computing tasks are being executed) among the multiple computing units 121, and distributes a number of sub-data groups to the computing units 121 that are in an idle state that are found in the order of reading. The control module 130 obtains the final results of the outputs from all the computing units 121 that participate in the current filtering task, and obtains the corresponding output samples according to the final results of all the computing units 121 that participate in the current filtering task. Finally, the control module 130 writes the filtered output samples corresponding to the input samples into the single-port RAM. For example, if the filter coefficient is divided into 60 filter sub-coefficients from w1 to w60, and the input samples are divided into 60 input sub-samples from d1 to d60, then the output samples are d1*w1+d2*w2+...+d60*w60, and the output samples are obtained from multiple output sub-samples, and the output sub-samples are equal to the product of the corresponding filter sub-coefficients and the input sub-samples. For example, if the filter sub-coefficient is w1 and the input sub-sample is d1, the corresponding output sub-sample is d1*w1. For example, if the filter coefficient is w60 and the input subsample is d60, the corresponding output subsample is d60*w60.

[0065] In the present application, since the operation module 120 includes a plurality of parallel computing units 121, the control module 130 can distribute a filter coefficient and an input sample at least twice to at least two idle computing units 121 to perform filtering processing, so that multiple computing units 121 can be used to process different data parts at the same time, thereby improving the computing efficiency and realizing parallel filtering, thereby speeding up the speed of the entire filtering process and improving the filtering efficiency. In addition, since the computing unit 121 to which the current sub-data group is distributed is in an idle state, the full utilization of computing resources is ensured, the idle time caused by waiting for data or tasks is avoided, and the utilization rate of computing resources is maximized, so new tasks can be assigned to improve the overall performance and filtering efficiency of the digital filter 100. Finally, since dual-port RAM usually takes up more space than single-port RAM, and because dual-port RAM requires more memory cells, circuits and control logic, when the depth and bit width are fixed, the area of ​​dual-port RAM is approximately 2 to 3 times that of single-port RAM. Therefore, the present application uses a single-port RAM in combination with multiple parallel computing units 121 to not only achieve parallel filtering and improve filtering efficiency, but also greatly reduce the area consumption of the digital filter 100, realize a small-size digital filter 100, and meet the needs of digital filters 100 at a smaller nanometer level (for example, below 12nm).

[0066] In some embodiments, the single-port random access memory 110 includes a first storage block for storing the filter coefficients and a second storage block for storing the input samples;

[0067] The control module 130 is further configured to write the filter coefficient corresponding to the current filter task into the first storage block, and write the input sample corresponding to the current filter task into the second storage block when switching from the idle state to the preloaded state.

[0068] Specifically, the single-port RAM includes a first storage block (not shown in the figure) and a second storage block (not shown in the figure), the first storage block is used to store filter coefficients, and the second storage block is used to store input samples. The control module 130 includes a state machine (not shown in the figure) and a FIFO (First Input First Output, First In First Out or First In First Out) control circuit (not shown in the figure). The state machine is used to control the state transition of the digital filter 100 to control the execution order of each stage in the filtering process of the digital filter 100, thereby ensuring that the digital filter 100 can correctly process the input samples and output the expected output samples. The first-in first-out control circuit 131 has a first-in first-out feature for reading data from the single-port RAM or writing data to the single-port RAM.

[0069] like Figure 2As shown, the digital filter 100 of the present application has multiple states, namely, an idle state, a preload state, a data distribution state, and a data collection state. Among them, the idle state refers to a state in which the digital filter 100 has neither input samples nor output samples. In the idle state, the digital filter 100 usually does not perform any processing or calculation, and the digital filter 100 usually waits for an external signal or instruction or command to start a new filtering operation. The preload state usually refers to a state in which the digital filter 100 performs some preparatory work such as loading initial parameters or data before starting filtering, which may involve the initialization and preparation of the digital filter 100 so that it can start processing data immediately when entering the working state. The data distribution state refers to a state in which the digital filter 100 distributes the data to different computing units 121 for preliminary data processing after receiving the data. The data collection state refers to a state in which the results output by the computing unit 121 are collected for further processing to obtain output samples.

[0070] The state machine describes the behavior of the digital filter 100 under different input conditions through a state transition diagram or a state transition table, thereby realizing complex sequential control. The state machine ensures that the digital filter 100 can efficiently and accurately process input samples and output expected output samples by controlling state transitions and coordinating signal actions.

[0071] When the state machine in the controller receives a preload command (preload) forwarded by the read / write port of the single-port RAM, the state machine switches from the idle state to the preload state, and the first-in-first-out control circuit 131 in the control module 130 accesses the single-port RAM to write the filter coefficients and part or all of the input samples corresponding to the current filter task into the same storage block of the storage area of ​​the single-port RAM. In the preload state, the first-in-first-out control circuit 131 of the control module 130 can access the single-port RAM through software or DMA (Direct Memory Access), so as to store the filter coefficients and part or all of the input samples in the single-port RAM.

[0072] Of course, in order to improve the management efficiency and flexibility of the single-port RAM, the storage area of ​​the single-port RAM of the present application can be divided into several fixed-size or variable-size storage blocks, and each storage block can perform data access operations independently. When the state machine in the controller receives the preload command forwarded by the read-write port of the single-port RAM, the state machine switches from the idle state to the preload state, and the first-in-first-out control circuit 131 in the control module 130 accesses the single-port RAM to write the filter coefficient corresponding to the current filtering task into the first storage block stored in the single-port RAM, and write the input sample corresponding to the current filtering task into the second storage block stored in the single-port RAM. The embodiment of the present application can reduce data access conflicts, reduce data transmission delays and conflicts, significantly improve data processing speed and computing efficiency, optimize the utilization of hardware resources, and improve the overall performance and filtering efficiency of the digital filter 100.

[0073] Reference Figure 1 and Figure 3 As shown, the present application provides a digital filter 100, Figure 1 is a structural diagram of a digital filter 100 in an embodiment of the present application, Figure 3 FIG. 1 is a schematic diagram of a circuit structure of a digital filter 100 in an embodiment of the present application. Figure 1 and Figure 3 As shown, the calculation unit 121 includes a multiplier 1213, a first adder 1214, a first register 1211, a second register 1212 and a third register 1215, the first register 1211 and the second register 1212 are connected in parallel and connected between the single-port random access memory 110 and the multiplier 1213, and the first adder 1214 is connected between the multiplier 1213 and the third register 1215;

[0074] The control module 130 is further configured to read at least two of the sub-data groups corresponding to the current filtering task from the single-port random access memory 110 when switching from the pre-loading state to the data distribution state, and store the filter sub-coefficients in the read sub-data groups into the first register 1211, and store the input sub-samples in the read sub-data groups into the second register 1212;

[0075] The control module 130 is further used to traverse and search for the computing unit 121 in the idle state among the multiple computing units 121, and send the sub-data group corresponding to the current filtering task to the multiplier 1213 of the computing unit 121 in the idle state; one sub-data group corresponds to the multiplier 1213 of the computing unit 121 in the idle state;

[0076] The multiplier 1213 substitutes the filter sub-coefficient and the input sub-sample in the sub-data group into the following formula to obtain a corresponding product result;

[0077] W k =b k *x k ;

[0078] The first adder 1214 substitutes the multiplication result and the first accumulated value stored in the third register 1215 into the following formula to obtain an updated first accumulated value;

[0079] E k =W k +E k-1 ;

[0080] The third register 1215 stores the first accumulated value, and replaces the first accumulated value with the updated first accumulated value;

[0081] The control module 130 is further configured to take the last updated first accumulated value read from the third register 1215 as the final result; the last updated first accumulated value is the sum of all the product results corresponding to all the sub-data groups corresponding to the current filtering task and the first preset initial value stored in the third register 1215;

[0082] Among them, W k is the kth product result corresponding to the current filtering task, b k is the kth filter coefficient of the filter parameter group corresponding to the current filter task, x k is the kth input subsample of the filter parameter group corresponding to the current filter task, E k is the first accumulated value after the update, E k-1 is the first accumulated value stored in the third register 1215 , k is a positive integer, and E0 is the first preset initial value stored in the third register 1215 .

[0083] Specifically, when the state machine in the controller receives the filtering start command forwarded by the read / write port of the single-port RAM, Figure 2As shown, the state machine switches from the preload state to the data distribution state, and the first-in-first-out control circuit 131 in the control module 130 accesses the single-port RAM to read at least two sub-data groups corresponding to the current filtering task from the single-port RAM. Then, the control module 130 will detect in real time whether all the computing units 121 in the operation module 120 are in an idle state at each moment in turn or polling. If they are in an idle state, they will be marked. The first-in-first-out control circuit 131 in the control module 130 will send the at least two sub-data groups corresponding to the current filtering task to the multipliers 1213 of at least two computing units 121 in an idle state, that is, the first-in-first-out control circuit 131 sends one sub-data group corresponding to the current filtering task to the multiplier 1213 of a computing unit 121 in an idle state, and sends another sub-data group corresponding to the current filtering task to the multiplier 1213 of another computing unit 121 in an idle state. After receiving a sub-data group of the current filtering task sent by the first-in-first-out control circuit 131 of the control module 130 in the current period, the multiplier 1213 multiplies a filter sub-coefficient and an input sub-sample of the sub-data group of the current filtering task received by the multiplier 1213 to obtain a product result and transmits it to the first adder 1214. Of course, if the multiplier 1213 receives another sub-data group of the current filtering task sent by the first-in-first-out control circuit 131 of the control module 130 in the next period, it multiplies another filter sub-coefficient and another input sub-sample of the other sub-data group of the current filtering task received by the multiplier 1213 to obtain another product result and transmit it to the first adder 1214. In short, one product result corresponds to a filter sub-coefficient and an input sub-sample in a sub-data group. The first adder 1214 adds the kth product result output by the connected multiplier 1213 to the first accumulated value stored in the connected third register 1215 to obtain an updated first accumulated value. The first accumulated value stored in the third register 1215 in the initial state is the first preset initial value E0. After receiving a multiplication result transmitted from the multiplier 1213 at the first moment, the first adder 1214 adds the received multiplication result to the first preset initial value stored in the third register 1215 to obtain an updated first cumulative value. After receiving another multiplication result transmitted from the multiplier 1213 at the second moment, the first adder 1214 adds the received another multiplication result to the updated first cumulative value stored in the third register 1215 to obtain the latest updated first cumulative value, until the last multiplication result calculated by the multipliers 1213 of all the computing units 121 participating in the current filtering task according to the last received sub-data group is added, and the obtained data is the result of the current computing unit 121, i.e., the final result. In short, the values ​​of the multiplier 1213, the first adder 1214, and the third register 1215 will change.

[0084] For example, assuming that the operation module 120 includes 10 parallel computing units 121, 4 computing units 121 are selected according to demand to participate in the current filtering task, an input sample and a filter coefficient corresponding to the current filtering task are divided into 60 times to be read from the single-port RAM, which is equivalent to an input sample being divided into 60 input sub-samples, and a filter coefficient being divided into 60 filter sub-coefficients, which is a total of 60 sub-data groups. The 60 sub-data groups are distributed to the selected 4 computing units 121 multiple times, and the number of sub-data groups distributed to each computing unit 121 can be the same (for example, each computing unit 121 is distributed 15 sub-data groups for time-sharing calculation). It can also be different, the first accumulated value obtained by the calculation unit 121 performing k multiplication and addition calculations on the k sub-data groups corresponding to all received current filtering tasks is the final result, that is, the calculation unit 121 multiplies all received current filtering tasks corresponding to the k sub-data groups k times respectively to obtain k product results, and the first accumulated value obtained by adding the k product results and the first preset initial value stored in the third register 1215 is the final result, wherein the calculation unit 121 is in an idle state before passing a sub-data group to the calculation unit 121 for multiplication and addition calculation (the multiplier 1213 performs the product calculation, and the first adder 1214 performs the addition calculation).

[0085] After the control module 130 receives the start filtering command (start), the state machine switches to the data distribution state and starts the filtering process. In the data distribution state, the first-in-first-out control circuit 131 of the control module 130 can access the single-port RAM through software or DMA, that is, in the data distribution state, the control module 130 can write input samples to the single-port RAM or read output samples from the single-port RAM. Secondly, in the data distribution state, the control module 130 will take turns or poll in real time to detect whether the multiple computing units 121 participating in the current filtering task in the operation module 120 are in an idle state. When a computing unit 121 is idle, a sub-data group (that is, a pair of input sub-samples and filter sub-coefficients) is read from the single-port RAM to the idle computing unit 121 for multiplication and addition operations, until all the data required for an output sample is distributed (that is, one filter coefficient of the filter parameter group of the current filtering task corresponds to all filter sub-coefficients and one input sample corresponds to all sub-input samples), the state machine switches to the data collection state.

[0086] In some embodiments, Figure 1 and Figure 3 As shown, the control module 130 further includes a selector 132, a second adder 133 and a fourth register 134, the selector 132 is connected to the plurality of third registers 1215, and the second adder 133 is connected between the selector 132 and the fourth register 134;

[0087] The control module 130 is further used to traverse and detect whether the calculation unit 121 participating in the current filtering task is in an idle state at the current moment when switching from the data distribution state to the data collection state, and to pass the final result to the calculation unit 121 of the second adder 133 to clear it and mark it as a completed state;

[0088] The selector 132 reads the final result from the third register 1215 in the target computing unit 121 until the final results in all the computing units 121 participating in the current filtering task are read, and the target computing unit 121 is the computing unit 121 that is in the idle state at the current moment and participates in the current filtering task;

[0089] The second adder 133 substitutes the final result and the second accumulated value stored in the fourth register 134 into the following formula to obtain an updated second accumulated value:

[0090] Q k =E k +Q k-1 ;

[0091] The fourth register 134 stores the second accumulated value, and replaces the second accumulated value with the updated second accumulated value;

[0092] The control module 130 is further configured to use the last updated second accumulated value read from the fourth register 134 as the output sample; the last updated second accumulated value is the sum of all the final results of all the calculation units 121 participating in the current filtering task and the second preset initial value stored in the fourth register 134;

[0093] Among them, Q k is the updated second accumulated value, Q k-1 is the second accumulated value stored in the fourth register 134, E k is the final result stored in the kth third register 1215 , k is a positive integer, and Q0 is the second preset initial value stored in the fourth register 134 .

[0094] Specifically, Figure 2As shown, the state machine switches from the data distribution state to the data collection state. In the data collection state, the first-in first-out control circuit 131 of the control module 130 can access the single-port RAM by software or DMA, that is, in the data collection state, the control module 130 can write input samples to the single-port RAM or read output samples from the single-port RAM. The control module 130 will take turns or poll in real time to detect whether all the computing units 121 participating in the current filtering task in the operation module 120 are in an idle state at the current moment. If only one computing unit 121 participating in the current filtering task is in an idle state at the current moment, the selector 132 of the control module 130 will send the final result of the third register 1215 of the computing unit 121 that is in an idle state at the current moment to the second adder 133 of the last level, and then the first-in first-out control circuit 131 will clean up the data of the computing unit 121 that has transmitted the final result and mark it as a completed state. If at the current moment, at least two computing units 121 participating in the current filtering task are in an idle state, the selector 132 of the control module 130 will select one from the at least two computing units 121 participating in the current filtering task that are in an idle state at the current moment, and send the final result of the third register 1215 of the selected computing unit 121 to the second adder 133 of the last level, and then the first-in-first-out control circuit 131 cleans up the data of the computing unit 121 that has transmitted the final result and marks it as completed. At the next moment, the control module 130 repeats the above process until the final results in the third registers 1215 of all computing units 121 participating in the current filtering task are transmitted to the second adder 133 for calculation. After receiving a final result selected and transmitted by the selector 132 at the first moment, the second adder 133 adds the received final result to the second accumulated value stored in the fourth register 134 to obtain an updated second accumulated value. After receiving another final result selected and transmitted by the selector 132 at the second moment, the second adder 133 adds the received another final result to the updated second accumulated value stored in the fourth register 134 to obtain the latest updated second accumulated value, until the final results in the third register 1215 of all the calculation units 121 participating in the current filtering task are added, the obtained data is the output sample corresponding to the current filtering task. After the final results of all the calculation units 121 and the second preset initial value are accumulated to obtain the final accumulated value, the final accumulated value will be written to the single-port RAM, and the state machine switches from the data collection state to the data distribution state, so as to start the filtering calculation of the next input sample to obtain the corresponding output sample.

[0095] For example, continuing the above example, 4 computing units 121 are selected from 10 computing units 121 to participate in the current filtering task according to the requirements, and the selector 132 reads the final results from the 4 computing units 121 participating in the current filtering task 4 times, and adds the 4 final results corresponding to each of the 4 computing units 121 and the second preset initial value stored in the fourth register 134 to obtain the output sample. The computing unit 121 that is read before the final result is read from the computing unit 121 is in an idle state.

[0096] In some embodiments, Figure 1 and Figure 3 As shown, the control module 130 includes a plurality of control switches, the number of the control switches is the same as the number of the computing units 121, and the plurality of control switches are connected to the plurality of computing units 121 in a one-to-one correspondence; the read and write ports of the single-port random access memory 110 are connected to the corresponding computing units 121 through the control switches:

[0097] The control module 130 is also used to select the computing unit 121 in the idle state that participates in the current filtering task, and output a selection signal to the control switch connected to the selected computing unit 121 in the idle state to connect the read-write port with the selected computing unit 121.

[0098] Specifically, Figure 3 As shown, the multiple control switches of the control module 130 are connected to the multiple computing units 121 of the operation module 120 in a one-to-one correspondence, that is, one control switch is connected in series with one computing unit 121, and there is a one-to-one mapping relationship between the multiple control switches and the multiple computing units 121. The control module 130 can select any number of idle computing units 121 participating in the current filtering task according to the data size of the filter coefficients and input samples included in the filter parameter group corresponding to the current filtering task. Since the control switch is connected in series with the computing unit 121, a selection signal can be output to the control switch connected to the selected computing unit 121 in the idle state, so that the control switch connected to the selected computing unit 121 in the idle state is turned on or opened, thereby connecting the selected computing unit 121 in the idle state to the read and write port of the single-port RAM. Then, the control module 130 will pass the filter coefficients and input samples included in the filter parameter group corresponding to the current filtering task to the selected computing unit 121 in the idle state. In summary, the control module 130 will sequentially transfer the filter coefficients and input samples included in the filter parameter group corresponding to the current filter task to the selected computing unit 121 in the idle state according to the idle state of the selected computing unit 121 .

[0099] Among them, the number of control switches that are turned on or selected to be turned on may be positively correlated with the data size corresponding to the current filtering task, that is, the larger the data size corresponding to the current filtering task, the larger the number of control switches that are turned on, and the more the number of computing units 121 participating in the current filtering task, and vice versa, the smaller the data size corresponding to the current filtering task, the smaller the number of control switches that are turned on, and the fewer the number of computing units 121 participating in the current filtering task. The more the number of computing units 121 participating in the current filtering task, the faster the calculation speed.

[0100] Continuing with the above example, 6 idle computing units 121 are selected from 10 computing units 121 according to demand to participate in the current filtering task. These 6 computing units 121 are the selected computing units 121 participating in the current filtering task. The control module 130 will continuously poll the status of the 6 selected computing units 121 in sequence. During the polling process, if it is found that the status of the selected computing units 121 is idle, it will send out a corresponding selection signal, and transfer a sub-data group included in the filtering parameter group corresponding to the current filtering task to the selected computing unit 121 in FIFO order. The multiplier 1213 and the first adder 1214 of the computing unit 121 are always in working state. After the computing unit 121 receives a sub-data group, it will get a corresponding calculation result as an output sample after a certain period of time.

[0101] In some embodiments, the control module 130 accesses the single-port random access memory 110 through software or direct memory access.

[0102] Specifically, software access to the single-port random access memory 110 refers to writing program code and executing a series of instructions to read and write data to the single-port RAM. Direct memory access, or DMA, is an efficient data transmission technology that allows external devices to directly exchange data with the single-port RAM. In DMA mode, data transmission is managed by the DMA controller, allowing multiple external hardware devices to access the single-port RAM at the same time, thereby improving data transmission efficiency.

[0103] In some embodiments, the storage depth of the first storage block is the same as the number of the filter sub-coefficients corresponding to the current filtering task, and the storage depth of the second storage block is greater than or equal to the number of the filter sub-coefficients corresponding to the current filtering task.

[0104] Specifically, the storage depth of a storage block refers to the number of data points that can be stored in the memory, and is usually used to describe the storage capacity of devices such as oscilloscopes. The storage depth of the first storage block is equal to the number of filter coefficients corresponding to the current filtering task, and the storage depth of the second storage block is greater than or equal to the number of filter coefficients corresponding to the current filtering task. It should be noted that after all filter coefficients are written in the preloading stage, the first storage block will no longer be written until the next filtering task is restarted. The full flag of the second storage block means that the storage space is full of valid data, and the empty flag of the second storage block means that the input samples required for subsequent filtering operations stored in the storage space are less than the number of filter coefficients.

[0105] Assuming that the digital filter 100 is an FIR (Finite Impulse Response) in the following embodiment, the storage depth of the first storage block is equal to the number of feedforward filter coefficients, and the storage depth of the second storage block is greater than or equal to the number of feedforward filter coefficients. Assuming that the digital filter 100 is an IIR (Infinite Impulse Response) in the following embodiment, the storage depth of the first storage block is equal to the sum of the number of feedforward filter coefficients and the feedback filter coefficients, and the storage depth of the second storage block is greater than or equal to the sum of the number of feedforward filter coefficients and the feedback filter coefficients. Both the first storage block and the second storage block are accessed in the order of FIFO.

[0106] In some embodiments, the number of the filter sub-coefficients corresponding to the current filtering task is the same as the order of the filter coefficients corresponding to the current filtering task.

[0107] Specifically, the order of the filter coefficient refers to the complexity and performance index of the filter when processing the signal. The order of the filter coefficient is usually expressed as the number of the highest order derivative in the filter transfer function, or the order of the highest order differential term in the filter causal differential equation. Among them, the higher the order, the stronger the filter's signal processing ability, the more finely it can adjust the characteristics of the signal, and effectively filter out more noise and interference. In the digital filter 100, the order is also often used to describe the number of the highest power of z in the z-transform function of the filter. The higher the order, the steeper the frequency response of the filter, and the stronger the suppression ability of the out-of-band signal. In summary, the order of the filter coefficient is an important parameter for measuring the performance and complexity of the filter, which determines the effect and resource consumption of the filter in signal processing. The number of filter coefficients corresponding to the current filtering task is the same as the order of the filter coefficient corresponding to the current filtering task.

[0108] Assuming that the digital filter 100 is an FIR (Finite Impulse Response) filter in the following embodiment, the order of the feedforward sub-filter coefficient corresponding to the current filtering task is N, and the number of the feedforward filter sub-coefficients corresponding to the current filtering task is equal to N. Continuing with the above embodiment, the storage depth of the first storage block is equal to N, and the storage depth of the second storage block is greater than or equal to N. Assuming that the digital filter 100 is an IIR (Infinite Impulse Response) filter in the following embodiment, the order of the feedforward sub-filter coefficient corresponding to the current filtering task is N, and the order of the feedback sub-filter coefficient corresponding to the current filtering task is M. Therefore, the number of the feedforward filter sub-coefficients corresponding to the current filtering task is equal to N, and the number of the feedback filter sub-coefficients corresponding to the current filtering task is equal to M. Continuing with the above embodiment, the storage depth of the first storage block is equal to M+N, and the storage depth of the second storage block is greater than or equal to M+N.

[0109] In some embodiments, the digital filter 100 is a finite impulse response filter.

[0110] Specifically, the filter sub-coefficients of the current filtering task corresponding to FIR include N feedforward sub-coefficients, and the output samples include N output sub-samples. The algorithm formula for the filtering operation corresponding to FIR is:

[0111]

[0112] Where N is the feedforward coefficient of the FIR, b k is the kth feedforward sub-coefficient of the FIR corresponding to the current filtering task, x n-k is the kth input subsample corresponding to the current filtering task of FIR, y n It is the output sample corresponding to the current filtering task of FIR.

[0113] In some embodiments, the filter coefficients include feedforward coefficients, the filter sub-coefficients include feedforward sub-coefficients, the input samples include a current input signal, the input sub-samples include an input sub-signal and a previous output sub-sample, and the output samples include a current output signal.

[0114] In some embodiments, the digital filter 100 is an infinite impulse response filter.

[0115] Specifically, the filter sub-coefficients of the current filtering task corresponding to IIR include N feedforward sub-coefficients and M feedback sub-coefficients. For IIR, the corresponding filtering operation algorithm formula is:

[0116]

[0117] Where N is the order of the IIR feedforward coefficient, M is the order of the IIR feedback coefficient, and b k is the kth feedforward sub-coefficient of IIR corresponding to the current filtering task, k is the kth feedback sub-coefficient of the IIR corresponding to the current filtering task, x n-k is the kth input subsample corresponding to the current filtering task by IIR, y n is the output sample of IIR corresponding to the current filtering task, y n-k It is the kth output subsample in the kth filter parameter group corresponding to the current filtering task of FIR.

[0118] In some embodiments, the filter coefficient includes a feedforward coefficient and a feedback coefficient, the filter sub-coefficient includes a feedforward sub-coefficient and a previous feedback sub-coefficient in the previous filter parameter group, the input sample includes an input signal and a previous input sample in the previous filter parameter group, the input sub-sample includes an input sub-signal and a previous output sub-sample, and the output sample includes a current output signal.

[0119] In some embodiments, the control module 130 is also used to detect whether a preset value exists in the current sub-data group. If the preset value exists in the current sub-data group, it directly switches to detect whether the preset value exists in the next sub-data group. If the preset value does not exist in the current sub-data group, the current sub-data group is sent to the computing unit 121 in an idle state.

[0120] Specifically, the first-in-first-out control circuit 131 controls the slave computing unit 121a, computing unit 121b, computing unit 121i, ..., computing unit 121p in the data distribution state, and continuously queries its status in turn. When there is an idle computing unit 121, a control signal is sent to transfer the input sub-sample and feedforward sub-coefficient, the calculated output sample and feedback sub-coefficient from the single-port RAM to the idle computing unit 121 in turn. The preset value is 0, that is, it is detected whether the binary filter sub-coefficient in the current sub-data group is equal to 0, and whether the binary input sub-coefficient in the current sub-data group is equal to 0. If so, the current sub-data group is discarded, and the next sub-data group is switched to continue to detect whether there is a preset value. Of course, if it is not equal to 0, the current sub-data group is sent to the idle computing unit 121 according to the above embodiment. In this way, unnecessary calculations are reduced, thereby accelerating the calculation speed and improving the filtering efficiency.

[0121] In some embodiments, the single-port random access memory further includes a third storage block for storing the output samples, and a storage depth of the third storage block is greater than or equal to a first preset value.

[0122] Specifically, assuming that the digital filter 100 is FIR, the first preset value is 1. Assuming that the digital filter is IIR, the first preset value is equal to the order of the feedback sub-filter coefficient, that is, the first preset value is M.

[0123] The present application provides a design method for a digital filter based on a single-port RAM with filter coefficients, orders and multiplication-addition parallelism. The digital filter is composed of a single-port RAM, a multiplication-addition operation group (i.e., a plurality of parallel computing units of the present application), and a control circuit, etc., and can realize FIR, IIR digital filtering operations and vector operations and finite-length series convolution operations, and the filter coefficients, orders, and multiplication-addition parallelism are configurable, so various FIR digital filtering operations can be realized. Among them, the multiplication-addition parallelism is determined by the number of units contained in the multiplication-addition operation group. The circuit structure proposed in the present application supports arbitrary expansion of multiplication-addition units and software configurability to meet the requirements of different speeds and areas. Secondly, by selecting a single-port RAM as the storage medium, the RAM IP of various process libraries can be directly called for instantiation, and the filter can be easily realized. The method proposed in the present application is to store input samples, output samples and filter coefficients in a single-port RAM, and the control circuit continuously sends control signals to take out the data from the RAM and continuously distribute it to the multiplication and addition units for multiplication and accumulation operations. After the calculation is completed, the calculation results of all the multiplication and addition units are summed to obtain an output sample, and the output sample is written back to the RAM. In this way, continuous calculation is performed until the filtering operation stops. During this period, new input samples will be added to the RAM and the calculated output samples will be read by software or DMA. The digital filter of the present application takes into account the different requirements of speed and area, and achieves software and hardware configurability of parallelism, and realizes configurable filter coefficients and orders, so that various filtering operations can be flexibly and repeatedly implemented.

[0124] The present application also provides a filtering processing method, which is applied to a digital filter 100, wherein the digital filter 100 comprises: a single-port random access memory 110, a calculation module 120 and a control module 130, wherein the calculation module 120 is connected between the single-port random access memory 110 and the control module 130, and the control module 130 is also connected to the single-port random access memory 110, and the calculation module 120 comprises a plurality of parallel calculation units 121; the method comprises:

[0125] The control module 130 writes the filter parameter group corresponding to the current filter task into the single-port random access memory 110; each of the filter parameter groups includes a filter coefficient and an input sample;

[0126] The control module 130 reads sub-data groups from the single-port random access memory 110 in a first-in first-out order and distributes the sub-data groups to the computing unit 121 in an idle state, each of the sub-data groups includes a filter sub-coefficient and an input sub-sample, the filter sub-coefficient is a part of the filter coefficient, and the input sub-sample is a part of the input sample;

[0127] The control module 130 obtains corresponding output samples according to the final results of the calculation units 121 participating in the current filtering task, and writes the output samples into the single-port random access memory 110 .

[0128] The digital filter 100 and the filtering processing method provided in the embodiments of the present application are introduced in detail above. The principles and implementation methods of the present application are explained in this article by using specific examples. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A digital filter, characterized in that: include: A single-port random access memory, a computing module and a control module, wherein the computing module is connected between the single-port random access memory and the control module, the control module is also connected to the single-port random access memory, and the computing module includes a plurality of parallel computing units; The control module writes the filter parameter group corresponding to the current filter task into the single-port random access memory; each of the filter parameter groups includes a filter coefficient and an input sample; The control module is further used to read sub-data groups from the single-port random access memory in a first-in first-out order and distribute them to the computing units in an idle state, each of the sub-data groups includes a filter sub-coefficient and an input sub-sample, the filter sub-coefficient is a part of the filter coefficient, and the input sub-sample is a part of the input sample; The control module is further used to obtain corresponding output samples according to the final results of the calculation units participating in the current filtering task, and write the output samples into the single-port random access memory; The computing unit includes a multiplier, a first adder, a first register, a second register and a third register, wherein the first register and the second register are connected in parallel and between the single-port random access memory and the multiplier, and the first adder is connected between the multiplier and the third register; The control module is further configured to read at least two of the sub-data groups corresponding to the current filtering task from the single-port random access memory when switching from the pre-loading state to the data distribution state, and store the filter sub-coefficients in the read sub-data groups into the first register, and store the input sub-samples in the read sub-data groups into the second register; The control module is further used to traverse and search for the computing unit in the idle state among the plurality of computing units, and send the sub-data group corresponding to the current filtering task to the multiplier of the computing unit in the idle state; one sub-data group corresponds to the multiplier of one computing unit in the idle state; The multiplier substitutes the filter coefficient and the input sub-sample in the sub-data group into the following formula to obtain a corresponding product result; W k =b k *x k ; The first adder substitutes the multiplication result and the first accumulated value stored in the third register into the following formula to obtain an updated first accumulated value; HAVE BEEN k =W k +E k-1 ; The third register stores the first accumulated value, and replaces the first accumulated value with the updated first accumulated value; The control module is further configured to take the last updated first accumulated value read from the third register as the final result; the last updated first accumulated value is the sum of all the product results corresponding to all the sub-data groups corresponding to the current filtering task and the first preset initial value stored in the third register; Among them, W k is the kth product result corresponding to the current filtering task, b k is the kth filter coefficient of the filter parameter group corresponding to the current filter task, x k is the kth input subsample of the filter parameter group corresponding to the current filter task, E k is the first accumulated value after the update, E k-1 is the first accumulated value stored in the third register, k is a positive integer, and E0 is the first preset initial value stored in the third register.

2. The digital filter according to claim 1, characterized in that The single-port random access memory comprises a first storage block for storing the filter coefficients and a second storage block for storing the input samples; The control module is further configured to write the filter coefficient corresponding to the current filter task into the first storage block, and write the input sample corresponding to the current filter task into the second storage block when switching from the idle state to the preloaded state.

3. The digital filter according to claim 1, characterized in that The control module further comprises a selector, a second adder and a fourth register, wherein the selector is connected to a plurality of the third registers, and the second adder is connected between the selector and the fourth register; The control module is further used for, when switching from the data distribution state to the data collection state, traversing and detecting whether the computing units participating in the current filtering task are in the idle state at the current moment, and passing the final result to the computing unit of the second adder to be cleared and marked as completed; The selector reads the final result from the third register in the target computing unit until the final results in all the computing units participating in the current filtering task are read, and the target computing unit is the computing unit that is in the idle state at the current moment and participates in the current filtering task; The second adder substitutes the final result and the second accumulated value stored in the fourth register into the following formula to obtain an updated second accumulated value; Q k =E jk ’+Q k-1 ; The fourth register stores the second accumulated value, and replaces the second accumulated value with the updated second accumulated value; The control module is further configured to use the last updated second accumulated value read from the fourth register as the output sample; the last updated second accumulated value is the sum of all the final results of all the calculation units participating in the current filtering task and the second preset initial value stored in the fourth register; Among them, Q k is the updated second accumulated value, Q k-1 is the second accumulated value stored in the fourth register, E jk ' is the final result stored in the jth third register, j is a positive integer, and Q0 is the second preset initial value stored in the fourth register.

4. The digital filter according to claim 1, characterized in that The control module includes a plurality of control switches, the number of the control switches is the same as the number of the computing units, and the plurality of control switches are connected to the plurality of computing units in a one-to-one correspondence; the read and write ports of the single-port random access memory are connected to the corresponding computing units through the control switches: The control module is also used to select the computing unit in the idle state that participates in the current filtering task, and output a selection signal to the control switch connected to the selected computing unit in the idle state to connect the read and write port with the selected computing unit.

5. The digital filter according to claim 1, characterized in that: The control module accesses the single-port random access memory through software or direct memory access.

6. The digital filter according to claim 2, characterized in that: The storage depth of the first storage block is the same as the number of the filter sub-coefficients corresponding to the current filtering task, and the storage depth of the second storage block is greater than or equal to the number of the filter sub-coefficients corresponding to the current filtering task.

7. The digital filter according to any one of claims 1 to 6, characterized in that: The number of the filter sub-coefficients corresponding to the current filtering task is the same as the order of the filter coefficients corresponding to the current filtering task.

8. The digital filter according to claim 7, characterized in that: The digital filter is a finite impulse response filter.

9. The digital filter according to claim 8, characterized in that: The filter coefficients include feedforward coefficients, the filter sub-coefficients include feedforward sub-coefficients, the input samples include current input signals, the input sub-samples include input sub-signals and previous output sub-samples, and the output samples include current output signals.

10. The digital filter according to claim 7, characterized in that: The digital filter is an infinite impulse response filter.

11. The digital filter according to claim 10, characterized in that: The filter coefficients include feedforward coefficients and feedback coefficients, the filter sub-coefficients include feedforward sub-coefficients and previous feedback sub-coefficients in the previous filter parameter group, the input samples include input signals and previous input samples in the previous filter parameter group, the input sub-samples include input sub-signals and previous output sub-samples, and the output samples include current output signals.

12. The digital filter according to any one of claims 9 to 11, characterized in that: The control module is further used to detect whether a preset value exists in the current sub-data group. If the preset value exists in the current sub-data group, directly switch to detect whether the preset value exists in the next sub-data group. If the preset value does not exist in the current sub-data group, send the current sub-data group to the calculation unit in the idle state.

13. The digital filter according to claim 1, characterized in that: The single-port random access memory also includes a third storage block for storing the output samples, and a storage depth of the third storage block is greater than or equal to a first preset value.

14. A filtering processing method, characterized in that: The invention is applied to a digital filter, wherein the digital filter comprises: a single-port random access memory, a calculation module and a control module, wherein the calculation module is connected between the single-port random access memory and the control module, and the control module is also connected to the single-port random access memory, and the calculation module comprises a plurality of parallel calculation units; the method comprises: The control module writes the filter parameter group corresponding to the current filter task into the single-port random access memory; each of the filter parameter groups includes a filter coefficient and an input sample; The control module reads sub-data groups from the single-port random access memory in a first-in first-out order and distributes the sub-data groups to the computing units in an idle state, each of the sub-data groups includes a filter sub-coefficient and an input sub-sample, the filter sub-coefficient is a part of the filter coefficient, and the input sub-sample is a part of the input sample; The control module obtains corresponding output samples according to the final results of the calculation units participating in the current filtering task, and writes the output samples into the single-port random access memory; The computing unit includes a multiplier, a first adder, a first register, a second register and a third register, wherein the first register and the second register are connected in parallel and between the single-port random access memory and the multiplier, and the first adder is connected between the multiplier and the third register; The control module is further configured to read at least two of the sub-data groups corresponding to the current filtering task from the single-port random access memory when switching from the pre-loading state to the data distribution state, and store the filter sub-coefficients in the read sub-data groups into the first register, and store the input sub-samples in the read sub-data groups into the second register; The control module is further used to traverse and search for the computing unit in the idle state among the plurality of computing units, and send the sub-data group corresponding to the current filtering task to the multiplier of the computing unit in the idle state; one sub-data group corresponds to the multiplier of one computing unit in the idle state; The multiplier substitutes the filter coefficient and the input sub-sample in the sub-data group into the following formula to obtain a corresponding product result; W k =b k *x k ; The first adder substitutes the multiplication result and the first accumulated value stored in the third register into the following formula to obtain an updated first accumulated value; HAVE BEEN k =W k +E k-1 ; The third register stores the first accumulated value, and replaces the first accumulated value with the updated first accumulated value; The control module is further configured to take the last updated first accumulated value read from the third register as the final result; the last updated first accumulated value is the sum of all the product results corresponding to all the sub-data groups corresponding to the current filtering task and the first preset initial value stored in the third register; Among them, W k is the kth product result corresponding to the current filtering task, b k is the kth filter coefficient of the filter parameter group corresponding to the current filter task, x k is the kth input subsample of the filter parameter group corresponding to the current filter task, E k is the first accumulated value after the update, E k-1 is the first accumulated value stored in the third register, k is a positive integer, and E0 is the first preset initial value stored in the third register.

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