Phase adjustment circuit and method and memory

Abstract

The embodiment of the invention discloses a phase adjustment circuit and method and a memory. The phase adjustment circuit includes: a multi-phase clock signal generator configured to generate an initial multi-phase clock signal, a phase error detector configured to detect a phase error of the initial multi-phase clock signal, and a phase error canceller configured to cancel a phase error of the initial multi-phase clock signal; the phase error detector is connected with the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signals to obtain error signals used for representing phase difference information among the initial multi-phase clock signals; the phase error eliminator is connected with the phase error detector and is configured to detect the error signal to obtain an error elimination code; and the multi-phase clock signal generator is also connected with the phase error eliminator and is configured to receive the error elimination code and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular to a phase adjustment circuit, method and memory. Background Art

[0002] In the related art, a circuit that operates based on a multi-phase clock signal usually generates a phase error during the transmission process of the multi-phase clock signal, which causes uncertainty in the circuit when performing related operations. Summary of the invention

[0003] Based on this, an embodiment of the present application provides a phase adjustment circuit, method and memory, which phase adjusts the initial multi-phase clock signal through an error elimination code corresponding to the phase error of the initial multi-phase clock signal to obtain a target multi-phase clock signal in which the phase difference between the clock signals meets preset requirements.

[0004] To achieve the above object, an embodiment of the present application provides a phase adjustment circuit, the phase adjustment circuit comprising: a multi-phase clock signal generator, a phase error detector and a phase error eliminator, wherein:

[0005] The multi-phase clock signal generator is configured to generate an initial multi-phase clock signal;

[0006] The phase error detector is connected to the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for representing phase difference information between the initial multi-phase clock signals;

[0007] The phase error eliminator is connected to the phase error detector and is configured to detect the error signal to obtain an error elimination code;

[0008] The multi-phase clock signal generator is also connected to the phase error eliminator, and is configured to receive the error elimination code, and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

[0009] The present application also provides a phase adjustment method, the phase adjustment method comprising:

[0010] Using a multi-phase clock signal generator to generate an initial multi-phase clock signal;

[0011] Using a phase error detector to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for representing phase difference information between the initial multi-phase clock signals;

[0012] Using a phase error eliminator to detect the error signal to obtain an error elimination code;

[0013] The multi-phase clock signal generator is used to perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

[0014] An embodiment of the present application further provides a memory, which at least includes the phase adjustment circuit described in any one of the above embodiments.

[0015] The embodiment of the present application provides a phase adjustment circuit, method and memory; the phase adjustment circuit includes: a multi-phase clock signal generator, a phase error detector and a phase error eliminator, wherein: the multi-phase clock signal generator is configured to generate an initial multi-phase clock signal; the phase error detector is connected to the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for characterizing the phase difference information between the initial multi-phase clock signals; the phase error eliminator is connected to the phase error detector and is configured to detect the error signal to obtain an error elimination code; the multi-phase clock signal generator is also connected to the phase error eliminator and is configured to receive the error elimination code, and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal. In this way, the initial multi-phase clock signal only needs to be phase adjusted by the error elimination code corresponding to the phase error of the initial multi-phase clock signal to obtain a target multi-phase clock signal whose phase difference between clock signals meets the preset requirements.

[0016] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions provided in the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology description are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work:

[0018] Figure 1 A schematic diagram of a delay-locked loop circuit that generates and outputs a four-phase clock signal in the related art;

[0019] Figure 2 A schematic diagram of the composition of a phase adjustment circuit provided in an embodiment of the present application;

[0020] Figure 3 A schematic diagram of the composition of another phase adjustment circuit provided in an embodiment of the present application;

[0021] Figure 4A A schematic diagram of the composition of the phase adjustment circuit provided in the embodiment of the present application for phase adjustment of a four-phase clock signal;

[0022] Figure 4B A schematic diagram corresponding to the transmission process of the four-phase clock signal in the phase adjustment circuit provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of the composition of another phase adjustment circuit provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of the composition of another phase adjustment circuit provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the composition of another phase adjustment circuit provided in an embodiment of the present application;

[0026] Figure 8 A schematic diagram of a duty cycle detector and an error elimination code generator in a phase adjustment circuit provided in an embodiment of the present application;

[0027] Fig. 9 A schematic diagram of another phase adjustment circuit provided in an embodiment of the present application;

[0028] Fig.10 A schematic diagram of a flow chart corresponding to the generation of a target multi-phase clock signal by a phase adjustment circuit provided in an embodiment of the present application;

[0029] Fig.11 A flow chart of a phase adjustment method provided in an embodiment of the present application;

[0030] Fig.12 A schematic diagram of the composition of a memory provided in an embodiment of the present application;

[0031] Description of reference numerals:

[0032] 1-memory; 10-phase adjustment circuit; 11-multi-phase clock signal generator; 111-delay device; 12-phase error detector; 121-first logic operation module; 122-second logic operation module; 13-phase error eliminator; 131-duty cycle detector; 1311-signal converter; 1312-voltage comparator; 132-error elimination code generator; 1321-synchronous counter; 1322-D flip-flop. DETAILED DESCRIPTION

[0033] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It is understandable that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only the parts related to the present application but not all structures are shown in the accompanying drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0034] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0035] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0036] In order to better understand the embodiments of the present application, the shortcomings existing in the related art are first described.

[0037] In the related art, a multi-phase clock signal (e.g., a two-phase clock signal, a four-phase clock signal, etc.) usually generates a phase error when being transmitted in a circuit, which may cause uncertainty in the read / write operation of the storage device in the circuit or cause a read / write error due to timing mismatch, and thus a phase error calibration of the multi-phase clock signal is required. Figure 1 As shown in the figure, it is a schematic diagram of a delay-locked loop (DLL) circuit corresponding to the generation and transmission of a four-phase clock signal in the related art. First, a pair of differential clock signals: CK_c and CK_t are input, where CK_t is a real clock signal and CK_c is its phase differential clock signal. Then, CK_c and CK_t are sequentially passed through a DLL circuit which includes at least: a clock buffer, a four-phase clock signal generator, a regulator for adjusting the phase of the clock signal, and an output circuit to realize the transmission of the four-phase clock signal. Among them, the four-phase clock signal generator usually includes a four-phase clock divider and a frequency regulator, such as Figure 1 The phase adjustment of the four-phase clock signal shown in the transmission process mainly relies on the DLL circuit, and the four-phase clock signal usually exists as a reference clock signal (internal clock signal). If there is a phase error between the clock signals, it will cause the related storage device to have problems such as sampling errors and timing conflicts during data read / write operations.

[0038] In order to solve the phase error problem of multi-phase clock signals in the DLL circuit transmission in the related art, the embodiment of the present application provides a phase adjustment circuit, which uses a phase error detector to detect the phase error of the initial multi-phase clock signal generated by the multi-phase clock signal generator, and obtains an error signal used to characterize the phase difference information between the initial multi-phase clock signals; uses a phase error eliminator to convert the error signal into a corresponding error elimination code, so that the multi-phase clock signal generator is used to directly adjust the phase of the initial multi-phase clock signal based on the error elimination code, so as to obtain a target multi-phase clock signal whose phase difference between the clock signals meets the preset requirements. In this way, the phase error calibration of the initial multi-phase clock signal can be achieved, and a multi-phase clock signal with an accurate relative phase relationship can be obtained, as well as an internal clock signal that is precisely synchronized with the external clock signal and accurate, thereby ensuring the accuracy of the relevant storage device in the data read / write operation link.

[0039] Figure 2 The schematic diagram of the composition of a phase adjustment circuit provided by an embodiment of the present application is shown. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a phase error detector 12 and a phase error eliminator 13, wherein:

[0040] The multi-phase clock signal generator 11 is configured to generate an initial multi-phase clock signal;

[0041] The phase error detector 12 is connected to the multi-phase clock signal generator 11 and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for representing phase difference information between the initial multi-phase clock signals;

[0042] The phase error eliminator 13 is connected to the phase error detector 12 and is configured to detect the error signal to obtain an error elimination code;

[0043] The multi-phase clock signal generator 11 is also connected to the phase error eliminator 13 and is configured to receive the error elimination code and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

[0044] Here, the phase adjustment circuit 10 includes but is not limited to: a multi-phase clock signal generator 11, a phase error detector 12, and a phase error eliminator 13. At the same time, the phase adjustment circuit 10 can be a partial circuit in the DLL circuit, or a circuit parallel to the DLL circuit. Here, the phase adjustment circuit 10 can be an adjustment circuit deployed in any memory 1 for adjusting the phase difference of the related clock signal or non-clock signal.

[0045] Here, the multi-phase clock signal generator 11 includes a frequency divider for frequency-dividing the input external clock signal to generate an initial multi-phase clock signal. The multi-phase clock signal generator 11 may also include an adjustment unit for performing phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal. Here, the adjustment unit may be a delay unit for adjusting the switching state of its delay unit based on the error elimination code, thereby achieving the delay time corresponding to the adjustment, so as to perform phase adjustment on the initial multi-phase clock signal based on the delay time to obtain a target multi-phase clock signal.

[0046] Here, the initial multi-phase clock signal refers to a plurality of initial clock signals with different phases and relative phase relationships, such as a two-phase clock signal, a four-phase clock signal, an eight-phase clock signal, etc. Based on this, the multi-phase clock signal generator can be composed of a multi-phase clock divider, a frequency adjuster, and a delayer for adjusting the phase of the multi-phase clock signal.

[0047] In the following other embodiments of the present application, the initial multi-phase clock signal is taken as an example to be described as a four-phase clock signal.

[0048] Here, the phase error detector 12 is connected to the multi-phase clock signal generator 11, which may include multiple logic operation modules for performing relevant logic operations on each clock signal in the four-phase clock signal, such as: AND operation, NOT operation, AND-NOT operation, etc., to determine the error information of the phase difference information between the clock signals of adjacent phases in the four-phase clock signal.

[0049] Here, the phase error eliminator 13 is connected to the phase error detector 12 and the multi-phase clock signal generator 11. The phase error eliminator 13 is used to detect the error signal output by the phase error detector 12 (for example: duty cycle detection, frequency detection, etc.) to obtain an error elimination code that can be recognized by the multi-phase clock signal generator 11; thereby, the multi-phase clock signal generator 11 can adjust the phase of the initial multi-phase clock signal (eliminate the phase error) based on the error elimination code to obtain a target multi-phase clock signal in which the phase difference between the clock signals meets the preset requirements.

[0050] It should be noted that the connections referred to in the present disclosure, such as the phase error detector 12 connected to the multi-phase clock signal generator 11, the phase error eliminator 13 connected to the phase error detector 12, and the multi-phase clock signal generator 11 also connected to the phase error eliminator 13, may be direct connections or indirect connections through other structures.

[0051] The phase adjustment circuit provided in the embodiment of the present application firstly uses a phase error detector 12 to perform phase error detection on the initial multi-phase clock signal generated by the multi-phase clock signal generator 11, and obtains an error signal for characterizing the phase difference information between the initial multi-phase clock signals. Secondly, a phase error eliminator 13 is used to convert the error signal into a corresponding error elimination code, so that the multi-phase clock signal generator 11 can directly perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal whose phase difference between the clock signals meets the preset requirements. In this way, the phase error calibration of the initial multi-phase clock signal can be achieved, and a multi-phase clock signal with an accurate relative phase relationship and an internal clock signal that is precisely synchronized with the external clock signal and accurate can be obtained, thereby ensuring the timing accuracy of the storage device in which the phase error adjustment circuit is located in the data read / write operation link.

[0052] In some embodiments, Figure 3 As shown, in the case where the phase error detector 12 includes: a first logic operation module 121 and a second logic operation module 122, first, the first logic operation module 121 is used to control the logic AND operation of each initial clock signal in the initial multi-phase clock signal through an enable signal to generate an intermediate signal, so that the initial logic operation of each initial clock signal is controllable, which is convenient for subsequent practical operations. Then, the second logic operation module 122 is used to perform a logic operation on the intermediate signals of adjacent phases in the intermediate signal output by the first logic operation module 121, so as to obtain an error signal for characterizing the phase difference information between the initial multi-phase clock signals. In this way, it is possible to achieve a controllable operation of each initial clock signal in the multi-phase clock signal, and to obtain an error signal for characterizing the phase difference information between the initial multi-phase clock signals more conveniently and accurately. Figure 3 A schematic diagram of another phase adjustment circuit provided in an embodiment of the present application is shown. The phase adjustment circuit 10 comprises: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122 and a phase error eliminator 13, wherein:

[0053] The first logic operation module 121 is configured to perform an AND operation on the received preset enable signal and each initial clock signal in the initial multi-phase clock signal to obtain an intermediate signal of each initial clock signal;

[0054] The second logic operation module 122 is configured to perform a logic operation on the intermediate signals of adjacent phases in the initial multi-phase clock signal to obtain the error signal.

[0055] Here, if Figure 4A As shown, a schematic diagram of the composition of the phase adjustment circuit provided in an embodiment of the present application for phase adjustment of a four-phase clock signal is shown. Wherein, the first logic operation module 121, when the initial multi-phase clock signal is a four-phase clock signal, includes four operation sub-units. Wherein, each operation sub-unit can be composed of an AND gate circuit (the AND gate circuit can be composed of a NAND gate circuit and a NOT gate circuit), and the operation sub-unit is used to perform an AND operation on a preset enable signal EN (that is, a trigger signal) and a corresponding initial clock signal to obtain an intermediate signal of each initial clock signal.

[0056] In the embodiment of the present application, the preset enable signal EN is valid at a high level.

[0057] In a possible implementation, the initial multi-phase clock signal includes a four-phase initial clock signal; the four-phase initial clock signal includes a first initial clock signal, a second initial clock signal, a third initial clock signal, and a fourth initial clock signal in sequence. Since there is a fixed phase relationship between the multi-phase clock signals, for example, the third initial clock signal is the inverted signal of the first initial clock signal, and the fourth initial clock signal is the inverted signal of the second initial clock signal. Therefore, the first error signal and the second error signal that can characterize the phase difference information between the four-phase initial clock signals can be obtained through the operation of the second logic operation module 122. In this way, the relevant execution logic in the second logic operation module 122 can be made simple, and only half of the signals can be used to represent the phase difference information between all the initial clock signals, which greatly saves the circuit area and the amount of information that needs to be processed. That is:

[0058] The second logic operation module 122 is also configured to perform a NAND operation on the intermediate signal of the first initial clock signal and the inverted signal of the intermediate signal of the second initial clock signal to obtain the first error signal, and to perform a NAND operation on the intermediate signal of the second initial clock signal and the inverted signal of the intermediate signal of the third initial clock signal to obtain the second error signal.

[0059] Here, if Figure 4AAs shown, the second logic operation module 122 includes at least two operation subunits, each of which is composed of a NOT gate circuit and a NAND gate circuit. The NOT gate circuit in each operation subunit can be used to obtain the inverted signal of the input related clock signal (for example, the intermediate signal of the second initial clock signal or the intermediate signal of the third initial clock signal), and then the NAND gate circuit in each operation subunit can be used to perform a NAND operation on the obtained inverted signal and the intermediate signal of the initial clock signal of the previous phase to obtain the first or second error signal.

[0060] Continuing from the above description, the second logic operation module 122 can also be used to perform a NAND operation on the intermediate signal of the third initial clock signal and the inverted signal of the intermediate signal of the fourth initial clock signal to generate a third error signal representing the phase difference information between the third initial clock signal and the fourth initial clock signal. Since there is a fixed phase relationship between the multi-phase clock signals (as mentioned above, the first clock signal and the third clock signal are mutually inverted signals, and the second clock signal and the fourth clock signal are mutually inverted signals), the first error signal and the second error signal mentioned above can already represent the phase difference between adjacent phase signals in the four-phase clock signal. In order to save circuit area and power consumption, in another embodiment of the present disclosure, the circuit for generating the third error signal may not be provided.

[0061] Here, if Figure 4B , which shows a schematic diagram corresponding to the four-phase clock signal in the phase adjustment circuit provided in the embodiment of the present application during the transmission process. In which, the four-phase initial clock signal is shown to include signals in sequence according to the phase order, namely: CLKI, CLKQ, CLKIB and CLKQB, and the phase difference between CLKI and CLKQ is shown: T I to Q , the phase difference between CLKQ and CLKIB: T Q to IB .

[0062] Furthermore, since there is a fixed phase relationship between the four-phase initial clock signals, the second logic operation module 122 can be used to perform a NAND operation only on the intermediate signal of CLKI and the inverted signal of the intermediate signal of CLKQ, and to perform a NAND operation on the intermediate signal of CLKQ and the inverted signal of the intermediate signal of CLKIB, and obtain the following: Figure 4B Shown: CLK representing the phase difference information between CLKI, CLKQ, CLKIB, and CLKQB I_Q and CLK Q_IB .

[0063] In addition, if Figure 4BAs shown, the clock signals input to the NAND gate of the second logic operation module 122 for NAND operation are: the intermediate signal of CLKI, the inverted signal of the intermediate signal of CLKQ, the intermediate signal of CLKQ, and the inverted signal of the intermediate signal of CLKIB.

[0064] In some embodiments, Figure 5 As shown, in the case where the phase error eliminator 13 includes: a duty cycle detector 131 and an error elimination code generator 132, the duty cycle detector 131 can be used to perform duty cycle detection on the error signal representing the phase difference information between the initial multi-phase clock signals to obtain a detection result, and then the error elimination code generator 132 is used to generate an error elimination code based on the detection result to eliminate the phase offset of the initial multi-phase clock signal. In this way, the corresponding phase error elimination code is generated by the duty cycle detection result corresponding to the error signal representing the phase difference information between the initial multi-phase clock signals, so that the overall execution logic of the phase adjustment circuit 10 is concise, and the target multi-phase clock signal finally obtained is more in line with the preset requirements. Figure 5 A schematic diagram of another phase adjustment circuit provided in an embodiment of the present application is shown, that is, the phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122, a duty cycle detector 131 and an error elimination code generator 132; wherein:

[0065] The duty cycle detector 131 is connected to the phase error detector 12 and is configured to perform duty cycle detection on the error signal to obtain a detection result;

[0066] The error elimination code generator 132 is connected to the duty cycle detector 131 and is configured to generate the error elimination code for phase adjustment of the initial multi-phase clock signal based on the detection result.

[0067] Here, the duty cycle detector 131 may be directly connected to the phase error detector 12 or indirectly connected. Similarly, the error elimination code generator 132 may be directly connected to the duty cycle detector 131 or indirectly connected. In addition, the error elimination code generator 131 is also connected to the multi-phase clock signal generator 11, and the connection relationship between them may also be directly connected or indirectly connected.

[0068] The duty cycle detector 131 may be used to perform duty cycle detection on the error signal (duty cycle=high level time / cycle time) to obtain a detection result that can be represented by a numerical value or a code.

[0069] Continuing from the above description, the initial multi-phase clock signal is a four-phase clock signal. After the phase error detection is performed by the phase error detector 12, the error signal obtained includes: a first error signal and a second error signal. Then, the duty cycle detector 131 can be used to perform duty cycle detection on the first error signal and the second error signal to obtain a detection result.

[0070] Here, the error elimination code generator 132 may be used to adjust the preset elimination code based on the detection result to obtain the error elimination code, or to generate an error elimination code matching the detection result. The preset elimination code may be a binary code pre-stored in the error elimination code generator 132 .

[0071] Here, the error elimination code may be a binary code; the corresponding number of bits may be determined according to actual needs, such as a three-bit binary code, a four-bit binary code, etc.

[0072] In some possible implementations, such as Figure 6 As shown, in the case where the duty cycle detector 131 includes: a signal converter 1311 and a voltage comparator 1312; the signal converter 1311 can be used to convert the duty cycle information in the first error signal and the second error signal into corresponding voltage signals, and then the voltage comparator 1312 can be used to compare the voltage signals output by the signal converter 1311 to obtain a detection result for performing a counting operation. In this way, the two error signals are sequentially converted and compared to obtain a detection result that can be used for a counting operation, which provides a basis for the subsequent generation of a correlation error elimination code based on the detection result that can be used for a counting operation. Figure 6 FIG. 1 is a schematic diagram of another phase adjustment circuit provided in an embodiment of the present application. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122, a signal converter 1311, a voltage comparator 1312, and an error elimination code generator 132, wherein:

[0073] The signal converter 1311 is configured to use the first error signal to charge and discharge the first capacitor to convert the duty cycle information in the first error signal into the first voltage signal, and use the second error signal to charge and discharge the second capacitor to convert the duty cycle information in the second error signal into the second voltage signal;

[0074] The voltage comparator 1312 is configured to compare the first voltage signal and the second voltage signal to obtain a comparison signal, and convert the comparison signal into the detection result for performing a counting operation.

[0075] Here, the signal converter 1311 may include at least two conversion units. The devices included in each of the two conversion units may be the same or different, that is, the devices may be capable of converting the duty cycle information in the relevant error signal into the relevant voltage signal.

[0076] Among them, a signal converter 1311 can be used to convert the duty cycle information in the first error signal and the second error signal into different voltage signals based on the difference; and then a voltage comparator 1312 is used to compare the first voltage signal and the second voltage signal to obtain a corresponding detection result.

[0077] It should be noted that, in the phase adjustment circuit 10, the signal converter 1311 is connected to the second logic operation module 122 in the phase error detector 12, and the voltage comparator 1312 is connected to the error elimination code generator 132. Thus, when the voltage comparator 1312 outputs a detection result that can be used for counting operation, the error elimination code generator 132 connected thereto can be a counter.

[0078] Here, the counter may be a synchronous counter or an asynchronous counter, etc.

[0079] In some possible implementations, such as Figure 7 As shown, when the error elimination code generator 132 includes a synchronous counter 1321, the synchronous counter 1321 can be used to count the detection result to obtain the corresponding error elimination code. In this way, the detection result is converted into an error elimination code that can be recognized by the multi-phase clock signal generator 11 only through a conventional synchronous counter, which not only makes the overall execution logic of the phase adjustment circuit 10 simple, but also can generate an error elimination code for phase error elimination more conveniently. Figure 7 , which is a schematic diagram of the structure of another phase adjustment circuit provided in an embodiment of the present application. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a first logic operation module 121, a second logic operation module 122, a signal converter 1311, a voltage comparator 1312 and a synchronous counter 1321, wherein:

[0080] The synchronous counter 1321 is connected to the duty cycle detector 131 and is configured to generate an error elimination code based on the detection result.

[0081] Here, the synchronous counter 1321 may be composed of a flip-flop (Flip-Flop, FF) and a gate circuit, and is used to be triggered by the internal FF after receiving the detection result to generate an error elimination code.

[0082] Here, if Figure 8As shown, the error elimination code generator 132 can also be composed of a D flip-flop (D Flip-Flop, DFF) 1322 and a synchronous counter 1321. The D flip-flop 1322 can be used to receive a latch signal when a target multi-phase clock signal in which the phase difference between adjacent phase signals meets a preset condition is obtained, so that the result output by the voltage comparator 1312 remains unchanged, and the voltage comparator 1312 will not output a new detection result to the synchronous counter 1321. It can also latch the detection result output by the voltage comparator 1312 and output it to the synchronous counter 1321 at an appropriate time.

[0083] Continuing from the above description, when the initial multi-phase clock signal is a four-phase clock signal, the second logic operation module 122 included in the phase adjustment circuit 10 outputs a first error signal and a second error signal, and then the first error signal and the second error signal can be synchronously input to the duty cycle detector 131. Figure 8 FIG. 1 is a schematic diagram showing a duty cycle detector and an error elimination code generator in a phase adjustment circuit provided in an embodiment of the present application. Figure 8 The signal converter 1311 shown in FIG. 1 (including: two identical circuits: a signal conversion circuit composed of MOS transistors) converts the duty cycle information in the first error signal and the second error signal into a first voltage signal and a second voltage signal respectively. Figure 8 The voltage comparator 1312 shown compares the input first voltage signal and the second voltage signal to obtain a detection result; the detection result is input to the synchronous counter 1321 based on the control signal of the D trigger 1322 to generate an error elimination code corresponding to the increase or decrease of the signal delay.

[0084] Here, if Figure 8 As shown, the signal converter 1311 can be used to charge and discharge the first capacitor using the first error signal to convert the duty cycle information in the first error signal into a first voltage signal, and can also charge and discharge the second capacitor using the second error signal to convert the duty cycle information in the second error signal into a second voltage signal.

[0085] It should be noted that if Figure 8 As shown, under certain conditions (for example, the phase adjustment circuit 10 is used to obtain a target multi-phase clock signal in which the phase difference between adjacent phase signals meets the preset conditions), the synchronous counter 1321 can be stopped from generating the related error elimination code, and the stopping operation can be carried out in two ways: 1. Stop the clock signal input to the synchronous counter 1321; 2. Use a latch signal to keep the result output by the voltage comparator 1312 unchanged.

[0086] At the same time, if Figure 8The voltage comparator 1312 shown can connect the first voltage signal and the second voltage signal to the corresponding "+" input terminal and "-" input terminal according to actual needs, and then output different levels based on the different voltages of the two input terminals. Exemplarily, when the voltage of the "+" input terminal is higher than that of the "-" input terminal, the output of the voltage comparator 1312 is a high level; when the voltage of the "+" input terminal is lower than that of the "-" input terminal, the output of the voltage comparator 1312 is a low level. Among them, the high level can be represented by 1, and the corresponding low level can be represented by 0.

[0087] In some feasible implementations, a synchronous counter 1321 may be used to adjust the value of a preset elimination code differently based on different detection results, thereby obtaining an error elimination code that indicates an increase or decrease in signal delay, and then based on the error elimination code, the phase of the initial multi-phase clock signal is delayed or reduced to obtain a target multi-phase clock signal that meets the preset requirements. In this way, only one synchronous counter is used to generate an error elimination code for increasing or decreasing signal delay based on different detection results, so that the overall execution logic of the phase adjustment circuit 10 is relatively simple. That is, the synchronous counter 1321 can be configured as follows:

[0088] The synchronization counter 1321 is configured to, when the detection result is a first value, make a first adjustment to the value of the preset elimination code to obtain the error elimination code corresponding to the increase in signal delay;

[0089] The synchronization counter 1321 is further configured to, when the detection result is a second value, perform a second adjustment on the value of the preset elimination code to obtain the error elimination code corresponding to the signal delay reduction.

[0090] Here, the detection result can be represented by any numerical value. The first numerical value and the second numerical value are different numerical values. For example, the first numerical value can be 1 or 0, and correspondingly, the second numerical value can be 0 or 1.

[0091] Here, the synchronous counter 1321 can be used to adjust the value of the preset erasure code based on the detection result, and the adjustment includes but is not limited to: increase, decrease, unchanged, etc. The increase or decrease of the corresponding value can be determined according to actual needs.

[0092] Among them, a synchronous counter 1321 can be used to increase the value of the preset elimination code when the detection result is a first value to obtain an error elimination code corresponding to the increase in signal delay, or to reduce the value of the preset elimination code when the detection result is a second value to obtain an error elimination code corresponding to the reduction in signal delay.

[0093] Here, a synchronous counter 1321 can also be used. When the detection result is 1, the value of the preset elimination code is added by 1 to obtain the error elimination code corresponding to the increase in signal delay, or when the detection result is 0, the value of the preset elimination code is subtracted by 1 to obtain the error elimination code corresponding to the decrease in signal delay.

[0094] It should be noted that the preset elimination code can be a code represented in any form, such as a three-bit binary code, a four-bit binary code, etc. And the error elimination code is a code represented in the same form as the preset elimination code.

[0095] In some embodiments, Fig. 9 As shown, when a multi-phase clock signal generator 11 is used to perform phase adjustment on the initial multi-phase clock signal based on an error elimination code to obtain a target multi-phase clock signal, the multi-phase clock signal generator 11 may also include a delay device 111, which can be used to adjust the switch state of its delay unit based on the received error elimination code, thereby achieving the delay time corresponding to its adjustment, so as to perform phase adjustment on the initial multi-phase clock signal based on the delay time to obtain a target multi-phase clock signal. In this way, the delay device 111 in the multi-phase clock signal generator 11 is directly used to calibrate the phase error between the initial multi-phase clock signals generated by the multi-phase clock signal generator 11 based on the error elimination code, so that the target multi-phase clock signal whose phase difference between the clock signals meets the preset requirements can be obtained more accurately. Fig. 9 FIG. 1 is a schematic diagram showing the composition of another phase adjustment circuit provided in an embodiment of the present application. The phase adjustment circuit 10 includes: a multi-phase clock signal generator 11 including a delayer 111, a first logic operation module 121, a second logic operation module 122, a signal converter 1311, a voltage comparator 1312 and a synchronous counter 1321, wherein:

[0096] The delay device 111 is configured to adjust the delay time based on the error elimination code, and perform phase adjustment on the initial multi-phase clock signal based on the delay time to obtain the target multi-phase clock signal.

[0097] Here, the delay device 111 is an electronic component for realizing the delay effect, such as a capacitor, an inductor, a transistor, etc.; illustratively, when the error elimination code is a 3-bit code, the delay device 111 can be used to turn on the delay device and delay for a first time length when the error elimination code is 000; when the error elimination code is 001, the delay device delays for a second time length; when the error elimination code is 100, the delay device delays for a third time length; when the error elimination code is 111, the delay device delays for a fourth time length; wherein, the fourth time length>the third time length>the second time length>the first time length.

[0098] It should be noted that the delayer 111 can receive an enable signal, and is used to adjust the switch state of its adjustment unit based on the error elimination code when the enable signal is valid, thereby obtaining the delay time corresponding to the error elimination code. Here, whether the enable signal is high level valid or low level valid depends on the actual application.

[0099] Continuing from the above description, the initial multi-phase clock signal includes a four-phase initial clock signal; the four-phase initial clock signal includes a first initial clock signal, a second initial clock signal, a third initial clock signal and a fourth initial clock signal in sequence; the target multi-phase clock signal includes a four-phase target clock signal, and the four-phase target clock signal includes a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal in sequence. In this way, by using a delay device 111, only the phases of the second initial clock signal and the fourth initial clock signal are adjusted based on the error elimination code, and a four-phase clock signal with a phase difference of 90 degrees between adjacent clock signals can be easily obtained. In other words, the delay device 111 can also be configured as follows:

[0100] The delay device 111 is configured to adjust the phase of the second initial clock signal and the fourth initial clock signal based on the error elimination code, so that the phase difference between adjacent clock signals in the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal is 90 degrees.

[0101] Here, the delay device 111 can be used to adjust the phase of the second initial clock signal and the fourth initial clock signal based on the delay time matched by the error elimination code, so as to obtain a four-phase target clock signal with a phase difference of 90 degrees between adjacent clock signals. However, the present invention is not limited to this, and the phase of the first initial clock signal and the third initial clock signal can also be adjusted based on the delay code, or the phase of the second initial clock signal and the third initial clock signal can be adjusted, and so on.

[0102] Based on the above description, if Fig.10 As shown in FIG. 1 , a flow chart of a phase adjustment circuit according to an embodiment of the present application generating a target multi-phase clock signal is shown. Figure 1The DLL circuit is shown in FIG. 1 , and the phase error detector 12 (refer to the above description, which may further include a first logic operation module 121 and a second logic operation module 122), the duty cycle detector 131 (refer to the above description, which may further include a signal converter 1311 and a voltage comparator 1312), and the error elimination code generator 132 (refer to the above description, which may include a synchronous counter 1321 and a D flip-flop 1322). In the embodiment of the present application, based on the DLL circuit, the error elimination code corresponding to the phase error of the initial four-phase clock signal is generated by the newly added phase error detector 12, the duty cycle detector 131, and the error elimination code generator 132, and the delay device 111 included in the four-phase clock signal generator 11 provided in the embodiment of the present application is synchronously used to adjust the phase of the initial four-phase clock signal based on the error elimination code, so as to obtain a target four-phase clock signal whose phase difference between the clock signals meets the preset requirements (such as the phase difference between adjacent clock signals is 90°). In this way, the phase error calibration of the initial multi-phase clock signal can be achieved to obtain a multi-phase clock signal with an accurate relative phase relationship, as well as an internal clock signal that is precisely synchronized with the external clock signal and is accurate, thereby ensuring the accuracy of the relevant storage device in the read / write operation link.

[0103] The present application also provides a phase adjustment method. Fig.11 As shown, a flow chart of a phase adjustment method provided in an embodiment of the present application is shown. The phase adjustment method can be applied to any phase adjustment circuit 10 provided in the above embodiments, and includes the following steps:

[0104] Step S101, using a multi-phase clock signal generator to generate an initial multi-phase clock signal;

[0105] Step S102, using a phase error detector to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for representing phase difference information between the initial multi-phase clock signals;

[0106] Step S103, using a phase error eliminator to detect the error signal to obtain an error elimination code;

[0107] Step S104 : using the multi-phase clock signal generator to perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

[0108] In some embodiments, the phase adjustment method can be applied to the phase adjustment circuit 10 provided in any of the above embodiments, and the phase adjustment circuit 10 includes: a multi-phase clock signal generator 11, a phase error detector 12 connected to the multi-phase clock signal generator 11, and a phase error eliminator 13 respectively connected to the phase error detector 12 and the multi-phase clock signal generator 11. Here, for the detailed description of the multi-phase clock signal generator 11, the phase error detector 12, and the phase error eliminator 13, reference can be made to the detailed description of the above-mentioned related adjustment circuit 10.

[0109] Here, an example is given in which the initial multi-phase clock signal generated by the multi-phase clock signal generator 11 includes a four-phase clock signal, and the four-phase clock signal includes: a first initial clock signal, a second initial clock signal, a third initial clock signal, and a fourth initial clock signal in sequence: First, the logic operation module in the phase error detector 12 is used to perform phase error detection on the initial four-phase clock signal to obtain a first error signal representing the phase difference information between the first initial clock signal and the second initial clock signal, and a second error signal representing the phase difference information between the second initial clock signal and the third initial clock signal in the initial four-phase clock signal. Then, the error eliminator 13 is used to simultaneously input the first error signal and the second error signal into the relevant signal converter for duty cycle detection, and a detection result is obtained, thereby generating an error elimination code (for example, an n-bit binary code, where n is greater than or equal to 1) that matches the detection result. Finally, a device (such as a delay device) inside the multi-phase clock signal generator 11 can be used to identify the error elimination code, and the phase delay of the second initial clock signal and the fourth initial clock signal can be adjusted based on the error elimination code (for example, the switching state and delay time of the delay device can be adjusted through the error elimination code), thereby obtaining a target four-phase clock signal with a phase difference of 90 degrees between adjacent clock signals.

[0110] Here, for further detailed implementation process, reference may be made to the detailed description of the phase adjustment circuit 10 in the above embodiment, which will not be repeated here.

[0111] The phase adjustment method provided in the embodiment of the present application performs phase error detection on the initial multi-phase clock signal to obtain an error signal for characterizing the phase difference information between the initial multi-phase clock signals. The error signal is then converted into a corresponding error elimination code, and the initial multi-phase clock signal is phase adjusted directly based on the error elimination code to obtain a target multi-phase clock signal whose phase difference between the clock signals meets the preset requirements. In this way, the phase error calibration of the initial multi-phase clock signal can be achieved, and a multi-phase clock signal with an accurate relative phase relationship and an internal clock signal that is precisely synchronized with the external clock signal and accurate can be obtained, thereby ensuring the accuracy of the relevant storage device in the data read / write operation link.

[0112] In addition, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the phase adjustment method provided in any of the above embodiments are implemented.

[0113] The present application embodiment also provides a memory 1, such as Fig.12 As shown, a schematic diagram of the composition of a memory provided in an embodiment of the present application is shown; wherein the memory 1 includes the phase adjustment circuit 10 provided in any example of the present application.

[0114] Here, the phase adjustment circuit 10 is a circuit that can detect and adjust the phase difference between multi-phase clock signals. It can be used as a part of the DLL circuit in the memory 1 or deployed in parallel with the DLL circuit in the memory 1 .

[0115] The phase adjustment circuit 10 is used to provide an internal clock signal (ie, the target multi-phase clock signal mentioned in the above embodiment) synchronized with the external clock signal to the memory 1. In this way, the accuracy of the memory 1 in the data read / write operation can be ensured.

[0116] In practical applications, the phase adjustment circuit provided in this embodiment can be applied to various memories, for example, including but not limited to dynamic random access memory (DRAM), static random access memory (Static Random-Access Memory, SRAM), etc. For example, DRAM includes but is not limited to any one of dynamic random access memories such as various generations of double data rate memory (Double Data Rate SDRAM, DDR), various generations of low power double data rate synchronous dynamic random access memory (LPDDR), etc., and no specific limitation is made to this.

[0117] Here, regarding the specific definition of the phase adjustment circuit 10 in the memory 1, reference may be made to the description of the above embodiment, which will not be repeated here.

[0118] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0119] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0120] The above are only some embodiments of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A phase adjustment circuit, characterized in that: The phase adjustment circuit comprises: a multi-phase clock signal generator, a phase error detector and a phase error eliminator, wherein: The multi-phase clock signal generator is configured to generate an initial multi-phase clock signal; The phase error detector is connected to the multi-phase clock signal generator and is configured to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for representing phase difference information between the initial multi-phase clock signals; The phase error eliminator is connected to the phase error detector and is configured to detect the error signal to obtain an error elimination code; The multi-phase clock signal generator is also connected to the phase error eliminator, and is configured to receive the error elimination code, and perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

2. The phase adjustment circuit according to claim 1, characterized in that: The phase error eliminator comprises: a duty cycle detector and an error elimination code generator; The duty cycle detector is connected to the phase error detector and is configured to perform duty cycle detection on the error signal to obtain a detection result; The error elimination code generator is connected to the duty cycle detector and is configured to generate the error elimination code for adjusting the phase of the initial multi-phase clock signal based on the detection result.

3. The phase adjustment circuit according to claim 2, characterized in that: The error elimination code generator includes a synchronous counter; The synchronous counter is connected to the duty cycle detector and is configured to generate the error elimination code based on the detection result.

4. The phase adjustment circuit according to claim 3, characterized in that: The synchronization counter is configured to, when the detection result is a first value, make a first adjustment to the value of the preset elimination code to obtain the error elimination code corresponding to the increase in signal delay; The synchronization counter is further configured to, when the detection result is a second value, perform a second adjustment on the value of the preset elimination code to obtain the error elimination code corresponding to the signal delay reduction.

5. The phase adjustment circuit according to claim 2, characterized in that: The phase error detector comprises: a first logic operation module and a second logic operation module; The first logic operation module is configured to perform an AND operation on the received preset enable signal and each initial clock signal in the initial multi-phase clock signal to obtain an intermediate signal of each initial clock signal; The second logic operation module is configured to perform a logic operation on intermediate signals of adjacent phases in the initial multi-phase clock signal to obtain the error signal.

6. The phase adjustment circuit according to claim 5, characterized in that: The initial multi-phase clock signal includes a four-phase initial clock signal; the four-phase initial clock signal includes a first initial clock signal, a second initial clock signal, a third initial clock signal and a fourth initial clock signal in sequence; the error signal includes a first error signal and a second error signal; The second logic operation module is also configured to perform a NAND operation on the intermediate signal of the first initial clock signal and the inverted signal of the intermediate signal of the second initial clock signal to obtain the first error signal, and to perform a NAND operation on the intermediate signal of the second initial clock signal and the inverted signal of the intermediate signal of the third initial clock signal to obtain the second error signal.

7. The phase adjustment circuit according to claim 6, characterized in that: The duty cycle detector comprises: a signal converter and a voltage comparator; The signal converter is configured to charge and discharge a first capacitor using the first error signal to convert the duty cycle information in the first error signal into the first voltage signal, and to charge and discharge a second capacitor using the second error signal to convert the duty cycle information in the second error signal into the second voltage signal; The voltage comparator is configured to compare the first voltage signal and the second voltage signal to obtain a comparison signal, and convert the comparison signal into the detection result for performing a counting operation.

8. The phase adjustment circuit according to claim 1, characterized in that: The multi-phase clock signal generator includes a delay device; The delay device is configured to adjust the delay time based on the error elimination code, and to perform phase adjustment on the initial multi-phase clock signal based on the delay time to obtain the target multi-phase clock signal.

9. The phase adjustment circuit according to claim 8, characterized in that: The initial multi-phase clock signal includes a four-phase initial clock signal; the four-phase initial clock signal includes a first initial clock signal, a second initial clock signal, a third initial clock signal and a fourth initial clock signal in sequence; The target multi-phase clock signal includes a four-phase target clock signal, and the four-phase target clock signal sequentially includes a first target clock signal, a second target clock signal, a third target clock signal, and a fourth target clock signal; The delay device is configured to adjust the phase of the second initial clock signal and the fourth initial clock signal based on the error elimination code, so that the phase difference between adjacent clock signals in the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal is 90 degrees.

10. A phase adjustment method, characterized in that: The phase adjustment method comprises: Using a multi-phase clock signal generator to generate an initial multi-phase clock signal; Using a phase error detector to perform phase error detection on the initial multi-phase clock signal to obtain an error signal for representing phase difference information between the initial multi-phase clock signals; Using a phase error eliminator to detect the error signal to obtain an error elimination code; The multi-phase clock signal generator is used to perform phase adjustment on the initial multi-phase clock signal based on the error elimination code to obtain a target multi-phase clock signal.

11. A memory, characterized in that: The memory at least comprises the phase adjustment circuit according to any one of claims 1 to 9.

Images