Method, apparatus, medium and system for continuous data reception and processing based on cyclic RAM

Abstract

This invention discloses a method, apparatus, medium, and system for continuous data reception and processing based on circular RAM, belonging to the field of aerospace telemetry, tracking, and command (TT&C) communication. The system includes: a ZYNQ chip PS unit and PL unit connected via an AXI bus; received data Ch1_Recv_Data to ChN_Recv_Data interconnected with the PL unit via an SPI bus. The PL unit stores the received data in Data_RAM, the packet length in Len_RAM, and updates the PL unit's enqueue pointer count; the PS unit, through periodic polling, reads Len_RAM based on the difference between the enqueue and dequeue pointer counts, and then reads data from Data_RAM based on the Len_RAM value for subsequent processing. This invention provides a solution that is simple to implement in software and increases the number of different data types that the receiving end can simultaneously store.

Description

Technical Field

[0001] This invention relates to the field of aerospace telemetry, tracking, and command (TT&C) communication, and more specifically, to a method, apparatus, medium, and system for receiving and processing continuous data based on cyclic RAM. Background Technology

[0002] ZYNQ, as a new generation of fully programmable system-on-a-chip (APSOC), perfectly integrates the software programmability of a processor with the hardware programmability of an FPGA, offering high flexibility and scalability to adapt to diverse application requirements. In recent years, ZYNQ has been increasingly used as a main control chip in hardware design for aerospace telemetry and control.

[0003] With the development of measurement and control technology, the data modes that receiving ends need to process are becoming increasingly diverse, and the data rates are also increasing. The receiving end needs to receive complete data packets before it can perform subsequent parsing and processing. Currently, in most system applications, the received data is stored in the local buffer RAM or FIFO of the ZYNQ chip's programmable logic (PL unit). After receiving a complete data packet, data parsing and processing are performed through interrupts or periodic polling by the ZYNQ chip's processor (PS unit). When the receiving end receives data from multiple hardware devices simultaneously, a ping-pong buffering method is typically used. For example, if two different types of data are received simultaneously, they are stored in two RAMs or FIFOs; if three different types of data are received simultaneously, they are stored in three RAMs or FIFOs; and so on, with the number of RAMs or FIFOs corresponding to the number of different types of data stored.

[0004] The above solution has certain limitations, mainly because different data types have different lengths and transmission intervals. The receiving end needs to define the size of its buffer RAM or FIFO based on the largest data length to maximize the ping-pong utilization of the buffer and ensure that each buffer RAM or FIFO is used. Taking the ZYNQ chip 7Z045 as an example, the total number of internal RAM resources of the 7Z045 is 545 36Kbit RAM units. Assuming the length of the received data packets is 8 bytes to 256K bytes, since the RAM size needs to be defined based on the largest received data packet length, the minimum storage capacity of a single RAM at the receiving end must reach 256Kbytes. Receiving one type of data requires 57 36Kbit RAM units, receiving four different types of data requires 228 36Kbit RAM units, and receiving ten different types of data requires 570 36Kbit RAM units, which exceeds the limit of 545 internal RAM resources of a single ZYNQ chip 7Z045. The above calculation only shows the amount of RAM resources required for the first-level storage of the receiving end to receive data. In actual use, subsequent processing will also consume a large amount of RAM resources.

[0005] The above scheme is simple to implement, but as the number of data types received simultaneously in the first stage increases, firstly, it will significantly increase the resource usage of the first-stage RAM, squeezing the RAM resources required for subsequent processing; secondly, as the length of the received data packets increases unevenly, for example, when the length of a certain type of data further increases, it will further compress the number of data types received simultaneously in the first stage; and thirdly, the large-scale use of RAM resources will inevitably lead to timing convergence problems within the PL unit. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, apparatus, medium and system for continuous data reception and processing based on cyclic RAM. Without increasing the system hardware cost and the limited RAM resources of existing ZYNQ chips, it can increase the number of data types that the receiving end can store at the same time, reduce the complexity of software design and implementation, and effectively improve the reliability of the system.

[0007] The objective of this invention is achieved through the following solution:

[0008] A method for receiving and processing continuous data based on circular RAM, using the ZYNQ chip PS unit, ZYNQ chip PL unit, and received data Ch1_Recv_Data to received data ChN_Recv_Data, performs the following steps:

[0009] Step S1: The ZYNQ chip PS unit and PL unit are connected, including the connection using an AXI bus; the received data Ch1_Recv_Data to ChN_Recv_Data are interconnected with the ZYNQ chip PL unit, including the interconnection using an SPI bus.

[0010] Step S2: The PL unit receives data from received data Ch1_Recv_Data to received data ChN_Recv_Data, stores the data in Data_RAM, stores the data packet length in Len_RAM, and updates the enqueue pointer count of the PL unit; the PS unit reads Len_RAM based on the difference between the enqueue and dequeue pointer counts through a timed polling method.

[0011] Step S3: Based on the read length value of Len_RAM, read the data of the corresponding length in Data_RAM for subsequent processing.

[0012] Furthermore, the ZYNQ chip includes a Xilinx-7Z045 device or a domestically produced FMQ-7Z045 device.

[0013] Furthermore, the PL unit includes: a packet-level RAM module and an enqueue pointer counting module. The packet-level RAM module consists of data (Data_RAM) and length (Len_RAM). Data_RAM is defined with a capacity of 1 MByte, occupying 228 RAM units of 36 Kbit size. Len_RAM is defined with a capacity of 8 KByte, occupying 2 RAM units of 36 Kbit size. A total of 230 RAM units of 36 Kbit size are occupied.

[0014] Further, in step S2, the step of using the PL unit to receive data from received data Ch1_Recv_Data to received data ChN_Recv_Data specifically includes the following sub-steps: the PL unit receives data through the SPI bus, and the received data Ch1_Recv_Data to ChN_Recv_Data has a packet length range of 8 bytes to 256 KB.

[0015] Further, in step S2, updating the PL unit enqueue pointer count specifically includes the following sub-steps:

[0016] The number of received data packets is accumulated using the enqueue pointer counting module of the PL unit. The counter width of the enqueue pointer counting module is selected to be 64 bits, and the counter is incremented by 1 once every time the length Len_RAM is written.

[0017] Furthermore, the PS unit includes a timed query function module, a receive data processing function module, and a dequeue pointer counting function module. The dequeue pointer counting function adopts a 64-bit counting format. Each time the timed interval arrives, the dequeue pointer counting function is called. By comparing the difference between the enqueue and dequeue pointer counts, it is determined whether there are new data packets in the packet-level RAM of the PL unit that need to be read, and then handed over to the receive data processing function module for subsequent processing.

[0018] A continuous data reception and processing method based on circular RAM, using a ZYNQ chip PS unit and a ZYNQ chip PL unit, with the PS unit and PL unit connected, also includes a data reception processing flow in the PL unit: After power-on reset, the data reception processing flow in the PL unit enters an initial state, monitors for the arrival of new data packets, and if so, proceeds to the process of determining whether the current data packet has been received; otherwise, it continues monitoring. In the process of determining whether the current data packet has been received, if so, it proceeds to the state of updating the enqueue pointer count; otherwise, it continues judging. After the enqueue pointer count is updated, it returns to the initial state.

[0019] A continuous data reception and processing method based on circular RAM, based on the ZYNQ chip PS unit and ZYNQ chip PL unit, with the ZYNQ chip PS unit and PL unit connected, also includes a PS unit data reception processing flow: After power-on reset, the data reception processing flow in the PS unit enters the initial state, monitors whether the timed query time has arrived, if not, continues monitoring, if yes, it enters the state of reading the enqueue pointer count, after reading the enqueue pointer count value, it enters the process of judging whether the enqueue and dequeue pointer counts are equal, if yes, it means that no new data packet has arrived in this query, and returns to the initial state; otherwise, it means that a new data packet has arrived in this query, and enters the state of reading the Len_RAM value;

[0020] After reading the value of Len_RAM, the process enters the process of determining whether the length value of Data_RAM has been reached. If it has, the process enters the process of updating the dequeue pointer count; otherwise, the process continues to determine whether the dequeue pointer count is equal. After the dequeue pointer count is updated, the process returns to the process of determining whether the enqueue and dequeue pointer counts are equal.

[0021] A continuous data receiving and processing apparatus based on circular RAM includes a processor and a memory, wherein the memory stores a computer program that, when loaded by the processor, executes the method described in any of the preceding methods.

[0022] A computer-readable storage medium storing a computer program that, when loaded by a processor, executes the method described in any of the preceding claims.

[0023] A continuous data receiving and processing system based on cyclic RAM includes the apparatus described above.

[0024] The beneficial effects of this invention include:

[0025] (1) The present invention increases the number of different data types that the receiving end can store at the same time by using a circular RAM continuous storage method. On the one hand, it effectively improves the utilization rate of RAM resources and avoids defining each RAM according to the maximum length of all received data packets, which can effectively reduce the RAM space occupation. On the other hand, when the length range of received data packets is dynamically balanced, the number of data types that can be received at the same time can be greatly increased.

[0026] (2) The present invention reduces the complexity of software design and improves the data processing capability of the PS unit. By adopting the packet-level RAM (data RAM + length RAM) method, continuously input data can be restored into individual data packets, and the data packets and their corresponding lengths are recorded in RAM. Through the handshake method of counting enqueue pointers, on the one hand, the PS unit can effectively and smoothly process multiple consecutive data packets with very small packet lengths; on the other hand, since the data packets and their lengths are stored in RAM, it is convenient for subsequent processing to have the ability to obtain the same data multiple times, which has certain advantages when recovering from errors. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a continuous data receiving and processing method based on cyclic RAM according to an embodiment of the present invention.

[0029] Figure 2 for Figure 1 The implementation principle diagram.

[0030] Figure 3 for Figure 2 Flowchart of data receiving and processing in the PL unit.

[0031] Figure 4 for Figure 2 Flowchart of data receiving and processing in the PS unit. Detailed Implementation

[0032] All features disclosed in all embodiments of this specification, or steps in all methods or processes implied in the disclosure, may be combined and / or extended or replaced in any way, except for mutually exclusive features and / or steps.

[0033] The specific implementation process of this invention is as follows:

[0034] like Figure 1 As shown, this invention provides a method for continuous data reception and processing based on cyclic RAM, comprising: a ZYNQ chip PS unit, a ZYNQ chip PL unit, and received data Ch1_Recv_Data to ChN_Recv_Data. The ZYNQ chip PS unit and PL unit are connected via an AXI bus; the received data Ch1_Recv_Data to ChN_Recv_Data are interconnected with the ZYNQ chip PL unit via an SPI bus.

[0035] like Figure 2 As shown, the ZYNQ chip uses either the imported Xilinx-7Z045 device or the corresponding domestically produced FMQ-7Z045 device.

[0036] The PL unit includes a packet-level RAM module and an enqueue pointer counting module. The packet-level RAM module consists of data (Data_RAM) and length (Len_RAM). Data_RAM is defined with a capacity of 1 MByte, occupying 228 RAM units of 36 Kbit size; Len_RAM is defined with a capacity of 8 KByte, occupying 2 RAM units of 36 Kbit size; for a total of 230 RAM units of 36 Kbit size.

[0037] Figure 2 In this architecture, the PL unit receives data via the SPI bus, specifically Ch1_Recv_Data to ChN_Recv_Data, with packet lengths ranging from 8 bytes to 256 KB. Storing 8-byte packets consecutively allows for a maximum of 131,072 packets (equivalent to storing 131,072 different types of single-packet data); storing 256-byte packets consecutively allows for a maximum of 4,096 packets (equivalent to storing 4,096 different types of single-packet data); storing 4 KB packets consecutively allows for a maximum of 256 packets (equivalent to storing 256 different types of single-packet data); and storing 256 KB packets consecutively allows for a maximum of 4 packets (equivalent to storing 4 different types of single-packet data). It can be seen that when using contiguous RAM storage, the number of packet types stored per packet is linearly inversely proportional to the packet size; the smaller the packet length, the more pronounced the advantage of contiguous RAM storage becomes. The fixed RAM usage method, which is defined according to the maximum data packet length, will result in a large waste of RAM resources when the received data packet length is small.

[0038] Figure 2 In the PL unit, the main function of the enqueue pointer counting module is to accumulate and count the number of received data packets. The counter bit width of the enqueue pointer counting module is selected as 64 bits, and the counter increments by 1 once for each write to the length Len_RAM.

[0039] Figure 2 In the PS unit, there are three main components: a timer polling function, a receive data processing function, and a dequeue pointer counting function. The dequeue pointer counting function uses a 64-bit counting format. Each time a timer interval arrives, the dequeue pointer counting function is called. By comparing the difference between the enqueue and dequeue pointer counts, it determines whether there are new data packets in the packet-level RAM of the PL unit that need to be read, and then hands them over to the receive data processing function for further processing.

[0040] like Figure 3 As shown, the data receiving and processing flow in the PL unit enters the initial state after power-on reset. It monitors for new data packets; if so, it proceeds to the process of determining whether the current data packet has been received successfully. If so, it proceeds to the state of updating the enqueue pointer count; after the enqueue pointer count is updated, it returns to the initial state.

[0041] like Figure 4 As shown, the data processing flow in the PS unit enters the initial state after power-on reset. It monitors whether the timed query period has arrived; if so, it proceeds to the state of reading the enqueue pointer count. After reading the enqueue pointer count, it enters the process of determining whether the enqueue and dequeue pointer counts are equal. If they are equal, it means no new data packet has arrived, and it returns to the initial state; otherwise, it means a new data packet has arrived, and it enters the state of reading the Len_RAM value. After reading the Len_RAM value, it enters the process of determining whether the Data_RAM has reached the length corresponding to Len_RAM. If so, it enters the state of updating the dequeue pointer count; after the dequeue pointer count is updated, it returns to the process of determining whether the enqueue and dequeue pointer counts are equal. By using the above cyclic comparison of enqueue and dequeue pointer counts, multiple data packets in the packet-level RAM of the PL unit can be retrieved at once and handed over to the subsequent data receiving processing function through a single timed query, which can effectively improve the efficiency of PS data reading.

[0042] It should be noted that, within the scope of protection defined in the claims of this invention, the following embodiments can be combined and / or extended or replaced in any logical manner from the above specific embodiments, such as the disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0043] Example 1

[0044] A method for receiving and processing continuous data based on circular RAM, using the ZYNQ chip PS unit, ZYNQ chip PL unit, and received data Ch1_Recv_Data to received data ChN_Recv_Data, performs the following steps:

[0045] Step S1: The ZYNQ chip PS unit and PL unit are connected, including the connection using an AXI bus; the received data Ch1_Recv_Data to ChN_Recv_Data are interconnected with the ZYNQ chip PL unit, including the interconnection using an SPI bus.

[0046] Step S2: The PL unit receives data from received data Ch1_Recv_Data to received data ChN_Recv_Data, stores the data in Data_RAM, stores the data packet length in Len_RAM, and updates the enqueue pointer count of the PL unit; the PS unit reads Len_RAM based on the difference between the enqueue and dequeue pointer counts through a timed polling method.

[0047] Step S3: Based on the read length value of Len_RAM, read the data of the corresponding length in Data_RAM for subsequent processing.

[0048] Example 2

[0049] Based on Example 1, the ZYNQ chip includes a Xilinx-7Z045 device or a domestically produced FMQ-7Z045 device.

[0050] Example 3

[0051] Based on Embodiment 1, the PL unit includes: a packet-level RAM module and an enqueue pointer counting module. The packet-level RAM module consists of data (Data_RAM) and length (Len_RAM). Data_RAM is defined with a capacity of 1 MByte, occupying 228 RAM units of 36 Kbit size. Len_RAM is defined with a capacity of 8 KByte, occupying 2 RAM units of 36 Kbit size. A total of 230 RAM units of 36 Kbit size are occupied.

[0052] Example 4

[0053] Based on Example 1, in step S2, the step of using the PL unit to receive data from received data Ch1_Recv_Data to received data ChN_Recv_Data specifically includes the following sub-steps: the PL unit receives data through the SPI bus, and the received data Ch1_Recv_Data to ChN_Recv_Data has a packet length range of 8 bytes to 256 KB.

[0054] Example 5

[0055] Based on Example 1, step S2, which updates the PL unit enqueue pointer count, specifically includes the following sub-steps:

[0056] The number of received data packets is accumulated using the enqueue pointer counting module of the PL unit. The counter width of the enqueue pointer counting module is selected to be 64 bits, and the counter is incremented by 1 once every time the length Len_RAM is written.

[0057] Example 6

[0058] Based on Embodiment 1, the PS unit includes a timed query function module, a receive data processing function module, and a dequeue pointer counting function module. The dequeue pointer counting function adopts a 64-bit counting format. Each time the timed interval arrives, the dequeue pointer counting function is called. By comparing the difference between the enqueue and dequeue pointer counts, it is determined whether there are new data packets in the packet-level RAM of the PL unit that need to be read, and then handed over to the receive data processing function module for subsequent processing.

[0059] Example 7

[0060] A continuous data reception and processing method based on circular RAM, using a ZYNQ chip PS unit and a ZYNQ chip PL unit, with the PS unit and PL unit connected, also includes a data reception processing flow in the PL unit: After power-on reset, the data reception processing flow in the PL unit enters an initial state, monitors for the arrival of new data packets, and if so, proceeds to the process of determining whether the current data packet has been received; otherwise, it continues monitoring. In the process of determining whether the current data packet has been received, if so, it proceeds to the state of updating the enqueue pointer count; otherwise, it continues judging. After the enqueue pointer count is updated, it returns to the initial state.

[0061] Example 8

[0062] A continuous data reception and processing method based on circular RAM, based on the ZYNQ chip PS unit and ZYNQ chip PL unit, with the ZYNQ chip PS unit and PL unit connected, also includes a PS unit data reception processing flow: After power-on reset, the data reception processing flow in the PS unit enters the initial state, monitors whether the timed query time has arrived, if not, continues monitoring, if yes, it enters the state of reading the enqueue pointer count, after reading the enqueue pointer count value, it enters the process of judging whether the enqueue and dequeue pointer counts are equal, if yes, it means that no new data packet has arrived in this query, and returns to the initial state; otherwise, it means that a new data packet has arrived in this query, and enters the state of reading the Len_RAM value;

[0063] After reading the value of Len_RAM, the process enters the process of determining whether the length value of Data_RAM has been reached. If it has, the process enters the process of updating the dequeue pointer count; otherwise, the process continues to determine whether the dequeue pointer count is equal. After the dequeue pointer count is updated, the process returns to the process of determining whether the enqueue and dequeue pointer counts are equal.

[0064] Example 9

[0065] A continuous data receiving and processing device based on cyclic RAM includes a processor and a memory, wherein the memory stores a computer program, and when the computer program is loaded by the processor, it executes the method described in any one of Embodiments 1 to 8.

[0066] Example 10

[0067] A computer-readable storage medium storing a computer program that, when loaded by a processor, executes the method described in any one of Examples 1 to 8.

[0068] Example 11

[0069] A continuous data receiving and processing system based on cyclic RAM includes the apparatus described in Embodiment 9.

[0070] The units described in the embodiments of the present invention can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0071] According to one aspect of the present invention, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, causing the computer device to perform the methods provided in the various optional implementations described above.

[0072] In another aspect, embodiments of the present invention also provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the methods described in the above embodiments.

Claims

1. A method for receiving and processing continuous data based on circular RAM, characterized in that, Based on the ZYNQ chip PS unit, ZYNQ chip PL unit, and received data Ch1_Recv_Data to received data ChN_Recv_Data, the following steps are performed: Step S1: The ZYNQ chip PS unit and PL unit are connected, including the connection using an AXI bus; the received data Ch1_Recv_Data~ChN_Recv_Data are interconnected with the ZYNQ chip PL unit, and the interconnection includes the interconnection using an SPI bus. Step S2: The PL unit receives data from received data Ch1_Recv_Data to received data ChN_Recv_Data, stores the data in Data_RAM, stores the data packet length in Len_RAM, updates the PL unit's enqueue pointer count, and uses the PL unit's enqueue pointer counting module to accumulate the number of received data packets. Each time the length Len_RAM is written, the counter is incremented by 1. The PS unit monitors whether the timed query time has arrived through a timed query method. If not, it continues to monitor. If yes, it enters the state of reading the enqueue pointer count. After reading the enqueue pointer count value, it enters the process of judging whether the PS unit's dequeue pointer count and the PL unit's enqueue pointer count are equal. If they are equal, it means that no new data packets have arrived in this query, and it returns to the initial state. Otherwise, it indicates that a new data packet has arrived for this query, and the query enters the state of reading the Len_RAM value; Read Len_RAM; Step S3: After reading the Len_RAM value, proceed to the process of determining whether the length value of the Data_RAM has been reached. If yes, proceed to update the dequeue pointer count; otherwise, continue the determination. After the dequeue pointer count is updated, return to the process of determining whether the dequeue pointer count of the PS unit is equal to the enqueue pointer count of the PL unit.

2. The method for receiving and processing continuous data based on cyclic RAM according to claim 1, characterized in that, ZYNQ chips include Xilinx-7Z045 devices or domestically produced devices such as FMQ-7Z045.

3. The method for receiving and processing continuous data based on circular RAM according to claim 1, characterized in that, The PL unit includes a packet-level RAM module and an enqueue pointer counting module. The packet-level RAM module consists of data (Data_RAM) and length (Len_RAM). Data_RAM is defined with a capacity of 1 MByte, occupying 228 RAM units of 36 Kbit size. Len_RAM is defined with a capacity of 8 KByte, occupying 2 RAM units of 36 Kbit size. A total of 230 RAM units of 36 Kbit size are occupied.

4. The method for receiving and processing continuous data based on cyclic RAM according to claim 1, characterized in that, In step S2, the step of using the PL unit to receive data from received data Ch1_Recv_Data to received data ChN_Recv_Data specifically includes the following sub-steps: the PL unit receives data through the SPI bus, receiving data Ch1_Recv_Data to ChN_Recv_Data, with a packet length ranging from 8 bytes to 256 KB.

5. The method for receiving and processing continuous data based on cyclic RAM according to claim 3, characterized in that, In step S2, updating the PL unit enqueue pointer count specifically includes the sub-step of selecting a 64-bit counter width for the enqueue pointer counting module.

6. The method for receiving and processing continuous data based on cyclic RAM according to claim 1, characterized in that, The PS unit includes a timed query function module, a receive data processing function module, and a dequeue pointer counting function module. The dequeue pointer counting function uses a 64-bit counting format. Each time the timed interval arrives, the dequeue pointer counting function is called. By comparing the difference between the dequeue pointer count of the PS unit and the enqueue pointer count of the PL unit, it is determined whether there are new data packets in the packet-level RAM of the PL unit that need to be read, and then handed over to the receive data processing function module for further processing.

7. A continuous data receiving and processing device based on circular RAM, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when loaded by the processor, executes the method as described in any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, A computer program is stored in a readable storage medium, which, when loaded by a processor, executes the method as described in any one of claims 1 to 6.

9. A continuous data receiving and processing system based on circular RAM, characterized in that, Includes the apparatus as described in claim 7.

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