Data communication system

Abstract

The invention provides a data communication system, which comprises a first development board and a second development board, the first development board comprises a first processor and a first 10-gigabit PHY chip, the first processor is in communication connection with the first 10-gigabit PHY chip through a USXGMII interface protocol, the second development board comprises a second processor and a second 10-gigabit PHY chip, and the second processor is in communication connection with the second 10-gigabit PHY chip through a USXGMII interface protocol. The first processor is in communication connection with the first 10-gigabit PHY chip through a USXGMII interface protocol, the second processor is in communication connection with the second 10-gigabit PHY chip through a USXGMII interface protocol, the first development board and / or the second development board further comprises a storage chip which is connected with the first 10-gigabit PHY chip and / or the second 10-gigabit PHY chip, and the storage chip is used for storing firmware of the first 10-gigabit PHY chip and / or the second 10-gigabit PHY chip; wherein the first 10-gigabit PHY chip is connected with the second 10-gigabit PHY chip through a 10-gigabit Ethernet transmission line. Therefore, data mutual transmission between the two development boards through the 10-gigabit Ethernet is realized, and the transmission rate is high, so that the transmission efficiency of the vehicle-mounted Ethernet is improved, and the application scene of the vehicle-mounted Ethernet is expanded.

Description

Technical Field

[0001] The present application belongs to the technical field of automotive Ethernet, and in particular to a data communication system. Background Art

[0002] Cars often need to communicate data via automotive Ethernet. The media independent interface of automotive Ethernet, which is currently used to connect the physical interface transceiver and the media access control sublayer protocol, has a maximum data transmission rate of only 1000Mbps, resulting in poor transmission efficiency of automotive Ethernet and limited application scenarios. Summary of the invention

[0003] The embodiment of the present application provides a data communication system to solve the technical problems of poor transmission efficiency and limited application scenarios of in-vehicle Ethernet.

[0004] The present application provides a data communication system, including:

[0005] The first development board includes a first processor and a first 10G PHY chip, wherein the first processor is connected to the first 10G PHY chip through a USXGMII interface protocol.

[0006] The second development board includes a second processor and a second 10 Gigabit PHY chip, wherein the second processor and the second 10 Gigabit PHY chip are connected to each other through a USXGMII interface protocol.

[0007] The first development board and / or the second development board further includes:

[0008] A storage chip connected to the first 10 Gigabit PHY chip and / or the second 10 Gigabit PHY chip, and the storage chip is used to store firmware of the first 10 Gigabit PHY chip and / or the second 10 Gigabit PHY chip;

[0009] The first 10 Gigabit PHY chip and the second 10 Gigabit PHY chip are connected via a 10 Gigabit Ethernet transmission line.

[0010] In this way, the data communication system can connect the processor and the 10 Gigabit PHY chip through the USXGMII interface protocol, and then connect the 10 Gigabit PHY chips between the two development boards through a 10 Gigabit Ethernet transmission line. The storage chip is used to store the firmware of the first 10 Gigabit PHY chip and / or the second 10 Gigabit PHY chip to ensure that the first 10 Gigabit PHY chip and / or the second 10 Gigabit PHY chip can quickly and accurately read and run the firmware, thereby realizing data transmission between the two development boards through 10 Gigabit Ethernet with a fast transmission rate, thereby improving the transmission efficiency of the in-vehicle Ethernet and expanding the application scenarios of the in-vehicle Ethernet. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 It is one of the structural diagrams of the data communication system provided in the embodiment of the present application;

[0013] Figure 2 This is the second structural diagram of the data communication system provided in the embodiment of the present application;

[0014] Figure 3 It is a schematic diagram of the structure of a first 10 Gigabit PHY chip and a second 10 Gigabit PHY chip provided in an embodiment of the present application;

[0015] Figure 4 It is a schematic diagram of the structure of the first processor and the second processor provided in an embodiment of the present application.

[0016] Reference numerals:

[0017] 1. a first development board; 11. a first processor; 12. a first 10G PHY chip; 121. a first chip in a master mode; 122. a first chip in a slave mode;

[0018] 2. A second development board; 21. A second processor; 22. A second 10G PHY chip; 221. A second chip in a master mode; 222. A second chip in a slave mode;

[0019] 3. Memory chip;

[0020] 4. Ethernet switch; 41. main port; 42. data port;

[0021] 5. Deserializer and serializer. DETAILED DESCRIPTION

[0022] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0023] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0024] In order to solve the problems in the prior art, the embodiment of the present application provides a data communication system. The data communication system provided by the embodiment of the present application is first introduced below.

[0025] Figure 1 FIG. 1 is a schematic diagram showing the structure of a data communication system provided by an embodiment of the present application. Figure 1 and Figure 2 As shown, the data communication system may include a first development board 1 and a second development board 2, the first development board 1 includes a first processor 11 and a first 10 Gigabit physical layer (Physical Layer, PHY) chip 12, the first processor 11 and the first 10 Gigabit PHY chip 12 are communicatively connected via an Ethernet physical layer interface standard (Universal Serial 10GE Media Independent Interface, USXGMII) interface protocol, the second development board 2 includes a second processor 21 and a second 10 Gigabit PHY chip 22, the second processor 21 and the second 10 Gigabit PHY chip 22 are communicatively connected via a USXGMII interface protocol, the first development board 1 and / or the second development board 2 also include: a storage chip 3, connected to the first 10 Gigabit PHY chip 12 and / or the second 10 Gigabit PHY chip 22, the storage chip 3 is used to store the firmware of the first 10 Gigabit PHY chip 12 and / or the second 10 Gigabit PHY chip 22; wherein the first 10 Gigabit PHY chip 12 and the second 10 Gigabit PHY chip 22 are connected via a 10 Gigabit Ethernet transmission line.

[0026] It is understandable that the 10 Gigabit Ethernet standard was drafted by the IEEE 802.3ae working group, with the goal of extending the IEEE 802.3 protocol to enable it to transmit data at a rate of 10Gbps, expand the application scope of Ethernet, and support wide area network connections. 10 Gigabit Ethernet not only has a higher transmission rate, but also greatly improves its transmission distance.

[0027] In this embodiment, the data communication system may include a first development board 1 and a second development board 2 to be used for data transmission, each development board includes a processor and a 10G PHY chip, that is, the first development board 1 includes a first processor 11 and a first 10G PHY chip 12, and the second development board 2 includes a second processor 21 and a second 10G PHY chip 22. PHY indicates a physical interface transceiver, defines the electrical and optical signals, line states, clock references, data encoding and circuits required for data transmission, and provides a standard interface to data link layer devices.

[0028] The first processor 11 and the first 10G PHY chip 12, and the second processor 21 and the second 10G PHY chip 22 can communicate via the USXGMII interface protocol defined by IEEE 802.3ch. The 10G Ethernet bit rate of the USXGMII interface can reach 5Gbps or 10Gbps, and the data transmission rate is relatively high.

[0029] The first 10 Gigabit PHY chip 12 and the second 10 Gigabit PHY chip 22 can be connected via a dedicated 10 Gigabit Ethernet transmission line to achieve data transmission between the two development boards via the 10 Gigabit Ethernet.

[0030] It is understandable that during the power-on startup process of the first development board 1 and the second development board 2, the first 10G PHY chip 12 and / or the second 10G PHY chip 22 can be loaded and run based on the flashed driver. However, the driver often takes a certain amount of time to load, and flashing the driver often requires configuring more parameters, which is cumbersome and error-prone, thus affecting normal operation.

[0031] Based on this, in the present embodiment, the first development board 1 and / or the second development board 2 may further include a storage chip 3, which may be connected to the first 10 Gigabit PHY chip 12 and / or the second 10 Gigabit PHY chip 22 for storing the firmware of the first 10 Gigabit PHY chip 12 and / or the second 10 Gigabit PHY chip 22.

[0032] In some embodiments, the storage chip 3 is used for loading the firmware of the 10G PHY chip from the storage chip 3 and running it during the power-on startup process of the first development board 1 and the second development board 2, and building a communication link when the firmware runs successfully;

[0033] The 10 Gigabit PHY chip includes a first 10 Gigabit PHY chip 12 and / or a second 10 Gigabit PHY chip 22 .

[0034] It is understandable that the 10G PHY chip needs to run firmware for initialization processing before establishing a communication link for data communication. The firmware is usually set in the 10G PHY chip. When the 10G PHY chip is powered on, it starts to execute a series of initialization steps, including checking hardware connections, configuring internal registers, and preparing necessary resources. Loading firmware as part of the initialization process requires the 10G PHY chip to negotiate and configure firmware parameters through a serial peripheral interface (SPI), bus (I2C) or other serial communication protocols. The firmware parameters may include all instructions and configuration information required to control the operation of the PHY chip, such as initializing PHY registers, configuring automatic negotiation parameters, setting link speed and duplex mode, etc.

[0035] However, the entire configuration process takes a certain amount of time and resources, and if the firmware is damaged during the configuration process, the entire 10G PHY chip often needs to be replaced, resulting in poor stability of the data communication system.

[0036] In this embodiment, if Figure 2 and Figure 3 As shown, the first development board 1 and the second development board 2 both include a memory chip 3, the memory chip 3 is a non-volatile memory NORFLASH with a storage size of 32Mb, and each 88Q4364 chip is connected to a corresponding NORFLASH as an example, the firmware of the 88Q4364 chip is stored in NORFLASH, and this firmware is burned with a dedicated NORFLASH burner. Since only one master (MASTER) and one slave (SLAVE) can communicate between the 88Q4364 chips, two NORFLASH firmwares can be burned in the memory chip 3. If the transmission rate of the data communication system is 5Gbps, the two firmwares can be 5G_USXGMII_MASTER and 5G_USXGMII_SLAVE. If the transmission rate of the data communication system is 10Gbps, the two firmwares can be 10G_USXGMII_MASTER and 10G_USXGMII_SLAVE.

[0037] During the power-on startup of the first development board 1 and the second development board 2, the 88Q4364 chip will read the firmware in NORFLASH and run it. After the firmware runs successfully, the 88Q4364 chip is ready.

[0038] For example, during the power-on startup process of the first development board 1 and the second development board 2, the 10G PHY chip can load the firmware of the 10G PHY chip from the storage chip 3 and run it. The firmware stored in the storage chip 3 can pre-configure its firmware parameters, that is, initialize the PHY register, configure the automatic negotiation parameters, set the link speed and duplex mode, etc., so that the configuration work is pre-set, the initialization operation is simplified, the system startup time is shortened, and the response rate is improved.

[0039] After the firmware is loaded by the 10G PHY chip, the pre-configured firmware parameters can be automatically executed. After completing all necessary initialization tasks, the 10G PHY chip reaches the ready state. This means that it is ready to communicate and can start processing network data packets. After the 10G PHY chip is ready, you can try to establish a communication link with the peer device. Once the communication link is established, the 10G PHY chip can start processing the sending and receiving of high-speed network data.

[0040] In this way, the data communication system can connect the processor and the 10 Gigabit PHY chip through the USXGMII interface protocol, and then connect the 10 Gigabit PHY chips between the two development boards through a 10 Gigabit Ethernet transmission line. The storage chip 3 can be used to store the firmware of the first 10 Gigabit PHY chip 12 and / or the second 10 Gigabit PHY chip 22 to ensure that the first 10 Gigabit PHY chip 12 and / or the second 10 Gigabit PHY chip 22 can quickly and accurately read and run the firmware, thereby realizing data transmission between the two development boards through 10 Gigabit Ethernet with a fast transmission rate, thereby improving the transmission efficiency of the vehicle Ethernet and expanding the application scenarios of the vehicle Ethernet.

[0041] In addition, storing the firmware of the first 10 Gigabit PHY chip 12 and / or the second 10 Gigabit PHY chip 22 in the storage chip 3 can make the update and upgrade of the firmware more flexible and convenient. It is only necessary to replace or update the firmware file in the storage chip without replacing the entire 10 Gigabit PHY chip. It can also effectively prevent the firmware file from being accidentally deleted or damaged, thereby improving the reliability and stability of the data communication system. If the firmware is directly integrated on the 10 Gigabit PHY chip, once the firmware fails, the entire 10 Gigabit PHY chip may need to be replaced, which is costly. As an independent component, the failure of the storage chip will not directly affect the 10 Gigabit PHY chip, reducing the risk of overall hardware failure.

[0042] For the master-slave mode setting of the first 10G PHY chip 12 and the second 10G PHY chip 22 on the first development board 1 and the second development board 2, the storage chip 3 can realize resource sharing between the same development boards, avoiding the redundancy and waste of each chip needing to store firmware separately.

[0043] In some embodiments, the first 10 Gigabit PHY chip 12 includes N first chips, and the second 10 Gigabit PHY chip 22 includes N second chips, where N is a positive integer.

[0044] Among them, the N first chips and the N second chips are in master-slave mode with each other, the N first chips are all communicated with the first processor 11 through the USXGMII interface protocol, the N second chips are all communicated with the second processor 21 through the USXGMII interface protocol, and the N first chips and the N second chips are connected one-to-one through a 10 Gigabit Ethernet transmission line.

[0045] In this embodiment, it can be understood that the 10G PHY chips can communicate with each other under a master-slave design. In other words, to achieve data transmission between two development boards, the chip in the master mode in one development board must be set to correspond to the chip in the slave mode in the other development board.

[0046] That is, the first 10 Gigabit PHY chip 12 may include a first chip 121 in master mode and a first chip 122 in slave mode, which are connected to the first processor 11 through the USXGMII interface protocol, and the second 10 Gigabit PHY chip 22 may include a second chip 221 in master mode and a second chip 222 in slave mode, which are connected to the second processor 21 through the USXGMII interface protocol. The first chip 121 in master mode is connected to the second chip 222 in slave mode through a 10 Gigabit Ethernet transmission line, and the first chip 122 in slave mode is connected to the second chip 221 in master mode through a 10 Gigabit Ethernet transmission line, so as to realize data transmission between the first development board 1 and the second development board 2.

[0047] like Figure 2As shown, the first processor 11 and the second processor 21 are J784S4 / TDA4VH processors, and the first 10G PHY chip 12 and the second 10G PHY chip 22 are Marvell automotive-grade 10GBase-T1 compatible 88Q4364 chips as an example. Among them, the J784S4 / TDA4VH processor is used as a processor to control the sending and receiving of Ethernet data packets, and as a media access control sublayer protocol (Media Access Control, MAC) layer to provide Ethernet data packet communication for the PHY device, that is, the 88Q4364 chip. The first development board 1 and the second development board 2 both include a J784S4 / TDA4VH processor, an 88Q4364 (master) chip and an 88Q4364 (slave) chip, and the 88Q4364 (master) chip and the 88Q4364 (slave) chip communicate with the J784S4 / TDA4VH processor through the USXGMII interface protocol. The 88Q4364 (master) chip in the first development board 1 is connected to the 88Q4364 (slave) chip in the second development board 2 via a 10 Gigabit Ethernet transmission line ETH0, and the 88Q4364 (master) chip in the second development board 2 is connected to the 88Q4364 (slave) chip in the first development board 1 via a 10 Gigabit Ethernet transmission line ETH1.

[0048] In some embodiments, the 10 Gigabit Ethernet transmission line includes a first differential line, a second differential line, and an anti-interference layer, and the anti-interference layer wraps the first differential line and the second differential line.

[0049] In this embodiment, the 10 Gigabit Ethernet transmission line may include a first differential line and a second differential line. Figure 2 , taking the first processor 11 and the second processor 21 as J784S4 / TDA4VH processors, and the first 10G PHY chip 12 and the second 10G PHY chip 22 as Marvell automotive-grade 10GBase-T1 compatible 88Q4364 chips as an example. The 88Q4364 (master) chip in the first development board 1 and the 88Q4364 (slave) chip in the second development board 2 can be connected through the first differential line ETH0_P and the second differential line ETH0_N, and the 88Q4364 (master) chip in the second development board 2 and the 88Q4364 (slave) chip in the first development board 1 can be connected through the first differential line ETH1_P and the second differential line ETH1_N.

[0050] The 10 Gigabit Ethernet transmission line may further include an anti-interference layer, which wraps the first differential line and the second differential line to reduce noise interference in data transmission.

[0051] In some embodiments, the anti-interference layer includes a wire ground terminal and tin foil arranged in a stacked manner.

[0052] In this embodiment, the 10 Gigabit Ethernet transmission line is composed of two differential lines ETH_P and ETH_N, and is wrapped with a layer of wire ground terminal GND and tin foil to reduce noise interference in data transmission.

[0053] In some embodiments, the first processor 11 and the second processor 21 include:

[0054] The Ethernet switch 4 comprises a main port 41 and at least one data port 42, wherein a media independent interface (MII) of at least one data port 42 is configured as a USXGMII interface,

[0055] The deserializer 5 is connected to at least one data port 42 via a USXGMII interface 42 protocol communication, and the deserializer 5 is connected to the first 10 Gigabit PHY chip 12 or the second 10 Gigabit PHY chip 22 .

[0056] In this embodiment, if Figure 4 As shown, the first processor 11 and the second processor 21 may both include an Ethernet switch 4 and a deserializer 5. The Ethernet switch 4 may include a main port 41 and at least one data port 42, the deserializer 5 may be connected to the at least one data port 42 through a USXGMII interface protocol, and the deserializer 5 in the first processor 11 may be connected to the first 10 Gigabit PHY chip 12, and the deserializer 5 in the second processor 21 may be connected to the second 10 Gigabit PHY chip 22.

[0057] like Figure 3 and Figure 4As shown, when the application layer of the first development board 1 is about to send an Ethernet data message to the second development board 2, the data sending process of the first development board 1 is as follows: the J784S4 / TDA4VH processor can add transport layer, network layer and other header information to the transmitted data message in the Ethernet protocol stack, and transmit it to the main port 41 of the Ethernet switch 4. The data message transmitted by the main port 41 is forwarded to the data port 42, and then the data of the USXGMII interface protocol is processed by the deserializer 5. Finally, the deserializer 5 of the first development board 1 transmits it to the first 10 Gigabit PHY chip 12 of the first development board 1 through the data sending channel (TX_P, TX_N). The data receiving process of the second development board 2 is as follows: the second 10 Gigabit PHY chip 22 of the second development board 2 transmits the Ethernet data message to the deserializer 5 of the second development board 2 through the data receiving channel (RX_P, RX_N), and then the deserializer 5 processes the data of the USXGMII interface protocol, transmits it to the main port 41 through the data port 42, and finally transmits it to the J784S4 / TDA4VH processor of the second development board 2 through the main port 41 for processing, and finally transmits the data message to the application layer of the second development board 2.

[0058] In some embodiments, at least one data port includes N data ports, the N data ports are communicatively connected to the deserializer and the serializer via a USXGMII interface protocol, and the N data ports correspond one-to-one to N chips, and the chip includes a first chip or a second chip.

[0059] In this embodiment, the number of data ports is equal to the number of the first 10 Gigabit PHY chip 12 and the second 10 Gigabit PHY chip 22 , and isolation between data transmitted by each chip can be achieved through a one-to-one correspondence.

[0060] In some embodiments, when the first 10 Gigabit PHY chip 12 includes a first chip 121 in a master mode and a first chip 122 in a slave mode, and the second 10 Gigabit PHY chip 22 includes a second chip 221 in a master mode and a second chip 222 in a slave mode, the at least one data port 42 includes two data ports 42, and the deserializer 5 includes a first channel and a second channel.

[0061] Among them, one data port 42 is connected to the first channel, and the first channel is connected to the first chip 121 in master mode or the second chip 222 in slave mode, and another data port 42 is connected to the second channel, and the second channel is connected to the first chip 122 in slave mode or the second chip 221 in master mode.

[0062] In this embodiment, if Figure 2 and Figure 4As shown, the first 10G PHY chip 12 may include a first chip 121 in master mode and a first chip 122 in slave mode, and the second 10G PHY chip 22 may include a second chip 221 in master mode and a second chip 222 in slave mode. Accordingly, the two data ports 42 may include MAC1 and MAC2, and the deserializer 5 may include a first channel and a second channel.

[0063] Among them, the data port MAC1 can communicate with the first channel through the USXGMII interface protocol, and the data port MAC2 can communicate with the second channel through the USXGMII interface protocol. In the first development board 1, the first channel is connected to the first chip 121 in the master mode, and the second channel is connected to the first chip 122 in the slave mode. In the second development board 2, the first channel is connected to the second chip 222 in the slave mode, and the second channel is connected to the second chip 221 in the master mode.

[0064] like Figure 4 As shown, the Ethernet switch 4 is a 9-port CPSW9G as an example. Among them, the MAC0 port is the main port 41, which is used for data exchange between the J784S4 / TDA4VH processor and the protocol stack. MAC1 to MAC8 are data ports 42, which are used for data exchange between the MAC layer and the physical layer PHY chip. MAC1 and MAC2 are set as the data port 42 of the medium independent interface configured as the USXGMII interface, which is used to connect the 88Q4364 (master) chip and the 88Q4364 (slave) chip.

[0065] Since CPSW9G includes 8 data ports, two 4-channel deserializers 5 can be used, and the 4 channels include LANE1, LANE2, LANE3 and LANE4. Among them, MAC1 is connected to LANE3 of the deserializer 5, and MAC2 is connected to LANE4 of the deserializer 5.

[0066] In some embodiments, the main port 41 performs filtering and isolation of data transmission with the N data ports 42 based on the VLAN ID.

[0067] In this embodiment, the Ethernet switch 4 can filter and isolate data packets based on VLAN IDs. For example, data packets with VLAN ID 2 can be forwarded to data port MAC1, and data packets with VLAN ID 3 can be forwarded to data port MAC2.

[0068] like Figure 3 and Figure 4As shown, when the application layer of the first development board 1 is about to send an Ethernet data message to the second development board 2, the data sending process of the first development board 1 is as follows: the J784S4 / TDA4VH processor of the first development board 1 adds the transport layer, network layer and other header information to the transmitted data message in the Ethernet protocol stack, and adds the relevant VLANID to the data link layer and forms a frame format to transmit to MAC0 of the CPSW9G Ethernet switch 4. The data message transmitted by MAC0 is forwarded to MAC1 or MAC2 according to the VLAN ID, and then the data of the data port 42 is processed by the deserializer 5. Finally, the deserializer 5 of the first development board 1 transmits it to the 88Q4364 (master) chip of the first development board 1 through TX_P and TX_N of MAC1 or MAC2. The data receiving process of the second development board 2 is as follows: the 88Q4364 (slave) chip of the second development board 2 transmits the Ethernet data message to the deserializer 5 through the RX_P or RX_N of the second development board 2 MAC1 or MAC2, and then enters the CPSW9G Ethernet switch 4 through the data port 42 to perform VLAN ID filtering and isolation on the data, and then transmits it to the J784S4 / TDA4VH processor of the second development board 2 through MAC0 for processing, and finally transmits the data message to the application layer of the second development board 2.

[0069] In some embodiments, when the rate of the first 10 Gigabit PHY chip and the second 10 Gigabit PHY chip is a fixed rate, the working mode is full-duplex mode, and the first processor and the second processor obtain the fixed rate and full-duplex mode through the automatic negotiation mode, the first processor 11 is connected to the first 10 Gigabit PHY chip 12 using a fixed rate connection method, and the second processor 21 is connected to the second 10 Gigabit PHY chip 22 using a fixed rate connection method.

[0070] In this embodiment, the first processor 11 and the first 10G PHY chip 12, and the second processor 21 and the second 10G PHY chip 22 can be connected in a fixed rate connection mode. For example, the data transmission rate between MAC1, MAC2 and the 10G PHY chip can be set to a fixed rate, and the working mode can be set to a full-duplex mode. The first processor and the second processor obtain the fixed rate and full-duplex mode from the 10G PHY chip through the automatic negotiation mode, that is, data can be transmitted at a fixed rate, and any development board can receive data while transmitting data.

[0071] In some embodiments, the fixed rate may be 5 Gbps or 10 Gbps, so after the deserializer 5 processes the data of the USXGMII interface protocol, the data rate of transmitting the Ethernet message may reach 5 Gbps or 10 Gbps.

[0072] The present application also provides a specific scenario embodiment of the configuration process of the above data communication system, which may include the following configuration process:

[0073] Step 1: Set the 10G PHY chip configuration information.

[0074] The configuration information of 10G PHY can be set on the SOC side. For example, a device node phy1 of the 10G PHY chip can be created in the device tree, and the phy1 MDIO protocol parameter can be set to "ethernet-phy-ieee802.3-c45", the PHY1 speed parameter ethphy-speed can be set to "5000", and the phy1 master-slave mode ethphy-mode can be set to master mode.

[0075] When the MDIO on the SOC side is started, the PMA_PMD_IEEE_DEVICE_ID of the 10G PHY chip will be read through the set "ethernet-phy-ieee802.3-c45" protocol to match the corresponding 10G PHY chip driver. In the 10G PHY chip driver, the speed of the 10G PHY chip will be set to "5000" according to the device tree ethphy-speed, and the master-slave mode of the 10G PHY chip will be set according to the ethphy-mode parameter in the device tree. In the 10G PHY chip driver, the negotiation mode of phy is set to auto-negotiation, and the duplex mode of phy is set to full-duplex working mode.

[0076] After the 10G PHY chip driver successfully sets the PHY parameters, the 10G PHY chip is in normal working state, waiting for negotiation and communication with MAC.

[0077] Step 2: Set the MAC MII data transmission mode to USXGMII.

[0078] In the Linux driver device tree, set the phy-mode of the SOC-side MAC port to USXGMII mode. In USXGMII mode, enable the RX and TX data transmission functions of the MAC port XGMII, and at the same time enable the 10Gigabit mode of the MAC port, so that the MAC port supports data transmission under the USXGMII protocol.

[0079] Step 3: Set the SERDES configuration information.

[0080] In the Linux device tree, set the cdns and phy-type parameters of SERDES to USXGMII mode, set the LANE parameters related to SERDES and MAC, and bind the MAC port to the LANE of SERDES. In USXGMII mode, set the reference clock of SERDES LANE to 156.25Mhz, and set the LINK rate of SERDES LANE to 5.156Gbps.

[0081] The parallel data packets transmitted by MACPORT enter the SERDES LANE for parallel-to-serial processing.

[0082] Step 4: MAC port negotiates connection with 10G PHY chip

[0083] Set the MAC port to USXGMII auto-negotiation mode. The MAC port will automatically negotiate with the 10G PHY chip, and will automatically negotiate the rate and duplex mode. Because the rate is set to "5000" and full-duplex in the 10G PHY driver, the MAC end sets the corresponding USXGMII rate and duplex mode.

[0084] Step 5: Connect the MAC and 10G PHY chip via USXGMII.

[0085] Check the connection status between MAC and 10G PHY chip through XGMII LINK register on SOC MAC side, poll the value of this register, and wait for MAC and 10G PHY chip to connect.

[0086] Step 6: MAC and 10G PHY perform data communication.

[0087] The above are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A data communication system, characterized in that: include: The first development board includes a first processor and a first 10G PHY chip, wherein the first processor is connected to the first 10G PHY chip through a USXGMII interface protocol. The second development board includes a second processor and a second 10 Gigabit PHY chip, wherein the second processor is connected to the second 10 Gigabit PHY chip through a USXGMII interface protocol. The first development board and / or the second development board further comprises: a storage chip, connected to the first 10 Gigabit PHY chip and / or the second 10 Gigabit PHY chip, wherein the storage chip is used to store firmware of the first 10 Gigabit PHY chip and / or the second 10 Gigabit PHY chip; The first 10 Gigabit PHY chip and the second 10 Gigabit PHY chip are connected via a 10 Gigabit Ethernet transmission line.

2. The system according to claim 1, characterized in that The storage chip is used for, during the power-on startup process of the first development board and the second development board, the 10 Gigabit PHY chip loads the firmware of the 10 Gigabit PHY chip from the storage chip and runs it, and when the firmware runs successfully, establishes a communication link; The 10 Gigabit PHY chip includes the first 10 Gigabit PHY chip and / or the second 10 Gigabit PHY chip.

3. The system according to claim 1, characterized in that The first 10G PHY chip includes N first chips, and the second 10G PHY chip includes N second chips, where N is a positive integer. Among them, the N first chips and the N second chips are in master-slave mode with each other, the N first chips are all communicated with the first processor through the USXGMII interface protocol, the N second chips are all communicated with the second processor through the USXGMII interface protocol, and the N first chips and the N second chips are connected one-to-one through a 10 Gigabit Ethernet transmission line.

4. The system according to any one of claims 1 to 3, characterized in that The 10 Gigabit Ethernet transmission line includes a first differential line, a second differential line and an anti-interference layer, and the anti-interference layer wraps the first differential line and the second differential line; The anti-interference layer includes a wire grounding terminal and tin foil which are stacked.

5. The system according to claim 3, characterized in that The first processor and the second processor include: An Ethernet switch comprising a master port and at least one data port, wherein a media independent interface of the at least one data port is configured as a USXGMII interface, A deserializer is communicatively connected to the at least one data port via a USXGMII interface protocol, and the deserializer is connected to the first 10 Gigabit PHY chip or the second 10 Gigabit PHY chip.

6. The system according to claim 5, characterized in that The at least one data port includes N data ports, the N data ports are communicatively connected to the deserializer and the serializer via a USXGMII interface protocol, and the N data ports correspond one-to-one to N chips, and the chip includes the first chip or the second chip.

7. The system according to claim 6, characterized in that In the case where the first 10 Gigabit PHY chip includes a first chip in a master mode and a first chip in a slave mode, and the second 10 Gigabit PHY chip includes a second chip in a master mode and a second chip in a slave mode, the at least one data port includes two data ports, and the deserializer includes a first channel and a second channel. Among them, one data port is connected to the first channel, and the first channel is connected to the first chip in master mode or the second chip in slave mode, and another data port is connected to the second channel, and the second channel is connected to the first chip in slave mode or the second chip in master mode.

8. The system according to claim 6, characterized in that The main port performs filtering and isolation of data transmission with the N data ports based on the VLAN ID.

9. The system according to any one of claims 1 to 3, characterized in that When the rate of the first 10 Gigabit PHY chip and the second 10 Gigabit PHY chip is a fixed rate, the working mode is a full-duplex mode, and the first processor and the second processor obtain the fixed rate and the full-duplex mode through an automatic negotiation mode, the first processor is connected to the first 10 Gigabit PHY chip in a fixed rate connection mode, and the second processor is connected to the second 10 Gigabit PHY chip in a fixed rate connection mode.

10. The system according to claim 9, characterized in that The fixed rate is 5 Gbps or 10 Gbps.

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