Semiconductor structure and preparation method thereof

Abstract

The present disclosure provides a semiconductor structure and a method for fabricating the same, relating to the field of semiconductors. The semiconductor structure comprises a substrate and an isolation structure. The substrate comprises a plurality of active regions arranged in an array of intervals. The isolation structure is located within the substrate and between adjacent active regions. The isolation structure comprises a dipole layer and an isolation layer. The dipole layer is located below the isolation layer and between the isolation layer and the substrate. The negatively charged surface of the dipole layer faces the substrate, while the positively charged surface of the dipole layer faces the isolation layer. The present disclosure reduces the likelihood of leakage in the semiconductor structure, thereby ensuring the storage performance of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to semiconductor structures and methods for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] The substrate of a DRAM includes a plurality of active regions spaced apart from each other, and a shallow trench isolation (STI) structure for isolating adjacent active regions.

[0004] However, the aforementioned shallow trench isolation structure has a hot electron induced punch through (HEIP) effect, which easily causes leakage, thereby affecting the storage performance of the memory. Summary of the Invention

[0005] The present disclosure provides a semiconductor structure and a preparation method thereof, which are used to solve the problem that a shallow trench isolation structure has a hot carrier penetration effect, is prone to leakage, and thus affects the storage performance of a memory.

[0006] In a first aspect, the present disclosure provides a semiconductor structure comprising a substrate and an isolation structure, wherein the substrate comprises a plurality of active regions arranged in an array of intervals, and the isolation structure is located in the substrate and between adjacent active regions;

[0007] The isolation structure includes a dipole layer and an isolation layer. The dipole layer is located at the bottom of the isolation layer and between the isolation layer and the substrate. The negative charge surface of the dipole layer faces the substrate, and the positive charge surface of the dipole layer faces the isolation layer.

[0008] In the above semiconductor structure, optionally, the dipole layer includes a metal film layer and a high dielectric constant film layer that are bonded to each other and subjected to heat treatment;

[0009] One of the surface of the metal film layer facing away from the high dielectric constant film layer and the surface of the high dielectric constant film layer facing away from the metal film layer forms a positive charge surface of the dipole layer; the other of the surface of the metal film layer facing away from the high dielectric constant film layer and the surface of the high dielectric constant film layer facing away from the metal film layer forms a negative charge surface of the dipole layer.

[0010] In the above semiconductor structure, optionally, the metal film layer is configured as an aluminum film layer;

[0011] The surface of the aluminum film layer facing away from the high dielectric constant film layer forms the positive charge surface of the dipole layer, and the surface of the high dielectric constant film layer facing away from the aluminum film layer forms the negative charge surface of the dipole layer.

[0012] In the above semiconductor structure, optionally, the metal film layer is configured as a lanthanum film layer;

[0013] The surface of the high dielectric constant film layer facing away from the lanthanum film layer forms the positive charge surface of the dipole layer, and the surface of the lanthanum film layer facing away from the high dielectric constant film layer forms the negative charge surface of the dipole layer.

[0014] In the above-mentioned semiconductor structure, optionally, the thickness of the metal film layer is greater than or equal to 2 nanometers and less than or equal to 5 nanometers; and / or the thickness of the high dielectric constant film layer is greater than or equal to 2 nanometers and less than or equal to 20 nanometers.

[0015] In the above semiconductor structure, optionally, the substrate has a trench, and the dipole layer and at least a portion of the isolation layer are located in the trench;

[0016] The dipole layer is located at the bottom of the groove; or, part of the dipole layer is located at the bottom of the groove, and the rest of the dipole layer is located at a position on the side surface of the groove close to the bottom.

[0017] In the above semiconductor structure, optionally, the isolation layer includes a first isolation layer, a second isolation layer, and a third isolation layer that are stacked;

[0018] The first isolation layer covers the inner wall of the trench and the dipole layer, and the first isolation layer is away from the surface of the substrate to form a first groove;

[0019] The second isolation layer is disposed in the first groove, the second isolation layer adheres to the surface of the first isolation layer facing away from the substrate, and the surface of the second isolation layer facing away from the first isolation layer forms a second groove;

[0020] The third isolation layer fills the second groove.

[0021] In the above semiconductor structure, optionally, a material of the first isolation layer is the same as a material of the third isolation layer, and different from a material of the second isolation layer.

[0022] In the above-mentioned semiconductor structure, optionally, the thickness of the first isolation layer close to the top surface of the substrate is greater than the thickness of the first isolation layer away from the top surface of the substrate; or, the thickness of the second isolation layer close to the top surface of the substrate is greater than the thickness of the second isolation layer away from the top surface of the substrate.

[0023] In the above semiconductor structure, optionally, the material of the first isolation layer and the material of the third isolation layer are both set to oxide, and the material of the second isolation layer is set to nitride.

[0024] In a second aspect, the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0025] Providing a substrate comprising a plurality of active regions arranged in an array;

[0026] forming an isolation structure, wherein the isolation structure is located in the substrate and between adjacent active regions;

[0027] The isolation structure includes a dipole layer and an isolation layer, wherein the dipole layer is located at the bottom of the isolation layer and between the isolation layer and the substrate; the negatively charged surface of the dipole layer faces the substrate, and the positively charged surface of the dipole layer faces the isolation layer.

[0028] In the above-mentioned method for preparing a semiconductor structure, optionally, forming the isolation structure includes:

[0029] forming a trench in the substrate, wherein the trench is located between adjacent active regions;

[0030] forming a dipole layer, wherein the dipole layer is located at the bottom of the groove, wherein the bottom of the groove includes the groove bottom surface of the groove; or, the bottom of the groove includes the groove bottom surface of the groove and a position close to the groove bottom among the groove side surfaces of the groove;

[0031] The isolation layer is formed, and the isolation layer is located in the trench and covers the dipole layer.

[0032] In the above-mentioned method for preparing a semiconductor structure, optionally, forming the dipole layer includes:

[0033] forming a metal film layer, wherein the metal film layer is located at the bottom of the groove, and the metal film layer is configured as an aluminum film layer;

[0034] forming a high dielectric constant film layer, wherein the high dielectric constant film layer covers the top surface of the aluminum film layer;

[0035] The aluminum film layer and the high dielectric constant film layer are heat-treated; the surface of the aluminum film layer facing away from the high dielectric constant film layer forms a positive charge surface of the dipole layer, and the surface of the high dielectric constant film layer facing away from the aluminum film layer forms a negative charge surface of the dipole layer.

[0036] In the above-mentioned method for preparing a semiconductor structure, optionally, forming the dipole layer includes:

[0037] forming a high dielectric constant film layer, wherein the high dielectric constant film layer is located at the bottom of the trench;

[0038] forming a metal film layer, wherein the metal film layer is configured as a lanthanum film layer, and the lanthanum film layer covers a top surface of the high dielectric constant film layer;

[0039] The lanthanum film layer and the high dielectric constant film layer are heat-treated; the surface of the high dielectric constant film layer facing away from the lanthanum film layer forms a positive charge surface of the dipole layer, and the surface of the lanthanum film layer facing away from the high dielectric constant film layer forms a negative charge surface of the dipole layer.

[0040] In the above-mentioned method for preparing a semiconductor structure, optionally, the isolation layer includes a first isolation layer, a second isolation layer, and a third isolation layer that are stacked; and forming the isolation layer includes:

[0041] forming a first isolation layer, wherein the first isolation layer covers the inner wall of the trench and the dipole layer, and a surface of the first isolation layer facing away from the substrate forms a first groove;

[0042] forming a second isolation layer, the second isolation layer being disposed in the first groove, the second isolation layer being in contact with a surface of the first isolation layer facing away from the inner wall of the groove, and a surface of the second isolation layer facing away from the first isolation layer forming a second groove;

[0043] The third isolation layer is formed, and the third isolation layer fills the second groove.

[0044] The present disclosure provides a semiconductor structure and a method for fabricating the same. The structure comprises a plurality of active regions arranged in an array of intervals, and an isolation structure positioned between adjacent active regions. The isolation structure isolates the different active regions, thereby preventing electrical interference between the active regions. The isolation structure includes a dipole layer and an isolation layer. The dipole layer is positioned below the isolation layer and between the isolation layer and the substrate. The negatively charged surface of the dipole layer faces the substrate, while the positively charged surface of the dipole layer faces the isolation layer.

[0045] In this way, a dipole layer can be set with the negatively charged surface of the dipole layer facing the substrate and the positively charged surface of the dipole layer facing the isolation layer, so that the electrostatic potential at the bottom of the isolation structure is higher than the electrostatic potential at the top of the isolation structure, and the electrostatic potential energy of the hot carriers at the top of the isolation structure is higher than the electrostatic potential energy of the hot carriers at the bottom of the isolation structure, so that the hot carriers at the top of the isolation structure move to the bottom of the isolation structure. In this way, the possibility of hot carriers in the substrate being captured by the top of the isolation structure to form an electron accumulation zone can be reduced, thereby preventing the formation of a hole accumulation zone corresponding to the electron accumulation zone in the active area, reducing the possibility of breakdown between the two, reducing the possibility of HEIP effect in the semiconductor structure, and reducing the possibility of leakage in the semiconductor structure, thereby improving the yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0047] Figure 1 Schematic diagram of the structure of a silicon nitride layer and source / drain regions;

[0048] Figure 2 A schematic structural diagram of a semiconductor structure including a gate layer and a gate dielectric layer provided in an embodiment of the present disclosure;

[0049] Figure 3 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0050] Figure 4 A schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0051] Figure 5 A schematic diagram of the movement direction of hot carriers under the action of a dipole layer provided in an embodiment of the present disclosure;

[0052] Figure 6 A schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0053] Figure 7 A schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0054] Figure 8 A schematic flow chart of a method for preparing a semiconductor junction is provided for an embodiment of the present disclosure;

[0055] Figure 9 A schematic structural diagram of a substrate with grooves provided in an embodiment of the present disclosure;

[0056] Figure 10 A schematic diagram of a structure for forming a dipole layer according to an embodiment of the present disclosure;

[0057] Figure 11 A schematic structural diagram of forming a first isolation layer according to an embodiment of the present disclosure;

[0058] Figure 12 A schematic structural diagram of forming a second isolation layer according to an embodiment of the present disclosure;

[0059] Figure 13 A schematic structural diagram of forming a third isolation layer according to an embodiment of the present disclosure.

[0060] Description of reference numerals:

[0061] 1. Silicon nitride layer; 2. Source / drain region;

[0062] 100, substrate;

[0063] 110, active region; 111, first active region; 112, second active region; 113, gate layer; 114, gate dielectric layer; 120, trench;

[0064] 200, isolation structure;

[0065] 210, dipole layer;

[0066] 211, metal film layer; 212, high dielectric constant film layer; 220, isolation layer; 221, first isolation layer; 2211, first groove; 222, second isolation layer; 2221, second groove; 223, third isolation layer.

[0067] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0068] The substrate of a DRAM device is equipped with multiple spaced-apart source / drain regions. Adjacent source / drain regions are separated by isolation regions, each containing an isolation structure to isolate adjacent source / drain regions and prevent electrical interference. This isolation structure is often fabricated using shallow trench isolation (STI). The isolation structure comprises multiple stacked isolation layers, each of which includes a silicon nitride layer.

[0069] Reference Figure 1 As shown, the source / drain region 2 and the silicon nitride layer 1 of the isolation structure are spaced apart, and an isolation layer can be provided between the two (the isolation layer between the source / drain region 2 and the isolation structure is not shown in the figure). Figure 1The hot carriers in the source / drain region 2 will be captured by the silicon nitride layer 1 located at the side wall position of the source / drain region 2, so that an electron accumulation region is formed in the silicon nitride layer 1, and a hole accumulation region corresponding to the electron accumulation region is formed at the side wall position of the source / drain region 2. For example, in a P-channel metal oxide semiconductor structure (PMOS) in which holes are the main carriers, when the semiconductor structure is in a working state, hot carriers will continue to accumulate on the top of the isolation structure, making the semiconductor structure prone to HEIP effect, shortening the channel length of the semiconductor structure, and increasing the leakage current, resulting in leakage problems, leading to poor DRAM devices.

[0070] During the research process, it was found that increasing the amount of hot carriers captured at the bottom of the isolation structure can effectively alleviate the above-mentioned HEIP effect; increasing the amount of hot carriers captured at the bottom of the isolation structure can reduce the possibility of electron accumulation areas and hole accumulation areas formed between the top of the isolation structure and the source / drain region 2, and reduce the possibility of hot carriers accumulating at the top of the isolation structure. In this way, the problem of shortening the channel length can be alleviated, and leakage problems can be avoided or alleviated, thereby improving the yield of DRAM devices.

[0071] In light of this, the present disclosure provides a semiconductor structure and a method for fabricating the same. The structure comprises a substrate containing multiple active regions arranged in an array of intervals, and an isolation structure positioned between adjacent active regions. The isolation structure isolates the different active regions and prevents electrical interference between the active regions. The isolation structure includes a dipole layer and an isolation layer. The dipole layer is positioned below the isolation layer and between the isolation layer and the substrate. The negatively charged surface of the dipole layer faces the substrate, while the positively charged surface of the dipole layer faces the isolation layer.

[0072] In this way, a dipole layer can be set with the negatively charged surface of the dipole layer facing the substrate and the positively charged surface of the dipole layer facing the isolation layer, so that the electrostatic potential at the bottom of the isolation structure is higher than the electrostatic potential at the top of the isolation structure, and the electrostatic potential energy of the hot carriers at the top of the isolation structure is higher than the electrostatic potential energy of the hot carriers at the bottom of the isolation structure, so that the hot carriers at the top of the isolation structure move to the bottom of the isolation structure. In this way, the possibility of hot carriers in the substrate accumulating at the top of the isolation structure can be reduced, the possibility of the HEIP effect occurring in the semiconductor structure can be reduced, and the possibility of leakage in the semiconductor structure can be reduced, thereby improving the yield of the semiconductor structure.

[0073] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0074] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present disclosure, and should not be understood as limitations on the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. The embodiments of the present disclosure are described in detail below in conjunction with the drawings.

[0075] Reference Figure 2 and Figure 3 As shown, in the first aspect, an embodiment of the present disclosure provides a semiconductor structure, including a substrate 100 and an isolation structure 200, wherein the substrate 100 includes a plurality of active areas 110 arranged in an interval array, and the isolation structure 200 is located in the substrate 100 and between adjacent active areas 110, so as to isolate different active areas 110 through the isolation structure 200 and reduce the possibility of electrical interference between the active areas 110.

[0076] Reference Figure 3 and Figure 5 As shown, the isolation structure 200 includes a dipole layer 210 and an isolation layer 220. The dipole layer 210 is located at the bottom of the isolation layer 220 and between the isolation layer 220 and the substrate 100. The negatively charged surface of the dipole layer 210 faces the substrate 100, and the positively charged surface of the dipole layer 210 faces the isolation layer 220, so that the electrostatic potential at the bottom of the isolation structure 200 is higher than the electrostatic potential at the top of the isolation structure 200.

[0077] It should be noted that hot carriers usually carry negative charges. When the hot carriers are at a high electrostatic potential, the electrostatic potential energy of the hot carriers is low. When the hot carriers are at a low electrostatic potential, the classical potential energy of the hot carriers is high. Therefore, hot carriers can easily move from the low electrostatic potential in the isolation structure 200 to the high electrostatic potential in the isolation structure 200 to reduce the electrostatic potential energy of the hot carriers.

[0078] By placing the negatively charged surface of the dipole layer 210 toward the substrate 100 and the positively charged surface of the dipole layer 210 toward the isolation layer 220, the electrostatic potential at the bottom of the isolation structure 200 is higher than the electrostatic potential at the top of the isolation structure 200, and the entropy change at the bottom of the isolation structure 200 is greater than the entropy change at the top of the isolation structure 200, thereby making the probability of hot carriers being captured at the bottom of the isolation structure 200 greater than the probability of hot carriers being captured at the top of the isolation structure 200, thereby reducing the possibility of hot carriers in the substrate 100 being captured by the top of the isolation structure 200 to form an electron accumulation area.

[0079] The substrate 100 may provide a support base for the structural layers disposed on the substrate 100. The material of the substrate 100 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, silicon-on-insulator (SOI), or other materials known to those skilled in the art.

[0080] Reference Figure 2 and Figure 3 As shown, the substrate 100 includes an active region 110 . The active region 110 can be formed by ion doping. The active region 110 can be a source region and / or a drain region. This embodiment does not limit the type of the active region 110 .

[0081] There may be multiple active regions 110, and the multiple active regions 110 may be arranged in an array in a spaced-apart manner in the substrate 100. A trench 120 may be provided in the substrate 100 on one side of the active region 110. The trench 120 may serve as a structural foundation for the subsequent formation of an isolation structure 200. Alternatively, the trench 120 may be located between two adjacent active regions 110, so that the isolation structure 200 located in the trench 120 can be used to electrically isolate the two adjacent active regions 110, thereby reducing the possibility of electrical interference between the two adjacent active regions 110.

[0082] Exemplarily, the groove 120 is configured as follows: the groove 120 extends along the thickness direction of the substrate 100, and the bottom of the groove 120 includes the bottom surface of the groove 120; or, the bottom of the groove 120 includes the bottom surface of the groove 120 and a position close to the bottom of the groove on the side surface of the groove 120, and the top of the groove 120 is set to a position close to the top surface of the substrate 100.

[0083] Reference Figure 3 As shown, as an achievable embodiment, in the trench 120 of the substrate 100, the dipole layer 210 is located at the bottom surface of the trench 120; or, referring to Figure 4As shown, part of the dipole layer 210 is located at the bottom of the groove 120, and the remaining part of the dipole layer 210 is located at a position close to the bottom of the groove on the side surface of the groove 120, so that the dipole layer 210 is set at the bottom of the groove 120, and the surface of the dipole layer 210 facing away from the substrate 100 is connected to the isolation layer 220, so that hot carriers are easily gathered at the bottom of the groove 120 or at a position close to the bottom of the groove on the side surface of the groove 120.

[0084] The dipole layer 210 includes a metal film layer 211 and a high dielectric constant film layer 212 that are bonded to each other and have been heat-treated. One of the metal film layer 211 and the high dielectric constant film layer 212 is bonded to the substrate 100, and the other of the metal film layer 211 and the high dielectric constant film layer 212 is away from the substrate 100; one of the surface of the metal film layer 211 away from the high dielectric constant film layer 212 and the surface of the high dielectric constant film layer 212 away from the metal film layer 211 forms a positively charged surface of the dipole layer 210; the other of the surface of the metal film layer 211 away from the high dielectric constant film layer 212 and the surface of the high dielectric constant film layer 212 away from the metal film layer 211 forms a negatively charged surface of the dipole layer 210.

[0085] Exemplarily, the material of the high dielectric constant film layer 212 can be set to one of hafnium silicon oxide, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide and strontium titanium oxide; for example, the material of the high dielectric constant film layer 212 can be set to hafnium silicon oxide (chemical formula HfSiO x ).

[0086] Reference Figure 3 and Figure 4 As shown, in the dipole layer 210, the metal film layer 211 can be set as an aluminum film layer, the material of the aluminum film layer can be set as metal aluminum (chemical formula is Al), the high dielectric constant film layer 212 is attached to the substrate 100, and the aluminum film layer is away from the substrate 100 relative to the high dielectric constant film layer 212; after the aluminum film layer and the high dielectric constant film layer 212 are attached to each other and subjected to heat treatment, the surface of the aluminum film layer away from the high dielectric constant film layer 212 forms the positive charge surface of the dipole layer 210, and the surface of the high dielectric constant film layer 212 away from the aluminum film layer forms the negative charge surface of the dipole layer 210.

[0087] Alternatively, in the dipole layer 210, the metal film layer 211 can also be set as a lanthanum film layer, the material of the lanthanum film layer can be set as metal lanthanum (chemical formula is La), the lanthanum film layer is adhered to the substrate 100, and the high dielectric constant film layer 212 is away from the substrate 100 relative to the lanthanum film layer; after the lanthanum film layer and the high dielectric constant film layer 212 are adhered to each other and subjected to heat treatment, the surface of the high dielectric constant film layer 212 away from the lanthanum film layer forms the positive charge surface of the dipole layer 210, and the surface of the lanthanum film layer away from the high dielectric constant film layer 212 forms the negative charge surface of the dipole layer 210.

[0088] The depth of the groove 120 can be set to 300 nanometers, and the thickness of the metal film layer 211 can be greater than or equal to 2 nanometers and less than or equal to 5 nanometers. For example, the thickness of the metal film layer 211 can be set to one of 2 nanometers, 3 nanometers, 4 nanometers, and 5 nanometers.

[0089] And / or, the thickness of the high dielectric constant film layer 212 is greater than or equal to 2 nanometers and less than or equal to 20 nanometers. For example, the thickness of the high dielectric constant film layer 212 can be set to one of 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 8 nanometers, 10 nanometers, 15 nanometers and 20 nanometers to ensure that the bonded metal film layer 211 and the high dielectric constant film layer 212 can form a dipole layer 210 after heat treatment.

[0090] Reference Figure 3 As shown, as a feasible embodiment, the bottom of the isolation layer 220 can be set on the surface of the dipole layer 210 away from the bottom of the groove 120, and the top of the isolation layer 220 is farther away from the dipole layer 210 relative to the bottom of the isolation layer 220.

[0091] Exemplarily, the isolation layer 220 includes a first isolation layer 221, a second isolation layer 222, and a third isolation layer 223 that are stacked, wherein the first isolation layer 221 is disposed in the trench 120 of the substrate 100, and a portion of the first isolation layer 221 covers the dipole layer 210, and a portion of the first isolation layer 221 that does not cover the dipole layer 210 covers the inner wall of the substrate 100, and a first groove 2211 may be formed on a surface of the first isolation layer 221 facing away from the substrate 100;

[0092] The second isolation layer 222 can be arranged in the first groove 2211, and the second isolation layer 222 adheres to the surface of the first isolation layer 221 facing away from the substrate 100. The surface of the second isolation layer 222 facing away from the first isolation layer 221 can also form a second groove 2221, and the third isolation layer 223 is filled in the second groove 2221, so that the first isolation layer 221, the second isolation layer 222 and the third isolation layer 223 are stacked in sequence in the groove 120 to form an isolation layer 220.

[0093] The material of the first isolation layer 221 is the same as the material of the third isolation layer 223, and is different from the material of the second isolation layer 222. Exemplarily, the material of the first isolation layer 221 and the material of the third isolation layer 223 are both set to oxides, for example, the material of the first isolation layer 221 and the material of the third isolation layer 223 are both set to silicon oxide, and the material of the second isolation layer 222 is set to nitride, for example, the material of the second isolation layer 222 can be set to silicon nitride, so that the adsorption capacity of the second isolation layer 222 for hot carriers is higher than the adsorption capacity of the first isolation layer 221 and the third isolation layer 223 for hot carriers, so that the hot carriers are easily captured by the second isolation layer 222.

[0094] Reference Figure 6 As shown, as an achievable embodiment, the thickness of the first isolation layer 221 close to the top surface of the substrate 100 (ie Figure 6 a), is greater than the thickness of the first isolation layer 221 away from the top surface of the substrate 100 (ie Figure 6 b); because the second isolation layer 222 is disposed on the surface of the first isolation layer 221 facing away from the substrate 100, the distance between the second isolation layer 222 and the active area 110 is affected by the thickness of the first isolation layer 221. Therefore, in this embodiment, the thickness of the first isolation layer 221 near the top surface of the substrate 100 is set to be larger, which can ensure a larger distance between the second isolation layer 222 near the top surface of the substrate 100 and the active area 110.

[0095] Accordingly, the thickness of the portion of the first isolation layer 221 away from the top surface of the substrate 100 is set to be smaller, which can ensure that the distance between the second isolation layer 222 away from the top surface of the substrate 100 and the active area 110 is smaller.

[0096] It should be noted that in a semiconductor structure, a large number of hot carriers generally migrate closer to the opening of the trench 120 than to the bottom of the trench 120. Therefore, an electron accumulation region is generally formed in the second isolation layer 222 located on the top sidewall. Accordingly, a hole accumulation region is formed in the active area 110 corresponding to the top sidewall of the trench 120, so that the location where electrical breakdown occurs is correspondingly closer to the opening of the trench 120.

[0097] By setting the second isolation layer 222 as follows: the distance between the second isolation layer 222 close to the top surface of the substrate 100 and the active area 110 is larger, and the distance between the second isolation layer 222 away from the top surface of the substrate 100 and the active area 110 is smaller, the migration path of the hot carriers on the side of the notch close to the groove 120 can be effectively increased, the situation where the hot carriers are captured by the second isolation layer 222 is alleviated, the formed electron accumulation area and the corresponding hole accumulation area are reduced, thereby reducing the possibility of electrical breakdown, alleviating the leakage problem, and improving the isolation effect of the isolation structure 200 and the yield of the semiconductor structure.

[0098] Reference Figure 7 As shown, as another achievable embodiment, the thickness of the second isolation layer 222 close to the top surface of the substrate 100 (ie Figure 7 c), may be greater than the thickness of the second isolation layer 222 away from the top surface of the substrate 100 (ie Figure 7 Accordingly, compared to the above embodiment in which the thickness of the second isolation layer 222 close to the top surface of the substrate 100 and the thickness away from the top surface of the substrate 100 are equal, in this embodiment, the thickness of the first isolation layer 221 close to the top surface of the substrate 100 is greater.

[0099] In this way, the migration path of hot carriers near the notch side of the trench 120 can be effectively increased, reducing the possibility of hot carriers being captured by the second isolation layer 222, thereby reducing the possibility of breakdown between the isolation structure 200 and the active area 110. In addition, the second isolation layer 222 near the top surface of the substrate 100 is thicker, which can effectively ensure the structural integrity of the isolation structure 200, thereby ensuring the isolation effect of the isolation structure 200.

[0100] Reference Figure 6 As shown, in some embodiments, the thickness of the second isolation layer 222 gradually increases from the groove opening to the bottom of the groove 120. This effectively ensures the flatness of the second isolation layer 222 attached to the first isolation layer 221. Furthermore, the flatness of the third isolation layer 223 formed in the second groove 2221 inside the second isolation layer 222 can be ensured, thereby effectively improving the structural regularity of the isolation structure 200.

[0101] As a feasible embodiment, in the process of manufacturing the semiconductor structure, at least part of the first isolation layer 221 is located outside the groove 120, and the part of the first isolation layer 221 located outside the groove 120 is located on the top surface of the substrate 100; at least part of the second isolation layer 222 is located outside the first groove 2211, and the part of the second isolation layer 222 located outside the first groove 2211 is located on the top surface of the first isolation layer 221; at least part of the third isolation layer 223 is located outside the second groove 2221, and the part of the third isolation layer 223 located outside the second groove 2221 is located on the top surface of the second isolation layer 222, or the third isolation layer 2211 is arranged flush with the top surface of the second isolation layer 222.

[0102] Among them, the top surface of the second isolation layer 222 located outside the first groove 2211 is flush with the top surface of the third isolation layer 223. In semiconductor preparation, the first isolation layer 221 located outside the groove 120, the second isolation layer 222 located outside the first groove 2211, and the third isolation layer 223 located outside the second groove 2221 can be polished along the top surface of the substrate 100 by a chemical mechanical polishing process (CMP), so that the top surfaces of the first isolation layer 221, the second isolation layer 222, and the third isolation layer 223 are all flush with the top surface of the substrate 100. The formed structure can be referred to Figure 3 shown.

[0103] Reference Figure 2 As shown, as an achievable embodiment, the plurality of active areas 110 include a first active area 111 and a second active area 112 spaced apart, and the trench 120 is located between the first active area 111 and the second active area 112. PMOS transistors are disposed in both the first active area 111 and the second active area 112.

[0104] It should be noted that in this embodiment, a first active region 111 and a second active region 112 are respectively provided on opposite sides of the isolation structure 200. The isolation structure 200 can electrically isolate the first active region 111 from the second active region 112. Transistor structures can be formed in both the first active region 111 and the second active region 112. The figure only shows the gate layer 113 and gate dielectric layer 114 of the transistor in the first active region 111. The gate dielectric layer 114 is provided between the gate layer 113 and the substrate 100. A channel region is provided in the substrate 100 at a location corresponding to the gate dielectric layer 114.

[0105] Based on the above, PMOS transistors are provided in both the first active region 111 and the second active region 112, and the first active region 111 and the second active region 112 near the first trench 120 are both P-type semiconductors. Of course, in some embodiments, NMOS transistors may be provided in the first active region 111 and the second active region 112 near the trench 120, and the first active region 111 and the second active region 112 near the trench 120 are both N-type semiconductors.

[0106] In the present disclosure, increasing the thickness of the first isolation layer 221 of the isolation structure 200 can also reduce the leakage current loff of the transistor in the off state, thereby increasing the gate control capability of the transistor.

[0107] In summary, in the semiconductor structure, by configuring the isolation structure 200 to include the dipole layer 210 and the isolation layer 220, with the negatively charged surface of the dipole layer 210 facing the substrate 100 and the positively charged surface of the dipole layer 210 facing the isolation layer 220, the electrostatic potential at the bottom of the isolation structure 200 is higher than the electrostatic potential at the top of the isolation structure 200, and the electrostatic potential energy of the hot carriers at the top of the isolation structure 200 is higher than the electrostatic potential energy of the hot carriers at the bottom of the isolation structure 200, so that the hot carriers at the top of the isolation structure 200 move toward the bottom of the isolation structure 200;

[0108] In this way, the entropy change at the bottom of the isolation structure 200 can be increased to increase the possibility of capturing hot carriers at the bottom of the isolation structure 200, reduce the possibility of hot carriers in the substrate 100 being captured by the top of the isolation structure 200, thereby forming an electron accumulation area, and prevent the formation of a hole accumulation area corresponding to the electron accumulation area in the active area 110, reduce the possibility of the HEIP effect in the semiconductor structure, and reduce the possibility of leakage in the isolation structure 200, thereby improving the yield of the semiconductor structure.

[0109] Reference Figures 8-13 As shown, in a second aspect, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0110] S100 , providing a substrate, wherein the substrate includes a plurality of active regions arranged in an array at intervals.

[0111] Reference Figure 9 As shown, the material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound, silicon-on-insulator, or other materials known to those skilled in the art. In addition, the active region 110 can be formed by ion doping. The active region 110 can be a source region and / or a drain region. This embodiment does not limit the type of the active region 110.

[0112] S200 , forming an isolation structure, where the isolation structure is located in the substrate and between adjacent active regions.

[0113] Reference Figure 3 As shown, the isolation structure 200 includes a dipole layer 210 and an isolation layer 220. The dipole layer 210 is located at the bottom of the isolation layer 220 and between the isolation layer 220 and the substrate 100. The negatively charged surface of the dipole layer 210 faces the substrate 100, and the positively charged surface of the dipole layer 210 faces the isolation layer 220.

[0114] Specifically, forming the isolation structure 200 includes:

[0115] A trench 120 is formed in the substrate 100 , wherein the trench 120 is located between adjacent active regions 110 ;

[0116] Reference Figure 9 As shown, for example, the trench 120 can be formed by masking and photolithography. That is, a hard mask and photoresist are sequentially formed on the substrate 100, and the mask pattern is transferred to the hard mask by etching with a high selectivity ratio. The hard mask pattern is then transferred to the substrate 100, thereby forming the trench 120. The depth of the trench 120 can be set to 300 nanometers.

[0117] Reference Figure 10 As shown, a dipole layer 210 is formed, and the dipole layer 210 is located at the bottom of the trench 120, and the bottom of the trench 120 includes the bottom surface of the trench 120; or, the bottom of the trench 120 includes the bottom surface of the trench 120 and a position close to the bottom of the trench 120 on the side surface of the trench 120;

[0118] Illustratively, the bottom of the groove 120 includes the bottom surface of the groove 120 ; or, the bottom of the groove 120 includes the bottom surface of the groove 120 and a position close to the bottom of the groove side surface of the groove 120 .

[0119] The dipole layer 210 includes a metal film layer 211 and a high dielectric constant film layer 212 that are bonded to each other and have been heat-treated. One of the metal film layer 211 and the high dielectric constant film layer 212 is bonded to the substrate 100, and the other of the metal film layer 211 and the high dielectric constant film layer 212 is away from the substrate 100; one of the surface of the metal film layer 211 away from the high dielectric constant film layer 212 and the surface of the high dielectric constant film layer 212 away from the metal film layer 211 forms a positively charged surface of the dipole layer 210; the other of the surface of the metal film layer 211 away from the high dielectric constant film layer 212 and the surface of the high dielectric constant film layer 212 away from the metal film layer 211 forms a negatively charged surface of the dipole layer 210.

[0120] Specifically, as an achievable implementation method, forming the dipole layer 210 includes:

[0121] forming a metal film layer 211, the metal film layer 211 being located at the bottom of the trench 120, and the metal film layer 211 being configured as an aluminum film layer;

[0122] For example, the aluminum film layer can be formed at the bottom of the trench 120 by an atomic layer deposition (ALD) process or a physical vapor deposition (PVD) process. The thickness of the aluminum film layer is greater than or equal to 2 nanometers and less than or equal to 5 nanometers. For example, the thickness of the aluminum film layer can be set to one of 2 nanometers, 3 nanometers, 4 nanometers, and 5 nanometers.

[0123] forming a high dielectric constant film layer 212, wherein the high dielectric constant film layer 212 covers the top surface of the aluminum film layer;

[0124] The high dielectric constant film layer 212 can be formed by a chemical vapor deposition process (CVD) on the surface of the aluminum film layer facing away from the substrate 100, and the thickness of the high dielectric constant film layer 212 is greater than or equal to 2 nanometers and less than or equal to 20 nanometers. For example, the thickness of the high dielectric constant film layer 212 can be set to one of 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 8 nanometers, 10 nanometers, 15 nanometers and 20 nanometers.

[0125] The aluminum film layer and the high dielectric constant film layer 212 are heat-treated; the surface of the aluminum film layer facing away from the high dielectric constant film layer 212 forms the positive charge surface of the dipole layer 210 , and the surface of the high dielectric constant film layer 212 facing away from the aluminum film layer forms the negative charge surface of the dipole layer 210 .

[0126] After a high dielectric constant film layer 212 is formed on the surface of the aluminum film layer facing away from the substrate 100, the aluminum film layer and the high dielectric constant film layer 212 can be heat-treated so that the surface of the aluminum film layer facing away from the high dielectric constant film layer 212 forms a positive charge surface of the dipole layer 210, and the surface of the high dielectric constant film layer 212 facing away from the aluminum film layer forms a negative charge surface of the dipole layer 210, thereby realizing the preparation of the dipole layer 210.

[0127] As another achievable implementation, forming the dipole layer 210 includes:

[0128] forming a high dielectric constant film layer 212 , the high dielectric constant film layer 212 being located at the bottom of the trench 120 ;

[0129] Exemplarily, the high dielectric constant film layer 212 can be formed at the bottom of the groove 120 by a chemical vapor deposition process, and the thickness of the high dielectric constant film layer 212 is greater than or equal to 2 nanometers and less than or equal to 20 nanometers. For example, the thickness of the high dielectric constant film layer 212 can be set to one of 2 nanometers, 3 nanometers, 4 nanometers, 5 nanometers, 8 nanometers, 10 nanometers, 15 nanometers and 20 nanometers.

[0130] forming a metal film layer 211, wherein the metal film layer 211 is configured as a lanthanum film layer, and the lanthanum film layer covers a top surface of the high dielectric constant film layer 212;

[0131] The lanthanum film layer can be formed on the top surface of the high dielectric constant film layer 212 by an atomic layer deposition process or a physical vapor deposition process. The thickness of the aluminum film layer is greater than or equal to 2 nanometers and less than or equal to 5 nanometers. For example, the thickness of the aluminum film layer can be set to one of 2 nanometers, 3 nanometers, 4 nanometers, and 5 nanometers.

[0132] The lanthanum film layer and the high dielectric constant film layer 212 are heat-treated; the surface of the high dielectric constant film layer 212 facing away from the lanthanum film layer forms a positively charged surface of the dipole layer 210, and the surface of the lanthanum film layer facing away from the high dielectric constant film layer 212 forms a negatively charged surface of the dipole layer 210;

[0133] After a lanthanum film layer is formed on the top surface of the high dielectric constant film layer 212, the lanthanum film layer and the high dielectric constant film layer 212 can be heat-treated so that the surface of the high dielectric constant film layer 212 facing away from the lanthanum film layer forms a positive charge surface of the dipole layer 210, and the surface of the lanthanum film layer facing away from the high dielectric constant film layer 212 forms a negative charge surface of the dipole layer 210, thereby realizing the preparation of the dipole layer 210.

[0134] forming an isolation layer 220 , wherein the isolation layer 220 is located in the trench 120 and covers the dipole layer 210 ;

[0135] Reference Figure 11-13 As shown, specifically, the isolation layer 220 includes a first isolation layer 221, a second isolation layer 222, and a third isolation layer 223 that are stacked, wherein the first isolation layer 221 is disposed in the groove 120 of the substrate 100, and a portion of the first isolation layer 221 covers the dipole layer 210, and a portion of the first isolation layer 221 not covering the dipole layer 210 covers the inner wall of the substrate 100, and a first groove 2211 is formed on the surface of the first isolation layer 221 facing away from the substrate 100; the second isolation layer 222 is disposed in the first groove 2211, and the second isolation layer 222 is attached to the surface of the first isolation layer 221 facing away from the substrate 100, and a second groove 2221 is formed on the surface of the second isolation layer 222 facing away from the first isolation layer 221, and the third isolation layer 223 fills the second groove 2221;

[0136] The material of the first isolation layer 221 is the same as the material of the third isolation layer 223, and is different from the material of the second isolation layer 222. Exemplarily, the material of the first isolation layer 221 and the material of the third isolation layer 223 are both set to oxide, for example, the material of the first isolation layer 221 and the material of the third isolation layer 223 are both set to silicon oxide, and the material of the second isolation layer 222 is set to nitride, for example, the material of the second isolation layer 222 is set to silicon nitride.

[0137] As an achievable implementation manner, forming the isolation layer 220 includes:

[0138] forming a first isolation layer 221 , the first isolation layer 221 covering the inner wall of the trench 120 and the dipole layer 210 , and forming a first groove 2211 on a surface of the first isolation layer 221 facing away from the substrate 100 ;

[0139] Reference Figure 11 As shown, the first isolation layer 221 is prepared and formed in the groove 120 by an atomic layer deposition process or a chemical vapor deposition process, and the thickness of the first isolation layer 221 is uniformly set. Part of the first isolation layer 221 covers the dipole layer 210, and the part of the first isolation layer 221 that does not cover the dipole layer 210 covers the inner wall of the substrate 100. A first groove 2211 is formed on the surface of the first isolation layer 221 facing away from the substrate 100; and at least part of the first isolation layer 221 is located outside the groove 120, and the part of the first isolation layer 221 located outside the groove 120 is located on the top surface of the substrate 100.

[0140] Exemplarily, the first isolation layer 221 can also be prepared by an atomic layer deposition process and a low stage coverage (LSC) process, so that the thickness of the first isolation layer 221 close to the top surface of the substrate 100 is greater than the thickness of the first isolation layer 221 away from the top surface of the substrate 100.

[0141] A second isolation layer 222 is formed. The second isolation layer 222 is disposed in the first groove 2211. The second isolation layer 222 adheres to the surface of the first isolation layer 221 away from the inner wall of the trench 120. The surface of the second isolation layer 222 away from the first isolation layer 221 forms a second groove 2221.

[0142] Reference Figure 12As shown, illustratively, the second isolation layer 222 can be formed in the first groove 2211 by deposition, such as chemical vapor deposition, and the second isolation layer 222 is formed on the surface of the first isolation layer 221 away from the dipole layer 210 and the inner wall of the groove 120, and the second groove 2221 is formed on the surface of the second isolation layer 222 away from the first isolation layer 221. The thickness of the second isolation layer 222 is uniformly set, at least part of the second isolation layer 222 is formed outside the first groove 2211, and part of the second isolation layer 222 located outside the first groove 2211 is formed on the top surface of the first isolation layer 221.

[0143] Alternatively, the thickness of the second isolation layer 222 close to the top surface of the substrate 100 may be greater than the thickness of the second isolation layer 222 away from the top surface of the substrate 100, so that the thickness of the first isolation layer 221 close to the top surface of the substrate 100 is greater.

[0144] It should be noted that the above configuration can reduce the possibility of hot carriers near the notch side of the trench 120 being captured by the second isolation layer 222, thereby reducing the possibility of breakdown between the isolation structure 200 and the active area 110. In addition, the second isolation layer 222 near the top surface of the substrate 100 has a greater thickness, which can effectively ensure the structural integrity of the isolation structure 200, thereby ensuring the isolation effect of the isolation structure 200.

[0145] It is achievable that the thickness of the second isolation layer 222 can gradually increase along the direction from the groove opening to the groove bottom of the groove 120 , thereby improving the structural regularity of the isolation structure 200 .

[0146] A third isolation layer 223 is formed, and the third isolation layer 223 fills the second groove 2221 .

[0147] Reference Figure 13 As shown, illustratively, the third isolation layer 223 can also be formed by deposition to fill the second groove 2221, and the top surface of the third isolation layer 223 is flush with the top surface of the second isolation layer 222. It should be noted that after the third isolation layer 223 is formed, the tops of the first isolation layer 221, the second isolation layer 222, and the third isolation layer 223 can be polished by a CMP process so that the top surfaces of the three are flush with the top surface of the substrate 100, so that the first isolation layer 221, the second isolation layer 222, and the third isolation layer 223 form an isolation layer, thereby completing the formation process of the isolation structure 200.

[0148] In a third aspect, an embodiment of the present disclosure provides a memory, which may include the above-mentioned semiconductor structure. The memory may include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM) or magnetoresistive random access memory (MRAM). The non-memory device may be a logic device (such as a microprocessor, a digital signal processor or a microcontroller) or a device similar thereto.

[0149] The semiconductor structure in the memory in this embodiment is the same as that in the above-mentioned embodiment, and can achieve the same technical effects as those thereof, and thus will not be described in detail here.

[0150] In the description of the embodiments of the present disclosure, it should be understood that, unless otherwise expressly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances. The orientations or positional relationships indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0151] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of the present disclosure and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein, for example, can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that The device comprises a substrate and an isolation structure, wherein the substrate comprises a plurality of active areas arranged in an array, and the isolation structure is located in the substrate and between adjacent active areas; The isolation structure includes a dipole layer and an isolation layer. The dipole layer is located at the bottom of the isolation layer and between the isolation layer and the substrate. The negative charge surface of the dipole layer faces the substrate, and the positive charge surface of the dipole layer faces the isolation layer.

2. The semiconductor structure according to claim 1, wherein: The dipole layer includes a metal film layer and a high dielectric constant film layer that are bonded to each other and subjected to heat treatment; One of the surface of the metal film layer facing away from the high dielectric constant film layer and the surface of the high dielectric constant film layer facing away from the metal film layer forms a positive charge surface of the dipole layer; the other of the surface of the metal film layer facing away from the high dielectric constant film layer and the surface of the high dielectric constant film layer facing away from the metal film layer forms a negative charge surface of the dipole layer.

3. The semiconductor structure according to claim 2, wherein: The metal film layer is configured as an aluminum film layer; The surface of the aluminum film layer facing away from the high dielectric constant film layer forms the positive charge surface of the dipole layer, and the surface of the high dielectric constant film layer facing away from the aluminum film layer forms the negative charge surface of the dipole layer.

4. The semiconductor structure according to claim 2, wherein: The metal film layer is configured as a lanthanum film layer; The surface of the high dielectric constant film layer facing away from the lanthanum film layer forms the positive charge surface of the dipole layer, and the surface of the lanthanum film layer facing away from the high dielectric constant film layer forms the negative charge surface of the dipole layer.

5. The semiconductor structure according to claim 2, wherein: The thickness of the metal film layer is greater than or equal to 2 nanometers and less than or equal to 5 nanometers; and / or the thickness of the high dielectric constant film layer is greater than or equal to 2 nanometers and less than or equal to 20 nanometers.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The substrate has a groove, and the dipole layer and at least a portion of the isolation layer are located in the groove; The dipole layer is located at the bottom of the groove; or, part of the dipole layer is located at the bottom of the groove, and the rest of the dipole layer is located at a position on the side surface of the groove close to the bottom.

7. The semiconductor structure according to claim 6, wherein: The isolation layer includes a first isolation layer, a second isolation layer and a third isolation layer which are stacked; The first isolation layer covers the inner wall of the trench and the dipole layer, and the first isolation layer is away from the surface of the substrate to form a first groove; The second isolation layer is disposed in the first groove, the second isolation layer adheres to the surface of the first isolation layer facing away from the substrate, and the surface of the second isolation layer facing away from the first isolation layer forms a second groove; The third isolation layer fills the second groove.

8. The semiconductor structure according to claim 7, wherein: A material of the first isolation layer is the same as a material of the third isolation layer, and different from a material of the second isolation layer.

9. The semiconductor structure according to claim 7, wherein: The thickness of the first isolation layer close to the top surface of the substrate is greater than the thickness of the first isolation layer away from the top surface of the substrate; or the thickness of the second isolation layer close to the top surface of the substrate is greater than the thickness of the second isolation layer away from the top surface of the substrate.

10. The semiconductor structure according to claim 7, wherein: The material of the first isolation layer and the material of the third isolation layer are both set to oxide, and the material of the second isolation layer is set to nitride.

11. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate comprising a plurality of active regions arranged in an array; forming an isolation structure, wherein the isolation structure is located in the substrate and between adjacent active regions; The isolation structure includes a dipole layer and an isolation layer, wherein the dipole layer is located at the bottom of the isolation layer and between the isolation layer and the substrate; the negatively charged surface of the dipole layer faces the substrate, and the positively charged surface of the dipole layer faces the isolation layer.

12. The method for preparing a semiconductor structure according to claim 11, wherein: Forming the isolation structure includes: forming a trench in the substrate, wherein the trench is located between adjacent active regions; forming a dipole layer, wherein the dipole layer is located at the bottom of the groove, wherein the bottom of the groove includes the groove bottom surface of the groove; or, the bottom of the groove includes the groove bottom surface of the groove and a position close to the groove bottom among the groove side surfaces of the groove; The isolation layer is formed, and the isolation layer is located in the trench and covers the dipole layer.

13. The method for preparing a semiconductor structure according to claim 12, wherein: Forming the dipole layer comprises: forming a metal film layer, wherein the metal film layer is located at the bottom of the groove, and the metal film layer is configured as an aluminum film layer; forming a high dielectric constant film layer, wherein the high dielectric constant film layer covers the top surface of the aluminum film layer; The aluminum film layer and the high dielectric constant film layer are heat-treated; the surface of the aluminum film layer facing away from the high dielectric constant film layer forms a positive charge surface of the dipole layer, and the surface of the high dielectric constant film layer facing away from the aluminum film layer forms a negative charge surface of the dipole layer.

14. The method for preparing a semiconductor structure according to claim 12, wherein: Forming the dipole layer comprises: forming a high dielectric constant film layer, wherein the high dielectric constant film layer is located at the bottom of the trench; forming a metal film layer, wherein the metal film layer is configured as a lanthanum film layer, and the lanthanum film layer covers a top surface of the high dielectric constant film layer; The lanthanum film layer and the high dielectric constant film layer are heat-treated; the surface of the high dielectric constant film layer facing away from the lanthanum film layer forms a positive charge surface of the dipole layer, and the surface of the lanthanum film layer facing away from the high dielectric constant film layer forms a negative charge surface of the dipole layer.

15. The method for preparing a semiconductor structure according to claim 12, wherein: The isolation layer includes a first isolation layer, a second isolation layer, and a third isolation layer stacked together; forming the isolation layer includes: forming a first isolation layer, wherein the first isolation layer covers the inner wall of the trench and the dipole layer, and a surface of the first isolation layer facing away from the substrate forms a first groove; forming a second isolation layer, the second isolation layer being disposed in the first groove, the second isolation layer being in contact with a surface of the first isolation layer facing away from the inner wall of the groove, and a surface of the second isolation layer facing away from the first isolation layer forming a second groove; The third isolation layer is formed, and the third isolation layer fills the second groove.

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