Memory manufacturing method, memory, device and equipment

Abstract

The present application provides a method for manufacturing a memory, a memory, a device, and an apparatus. The method includes: forming a first active structure, a semiconductor structure, and a second active structure stacked in sequence on a substrate, wherein the doping concentration of the first active structure is the same as the doping concentration of the second active structure, and the doping concentration of the semiconductor structure is different from the doping concentration of the first active structure; forming a first memory based on the first active structure; flipping the first memory and removing the substrate to expose the second active structure and the semiconductor structure; depositing a metal material on both sides of the semiconductor structure within a BL region to form a metal structure, wherein the metal structure connects the semiconductor structure to an adjacent semiconductor structure; and forming a second memory based on the second active structure, wherein a first source-drain structure of the first memory and a second source-drain structure of the second memory share the semiconductor structure and the metal structure. The present application can improve the integration of the memory.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a memory, a memory, a device, and an apparatus. Background Art

[0002] Dynamic random access memory (DRAM) usually uses a transistor and a capacitor (1T1C) structure as the chip's storage unit. Through the continuous evolution of the architecture, the area of ​​DRAM storage unit is 4F. 2 (F is the feature size.) However, as Moore's Law continues, the area scaling of traditional DRAM has reached a bottleneck, and there is an urgent need for a method to reduce the area of ​​DRAM memory cells and increase storage density. Summary of the Invention

[0003] The present application provides a method for preparing a memory, a memory, a device and an apparatus, which can reduce the area of ​​a storage unit of the memory and improve the storage density and integration.

[0004] In a first aspect, an embodiment of the present application provides a method for preparing a memory, the method comprising: forming a stacked structure on a substrate, the stacked structure comprising: a first active structure, a semiconductor structure and a second active structure stacked in sequence in a first direction, the first active structure being farther away from the substrate than the second active structure, the first active structure, the semiconductor structure and the second active structure being self-aligned along the first direction, the doping concentration of the first active structure being the same as the doping concentration of the second active structure, and the doping concentration of the semiconductor structure being different from the doping concentration of the first active structure; forming a first memory based on the first active structure; flipping the first memory and removing the substrate to expose the second active structure and the semiconductor structure; depositing metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure, the metal structure connecting the semiconductor structure with an adjacent semiconductor structure; forming a second memory based on the second active structure, wherein the first source-drain structure in the first memory and the second source-drain structure in the second memory share the semiconductor structure and the metal structure.

[0005] In one possible embodiment, metal material is deposited on both sides of the semiconductor structure in the bit line BL region to form a metal structure, including: depositing metal material on both sides of the semiconductor structure, the height of the metal material being the height of the semiconductor structure; and etching the metal material in the WL region to form a metal structure.

[0006] In one possible embodiment, a stacked structure is formed on a substrate, including: stacking a first material layer, a second material layer, and a third material layer in sequence on the substrate; and etching the third material layer, the second material layer, and the first material layer to form a first active structure, a semiconductor structure, and a second active structure.

[0007] In one possible implementation, a first memory is formed based on a first active structure, including: forming a first transistor based on the first active structure; forming a first capacitor structure on the first transistor; and a second memory is formed based on a second active structure, including: forming a second transistor based on the second active structure; and forming a second capacitor structure on the second transistor.

[0008] In one possible embodiment, a first transistor is formed based on the first active structure, including: forming a first gate structure based on the first active structure; removing the first gate structure in the BL region to form a first groove; depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, the upper surface of the first insulating layer is flush with the upper surface of the first mask, and the first mask is located on the first active structure; removing the first mask to form a second groove; and forming a first source-drain structure in the second groove.

[0009] In one possible embodiment, the first gate structure includes a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, wherein the height of the first gate electrode layer is lower than the height of the first gate dielectric layer; the first gate structure is removed in the BL region to form a first groove, comprising: forming a sacrificial layer on the first gate electrode layer located in the BL region, wherein the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer; and anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer located below the sacrificial layer to form the first groove.

[0010] In one possible embodiment, forming a first capacitor structure on the first transistor includes: forming a first dielectric layer on the first source-drain structure; etching a first portion of the first dielectric layer to expose the first source-drain structure; and forming a first capacitor structure on the first source-drain structure.

[0011] In a second aspect, an embodiment of the present application provides a memory, which is manufactured using the preparation method described in the first aspect and any one of its embodiments, and includes: a BL structure, the BL structure is composed of a semiconductor structure and a metal structure; a first memory; a second memory, the second memory is arranged back to back to the first memory, and the first source-drain structure in the second memory and the second source-drain structure in the first memory share the BL structure.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a memory as described in the second aspect above.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and the semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0014] In the present application, a stacked structure including a first active structure, a semiconductor structure and a second active structure is formed on a substrate, and then a first memory (front memory) can be prepared based on the front active structure (first active structure); the front memory is flipped and the substrate is removed to expose the first active structure and the semiconductor structure; then metal material is deposited on both sides of the semiconductor structure in the BL area to form a metal structure, which connects the semiconductor structure with the adjacent semiconductor structure; finally, based on the second active structure, a second memory (back memory) is prepared. The embodiment of the present application forms an active structure by etching the BL area and the WL area at one time, ensuring self-alignment of the front and back BL and WL. Through wafer bonding and flipping, the front and back integrated 4F is realized. 2 The equivalent area of ​​the memory is 2F. 2 , which is equivalent to reducing the area of ​​the memory cell and improving the storage density and integration of the memory.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] Figure 1 A schematic diagram of an implementation flow of a method for preparing a memory in an embodiment of the present application;

[0018] Figure 2 This is a schematic top view of a memory according to an embodiment of the present application;

[0019] Figures 3 to 21 This is a schematic structural diagram of the memory in the first preparation process in an embodiment of the present application;

[0020] Figure 22 This is a schematic diagram of the first structure of the memory in the embodiment of the present application;

[0021] Figure 23 A schematic top view of another memory according to an embodiment of the present application;

[0022] Figures 24 to 33 This is a schematic diagram of the structure of the memory in the second preparation process in an embodiment of the present application;

[0023] Figure 34 This is a schematic diagram of the second structure of the memory in the embodiment of the present application.

[0024] The above pictures:

[0025] 10. Memory; 11. First transistor (front transistor); 111. First active structure; 112. First source-drain structure; 113. First gate structure; 1131. First gate dielectric layer; 1132. First gate electrode layer; 12. Second transistor; 121. Second active structure; 122. Second source-drain structure; 123. Second gate structure; 1231. Second gate dielectric layer; 1232. Second gate electrode layer; 13. Third insulating layer; 14. Carrier wafer; 20. Substrate; 21. First material layer; 2 2. Second material layer; 23. Third material layer; 24. First mask; 25. Semiconductor structure; 26. First shallow trench isolation structure; 27. Isolation layer; 28. Sacrificial layer; 29. ​​First groove; 30. First oxide layer; 31. First insulating layer; 32. Second groove; 33. First dielectric layer; 34. First capacitor structure; 35. BL structure; 36. Active structure; 37. Second shallow trench isolation structure; 38. Second oxide layer; 39. Second insulating layer; 40. Second dielectric layer; 41. Second capacitor structure. DETAILED DESCRIPTION

[0026] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0027] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size. With the continuous development of transistor technology, a flip-chip stacked transistor has emerged. The active area of ​​the upper and lower layers of the same source transistors is formed by etching, and the flip-chip stacked transistors are made on the front and back of the wafer by flipping the wafer, which can overcome the shortcomings of the existing solution.

[0028] In DRAM, ferroelectric random access memory (FeRAM), or other memory devices, a memory cell may include a transistor and a capacitor structure. The transistor is disposed on a substrate, and the capacitor structure is located at the end of the transistor away from the substrate, with the transistor and the capacitor structure electrically connected.

[0029] Taking DRAM as an example, the basic structure of DRAM is 1T1C. Currently, there are three main forms of DRAM. The first type of DRAM has an area of ​​8F. 2 , which is achieved by placing transistors and capacitors horizontally; the area of ​​the second DRAM is 6F 2 By tilting the placement of transistors and capacitors, the arrangement density can be increased, thereby achieving a smaller integration area; the area of ​​the third type of DRAM is 4F 2 By placing transistors and capacitor structures vertically, the vertical volume is fully utilized to achieve smaller DRAM area scaling.

[0030] As integrated circuits continue to shrink in size, there is an urgent need for a method that can reduce the area of ​​memory cells and increase storage density.

[0031] Based on this, an embodiment of the present application provides a method for preparing a memory, which can reduce the area of ​​a storage unit of the memory and improve the storage density and integration.

[0032] In some embodiments, the memory may include a plurality of memory cells, each of which may include a flip-stack transistor and a capacitance structure (capacitor), wherein the capacitance structure is electrically connected to the flip-stack transistor.

[0033] In some embodiments, the flip-stack transistor may include a gate structure, a source structure, and a drain structure. The capacitor structure and the flip-stack transistor may be electrically connected by the source structure of the flip-stack transistor and the capacitor structure, or by the drain structure of the flip-stack transistor and the capacitor structure. The flip-stack transistor controls the writing, modification, or reading of information in the capacitor structure. That is, the flip-stack transistor acts as a selection device (or switching device) to control the writing, modification, or reading of information in the capacitor structure.

[0034] In some embodiments, the capacitor structure may include a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode. For example, the first electrode may be electrically connected to the drain structure of the flip-chip stack transistor, and the second electrode may be grounded.

[0035] In some embodiments, the memory cell may further include multiple word line (WL) structures and multiple bit line (BL) structures, wherein the WL structure and the BL structure are arranged perpendicularly. The WL structure may be connected to the gate structure of the flip-stack transistor to control the on and off of the flip-stack transistor. The BL structure may be connected to the source structure or the drain structure of the flip-stack transistor to write data to the capacitor structure connected to the flip-stack transistor when the flip-stack transistor is turned on.

[0036] In some embodiments, a flip-chip stacked transistor may include at least two transistors. Taking a first transistor and a second transistor as an example, the first transistor and the second transistor are arranged back to back, and the first active structure of the first transistor and the second active structure of the second transistor are formed through the same process. Therefore, it can be understood that the first transistor and the second transistor share an active structure.

[0037] In the embodiment of the present application, the first transistor and the second transistor in the flip-chip stack transistor are transistors of the same type, such as vertical channel transistors (VCT), which may also be referred to as vertical gate-all-around transistors.

[0038] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a memory in an embodiment of the present application, such as Figure 1 As shown, the method for preparing the memory in the embodiment of the present application may include:

[0039] Step S110: forming a stacked structure on a substrate.

[0040] The stacked structure includes: a first active structure, a semiconductor structure and a second active structure stacked in sequence in a first direction, the first active structure is farther away from the substrate than the second active structure, and the first active structure, the semiconductor structure and the second active structure are self-aligned along the first direction.

[0041] In some embodiments, the implementation process of step S110 can be divided into the following two steps: step 1: stacking a first material layer, a second material layer and a third material layer in sequence on the substrate; step 2: etching the third material layer, the second material layer and the first material layer to form a first active structure, a semiconductor structure and a second active structure.

[0042] In step 1, the first material layer and the third material layer have the same doping concentration, and the doping concentration of the second material layer is different from the doping concentration of the first material layer.

[0043] For example, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon carbide substrate.

[0044] It can be understood that the first material layer and the third material layer have the same doping concentration, and the doping concentration of the second material layer is different from the doping concentration of the first material layer. In this way, the first material layer and the third material layer with the same doping can be etched later and used as the active structure shared by the front transistor (first transistor) and the back transistor (second transistor) in the flip-chip stacked transistor, and the second material layer with different doping can be used as the BL structure of the memory.

[0045] In some embodiments, the doping concentration of the second material layer can be higher than that of the first material layer. As a data transmission channel, the doping concentration of the BL structure primarily affects data transmission efficiency and noise performance. A higher doping concentration can improve the BL structure's conductivity, reduce resistance, and thus accelerate data transmission.

[0046] Since the memory cell includes the WL region and the BL region, after the first material layer, the second material layer and the third material layer are sequentially stacked on the substrate, the material layers in the WL region and the BL region can be etched to form an active structure.

[0047] In some embodiments, step 2 can be implemented by forming a first mask on the third material layer, the first mask being used to position the WL region and the BL region; and etching the third material layer, the second material layer, and the first material layer based on the first mask to form the first active structure, the semiconductor structure, and the second active structure. Specifically, after forming the mask by photolithography, etching is performed simultaneously along the BL direction and the WL direction, thereby ensuring self-alignment between the BL region and the WL region.

[0048] As can be understood, a first mask is formed on the third material layer. The first mask is used to locate the WL region and the BL region. Therefore, the first mask covers a portion of the third material layer in both the WL region and the BL region. In this way, the third material layer, the second material layer, and the first material layer are etched based on the first mask to form the first active structure, the semiconductor structure, and the second active structure. The semiconductor structure is disconnected in both the WL region and the BL region.

[0049] For example, the etching process may be at least one of dry etching, wet etching, reactive ion etching, etc.

[0050] In some embodiments, after forming the first active structure, the semiconductor structure, and the second active structure, an oxide material may be deposited on the substrate to form a first shallow trench isolation (STI) structure.

[0051] It is understandable that an oxide material can be deposited on the substrate and thinned to a predetermined height so that the upper surface of the formed first shallow trench isolation structure is higher than the upper surface of the semiconductor structure and the gate structure of the front transistor is exposed, so as to facilitate the subsequent preparation of the gate structure of the front transistor. The oxide material forming the shallow trench isolation structure can be exemplarily any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO). The thinning process can be exemplarily a process such as chemical-mechanical planarization (CMP).

[0052] Step S120 : forming a first memory based on the first active structure.

[0053] In some embodiments, the implementation process of step S120 may include the following two steps: forming a first transistor based on the first active structure; and forming a first capacitor structure on the first transistor.

[0054] In some embodiments, based on the first active structure, the implementation process of forming the first transistor can be: based on the first active structure, forming a first gate structure; removing the first gate structure in the BL area to form a first groove; depositing insulating material on the first gate structure in the WL area and in the first groove to form a first insulating layer, and the upper surface of the first insulating layer is flush with the upper surface of the first mask; removing the first mask to form a second groove; forming a first source-drain structure in the second groove.

[0055] As can be understood, after thinning the first shallow trench isolation structure to a predetermined height, the gate region of the front transistor is exposed, i.e., a first gate recess is formed between the first active structures. Thus, an insulating material can be deposited in the first gate recess to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate electrode layer and the first gate dielectric layer surrounding the first gate electrode layer together constitute the first gate structure. The height of the first gate dielectric layer can be higher than the height of the first gate electrode layer.

[0056] For example, the first gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0057] For example, the first gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, and alloys of these metals.

[0058] Since the WL structure in the WL region is connected to the gate structure of the transistor, the first gate structure in the WL region is necessary, while the first gate structure in the BL region may not exist, so the first gate structure in the BL region may be selectively removed.

[0059] In some embodiments, the process of removing the first gate structure in the BL region to form the first groove can be: forming a sacrificial layer on the first gate electrode layer in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the first gate electrode layer located below the sacrificial layer to form the first groove.

[0060] It is understood that a sacrificial layer can be deposited on the first gate electrode layer in the BL region, attached to the bottom of the first gate electrode layer, the sidewalls of the first gate dielectric layer, and the sidewalls of the first mask. The upper surface of the sacrificial layer is flush with the upper surface of the first gate dielectric layer. Then, the bottom of the sacrificial layer and the first gate electrode layer below the sacrificial layer are anisotropically etched to form the first recess. Since the anisotropic etching is performed from the bottom of the sacrificial layer downward, a portion of the first gate electrode layer still exists below the sidewalls of the sacrificial layer, and thus this portion of the first gate electrode layer is retained.

[0061] The insulating material may be, for example, oxide, nitride, etc. When depositing the sacrificial layer, a very thin film may be deposited on the surface of the substrate by atomic layer deposition (ALD).

[0062] In some embodiments, after the first groove is formed, the sacrificial layer may be removed.

[0063] It can be understood that after forming the first groove, an insulating material can be deposited on the first gate structure in the WL region and in the first groove to form a first insulating layer, and the upper surface of the first insulating layer is flush with the upper surface of the first mask. The first mask can then be removed to form a second groove, and the first source and drain structure of the front transistor can be formed in the second groove. Among them, the first insulating layer is used to isolate from the first source and drain structure of the front transistor. In the case where the transistor formed in the embodiment of the present application is a VCT, the source structure and drain structure of the VCT are approximately symmetrical. Therefore, for the sake of convenience, the first source and drain structure mentioned in the embodiment of the present application is a short name, specifically referring to the first source structure and / or the first drain structure. In addition, the same is true for the second source and drain structure that appears later.

[0064] For example, ion implantation can be performed in the second groove to deposit a metal material, which can then be annealed to form a silicide. The silicide can be used as the first source-drain structure. This is merely an example, and the actual operation can be determined as needed. When the silicide is used as the first source structure, the BL structure can be used as the first drain structure. When the silicide is used as the first drain structure, the BL structure can be used as the first source structure.

[0065] In some embodiments, an insulating material may be deposited on the first gate structure in the WL region to form an isolation layer so that only the BL region can be processed. Thus, after removing the sacrificial layer, the isolation layer above the WL region can be removed to form a first insulating layer on both the WL region and the BL region.

[0066] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the first recess in the BL region to form a first oxide layer. A first insulating layer may then be formed on the first oxide layer in the BL region and the first gate structure in the WL region. The first oxide layer may also be formed, for example, by ALD deposition.

[0067] After the first source-drain structure is formed, a capacitor structure of a front-side memory may be formed on the front-side transistor.

[0068] In some embodiments, the process of forming the first capacitor structure on the first transistor may be: forming a first dielectric layer on the first source-drain structure; etching a first portion of the first dielectric layer to expose the first source-drain structure; and forming the first capacitor structure on the first source-drain structure.

[0069] It is understandable that an insulating dielectric can be deposited on the first source-drain structure to form a first dielectric layer, and then a portion of the first dielectric layer can be etched to expose the first source-drain structure below. A layer of metal material can be first deposited on the first source-drain structure, followed by a dielectric material, and then another layer of metal material. In this way, a first capacitor structure including a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode can be formed, thereby completing the preparation of a front-side memory. The first dielectric layer located between the first capacitor structures can serve as an isolation structure between the first capacitor structures.

[0070] Step S130: flipping the first memory and removing the substrate to expose the second active structure and the semiconductor structure.

[0071] In some embodiments, the implementation process of step S130 may be: flipping the first memory and removing the substrate; thinning the first shallow trench isolation structure to a preset height to expose the second active structure and the semiconductor structure, and the thinned first shallow trench isolation structure is used to isolate the first transistor from the second transistor.

[0072] It can be understood that after the first capacitor structure is formed, the first capacitor structure can be bonded to the carrier wafer, and then the first capacitor structure can be flipped over, and the substrate can be removed and the first shallow trench isolation structure can be thinned to expose the second active structure and the semiconductor structure, so as to facilitate the subsequent formation of the BL structure and the preparation of the back side memory.

[0073] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first capacitor structure to form a third insulating layer, and the third insulating layer may be bonded to the carrier wafer. The first capacitor structure may then be flipped over and the substrate removed.

[0074] After removing the substrate, the upper surface of the second active structure is flush with the upper surface of the first shallow trench isolation structure, so the first shallow trench isolation structure can be thinned to a predetermined height to expose the semiconductor structure. The predetermined height can be set according to actual needs and is not limited in this embodiment of the application.

[0075] Step S140 : depositing metal material on both sides of the semiconductor structure in the BL region to form a metal structure.

[0076] It can be understood that the semiconductor structure in step S110 is not connected in the BL area and the WL area, while the BL structure in the memory is not connected in the WL area, but is connected in the BL area. Therefore, the embodiment of the present application deposits metal material between the semiconductor structures in the BL area to form a metal structure, and connects adjacent semiconductor structures through the metal structure. In this way, a BL structure including a semiconductor structure and a metal structure can be formed, and the semiconductor structure in the WL area is not affected.

[0077] In some embodiments, the implementation process of step S140 may be: depositing metal material on both sides of the semiconductor structure, the height of the metal material being the same as the height of the semiconductor structure; and etching the metal material in the WL region to form a metal structure.

[0078] As will be appreciated, metal material can first be deposited on both sides of the semiconductor structures in the WL region and the BL region, and then the metal material in the WL region can be etched, leaving the metal material in the BL region. Because the height of the metal material is equal to the height of the semiconductor structure, the semiconductor structures in the BL region can be connected via the metal material, while the metal material between the semiconductor structures in the WL region is removed to prevent short circuits, thereby forming a metal structure.

[0079] In some embodiments, metal material can be deposited in both the WL region and the BL region. However, due to layout design and process manufacturing, the metal deposition coverage areas of the BL and WL regions differ. The metal material in the BL region can completely fill both sides of the semiconductor structure and the second active structure, that is, fill the groove between adjacent semiconductor structures and the second active structure, while the metal material in the WL region only covers the surfaces on both sides of the semiconductor structure and the second active structure. The metal material in both regions can then be etched using anisotropic etching, with the etching rate strictly controlled, so that sufficient metal material remains at the semiconductor structure in the BL region to achieve conduction of the BL structure, while the metal material at the semiconductor structure in the WL region is removed to prevent short circuits between the BL and WL regions.

[0080] In some embodiments, the metal material may be deposited by ALD deposition, for example.

[0081] In some embodiments, after the BL structure is formed, an oxide material may be deposited on the BL structure in the BL region and the first shallow trench isolation structure in the WL region to form a second shallow trench isolation structure.

[0082] It is understandable that after forming the second shallow trench isolation structure, the third shallow trench isolation structure may be thinned to a predetermined height to expose the gate region of the back transistor, so as to facilitate subsequent preparation of the gate structure of the back transistor.

[0083] Step S150: forming a second memory based on the second active structure.

[0084] In some embodiments, the implementation process of step S150 may include the following two steps: forming a second transistor based on the second active structure; and forming a second capacitor structure on the second transistor.

[0085] In some embodiments, the implementation process of forming the second transistor based on the second active structure may be: forming a second gate structure based on the second active structure; removing the second gate structure in the BL region to form a third groove; depositing an insulating material on the second gate structure in the WL region and in the second groove to form a second insulating layer, the upper surface of the second insulating layer is flush with the upper surface of the second mask, and the second mask is located on the second active structure; removing the second mask to form a fourth groove; and forming a second source-drain structure in the fourth groove.

[0086] As can be understood, after thinning the second shallow trench isolation structure to a predetermined height, the gate region of the backside transistor is exposed, i.e., a second gate recess is formed between the second active structures. Thus, an insulating material can be deposited in the second gate recess to form a second gate dielectric layer, and a metal material can be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute the second gate structure. The height of the second gate dielectric layer can be higher than the height of the second gate electrode layer.

[0087] In some embodiments, the process of removing the second gate structure in the BL region to form the third groove can be: forming a sacrificial layer on the second gate electrode layer located in the BL region, and the upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer; anisotropically etching the bottom of the sacrificial layer and the second gate electrode layer located below the sacrificial layer to form the third groove.

[0088] It is understood that a sacrificial layer can be deposited on the second gate electrode layer in the BL region, attached to the bottom of the second gate electrode layer, the sidewalls of the second gate dielectric layer, and the sidewalls of the second mask. The upper surface of the sacrificial layer is flush with the upper surface of the second gate dielectric layer. The bottom of the sacrificial layer and the second gate electrode layer below the sacrificial layer are then anisotropically etched to form the third recess. Since the anisotropic etching is performed from the bottom of the sacrificial layer downward, a portion of the second gate electrode layer still exists below the sidewalls of the sacrificial layer, and thus this portion of the second gate electrode layer is retained.

[0089] In some embodiments, after the third groove is formed, the sacrificial layer may be removed.

[0090] In some embodiments, before forming the second insulating layer, a second mask can be formed on the second active structure in the WL region and the BL region, where the width of the second mask is the same as the width of the second active structure. After forming the third recess, an insulating material can be deposited on the second gate structure in the WL region and within the third recess to form a second insulating layer, where the upper surface of the second insulating layer is flush with the upper surface of the second mask. The second mask can then be removed to form a fourth recess, and the second source and drain structure of the back-side transistor can be formed within the fourth recess.

[0091] In some embodiments, an insulating material may be deposited on the second gate structure in the WL region to form an isolation layer, so that only the BL region can be processed. In this manner, after removing the sacrificial layer, the isolation layer above the WL region can be removed to form a second insulating layer over both the WL region and the BL region.

[0092] In some embodiments, after removing the sacrificial layer, an oxide material may be deposited in the third recess in the BL region to form a second oxide layer. A second insulating layer may then be formed on the second oxide layer in the BL region and the second gate structure in the WL region. The second oxide layer may also be formed, for example, by ALD deposition.

[0093] After the second source-drain structure is formed, a capacitor structure of a back-side memory may be formed on the back-side transistor.

[0094] In some embodiments, the second capacitor structure may be formed on the second transistor by: forming a second dielectric layer on the second source-drain structure; etching a first portion of the second dielectric layer to expose the second source-drain structure; and forming a second capacitor structure on the second source-drain structure.

[0095] It is understandable that an insulating dielectric can be deposited on the second source-drain structure to form a second dielectric layer, and then a portion of the second dielectric layer can be etched to expose the second source-drain structure below. A layer of metal material can be first deposited on the second source-drain structure, followed by a dielectric material, and then another layer of metal material. In this way, a second capacitor structure including a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode can be formed, thereby completing the back-side memory. The second dielectric layer located between the second capacitor structures can serve as an isolation structure between the second capacitor structures.

[0096] In addition, in some embodiments, the spacing between the BL structures and the spacing between the WL structures in the embodiments of the present application can be the same or different, as long as the product of the spacing between the two is 4F 2 For example, the spacing between the BL structures and the spacing between the WL structures are both 2F, or the spacing between the BL structures is 4F and the spacing between the WL structures is F. This embodiment of the present application is not limited to this.

[0097] In the present application, a stacked structure including a first active structure, a semiconductor structure and a second active structure is formed on a substrate, and then a first memory (front memory) can be prepared based on the front active structure (first active structure); the front memory is flipped and the substrate is removed to expose the first active structure and the semiconductor structure; then a metal material is deposited on both sides of the semiconductor structure in the BL region to form a metal structure; finally, based on the second active structure, a second memory (back memory) is prepared. The embodiment of the present application forms an active structure by etching the BL region and the WL region at one time, ensuring self-alignment of the front and back BL and WL. Through wafer bonding and flipping, two memory cells of 4F2 size are integrated on the front and back sides, so the equivalent area of ​​the memory is 2F2, which is equivalent to reducing the area of ​​the memory cell of the memory and improving the storage density and integration of the memory. In addition, the embodiment of the present application can also realize the diversification of the memory structure by changing the spacing between the BL structure and the WL structure.

[0098] The following describes the fabrication method of the memory provided by the embodiments of the present application, using the nanowire structure as an example of the active structure in the VCT. First, the first fabrication process is introduced, where the active structure of the transistor in the memory is still a standard nanowire structure, with different spacing between the WL structure and the BL structure. Figure 2 This is a schematic top view of a memory device according to an embodiment of the present application. It should be noted that for ease of understanding, only the nanowire structure, BL structure, and WL structure are shown in this top view. The AA' direction is the cross-sectional direction of the memory device along the BL structure; the BB' direction is the cross-sectional direction of the memory device along the WL structure. Figures 3 to 21This is a schematic diagram of the structure of the memory in the first preparation process in an embodiment of the present application. Figure 22 This is a schematic diagram of the first structure of the memory in the embodiment of the present application. Figures 3 to 22 (a) is a cross-sectional view of the memory along the cross-sectional direction of the BL structure (i.e., the AA' direction). Figures 3 to 22 (b) is a cross-sectional view of the memory along the cross-sectional direction of the WL structure (ie, the BB' direction).

[0099] In one example, the preparation process of the memory 10 may include the following steps:

[0100] Step 1: Form a first material layer 21, a second material layer 22 and a third material layer 23 on the original substrate 20 in sequence, and obtain Figure 3 The structure shown.

[0101] The first material layer and the third material layer are doped in the same manner, and the doping concentration of the second material layer is higher than that of the first material layer.

[0102] For example, a layer of highly doped silicon can be epitaxially grown on a silicon substrate to serve as the BL structure of the memory, and then a thicker layer of low-doped silicon can be epitaxially grown on this basis to prepare for the front-side memory device.

[0103] Step 2: Form a first mask 24 on the third material layer 23. The first mask 24 is used to define the active structures of the WL and BL regions. Then, based on the first mask 24, the third material layer 23, the second material layer 22 and the first material layer 21 are sequentially etched until the substrate 20, so as to form a self-aligned first active structure 111, a semiconductor structure 25 and a second active structure 121. Figure 4 The structure shown.

[0104] It can be understood that etching is performed simultaneously in the WL region and the BL region, so that self-alignment of the BL and the WL can be ensured.

[0105] Step 3: Deposit an oxide material on the substrate 20 to form a first shallow trench isolation structure 26, and perform CMP and etching to expose the front transistor to obtain the following: Figure 5 The structure shown.

[0106] Step 4: selectively deposit an insulating material on the surface of the first active structure 111 to form a first gate dielectric layer 1131, as shown in FIG. Figure 6 The structure shown.

[0107] Step 5: Deposit metal material on the first gate dielectric layer 1131 and perform CMP to a certain height to form a first gate electrode layer 1132. Figure 7 The structure shown.

[0108] The first gate dielectric layer 1131 and the first gate electrode layer 1132 constitute the first gate structure 113 , and the height of the first gate dielectric layer 1131 is higher than the height of the first gate electrode layer 1132 .

[0109] Step 6: Form an isolation layer 27 by photolithography and etching to cover the WL area so that only the BL area can be processed later. Figure 8 The structure shown.

[0110] Step 7: Deposit a sacrificial layer 28 on the first gate electrode layer 1132, attached to the bottom of the first gate electrode layer 1132, the sidewall of the first gate dielectric layer 1131, and the sidewall of the first mask 24, to obtain the following: Figure 9 The structure shown.

[0111] Step 8: Anisotropically etch the bottom of the sacrificial layer 28 and the first gate electrode layer 1132 located below the sacrificial layer 28, then remove the sacrificial layer 28 to form a first groove 29, and obtain the following: Figure 10 The structure shown.

[0112] It can be understood that the anisotropic etching is performed from the bottom of the sacrificial layer downwards, and a portion of the first gate electrode layer still exists below the sidewall of the sacrificial layer.

[0113] For example, when depositing the sacrificial layer, a very thin sacrificial layer may be deposited on the surface of the substrate by ALD deposition.

[0114] Step 9: Deposit oxide material in the first groove 29 to form a first oxide layer 30, as shown in FIG. Figure 11 The structure shown.

[0115] Step 10: Remove the isolation layer 27 above the WL region, and deposit an insulating material (such as SiN) in the two regions to form a first insulating layer 31, as shown in FIG. Figure 12 The structure shown.

[0116] Step 11: Selectively etch the first mask 24 to form a second groove 32, and obtain Figure 13 The structure shown.

[0117] Step 12: forming a first source-drain structure 112 in the second groove 32, and depositing an insulating dielectric on the first source-drain structure 112 to form a first dielectric layer 33, so as to obtain Figure 14 The structure shown.

[0118] For example, ion implantation may be performed first in the second groove 32 to deposit a metal material, which is then annealed to form silicide, and the silicide is used as the first source-drain structure.

[0119] Step 13: Etch a portion of the first dielectric layer 33 to expose the first source-drain structure 112, and form a first capacitor structure 34 on the first source-drain structure 112 to obtain Figure 15 The structure shown.

[0120] The first capacitor structure may include deposition of a metal upper plate, deposition of a dielectric layer, and deposition of a metal lower plate. Figure 15 For simplified representation only.

[0121] Step 14: Deposit insulating material on the first capacitor structure 34 to form a third insulating layer 13, and bond the third insulating layer 13 to the carrier wafer 14, and then flip the wafer to obtain the following: Figure 16 The structure shown.

[0122] Step 15: Remove the substrate 20 to the first shallow trench isolation structure 26 to obtain the following Figure 17 The structure shown.

[0123] Step 16: Thin the first shallow trench isolation structure 26 to the bottom of the semiconductor structure 25 to obtain Figure 18 The structure shown.

[0124] Step 17: Deposit metal materials in the WL region and the BL region simultaneously to obtain the following Figure 19 The structure shown.

[0125] It can be understood that, since the spacing between the active structures along the BL direction is small in the top view of the first preparation process, the deposited metal material is sufficient to fill the grooves between the adjacent second active structures 121 and the semiconductor structure 25, corresponding to Figure 19 (a). The spacing between the active structures along the WL direction is large, so the deposited metal material cannot fill the entire groove and can only cover the surface of the second active structure 121 and the semiconductor structure 25, corresponding to Figure 19 (b) For example, the metal material can be deposited by ALD.

[0126] Step 18: Anisotropically etch the metal material to form a BL structure 35, as shown below: Figure 20 The structure shown.

[0127] It can be understood that by anisotropically etching the metal material and strictly controlling the etching rate, there is enough metal material in the BL area, and the metal in the WL area is removed to prevent short circuit. Figure 20 As shown in (a) and (b), the BL structure connects the semiconductor structure through the metal material in the BL region, but not in the WL region. Figure 20(c) is a top view schematic diagram of the memory structure. The active structure 36 includes a first active structure 111 and a second active structure 121. The length of the active structure 36 along the WL direction and the BL direction is jointly determined by the metal deposition and etching processes. The spacing between the WL structure and the BL structure is different. F and 4F here are only examples.

[0128] Step 19: Deposit an oxide material on the BL structure in the BL region and the first shallow trench isolation structure in the WL region and perform CMP to a certain height to form a second shallow trench isolation structure 37, as shown below. Figure 21 The structure shown.

[0129] Step 20: Prepare the second transistor and the second capacitor structure 41 to obtain Figure 22 The structure shown.

[0130] As can be understood, a second mask can be formed on the second active structure 121 first, and then an insulating material can be selectively deposited on the surface of the second active structure 121 to form a second gate dielectric layer 1231. A metal material can be deposited on the second gate dielectric layer 1231 and subjected to CMP to a certain height to form a second gate electrode layer 1232, thereby forming the second gate structure 123. Subsequently, an isolation layer is formed by photolithography and etching to cover the WL region, facilitating processing of the BL region. A sacrificial layer may then be deposited on the second gate electrode layer 1232 to form a portion attached to the bottom of the second gate electrode layer 1242, the sidewalls of the second gate dielectric layer 1231, and the sidewalls of the second mask. The bottom of the sacrificial layer and the second gate electrode layer 1232 located below the sacrificial layer may be anisotropically etched. The sacrificial layer may then be removed to form a recess, and an oxide material may be deposited in the recess to form a second oxide layer 38. The isolation layer above the WL region may be removed, and an insulating material (e.g., SiN) may be deposited in the two regions to form a second insulating layer 39. The second mask may then be selectively etched to form a recess, and a second source / drain structure 122 may be formed in the recess. An insulating dielectric may be deposited on the second source / drain structure 122 to form a second dielectric layer 40. A portion of the second dielectric layer 40 may be etched to expose the second source / drain structure 122, and a second capacitor structure 41 may be formed on the second source / drain structure 122. Here, the second drain structure of the second transistor is connected to the BL structure 35, and the second source structure of the second transistor is connected to the second capacitor structure 41.

[0131] You can refer to steps 4 to 13 here.

[0132] The second fabrication process is described below. The active structure of the memory transistor is still a nanosheet structure, but the length and width of the nanosheet structure are different. The spacing between the WL structure and the BL structure is the same. Figure 23This is a top view of another memory device in an embodiment of the present application. Note that for ease of understanding, only the nanosheet structure, BL structure, and WL structure are shown in this top view. The AA' direction is the cross-sectional direction of the memory device along the BL structure, and the BB' direction is the cross-sectional direction of the memory device along the WL structure. Figures 24 to 33 This is a schematic diagram of the structure of the memory in the second preparation process in an embodiment of the present application. Figure 34 This is a schematic diagram of the second structure of the memory in the embodiment of the present application. Figures 24 to 34 (a) is a cross-sectional view of the memory along the cross-sectional direction of the BL structure (i.e., the AA' direction). Figures 24 to 34 (b) is a cross-sectional view of the memory along the cross-sectional direction of the WL structure (ie, the BB' direction).

[0133] In one example, the preparation process of the memory 10 may include the following steps:

[0134] Step 1: Form a first material layer 21, a second material layer 22 and a third material layer 23 on the original substrate 20 in sequence, and obtain Figure 24 The structure shown.

[0135] The first material layer and the third material layer are doped in the same manner, and the doping concentration of the second material layer is higher than that of the first material layer.

[0136] For example, a layer of highly doped silicon can be epitaxially grown on a silicon substrate to serve as the BL structure of the memory, and then a thicker layer of low-doped silicon can be epitaxially grown on this basis to prepare for the front-side memory device.

[0137] Step 2: Form a first mask 24 on the third material layer 23. The first mask 24 is used to define the active structures of the WL and BL regions. Then, based on the first mask 24, the third material layer 23, the second material layer 22 and the first material layer 21 are sequentially etched until the substrate 20, so as to form a self-aligned first active structure 111, a semiconductor structure 25 and a second active structure 121. Figure 25 The structure shown.

[0138] It can be understood that etching is performed simultaneously in the WL region and the BL region, so that self-alignment of the BL and the WL can be ensured.

[0139] Step 3: Deposit an oxide material on the substrate 20 to form a first shallow trench isolation structure 26, and perform CMP and etching to expose the front transistor to obtain the following: Figure 26 The structure shown.

[0140] Step 4: forming a first transistor and a first capacitor structure 34 on the first shallow trench isolation structure 26 to obtain Figure 27 The structure shown.

[0141] Here, please refer to the fourth to thirteenth steps in the first preparation process mentioned above, which will not be repeated here.

[0142] Step 5: Deposit insulating material on the first capacitor structure 34 to form a third insulating layer 13, and bond the third insulating layer 13 to the carrier wafer 14, and then flip the wafer to obtain the following: Figure 28 The structure shown.

[0143] Step 6: Remove the substrate 20 to the first shallow trench isolation structure 26 to obtain Figure 29 The structure shown.

[0144] Step 7: Thin the first shallow trench isolation structure 26 to the bottom of the semiconductor structure 25 to obtain Figure 30 The structure shown.

[0145] Step 8: Deposit metal materials in the WL region and the BL region simultaneously to obtain Figure 31 The structure shown.

[0146] It can be understood that, since the spacing between the active structures along the BL direction is smaller in the top view of the second preparation process, the deposited metal material is sufficient to fill the grooves between the adjacent second active structures 121 and the semiconductor structures 25, corresponding to Figure 31 (a). The spacing between the active structures along the WL direction is large, so the deposited metal material cannot fill the entire groove and can only cover the surface of the second active structure 121 and the semiconductor structure 25, corresponding to Figure 31 (b) For example, the metal material can be deposited by ALD.

[0147] Step 9: Anisotropically etch the metal material to form a BL structure 35, as shown below: Figure 32 The structure shown.

[0148] It can be understood that by anisotropically etching the metal material and strictly controlling the etching rate, there is enough metal material in the BL area, and the metal in the WL area is removed to prevent short circuit. Figure 32 As shown in (a) and (b), the BL structure connects the semiconductor structure through the metal material in the BL region, but not in the WL region. Figure 32 (c) is a top view schematic diagram of the memory structure. The active structure 36 includes a first active structure 111 and a second active structure 121. The lengths of the active structure along the WL direction and the BL direction are jointly determined by the metal deposition and etching processes. The spacing between the WL structure and the BL structure is the same.

[0149] Step 10: Deposit an oxide material on the BL structure in the BL region and the first shallow trench isolation structure in the WL region and perform CMP to a certain height to form a second shallow trench isolation structure 37, as shown in FIG. Figure 33 The structure shown.

[0150] Step 11: Prepare the second transistor and the second capacitor structure 41 to obtain Figure 34 The structure shown.

[0151] Here, reference may be made to steps 4 to 13 in the above-mentioned first preparation process.

[0152] This application starts from the specific process flow of self-aligned flip-chip stacked transistors and is similar to 4F 2 The DRAM production process is combined with the BL area and the WL area to form the active structure, ensuring the complete self-alignment of the BL and WL. Through wafer bonding and flipping, the front and back integrated 4F 2 The equivalent area of ​​the memory is 2F. 2 , which is equivalent to reducing the area of ​​the memory cell and improving the storage density and integration of the memory.

[0153] Furthermore, the memory provided in the embodiments of the present application can be inspected using testing and analysis instruments, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), or a scanning transmission electron microscope (STEM). Taking TEM as an example, the embodiments of the present application can use TEM slicing to inspect the structure of the memory, and can observe that the 1T1C structure, which is a basic structure of the memory, exists on both the front and back sides, and that the WL structure and BL structure are all self-aligned.

[0154] An embodiment of the present application provides a semiconductor device, including: a memory as described in the above embodiment.

[0155] An embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is disposed on the circuit board and includes the above memory.

[0156] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine different embodiments or examples described in this application and features of different embodiments or examples without contradiction.

[0157] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for preparing a memory, characterized in that: The method comprises: forming a stacked structure on a substrate, the stacked structure comprising: a first active structure, a semiconductor structure, and a second active structure stacked in sequence in a first direction, the first active structure being farther from the substrate than the second active structure, the first active structure, the semiconductor structure, and the second active structure being self-aligned along the first direction, the doping concentration of the first active structure being the same as the doping concentration of the second active structure, and the doping concentration of the semiconductor structure being different from the doping concentration of the first active structure; Based on the first active structure, forming a first memory; Flipping the first memory and removing the substrate to expose the second active structure and the semiconductor structure; Depositing metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure, wherein the metal structure connects the semiconductor structure with an adjacent semiconductor structure; A second memory is formed based on the second active structure, wherein the first source-drain structure in the first memory and the second source-drain structure in the second memory share the semiconductor structure and the metal structure.

2. The method according to claim 1, characterized in that Depositing metal material on both sides of the semiconductor structure in the bit line BL region to form a metal structure includes: Depositing metal material on both sides of the semiconductor structure, wherein the height of the metal material is equal to the height of the semiconductor structure; The metal material in the WL region is etched to form the metal structure.

3. The method according to claim 1, characterized in that The forming of the stacked structure on the substrate comprises: stacking a first material layer, a second material layer, and a third material layer in sequence on the substrate; The third material layer, the second material layer, and the first material layer are etched to form the first active structure, the semiconductor structure, and the second active structure.

4. The method according to claim 1, wherein The forming of a first memory based on the first active structure includes: Based on the first active structure, forming a first transistor; forming a first capacitor structure on the first transistor; The forming of a second memory based on the second active structure includes: forming a second transistor based on the second active structure; A second capacitor structure is formed on the second transistor.

5. The method according to claim 4, characterized in that The forming of a first transistor based on the first active structure includes: forming a first gate structure based on the first active structure; Removing the first gate structure in the BL region to form a first groove; Depositing an insulating material on the first gate structure in the WL region and in the first groove to form a first insulating layer, wherein an upper surface of the first insulating layer is flush with an upper surface of a first mask, and the first mask is located on the first active structure; removing the first mask to form a second groove; A first source-drain structure is formed in the second groove.

6. The method according to claim 5, characterized in that The first gate structure includes a first gate electrode layer and a first gate dielectric layer surrounding the first gate electrode layer, wherein the height of the first gate electrode layer is lower than the height of the first gate dielectric layer; The removing the first gate structure in the BL region to form a first groove includes: forming a sacrificial layer on the first gate electrode layer in the BL region, wherein an upper surface of the sacrificial layer is flush with an upper surface of the first gate dielectric layer; The bottom of the sacrificial layer and the first gate electrode layer located below the sacrificial layer are anisotropically etched to form the first groove.

7. The method according to claim 5, characterized in that The forming of a first capacitor structure on the first transistor includes: forming a first dielectric layer on the first source-drain structure; Etching a first portion of the first dielectric layer to expose the first source-drain structure; The first capacitor structure is formed on the first source-drain structure.

8. A memory, prepared using the preparation method according to any one of claims 1 to 7, characterized in that: include: A BL structure, wherein the BL structure is composed of a semiconductor structure and a metal structure; a first memory; The second memory is arranged opposite to the first memory, and the first source-drain structure in the second memory and the second source-drain structure in the first memory share the BL structure.

9. A semiconductor device, characterized in that: include: The memory as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and the semiconductor device according to claim 9, wherein the semiconductor device is provided on the circuit board.

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