Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device, and the semiconductor device comprises a plurality of grooves which are arranged at intervals in a third direction of the semiconductor device; the oxide layer is arranged on the inner wall of the groove, the oxide layer comprises a first oxidation part and a second oxidation part, the first oxidation part and the second oxidation part are arranged on the two sides of the gate electrode in the third direction respectively, the size of the first oxidation part in the third direction is T1, the size of the second oxidation part in the third direction is T2, and T1 and T2 meet the relational expression that T1 is larger than T2. Therefore, by increasing the thickness of the oxide layer on one side in the groove, not only can the short-circuit safe working area of the device be improved by reducing the saturation circuit density on the side, but also the capacitance between the corresponding grid electrode and emitter electrode can be reduced, so that the switching speed can be improved, and the switching loss can be reduced; and the compromise characteristic of forward conduction voltage drop and switching loss can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In the application of insulated gate bipolar transistors, low turn-off loss, low on-state voltage drop and high reliability have always been the goals pursued by R&D personnel. In order to reduce the on-state voltage drop and achieve a better compromise between on-state voltage drop and turn-off loss, a carrier storage layer is introduced under the base region, but at the same time, the device withstand voltage is significantly reduced. In order to improve the device withstand voltage, the structure of the insulated gate bipolar transistor is developing towards the characteristics of deep trenches and narrow terraces.

[0003] In the related technology, the synergistic effect of the carrier storage layer and the trench will not only increase the saturation current density of the device and reduce the short-circuit safe operating area while further reducing the on-state voltage drop, but also increase the gate capacitance of the device, reduce the switching speed, and increase the switching loss, thereby worsening the compromise characteristics of the on-state voltage drop and switching loss. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can improve the trade-off characteristics between forward conduction voltage drop and switching loss.

[0005] Another object of the present invention is to provide a method for manufacturing a semiconductor device.

[0006] According to an embodiment of the present invention, a semiconductor device comprises: a substrate, the substrate having a first main surface and a second main surface on the opposite side of the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being arranged on the substrate and located between the first main surface and the second main surface; a well layer of a second conductivity type, the well layer being arranged on a side of the drift layer facing the first main surface, a side surface of the well layer away from the drift layer in a first direction constituting a part of the first main surface, the thickness of the well layer extending from the first main surface along the first direction toward the second main surface; a groove, the groove thickness direction penetrating the well layer from the first main surface to reach the drift layer, the length direction of the groove being in a second direction of the semiconductor device Extending upward, the grooves are multiple, and the multiple grooves are spaced apart in the third direction of the semiconductor device, wherein the first direction, the second direction and the third direction are perpendicular to each other; a gate electrode, the gate electrode is arranged in the groove, and the gate electrode is spaced apart from the inner wall of the groove; an oxide layer, the oxide layer is arranged on the inner wall of the groove, the gate electrode is arranged opposite to the well layer and the drift layer via the oxide layer, the oxide layer includes a first oxide portion and a second oxide portion, the first oxide portion and the second oxide portion are respectively arranged on both sides of the gate electrode in the third direction, the size of the first oxide portion in the third direction is T1, the size of the second oxide portion in the third direction is T2, and T1 and T2 satisfy the relationship: T1>T2.

[0007] Therefore, by increasing the thickness of the oxide layer on one side of the trench, not only can the short-circuit safe operating area of ​​the device be improved by reducing the saturated circuit density on this side, but also the capacitance between the corresponding gate and emitter can be reduced, thereby increasing the switching speed and reducing the switching loss, which is beneficial to improving the compromise characteristics of the forward conduction voltage drop and switching loss.

[0008] In some examples of the present invention, the oxide layer also includes a third oxide portion, which is arranged on the side of the gate electrode facing the second main surface in the first direction, and the third oxide portion is respectively connected to the first oxide portion and the second oxide portion, and the size of the third oxide portion in the first direction is T3, and T3 and T2 satisfy the relationship: T3>T2.

[0009] In some examples of the present invention, T3 and T1 satisfy the relationship: T3<T1.

[0010] In some examples of the present invention, two adjacent grooves among the plurality of grooves are respectively set as a first adjacent groove and a second adjacent groove, and the first oxide portion in the first adjacent groove and the first oxide portion in the second adjacent groove are arranged opposite to each other in a third direction.

[0011] In some examples of the present invention, two adjacent grooves among the plurality of grooves are respectively set as a first adjacent groove and a second adjacent groove, and the second oxide portion in the first adjacent groove and the second oxide portion in the second adjacent groove are arranged opposite to each other in a third direction.

[0012] In some examples of the present invention, two adjacent grooves among the plurality of grooves are respectively set as a first adjacent groove and a second adjacent groove, and the first oxide portion in the first adjacent groove and the second oxide portion in the second adjacent groove are arranged opposite to each other in a third direction.

[0013] In some examples of the present invention, the semiconductor device has an active region and a terminal region, the terminal region is circumferentially arranged outside the active region, and the trench is arranged in the active region.

[0014] In some examples of the present invention, the active area has a fast recovery diode region and an insulated gate bipolar transistor region, the insulated gate bipolar transistor region is circumferentially arranged on the outside of the fast recovery diode region, the groove includes a first groove and a second groove, the first groove is correspondingly arranged in the fast recovery diode region, the second groove is correspondingly arranged in the insulated gate bipolar transistor region, and the gate electrode and the oxide layer are arranged in the second groove.

[0015] A method for manufacturing a semiconductor device according to an embodiment of the present invention is applicable to the method for manufacturing a semiconductor device described above, and comprises the following steps: preparing a substrate, and arranging a drift layer in the substrate, wherein the substrate has a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface are arranged at intervals in a first direction, and the drift layer is located between the first main surface and the second main surface; forming a well layer on a side of the drift layer facing the first main surface; forming grooves in the well layer and the drift layer, and penetrating the well layer from the first main surface in the thickness direction of the groove to reach the drift layer; forming an oxide layer in the groove; etching the oxide layer, the oxide layer comprising a first oxide portion and a second oxide portion, the first oxide portion and the second oxide portion are respectively arranged on both sides of the gate electrode in a third direction, the size of the first oxide portion in the third direction is T1, the size of the second oxide portion in the third direction is T2, and T1 and T2 satisfy the relationship: T1>T2.

[0016] In some examples of the present invention, the step of etching the oxide layer to form a first oxide portion and a second oxide portion, the first oxide portion and the second oxide portion are respectively arranged on both sides of the gate electrode in the third direction, the size of the first oxide portion in the third direction is T1, the size of the second oxide portion in the third direction is T2, and T1 and T2 satisfy the relationship: T1>T2 also includes: etching the oxide layer, the oxide layer includes a third oxide portion, the third oxide portion is arranged on the side of the gate electrode in the first direction facing the second main surface, the third oxide portion is respectively connected to the first oxide portion and the second oxide portion, the size of the third oxide portion in the first direction is T3, and T3 and T2 satisfy the relationship: T3>T2.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0019] Figure 1 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of a semiconductor device according to some embodiments of the present invention;

[0021] Figure 3 are schematic diagrams of semiconductor devices according to other embodiments of the present invention;

[0022] Figure 4 is a schematic diagram of a semiconductor device according to some further embodiments of the present invention;

[0023] Figure 5 is a schematic diagram of a semiconductor device according to some further embodiments of the present invention;

[0024] Figure 6 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0025] Figure 7 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0026] Figure 8 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0027] Fig. 9 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0028] Fig.10 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0029] Fig.11 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] Fig.12 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0031] Fig.13 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0032] Fig.14 is a partial schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0033] Fig.15 is a partial flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0034] Reference numerals:

[0035] 100. Semiconductor devices;

[0036] 1. substrate; 101. first main surface; 102. second main surface;

[0037] 2. Drift layer; 3. Well layer;

[0038] 4. Groove; 401. first adjacent groove; 402. second adjacent groove;

[0039] 5. Gate electrode;

[0040] 6. Oxide layer; 601. First oxide portion; 602. Second oxide portion; 603. Third oxide portion;

[0041] 7. Emitter metal; 8. Dielectric layer; 9. Contact hole; 10. Emitter region; 11. Contact hole region; 12. Carrier storage layer; 13. Field stop layer; 14. Collector layer; 15. Collector metal. DETAILED DESCRIPTION

[0042] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0043] Reference below Figure 1-Figure 5A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 according to the embodiment of the present invention is provided with a method for manufacturing the semiconductor device 100. The semiconductor device 100 is, for example, a reverse-conducting insulated gate bipolar transistor. In the following description, N and P represent the conductivity type of the semiconductor. In the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type for description. Similarly, the first conductivity type can also be set to P type and the second conductivity type can be set to N type.

[0044] Combination Figure 1 and 2 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 1, a drift layer 2 of a first conductive type, a well layer 3 of a second conductive type, a trench 4, a gate electrode 5 and an oxide layer 6, wherein the substrate 1 has a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in a first direction, which can provide a stable and reliable setting position for other structures in the semiconductor device 100.

[0045] In the embodiment of the present invention, the drift layer 2 of the first conductivity type is disposed on the substrate 1 and is located between the first main surface 101 and the second main surface 102 , so as to provide a transmission channel for the current in the semiconductor device 100 .

[0046] Further, the well layer 3 of the second conductivity type is arranged on the side of the drift layer 2 of the first conductivity type facing the first main surface 101, the side surface of the well layer 3 of the second conductivity type away from the drift layer 2 of the first conductivity type in the first direction constitutes a part of the first main surface 101, and the thickness of the well layer 3 of the second conductivity type extends from the first main surface 101 along the first direction toward the second main surface 102. In this way, the basic structure of the semiconductor device 100 can be formed, and the well layer 3 of the second conductivity type is not only used to isolate different types of semiconductor regions, but also used to optimize circuit performance, improve reliability and support the design of complex circuits.

[0047] Further, the depth direction of the groove 4 penetrates the well layer 3 of the second conductivity type from the first main surface 101 and reaches the drift layer 2 of the first conductivity type. The length direction of the groove 4 extends in the second direction of the semiconductor device 100. There are multiple grooves 4, and the multiple grooves 4 are arranged at intervals in the third direction of the semiconductor device 100, so that the electron flow channel in the semiconductor device 100 can be normally opened. It should be noted that the depth direction of the groove 4 in the embodiment of the present invention is the first direction in the figure, wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0048] Furthermore, the gate electrode 5 is disposed in the trench 4 and spaced apart from the inner wall of the trench 4. The gate electrode 5 is disposed opposite to the well layer 3 of the second conductivity type and the drift layer 2 of the first conductivity type via the oxide layer 6. Specifically, the gate electrode 5 has the function of controlling the on and off states of the semiconductor device 100. When the gate voltage is higher than the threshold voltage, a thin layer of carriers is generated between the trench 4 and the surrounding well layer 3 of the second conductivity type, forming a channel. The gate electrode 5 controls the formation and disappearance of the channel by applying a voltage, thereby controlling the on state of the semiconductor device 100.

[0049] Furthermore, the oxide layer 6 acts as an insulating layer to isolate the gate electrode 5 from the semiconductor material, ensuring that the gate voltage can effectively control the formation of the channel without directly exchanging current with the semiconductor material. The oxide layer 6 has good dielectric properties, can store charge and establish an electric field between the gate electrode 5 and the semiconductor material. This electric field determines the formation and disappearance of the channel, thereby controlling the on and off states of the transistor.

[0050] In the prior art, the research on the semiconductor device 100 is approaching the goal of low turn-off loss, low conduction voltage drop and high reliability. In order to obtain a lower conduction voltage drop and a better compromise between conduction voltage drop and turn-off loss, in the prior art, a carrier storage layer 12 of the first conductivity type having the same conductivity type as the drift region and a higher doping concentration than the drift region is arranged under the well layer 3 of the second conductivity type, thereby greatly improving the carrier concentration distribution on the emitter side of the semiconductor device 100 and improving the conductivity modulation effect of the drift region. However, this will significantly reduce the withstand voltage of the device.

[0051] In order to improve the adverse effects brought by the introduction of the first conductive type carrier storage layer 12, the structure of the insulated gate bipolar transistor is developed towards the characteristics of deep trench 4 and narrow terrace. However, the synergistic effect of such a first conductive type carrier storage layer 12 and the trench 4 will not only increase the saturation current density of the device and reduce the short-circuit safe operating area of ​​the device while further reducing the on-state voltage drop, but also increase the gate capacitance of the device, reduce the switching speed, and increase the switching loss, making the compromise characteristics of the on-state voltage drop and switching loss worse.

[0052] In an embodiment of the present invention, the oxide layer 6 includes a first oxide portion 601 and a second oxide portion 602, respectively. The first oxide portion 601 and the second oxide portion 602 are respectively arranged on both sides of the gate electrode 5 in the third direction. The size of the first oxide portion 601 in the third direction is T1, and the size of the second oxide portion 602 in the third direction is T2. T1 and T2 satisfy the relationship: T1>T2.

[0053] Specifically, the size of the oxide layer 6 on one side of the gate electrode 5 in the third direction increases, that is, the thickness of the oxide layer 6 on one side of the gate electrode 5 in the third direction increases.

[0054] In the semiconductor device 100, according to the ideal current-voltage relationship in the linear region of the insulated gate bipolar transistor device, under the same gate-emitter voltage conditions, the first oxide portion 601 has a larger thickness, which can increase the threshold voltage for opening the inversion channel on this side, reduce the channel width, and reduce the gate capacitance, which can ultimately lead to a reduction in the saturation current density on this side, thereby improving the short-circuit safe operating area of ​​the device.

[0055] At the same time, the first oxide portion 601 has a larger thickness and the corresponding gate-emitter capacitance is reduced, which can increase the switching speed of the device, reduce the switching loss of the semiconductor device 100, and further improve the trade-off characteristics of the forward conduction voltage drop and the switching loss.

[0056] Such an arrangement can solve the problems of reduced short-circuit safe operating area and deteriorated compromise characteristics of device on-state voltage drop and switching loss caused by the synergistic effect of the first conductive type carrier storage layer 12 and the trench 4 in the prior art.

[0057] Combination Figure 1 As shown, the oxide layer 6 also includes a third oxide portion 603, which is arranged on the side of the gate electrode 5 facing the second main surface 102 in the first direction, and the third oxide portion 603 is respectively connected to the first oxide portion 601 and the second oxide portion 602, so that the structural continuity of the oxide layer 6 can be ensured, and the reliability of the oxide layer 6 isolating the gate electrode 5 and the semiconductor material can be ensured.

[0058] Furthermore, the size of the third oxide portion 603 in the first direction is T3, and T3 and T2 satisfy the relationship: T3>T2. In this way, the size of the oxide layer 6 on the side of the gate electrode 5 facing the second main surface 102 in the first direction can be increased. In this way, the capacitance between the gate and the collector can be reduced, which can increase the switching speed of the device, reduce the switching loss of the device, and further improve the trade-off characteristics of the forward conduction voltage drop and the switching loss.

[0059] According to an embodiment of the present invention, T3 and T1 satisfy the relationship: T3<T1. Specifically, the size of the third oxidation portion 603 in the first direction is set not to exceed the size of the first oxidation portion 601 in the third direction, which can prevent the size of the third oxidation portion 603 in the first direction from being too large. If the size of the third oxidation portion 603 in the first direction is too large, the threshold voltage of the semiconductor device 100 will increase, and the device will require a larger gate voltage to turn on, which will increase the switching power consumption and reduce the switching speed. Therefore, it is necessary to set the size of the third oxidation portion 603 in the first direction not to exceed the size of the first oxidation portion 601 in the third direction.

[0060] Combination Figure 2 As shown, two adjacent trenches 4 among the plurality of trenches 4 are respectively set to be the first adjacent trench 401 and the second adjacent trench 402, and the first oxide portion 601 in the first adjacent trench 401 and the first oxide portion 601 in the second adjacent trench 402 are arranged relatively in the third direction. Specifically, in this way, the size of the oxide layer 6 on the opposite side of the first adjacent trench 401 and the second adjacent trench 402 in the third direction can be increased, the threshold voltage of the inversion channel on the opposite side of the first adjacent trench 401 and the second adjacent trench 402 can be increased, the channel width can be reduced, the gate capacitance can be reduced, and finally the saturation current density can be reduced, so that the short-circuit safe working area of ​​the device can be improved.

[0061] Furthermore, the gate-emitter capacitance corresponding to the opposite sides of the first adjacent trench 401 and the second adjacent trench 402 can be reduced, so that the switching speed of the device can be increased, the switching loss of the semiconductor device 100 can be reduced, and the compromise characteristics of the forward conduction voltage drop and the switching loss can be further improved. In this way, the semiconductor device 100 of the embodiment of the present invention can solve the problem of reducing the short-circuit safe operating area and worsening the compromise characteristics of the device conduction voltage drop and the switching loss caused by the synergistic effect of the first conductive type carrier storage layer 12 and the trench 4 in the prior art.

[0062] Combination Figure 5 As shown, two adjacent trenches 4 among the plurality of trenches 4 are respectively set to be the first adjacent trench 401 and the second adjacent trench 402, and the second oxide portion 602 in the first adjacent trench 401 and the second oxide portion 602 in the second adjacent trench 402 are arranged opposite to each other in the third direction. Specifically, in this way, the size of the oxide layer 6 in the third direction on the side where the first adjacent trench 401 and the second adjacent trench 402 are away from each other in the third direction can be increased, and the threshold voltage of the inversion channel opening on the side where the first adjacent trench 401 and the second adjacent trench 402 are away from each other in the third direction can be increased, the channel width can be reduced, and the gate capacitance can be reduced, which can eventually lead to a reduction in the saturation current density, thereby achieving an improvement in the short-circuit safe operating area of ​​the device.

[0063] Furthermore, the gate-emitter capacitance corresponding to the side of the first adjacent trench 401 and the second adjacent trench 402 that are away from each other in the third direction can be reduced, so that the switching speed of the device can be improved, the switching loss of the semiconductor device 100 can be reduced, and the compromise characteristics of the forward conduction voltage drop and the switching loss can be further improved. In this way, the semiconductor device 100 of the embodiment of the present invention can solve the problem of reducing the short-circuit safe operating area and worsening the compromise characteristics of the device conduction voltage drop and the switching loss caused by the synergistic effect of the first conductive type carrier storage layer 12 and the trench 4 in the prior art.

[0064] Combination Figure 3 and Figure 4 As shown, two adjacent trenches 4 among the plurality of trenches 4 are respectively set to be a first adjacent trench 401 and a second adjacent trench 402, and the first oxide portion 601 in the first adjacent trench 401 and the second oxide portion 602 in the second adjacent trench 402 are arranged opposite to each other in the third direction. Specifically, in this way, the size of the oxide layer 6 on the same side of the first adjacent trench 401 and the second adjacent trench 402 in the third direction can be increased, the threshold voltage of the inversion channel on the same side of the first adjacent trench 401 and the second adjacent trench 402 in the third direction can be increased, the channel width can be reduced, the gate capacitance can be reduced, and finally the saturation current density can be reduced, so that the short-circuit safe working area of ​​the device can be improved.

[0065] Furthermore, the gate-emitter capacitance corresponding to the same side of the first adjacent trench 401 and the second adjacent trench 402 in the third direction can be reduced, so that the switching speed of the device can be improved, the switching loss of the semiconductor device 100 can be reduced, and the compromise characteristics of the forward conduction voltage drop and the switching loss can be further improved. In this way, the semiconductor device 100 of the embodiment of the present invention can solve the problem of reducing the short-circuit safe operating area and worsening the compromise characteristics of the device conduction voltage drop and the switching loss caused by the synergistic effect of the first conductive type carrier storage layer 12 and the trench 4 in the prior art.

[0066] According to an embodiment of the present invention, the semiconductor device 100 has an active region and a terminal region, the terminal region is circumferentially arranged outside the active region, and the trench 4 is arranged in the active region. Specifically, the active region can realize electronic signal amplification or partial switching function. The active region is manufactured by a specific doping process (such as P-type or N-type doping) to realize the specific functions of a transistor or other active device.

[0067] Furthermore, the termination region is a special area designed to protect the active region from high voltage. In high voltage applications, if there is no proper protection, the active region may fail due to breakdown due to excessive electric fields. The design of the termination region can extend the depletion layer, thereby reducing the electric field strength near the active region and improving the overall voltage withstand capability of the device.

[0068] In an insulated gate bipolar transistor, a groove 4 is provided in the active region, which can be used to form a channel, thereby reducing the area of ​​the device and improving the integration and power density. In a MOSFET (metal-oxide-semiconductor field effect transistor), applying a voltage to the gate can control the channel formation, and thus control the current between the source and the drain.

[0069] According to some embodiments of the present invention, the semiconductor device 100 may be an RC-IGBT (reverse-conducting insulated gate bipolar transistor), wherein the RC-IGBT has an insulated gate bipolar transistor region and a fast recovery diode region. The insulated gate bipolar transistor region and the fast recovery diode region are reversely connected in parallel in the semiconductor device 100, so that the insulated gate bipolar transistor has a reverse conduction function. The insulated gate bipolar transistor region is circumferentially arranged outside the fast recovery diode region, and is spaced from the fast recovery diode region. The transition region is located between the fast recovery diode region and the insulated gate bipolar transistor region, which can prevent the currents flowing through the insulated gate bipolar transistor region and the fast recovery diode region from affecting each other, thereby ensuring the normal operation of the reverse-conducting insulated gate bipolar transistor.

[0070] According to an embodiment of the present invention, at the initial forward conduction stage of the RC-IGBT, after the gate voltage opens the channel on the active gate side of the semiconductor device 100, the carriers flow along a first direction from the emitter region 10 of the first conductivity type through the drift layer 2 of the first conductivity type, and reach the collector layer 14 of the second conductivity type close to the side of the drift layer 2 of the first conductivity type, and finally flow out from the short-circuit region of the first conductivity type in the fast recovery diode region. In this process, only electrons, one type of carrier, participate in conduction, and at this time, the reverse conducting insulated gate bipolar transistor is in a unipolar conduction state.

[0071] In the unipolar conduction state, carriers will generate a voltage drop on the path they flow through. When this voltage drop is greater than the built-in potential of the PN junction formed by the collector layer 14 of the second conductivity type and the drift layer 2 of the first conductivity type, the PN junction formed by the short-circuit region of the first conductivity type and the drift layer 2 of the first conductivity type is turned on, and holes are injected from the short-circuit region of the first conductivity type into the drift layer 2 of the first conductivity type, and then flow out from the well layer 3 after passing through the drift layer 2 of the first conductivity type. In this process, both electrons and holes are involved in conduction. At this time, the reverse conducting insulated gate bipolar transistor is in a bipolar conduction state.

[0072] In an embodiment of the present invention, a second trench 4 is provided in the insulated gate bipolar transistor region, and the second trench 4 is an active trench in which an active gate is provided. The active trench can extend the active gate of the insulated gate bipolar transistor region from the first main surface 101 to the drift layer 2 of the first conductive type. The active gate is electrically connected to the gate pad of the semiconductor device 100, so that the active gate and the gate pad can have the same potential.

[0073] In the active trench, the active gate is spaced apart from the inner wall of the active trench, an oxide layer 6 is arranged between the active gate and the active trench, the oxide layer 6 includes but is not limited to an active gate insulating film, the active gate is arranged opposite to the emitter region 10 of the first conductivity type, the well layer 3 of the second conductivity type and the drift layer 2 of the first conductivity type through the active gate insulating film, so as to ensure the normal operation of the function of the insulated gate bipolar transistor region.

[0074] In the semiconductor device 100 of the embodiment of the present invention, a first trench 4 is provided in both the fast recovery diode region and the transition region. The first trench 4 is a virtual trench. A virtual gate is provided inside the virtual trench. The virtual gate and the inner wall of the virtual trench are spaced apart. A virtual gate insulating film is provided between the virtual gate and the virtual trench.

[0075] Furthermore, in the structure of the RC-IGBT, the insulated gate bipolar transistor region and the fast recovery diode region are both integrated in the active region of the semiconductor device 100, and the oxide layer 6 between the trench 4 and the gate electrode 5 of the active region may include a first oxide portion 601, a second oxide portion 602 and a third oxide portion 603, wherein the size of the first oxide portion 601 in the third direction is larger than the size of the second oxide portion 602 in the third direction, and the size of the third oxide portion 603 in the first direction is larger than the size of the second oxide portion 602 in the third direction. This arrangement can solve the problem of a reduction in the short-circuit safe operating area of ​​the RC-IGBT and a deterioration in the compromise characteristics of the device's on-state voltage drop and switching loss.

[0076] According to some other embodiments of the present invention, the semiconductor device 100 may be a FS-IGBT (field-stop insulated gate bipolar transistor) having a field stop layer 13. The field stop layer 13 of the semiconductor device 100 of the embodiment of the present invention is located on the side of the first conductive type drift layer 2 facing the second main surface 102. When the device is turned off, the field stop layer 13 can quickly clear the charge stored in the first conductive type drift layer 2, thereby speeding up the switching speed and reducing losses.

[0077] Furthermore, in the structure of the FS-IGBT, the oxide layer 6 between the trench 4 of the active region and the gate electrode 5 may include a first oxide portion 601, a second oxide portion 602 and a third oxide portion 603, wherein the size of the first oxide portion 601 in the third direction is larger than the size of the second oxide portion 602 in the third direction, and the size of the third oxide portion 603 in the first direction is larger than the size of the second oxide portion 602 in the third direction. This arrangement can solve the problem of a reduction in the short-circuit safe operating area of ​​the FS-IGBT and a deterioration in the compromise characteristics of the device's on-state voltage drop and switching loss.

[0078] It should be noted that the semiconductor device 100 according to the embodiment of the present invention includes but is not limited to RC-IGBT and FS-IGBT.

[0079] Combine the following Figure 5-Figure 15 The manufacturing method of the semiconductor device 100 according to the embodiment of the present invention is described. It should be noted that in the embodiment of the present invention, the manufacturing method of the semiconductor device 100 is only for the preparation of the IGBT active area, and the semiconductor device 100 also includes an emitter metal 7, a dielectric layer 8, an emitter region 10 of the first conductivity type, a contact hole region 11 of the second conductivity type, a carrier storage layer 12 of the first conductivity type, a field stop layer 13 of the first conductivity type, a collector layer 14 of the second conductivity type, and a collector metal 15.

[0080] Combination Fig.15 As shown, the method for manufacturing the semiconductor device 100 includes the following steps:

[0081] S1, preparing a substrate 1, and arranging a drift layer 2 of a first conductivity type in the substrate 1, wherein the substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, the first main surface 101 and the second main surface 102 are arranged at intervals in a first direction, and the drift layer 2 of the first conductivity type is located between the first main surface 101 and the second main surface 102;

[0082] S2, forming a well layer 3 of a second conductivity type on a side of the drift layer 2 of the first conductivity type facing the first main surface 101;

[0083] S3, forming a trench 4 in the well layer 3 of the second conductivity type and the drift layer 2 of the first conductivity type, wherein the trench 4 penetrates the well layer 3 of the second conductivity type from the first main surface 101 in the thickness direction and reaches the drift layer 2 of the first conductivity type;

[0084] S4, forming an oxide layer 6 in the trench 4;

[0085] S5. Etch the oxide layer 6, where the oxide layer 6 includes a first oxide portion 601 and a second oxide portion 602. The first oxide portion 601 and the second oxide portion 602 are respectively arranged on both sides of the gate electrode 5 in the third direction. The size of the first oxide portion 601 in the third direction is T1, and the size of the second oxide portion 602 in the third direction is T2. T1 and T2 satisfy the relationship: T1>T2.

[0086] Specifically, a substrate 1 with a drift layer 2 of a first conductivity type as a semiconductor device 100 is provided, wherein the substrate 1 has a first main surface 101 and a second main surface 102 opposite to the first main surface 101, and the first main surface 101 and the second main surface 102 are spaced apart in a first direction. The semiconductor device 100 is manufactured based on the substrate 1.

[0087] Furthermore, ions of the first conductivity type are doped in the drift layer 2 of the first conductivity type near the second main surface 102 to form a field stop layer 13 of the first conductivity type, and ions of the second conductivity type are doped on one side of the field stop layer 13 of the first conductivity type near the second main surface 102 to form a collector layer 14 of the second conductivity type. The collector layer 14 of the second conductivity type constitutes the second main surface 102 of the substrate 1.

[0088] Furthermore, ions of the second conductivity type are doped on the side of the first conductivity type drift layer 2 facing the first main surface 101 to prepare a well layer 3 of the second conductivity type, and ions of the first conductivity type are doped on the side of the first conductivity type drift layer 2 close to the well layer 3 of the second conductivity type to prepare a carrier storage layer 12 of the first conductivity type, and a groove 4 is etched from the first main surface 101 along the first direction toward the second main surface 102 by a photolithography and etching process, and the thickness direction of the groove 4 penetrates the well layer 3 of the second conductivity type from the first main surface 101 to reach the drift layer 2 of the first conductivity type.

[0089] Furthermore, an oxide layer 6 is first deposited in the groove 4 to fill the groove 4, and then the oxide layer 6 is etched by a photolithography and etching process to form a first oxide portion 601 and a second oxide portion 602 respectively located on both sides of the third direction of the groove 4, wherein the size of the first oxide portion 601 in the third direction is larger than the size of the second oxide portion 602 in the third direction. In this way, the thickness of the oxide layer 6 on one side of the third direction of the gate electrode 5 can be increased, the threshold voltage for opening the inversion channel on this side can be increased, the channel width can be reduced, the gate capacitance can be reduced, and ultimately the saturation current density can be reduced, thereby improving the short-circuit safe operating area of ​​the device.

[0090] Furthermore, increasing the thickness of the oxide layer 6 on one side of the third direction of the gate electrode 5 can reduce the corresponding gate-emitter capacitance, which can increase the switching speed of the device, reduce the switching loss of the semiconductor device 100, and further improve the trade-off characteristics of the forward conduction voltage drop and switching loss.

[0091] Furthermore, by etching the oxide layer 6 through a photolithography etching process, a third oxide portion 603 can be formed. The third oxide portion 603 is arranged on the side of the gate electrode 5 facing the second main surface 102 in the first direction, and is respectively connected to the first oxide portion 601 and the second oxide portion 602. In this way, the structural continuity of the oxide layer 6 can be ensured, and the reliability of the oxide layer 6 isolating the gate electrode 5 and the semiconductor material can be ensured.

[0092] Furthermore, the size of the third oxide portion 603 in the first direction is larger than the size of the second oxide portion 602 in the third direction, so that the size of the oxide layer 6 on the side of the gate electrode 5 in the first direction toward the second main surface 102 can be increased. Such a setting can reduce the capacitance between the gate and the collector, thereby increasing the switching speed of the device, reducing the switching loss of the device, and further improving the compromise characteristics of the forward conduction voltage drop and switching loss.

[0093] Furthermore, polysilicon is deposited in the trench 4 to form a gate electrode 5 .

[0094] Further, using mask lithography, ions of the first conductivity type are implanted into the second conductivity type well layer 3 to form an emitter region 10 of the first conductivity type, which is located on at least one side of the third direction of the trench 4 and constitutes at least part of the first main surface 101 .

[0095] Furthermore, a dielectric layer 8 is deposited on the first main surface 101 of the substrate 1 , and the dielectric layer 8 is etched to form contact holes 9 at positions on the dielectric layer 8 corresponding to the gate and the emitter region 10 of the first conductivity type.

[0096] Further, ions of the second conductivity type are injected into the second conductivity type well layer 3 to form a contact hole region 11 of the second conductivity type, and then a tungsten plug and titanium or titanium nitride metal are filled in sequence. The contact hole region 11 of the second conductivity type constitutes at least a part of the first main surface 101 and is spaced apart from the groove 4 in the third direction.

[0097] Further, a top metal is sputtered on the first main surface 101 corresponding to the active area of ​​the substrate 1, and the top metal is etched by a photolithography process to form a gate pad and an emitter metal 7 layer, wherein the gate pad is electrically connected to the active gate, and the emitter metal 7 layer is electrically connected to the emitter region 10 of the first conductivity type, and then a passivation layer is deposited, the passivation layer is photoetched, and then a metal is sputtered on the side of the second main surface 102 away from the collector layer 14 of the second conductivity type to form a collector metal 15 layer. At this point, the semiconductor device 100 of the embodiment of the present invention is completed.

[0098] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0099] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0100] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction; a drift layer of a first conductivity type, the drift layer being disposed on the substrate and located between the first main surface and the second main surface; a well layer of a second conductivity type, the well layer being arranged on a side of the drift layer facing the first main surface, a surface of the well layer on a side away from the drift layer in a first direction constituting a part of the first main surface, and a thickness of the well layer extending from the first main surface along a first direction toward the second main surface; A groove, wherein the groove penetrates the well layer from the first main surface in the thickness direction to reach the drift layer, the length direction of the groove extends in the second direction of the semiconductor device, the groove is multiple, and the multiple grooves are arranged at intervals in the third direction of the semiconductor device, wherein the first direction, the second direction and the third direction are perpendicular to each other; A gate electrode, wherein the gate electrode is disposed in the groove, and the gate electrode is spaced apart from an inner wall of the groove; An oxide layer is provided on the inner wall of the groove, the gate electrode is arranged opposite to the well layer and the drift layer via the oxide layer, the oxide layer includes a first oxide portion and a second oxide portion, the first oxide portion and the second oxide portion are respectively provided on both sides of the gate electrode in a third direction, a size of the first oxide portion in the third direction is T1, a size of the second oxide portion in the third direction is T2, and T1 and T2 satisfy the relationship: T1>T2.

2. The semiconductor device according to claim 1, wherein: The oxide layer also includes a third oxide portion, which is arranged on the side of the gate electrode facing the second main surface in the first direction, and the third oxide portion is connected to the first oxide portion and the second oxide portion respectively. The size of the third oxide portion in the first direction is T3, and T3 and T2 satisfy the relationship: T3>T2.

3. The semiconductor device according to claim 2, wherein: T3 and T1 satisfy the relationship: T3<T1.

4. The semiconductor device according to claim 1, wherein: Two adjacent trenches among the plurality of trenches are respectively set to be a first adjacent trench and a second adjacent trench, and the first oxide portion in the first adjacent trench and the first oxide portion in the second adjacent trench are arranged opposite to each other in a third direction.

5. The semiconductor device according to claim 1, wherein: Two adjacent trenches among the plurality of trenches are respectively set to be a first adjacent trench and a second adjacent trench, and the second oxide portion in the first adjacent trench and the second oxide portion in the second adjacent trench are arranged opposite to each other in a third direction.

6. The semiconductor device according to claim 1, wherein: Two adjacent trenches among the plurality of trenches are respectively set to be a first adjacent trench and a second adjacent trench, and the first oxide portion in the first adjacent trench and the second oxide portion in the second adjacent trench are arranged opposite to each other in a third direction.

7. The semiconductor device according to claim 1, wherein: The semiconductor device has an active region and a terminal region. The terminal region is circumferentially arranged outside the active region, and the trench is arranged in the active region.

8. The semiconductor device according to claim 7, wherein: The active area comprises a fast recovery diode region and an insulated gate bipolar transistor region, wherein the insulated gate bipolar transistor region is circumferentially arranged outside the fast recovery diode region, and the groove comprises a first groove and a second groove, wherein the first groove is correspondingly arranged in the fast recovery diode region, and the second groove is correspondingly arranged in the insulated gate bipolar transistor region, and the gate electrode and the oxide layer are arranged in the second groove.

9. A method for manufacturing a semiconductor device, applicable to the semiconductor device according to any one of claims 1 to 8, characterized in that: The following steps are involved: Prepare a substrate, and arrange a drift layer in the substrate, wherein the substrate has a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface are arranged at intervals in a first direction, and the drift layer is located between the first main surface and the second main surface; forming a well layer on a side of the drift layer facing the first main surface; forming a trench in the well layer and the drift layer, wherein the trench penetrates the well layer from the first main surface in a thickness direction to reach the drift layer; forming an oxide layer in the trench; The oxide layer is etched, and the oxide layer includes a first oxide portion and a second oxide portion, the first oxide portion and the second oxide portion are respectively arranged on both sides of the gate electrode in the third direction, the size of the first oxide portion in the third direction is T1, the size of the second oxide portion in the third direction is T2, and T1 and T2 satisfy the relationship: T1>T2.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The step of etching the oxide layer, wherein the oxide layer includes a first oxide portion and a second oxide portion, wherein the first oxide portion and the second oxide portion are respectively arranged on both sides of the gate electrode in the third direction, wherein a size of the first oxide portion in the third direction is T1, and a size of the second oxide portion in the third direction is T2, and T1 and T2 satisfy the relationship: T1>T2, further includes: The oxide layer is etched, wherein the oxide layer includes a third oxide portion, wherein the third oxide portion is arranged on a side of the gate electrode facing the second main surface in the first direction, wherein the third oxide portion is connected to the first oxide portion and the second oxide portion respectively, and a size of the third oxide portion in the first direction is T3, and T3 and T2 satisfy the relationship: T3>T2.

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