P-GaN HEMT device with split coupling gate structure

Abstract

The invention relates to a p-GaN HEMT device with a split coupling gate structure, and belongs to the technical field of semiconductor devices. The device comprises a substrate; a buffer layer formed on the surface of the substrate; the channel layer is formed on the surface of the buffer layer; the barrier layer is formed on the surface of the channel layer; the source electrode and the drain electrode are formed on the surface of the barrier layer; the first p-GaN layer is formed on the surface of the barrier layer and is positioned between the source electrode and the drain electrode; the second p-GaN layer is formed on the surface of the barrier layer and is positioned between the first p-GaN layer and the drain electrode; the first grid electrode is formed on the surface of the first p-GaN layer; the second grid electrode is formed on the surface of the second p-GaN layer; a passivation layer formed on the barrier layer and located among the source electrode, the drain electrode, the first p-GaN layer and the second p-GaN layer; and gate electrodes formed on the surfaces of the first gate and the second gate. According to the invention, the charge accumulation effect can be reduced, and the drift of threshold voltage is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and relates to a p-GaN HEMT device with a split coupled gate structure. Background Art

[0002] The third-generation semiconductor material GaN has the advantages of wide bandgap, high electron saturation velocity, and good thermal conductivity, which makes AlGaN / GaN high electron mobility transistor (HEMT) have high electric field strength, high mobility and good thermal stability. Therefore, HEMT has great advantages in high-frequency and high-power application scenarios. The piezoelectric polarization effect at the interface of AlGaN and GaN and the spontaneous polarization effect of AlGaN and GaN form a high concentration of two-dimensional electron gas (2DEG) at the interface of AlGaN and GaN. Due to the natural existence of two-dimensional electron gas, the HEMT device is in the on state without gate voltage, that is, a depletion-type device. In order to match the working mode of the existing silicon-based driver circuit and reduce the energy loss in the power system, the enhancement mode (E-mode) technology is crucial in the market promotion process. At present, the mainstream enhancement mode device is mainly p-GaN HEMT, and the gate adopts Schottky contact. The Schottky gate structure is relatively complex. The p-GaN / AlGaN / GaN structure forms a pn heterojunction, and the p-GaN / gate forms a Schottky junction. Therefore, the p-GaN layer in the Schottky-type p-GaN gate HEMT is an electrically floating layer sandwiched between the pn heterojunction and the Schottky junction. When the device is subjected to drain high voltage bias stress, the charge accumulated in the p-GaN layer cannot be released, forming a charge storage effect, causing the threshold voltage to drift, which seriously affects the stability of the device.

[0003] Therefore, it is urgent to propose a p-GaN HEMT device that can alleviate the charge storage effect to improve the reliability and stability of the device in actual use. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a p-GaN HEMT device with a split coupled gate structure to reduce the drift of the threshold voltage.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A p-GaN HEMT device with a split coupled gate structure, the device comprising:

[0007] substrate;

[0008] a buffer layer formed on the surface of the substrate;

[0009] a channel layer formed on a surface of the buffer layer;

[0010] a barrier layer formed on a surface of the channel layer;

[0011] A source electrode and a drain electrode formed on the surface of the barrier layer;

[0012] A first p-GaN layer formed on the surface of the barrier layer and located between the source electrode and the drain electrode;

[0013] a second p-GaN layer formed on the surface of the barrier layer and located between the first p-GaN layer and the drain electrode;

[0014] A first gate formed on a surface of the first p-GaN layer;

[0015] A second gate formed on a surface of the second p-GaN layer;

[0016] A passivation layer formed on the barrier layer and located between the source electrode, the drain electrode, the first p-GaN layer and the second p-GaN layer. Specifically, a passivation layer is formed between the source electrode and the first p-GaN layer, between the first p-GaN layer and the second p-GaN layer, and between the second p-GaN layer and the drain electrode; and

[0017] A gate electrode is formed on the surface of the first gate and the second gate.

[0018] Furthermore, the second p-GaN layer is partially embedded in the barrier layer. By embedding the second p-GaN layer in the barrier layer, when the device is subjected to drain high voltage bias stress, the second p-GaN layer can block the high voltage on the drain side and isolate the potential.

[0019] In addition, the second p-GaN layer partially embedded in the barrier layer forms an ohmic gate with the second gate and the gate electrode, and the charges accumulated on the drain side of the device are released through the ohmic gate, thereby reducing the drift of the device threshold voltage.

[0020] Furthermore, the degree of reduction of the device threshold voltage drift can be adjusted by adjusting the depth of the second p-GaN layer embedded in the barrier layer.

[0021] Furthermore, the first p-GaN layer, the first gate and the gate electrode form a Schottky gate.

[0022] Furthermore, the second p-GaN layer is embedded in the barrier layer to a depth of 2 nm to 10 nm.

[0023] Furthermore, the first p-GaN layer and the second p-GaN layer have the same width, and the width ranges from 0.3 μm to 0.5 μm.

[0024] Furthermore, the distance between the first p-GaN layer and the second p-GaN layer is 0.4 μm to 0.7 μm.

[0025] The beneficial effect of the present invention is that the present invention forms a groove gate by etching the barrier layer locally and growing a p-GaN layer, and at the same time grows a p-GaN layer on the normal barrier layer on the left to form two independent P-GaN layers, that is, a split coupled gate structure. The p-GaN layer close to the source forms a Schottky contact with the gate metal, and the grooved p-GaN layer close to the drain forms an ohmic contact with the gate metal, and nitride is used to fill the middle to isolate the two p-GaN layers. When the device is subjected to high-voltage bias stress at the drain, the grooved p-GaN layer can block the high voltage on the drain side and isolate the potential. Relying on the ohmic contact formed by the grooved p-GaN layer and the gate metal, the accumulated charge can be released through the ohmic gate, thereby reducing the charge accumulation effect, thereby reducing the drift of the threshold voltage.

[0026] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 Schematic diagram of the structure of a traditional p-GaN HEMT device;

[0029] Figure 2 A schematic diagram of the structure of a p-GaN HEMT device with a split coupled gate structure proposed in the present invention;

[0030] Figure 3 (a) shows the change of threshold voltage of a conventional p-GaN HEMT device under drain high voltage bias stress;

[0031] Figure 3 (b) is the change of threshold voltage of the device of the present invention under drain high voltage bias stress;

[0032] Figure 4 Graph showing the relationship between threshold voltage drift at different groove depths T and different drain bias stresses.

[0033] Figure numerals: 1-substrate, 2-buffer layer, 3-channel layer, 4-barrier layer, 5-source metal electrode, 6-p-GaN layer, 7-grooved p-GaN layer, 8-Schottky gate, 9-ohmic gate, 10-passivation layer, 11-drain metal electrode. DETAILED DESCRIPTION

[0034] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0035] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0036] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0037] See also Figure 2 to Figure 4 The present invention provides a p-GaN HEMT device with a split coupled gate structure, and Figure 1 Different from the conventional p-GaN HEMT device shown in the figure, the present invention adopts a split p-GaN layer groove gate design to separate two independent p-GaN layers.

[0038] like Figure 2As shown, the device proposed in one embodiment of the present invention includes, from bottom to top, a substrate layer 1, a buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, a source metal electrode 5, a p-GaN layer 6, a recessed p-GaN layer 7, a Schottky gate 8, an ohmic gate 9, a passivation layer 10, and a drain metal electrode 11.

[0039] The grooved p-GaN layer 7 is located between the p-GaN layer 6 and the metal drain 11. Two independent p-GaN layers separate two gates, namely, a gate 8 close to the source and a gate 9 close to the drain, wherein the gate 8 close to the source forms a Schottky contact with the p-GaN layer 6, and the gate 9 close to the drain forms an ohmic contact with the grooved p-GaN layer 7; the passivation layer 10 is located between the metal source 5 and the p-GaN layer 6, between the p-GaN layer 6 and the grooved p-GaN layer 7, and between the grooved p-GaN layer 7 and the metal drain 11.

[0040] The principle of the device of the present invention is to form a groove gate by etching the right side of the barrier layer 4 and then growing a p-GaN layer; and growing a p-GaN layer on the left normal barrier layer to form two independent P-GaN layers, that is, a split coupled gate structure. The p-GaN layer close to the source forms a Schottky contact with the gate metal, and the grooved p-GaN layer close to the drain forms an ohmic contact with the gate metal, and nitride is used to fill the middle to isolate the two p-GaN layers. When the device is subjected to high-voltage bias stress at the drain, the grooved p-GaN layer can block the high voltage on the drain side and isolate the potential. Relying on the ohmic contact formed by the grooved p-GaN layer and the gate metal, the accumulated charge can be released through the ohmic gate, thereby reducing the charge accumulation effect, thereby reducing the drift of the threshold voltage.

[0041] In this embodiment, the groove depth of the grooved p-GaN layer 7 in the AlGaN barrier layer 4 is 6 nm.

[0042] In this embodiment, the width of the p-GaN layer 6 is consistent with that of the grooved p-GaN layer 7, which is 0.42 μm.

[0043] In this embodiment, the distance between the p-GaN layer 6 and the grooved p-GaN layer 7 is 0.56 μm.

[0044] In another embodiment of the present invention, the comparison of the threshold voltage changes of the conventional p-GaN HEMT device and the device of the present invention under different drain high voltage bias stresses is simulated. Figure 3 As shown in (a), under different drain high voltage bias stresses, the threshold voltage drift of the conventional p-GaN HEMT device is relatively large, while the threshold voltage drift of the device of the present invention is significantly reduced (e.g. Figure 3 (b) shows that the device of the present invention can effectively suppress the threshold voltage drift.

[0045] In another embodiment of the present invention, the threshold voltage drift under different drain high voltage bias stress with different groove depths T is simulated. Figure 4 As shown, it can be seen that as the groove depth increases, the drift of the threshold voltage gradually decreases.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A p-GaN HEMT device with a split coupled gate structure, characterized in that: The device includes: substrate; a buffer layer formed on the surface of the substrate; a channel layer formed on a surface of the buffer layer; a barrier layer formed on a surface of the channel layer; A source electrode and a drain electrode formed on the surface of the barrier layer; A first p-GaN layer formed on the surface of the barrier layer and located between the source electrode and the drain electrode; a second p-GaN layer formed on the surface of the barrier layer and located between the first p-GaN layer and the drain electrode; A first gate formed on a surface of the first p-GaN layer; A second gate formed on a surface of the second p-GaN layer; a passivation layer formed on the barrier layer and located between the source electrode, the drain electrode, the first p-GaN layer and the second p-GaN layer; and A gate electrode is formed on the surface of the first gate and the second gate.

2. The HEMT device according to claim 1, characterized in that: The second p-GaN layer is partially embedded in the barrier layer.

3. The HEMT device according to claim 2, characterized in that: The second p-GaN layer partially embedded in the barrier layer forms an ohmic gate with the second gate and the gate electrode, and the charges accumulated on the drain side of the device are released through the ohmic gate, thereby reducing the drift of the device threshold voltage.

4. The HEMT device according to claim 2 or 3, characterized in that: The degree of reduction of the device threshold voltage drift can be adjusted by adjusting the depth of the second p-GaN layer embedded in the barrier layer.

5. The HEMT device according to claim 2 or 3, characterized in that: The second p-GaN layer is embedded in the barrier layer to a depth of 2 nm to 10 nm.

6. The HEMT device according to claim 1, characterized in that: The first p-GaN layer and the second p-GaN layer have the same width.

7. The HEMT device according to claim 1, characterized in that: The distance between the first p-GaN layer and the second p-GaN layer is 0.4 μm to 0.7 μm.

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