Novel RC-IGBT structure with hole circulation path and good trade-off relationship

Abstract

The invention provides a novel RC-IGBT structure with a hole circulation path and a good compromise relationship, which comprises a device main body, collector metal is arranged at the bottom of the device main body, a p + collector region, an FS layer, an n-drift region, a groove with a grid electrode at the top, an n + emitter region, a p + contact region and a p base region are sequentially arranged upwards, a second CS storage layer is arranged at the bottom, and the emitter composite structure on the two sides comprises a deep p-type region, a deeper p-type region, a hole channel and a CS storage layer. Through the above structure, the deep p-type region and the deeper p-type region optimize the electric field distribution, improve the doping concentration of the CS layer, enhance the hole accumulation effect, reduce the conduction voltage drop, accelerate the carrier export during the turn-off of a hole channel, and shorten the turn-off time, and at the same time, under the short-circuit working condition, the structures cooperatively export holes, weaken the conductivity modulation effect, improve the short-circuit endurance capability, and improve the performance of the device. And finally, good balance of voltage resistance, conduction voltage drop and switching speed is realized, and the comprehensive performance of the device is remarkably improved.

Description

A novel RC-IGBT structure with hole flow path and good trade-off relationship Technical Field

[0001] This invention relates to the field of power electronic device manufacturing and application technology, specifically to a novel RC-IGBT structure with a hole flow path and a good trade-off relationship. Background Technology

[0002] In the field of power electronics, reverse-conducting insulated-gate bipolar transistors (IGBTs) integrate the functions of IGBTs and freewheeling diodes, offering advantages in high integration and efficiency. They are widely used in new energy power generation, electric vehicle drives, and other applications. However, traditional RC-IGBT structures have significant performance bottlenecks. First, it is difficult to balance hole accumulation and conductivity modulation effects during conduction, resulting in a high on-state voltage drop. Second, the slow carrier extraction speed during turn-off leads to high switching losses and frequency limitations. Third, there is a lack of effective current limiting mechanisms in the face of short-circuit faults, making the device prone to overheating failure. Furthermore, the uneven electric field distribution in traditional structures limits the increase in doping concentration of the CS storage layer, making it difficult to simultaneously optimize conduction and withstand voltage performance. Therefore, it is necessary to develop a novel RC-IGBT structure that optimizes the hole transport path and regulates the electric field distribution through innovative design, achieving a good trade-off between on-state voltage drop, switching speed, short-circuit capability, and withstand voltage performance, thus meeting the demands of modern power electronic systems for efficient and reliable devices. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] To address the shortcomings of existing technologies, this invention provides a novel RC-IGBT structure with a hole flow path and a good trade-off relationship, solving the problems of high conduction loss, slow switching speed, and weak short-circuit withstand capability.

[0005] (II) Technical Solution

[0006] To achieve the above objectives, the present invention provides the following technical solution: a novel RC-IGBT structure with a hole flow path and a good trade-off relationship, comprising: a device body, a collector metal disposed at the bottom of the device body, a p+ collector region disposed at the upper end of the collector metal, an FS layer disposed at the upper end of the p+ collector region, an n- drift region disposed at the upper end of the FS layer, a gate trench disposed at the top center of the n- drift region, an n+ emitter region disposed near the top of the gate trench, a p+ contact region disposed outside the n+ emitter region, a second insulating layer disposed at the top of the gate trench, a first emitter electrode disposed outside the second insulating layer, a p-base region disposed in the middle of the outer side of the gate trench, a second CS storage layer disposed near the bottom of the outer side of the gate trench, and emitter composite structures disposed on both sides inside the device body.

[0007] Preferably, the emitter composite structure is a deep p-type structure, and the deep p-type structure includes:

[0008] The first p-type region is located on both sides inside the device body;

[0009] The first insulating layer is located outside the first p-type region;

[0010] The second emitter electrode is located outside the first insulating layer;

[0011] The third insulating layer is located outside the second emitter electrode;

[0012] The first CS storage layer is located on both sides of the first p-type region near the bottom;

[0013] A channel mechanism is provided at the end of the first p-type region away from the side wall of the device body.

[0014] Preferably, the channel mechanism is a single-sided cavitation channel mechanism, which includes:

[0015] The first emitter trench has its right side in contact with the p-base region and its top in contact with the first insulating layer.

[0016] The second hole channel is located between the first emitter trench and the first CS memory layer.

[0017] Preferably, the channel mechanism is a double-sided cavitation channel mechanism, which includes:

[0018] The third emitter trench is located inside the first p-type region, and its top is in contact with the first insulating layer.

[0019] The first hole channel is located between the third emitter trench and the first CS memory layer;

[0020] The fourth hole channel is located between the third emitter trench and the p-base region.

[0021] Preferably, the emitter composite structure is a deeper p-type structure, and the deeper p-type structure includes:

[0022] The second p-type region is located on both sides inside the device body;

[0023] The second emitter trench is located inside the second p-type region;

[0024] The third hole channel is located between the second emitter trench and the p-base region;

[0025] An insulating mechanism is provided at the top of the second p-type region.

[0026] Preferably, the insulation mechanism is a partially insulated mechanism, which includes:

[0027] The fifth insulating layer has its bottom in contact with the second emitter trench;

[0028] The third emitter electrode is located outside the fifth insulating layer, and its bottom is in contact with the second p-type region.

[0029] The sixth insulating layer is located outside the third emitter electrode and its bottom contacts the second p-type region.

[0030] Preferably, the insulation mechanism is a fully insulating mechanism, which includes a fourth insulating layer, the top of the second p-type region is in contact with the fourth insulating layer, and the top of the second emitter trench is in contact with the fourth insulating layer.

[0031] Preferably, there are two n+ emitter regions symmetrically distributed on both sides of the gate trench, and there are two p+ contact regions corresponding one-to-one with the n+ emitter regions. The upper ends of the n+ emitter regions and p+ contact regions are in contact with the first emitter electrode.

[0032] (III) Beneficial Effects

[0033] This invention provides a novel RC-IGBT structure with a hole flow path and a good trade-off. It has the following beneficial effects:

[0034] This novel RC-IGBT structure, featuring a hole flow path and a favorable trade-off, enhances both turn-on and turn-off performance. The synergistic effect of the CS storage layer and the hole channel allows the device to fully utilize the hole accumulation effect during turn-on, reducing on-resistance and conduction losses. During turn-off, holes can be rapidly discharged through the hole channel on the first emitter trench side, significantly shortening the turn-off time and significantly improving switching efficiency. By adjusting the hole channel width, the on-voltage drop and turn-off time can be flexibly balanced to meet the needs of different application scenarios and enhance short-circuit withstand capability. Under short-circuit conditions, the high electric field drives holes to be rapidly discharged through the hole channel, effectively weakening the hole accumulation effect, limiting current growth, and forming an adaptive adjustment mechanism. This not only reduces the risk of device damage due to overcurrent but also improves short-circuit withstand capability, enhances system reliability, reduces electric field strength, and increases withstand voltage. The deep p-type structure surrounds the bottom of the first emitter trench and is connected to the emitter, placing it at zero potential, optimizing the electric field distribution at the bottom of the trench, and reducing the electric field strength. Attached Figure Description

[0035] Figure 1 is a schematic diagram of the cavitation channel on one side of the deep first p-type region of the present invention;

[0036] Figure 2 is a schematic diagram of the cavity channels on both sides of the deep first p-type region of the present invention;

[0037] Figure 3 shows the p-base region formed by p-type ion implantation on the front side of the first p-type region wafer according to the present invention.

[0038] Figure 4 is a schematic diagram of the first p-type region formed on the wafer of the present invention by photolithography and etching to form a mask for selective implantation of p-type ions and annealing.

[0039] Figure 5 shows the process of ion implantation of the middle CS layer in the deep first p-type region of the present invention using a mask, and then ion implantation of the CS layers on both sides using a mask.

[0040] Figure 6 shows the CS layer ion implantation on both sides of the deep first p-type region of the present invention using a mask;

[0041] Figure 7 is a schematic diagram of selective implantation of n-type ions into the first p-type region of the present invention and annealing to form an n+ emission region.

[0042] Figure 8 is a schematic diagram of selective implantation of p-type ions into the first p-type region of the present invention followed by annealing to form a P+ contact region.

[0043] Figure 9 is a schematic diagram of the structure in which the deeper first p-type region is not connected to the emitter in this invention;

[0044] Figure 10 is a schematic diagram of the connection structure between the deeper first p-type region and the emitter in this invention;

[0045] Figure 11 shows the p-base region and the second CS storage layer formed by p-type and n-type ion implantation annealing on the front side of the deeper first p-type region wafer according to the present invention.

[0046] Figure 12 shows the formation of a second p-type region on the wafer of the first p-type region of the present invention by selective implantation of p-type ions after a mask is formed by photolithography and etching processes;

[0047] Figure 13 shows the formation of n+ emission regions on the wafer of the deeper first p-type region of the present invention after the mask is formed by photolithography and etching processes, n-type ions are selectively implanted and annealed.

[0048] Figure 14 shows the P+ contact region formed on the wafer of the deeper first p-type region of the present invention by selective implantation of p-type ions and annealing after photolithography and etching processes to form a mask.

[0049] Figure 15 shows the selective etching trenches on the wafer after a mask is formed by photolithography and etching processes on the first p-type region of the present invention.

[0050] The components are as follows: 1. Device body; 2. First p-type region; 3. Collector metal; 4. p+ collector region; 5. FS layer; 6. n- drift region; 7. First emitter electrode; 8. First insulating layer; 9. Second insulating layer; 10. First hole channel; 11. n+ emitter region; 12. p+ contact region; 13. Gate trench; 14. First emitter trench; 15. First CS storage layer; 16. p-base region; 17. Second CS storage layer; 18. Third insulating layer; 19. Second emitter electrode; 20. Fourth insulating layer; 21. Second hole channel; 22. Second p-type region; 23. Second emitter trench; 24. Third hole channel; 25. Fourth hole channel; 26. Third emitter trench; 27. Sixth insulating layer; 28. Fifth insulating layer; 29. ​​Third emitter electrode. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Example 1

[0053] As shown in Figure 1, this embodiment of the invention provides a novel RC-IGBT structure with a hole flow path and a good trade-off relationship, including a device body 1, a collector metal 3 at the bottom of the device body 1, a p+ collector region 4 at the upper end of the collector metal 3, an FS layer 5 at the upper end of the p+ collector region 4, an n-drift region 6 at the upper end of the FS layer 5, a gate trench 13 at the top center of the n-drift region 6, an n+ emitter region 11 near the top of the gate trench 13, a p+ contact region 12 near the outside of the n+ emitter region 11, a second insulating layer 9 at the top of the gate trench 13, a first emitter electrode 7 on the outside of the second insulating layer 9, a p-base region 16 in the middle of the outer side of the gate trench 13, a second CS storage layer 17 near the bottom of the outer side of the gate trench 13, and emitter composite structures on both sides inside the device body 1.

[0054] There are two n+ emitter regions 11, which are symmetrically distributed on both sides of the gate trench 13. There are two p+ contact regions 12, which correspond one-to-one with the n+ emitter regions 11. The upper ends of the n+ emitter regions 11 and p+ contact regions 12 are in contact with the first emitter electrode 7.

[0055] The emitter composite structure is a deep p-type structure, which includes:

[0056] The first p-type region 2 is located on both sides inside the device body 1.

[0057] The first insulating layer 8 is located outside the first p-type region 2.

[0058] The second emitter electrode 19 is located outside the first insulating layer 8.

[0059] The third insulating layer 18 is located outside the second emitter electrode 19.

[0060] The first CS storage layer 15 is located on both sides of the first p-type region 2 near the bottom.

[0061] A channel mechanism is provided at the end of the first p-type region 2 that is away from the side wall of the device body 1.

[0062] The channel mechanism is a unilateral cavitary channel mechanism, which includes:

[0063] The first emitter trench 14 has its right side in contact with the p-base region 16 and its top in contact with the first insulating layer 8.

[0064] The second hole channel 21 is located between the first emitter trench 14 and the first CS storage layer 15.

[0065] Example 2

[0066] As shown in Figure 2, this embodiment of the invention provides a novel RC-IGBT structure with a hole flow path and a good trade-off relationship, including a device body 1, a collector metal 3 at the bottom of the device body 1, a p+ collector region 4 at the upper end of the collector metal 3, an FS layer 5 at the upper end of the p+ collector region 4, an n-drift region 6 at the upper end of the FS layer 5, a gate trench 13 at the top center of the n-drift region 6, an n+ emitter region 11 near the top of the gate trench 13, a p+ contact region 12 near the outside of the n+ emitter region 11, a second insulating layer 9 at the top of the gate trench 13, a first emitter electrode 7 on the outside of the second insulating layer 9, a p-base region 16 in the middle of the outer side of the gate trench 13, a second CS storage layer 17 near the bottom of the outer side of the gate trench 13, and emitter composite structures on both sides inside the device body 1.

[0067] There are two n+ emitter regions 11, which are symmetrically distributed on both sides of the gate trench 13. There are two p+ contact regions 12, which correspond one-to-one with the n+ emitter regions 11. The upper ends of the n+ emitter regions 11 and p+ contact regions 12 are in contact with the first emitter electrode 7.

[0068] The emitter composite structure is a deep p-type structure, which includes:

[0069] The first p-type region 2 is located on both sides inside the device body 1.

[0070] The first insulating layer 8 is located outside the first p-type region 2.

[0071] The second emitter electrode 19 is located outside the first insulating layer 8.

[0072] The third insulating layer 18 is located outside the second emitter electrode 19.

[0073] The first CS storage layer 15 is located on both sides of the first p-type region 2 near the bottom.

[0074] A channel mechanism is provided at the end of the first p-type region 2 that is away from the side wall of the device body 1.

[0075] The channel mechanism is a double-sided cavitation channel mechanism, which includes:

[0076] The third emitter trench 26 is located inside the first p-type region 2, and its top is in contact with the first insulating layer 8.

[0077] The first hole channel 10 is located between the third emitter trench 26 and the first CS storage layer 15.

[0078] The fourth hole channel 25 is located between the third emitter trench 26 and the p-base region 16.

[0079] Example 3

[0080] As shown in Figure 10, this embodiment of the invention provides a novel RC-IGBT structure with a hole flow path and a good trade-off relationship, including a device body 1, a collector metal 3 at the bottom of the device body 1, a p+ collector region 4 at the upper end of the collector metal 3, an FS layer 5 at the upper end of the p+ collector region 4, an n-drift region 6 at the upper end of the FS layer 5, a gate trench 13 at the top center of the n-drift region 6, an n+ emitter region 11 near the top of the gate trench 13, a p+ contact region 12 near the outside of the n+ emitter region 11, a second insulating layer 9 at the top of the gate trench 13, a first emitter electrode 7 on the outside of the second insulating layer 9, a p-base region 16 in the middle of the outer side of the gate trench 13, a second CS storage layer 17 near the bottom of the outer side of the gate trench 13, and emitter composite structures on both sides inside the device body 1.

[0081] There are two n+ emitter regions 11, which are symmetrically distributed on both sides of the gate trench 13. There are two p+ contact regions 12, which correspond one-to-one with the n+ emitter regions 11. The upper ends of the n+ emitter regions 11 and p+ contact regions 12 are in contact with the first emitter electrode 7.

[0082] The emitter composite structure is a deeper p-type structure, which includes:

[0083] The second p-type region 22 is located on both sides inside the device body 1.

[0084] The second emitter trench 23 is located inside the second p-type region 22.

[0085] The third hole channel 24 is located between the second emitter trench 23 and the p-base region 16.

[0086] An insulating mechanism is provided at the top of the second p-type zone 22.

[0087] The insulation mechanism is a partially insulated mechanism, which includes:

[0088] The bottom of the fifth insulating layer 28 is in contact with the second emitter trench 23.

[0089] The third emitter electrode 29 is located outside the fifth insulating layer 28, and its bottom is in contact with the second p-type region 22.

[0090] The sixth insulating layer 27 is located outside the third emitter electrode 29 and its bottom is in contact with the second p-type region 22.

[0091] Example 4

[0092] As shown in Figure 9, this embodiment of the invention provides a novel RC-IGBT structure with a hole flow path and a good trade-off relationship, including a device body 1, a collector metal 3 at the bottom of the device body 1, a p+ collector region 4 at the upper end of the collector metal 3, an FS layer 5 at the upper end of the p+ collector region 4, an n-drift region 6 at the upper end of the FS layer 5, a gate trench 13 at the top center of the n-drift region 6, an n+ emitter region 11 near the top of the gate trench 13, a p+ contact region 12 near the outside of the n+ emitter region 11, a second insulating layer 9 at the top of the gate trench 13, a first emitter electrode 7 on the outside of the second insulating layer 9, a p-base region 16 in the middle of the outer side of the gate trench 13, a second CS storage layer 17 near the bottom of the outer side of the gate trench 13, and emitter composite structures on both sides inside the device body 1.

[0093] There are two n+ emitter regions 11, which are symmetrically distributed on both sides of the gate trench 13. There are two p+ contact regions 12, which correspond one-to-one with the n+ emitter regions 11. The upper ends of the n+ emitter regions 11 and p+ contact regions 12 are in contact with the first emitter electrode 7.

[0094] The emitter composite structure is a deeper p-type structure, which includes:

[0095] The second p-type region 22 is located on both sides inside the device body 1.

[0096] The second emitter trench 23 is located inside the second p-type region 22 and on both sides of the gate trench.

[0097] The third hole channel 24 is located between the second emitter trench 23 and the p-base region 16.

[0098] An insulating mechanism is provided at the top of the second p-type zone 22.

[0099] The insulation mechanism is a fully insulating mechanism, which includes a fourth insulating layer 20, the top of the second p-type region 22 is in contact with the fourth insulating layer 20, and the top of the second emitter trench 23 is in contact with the fourth insulating layer 20.

[0100] Example 5

[0101] As shown in Figure 3-8, the manufacturing process of the deep p-type structure is described in the following embodiment: First, p-type ion implantation is performed on the front side of the wafer to form a p-base region 16. Then, a mask is formed on the wafer through photolithography and etching processes to selectively implant p-type ions, followed by annealing to form the first p-type region 2. Finally, the mask is removed. Then, similarly, a mask is formed on the wafer through photolithography and etching processes to selectively implant n-type ions and form the first CS storage layer 15 and the second CS storage layer 17. Finally, the mask is removed. Then, a mask is formed on the wafer through photolithography and etching processes to selectively implant n-type and p-type ions respectively, followed by annealing. An n+ emitter region 11 and a P+ contact region 12 are formed. The mask is then removed, and a mask is formed on the wafer through photolithography and etching processes to selectively etch trenches on the wafer. After etching, an insulating oxide layer is grown in the trench and filled with polysilicon to form the first emitter trench 14 and the gate trench 13. An insulating layer is then grown and metal is deposited on the front side of the wafer, and a pattern is formed through photolithography and etching processes. Finally, the back side of the wafer is ground to the target thickness, and n-type and p-type ion implantation and annealing are performed on the back side to form the FS layer 5 and the p+ collector region 4. Finally, the collector metal 3 is fabricated on the back side.

[0102] Example 6

[0103] As shown in Figures 11-15, the embodiment illustrates the manufacturing process of a deeper p-type structure: First, p-type and n-type ion implantation and annealing are performed on the front side of the wafer to form the p-base region 16 and the second CS storage layer 17. Then, after forming a mask on the wafer through photolithography and etching processes, p-type ions are selectively implanted to form the second p-type region 22. Finally, the mask is removed. Then, after forming a mask on the wafer through photolithography and etching processes, n-type and p-type ions are selectively implanted and annealed to form the n+ emitter region 11 and the P+ contact region 12. Finally, the mask is removed. After removing the mask, a mask is formed on the wafer through photolithography and etching processes. Then, trenches are selectively etched on the wafer. After etching, an insulating oxide layer is grown in the trench and filled with polysilicon to form the second emitter trench 23 and the gate trench 13. Then, an insulating layer is grown and metal is deposited on the front side of the wafer and a pattern is formed through photolithography and etching processes. Finally, the back side of the wafer is ground to the target thickness and n-type and p-type ion implantation and annealing are performed on the back side to form the FS layer 5 and the p+ collector region 4. Finally, the collector metal 3 is fabricated on the back side.

[0104] Working principle: The performance optimization of the new RC-IGBT stems from the coordinated design of the device body 1 and its internal functional structure. From bottom to top, the device consists of a collector metal 3, a p+ collector region 4, an FS layer 5, and an n- drift region 6 forming the current channel; the top forms a MOSFET-like control structure through a gate trench 13, an n+ emitter region 11, a p+ contact region 12, and a p-base region 16; the core innovation is the composite structure of emitters on both sides, which includes a deep p-type region, a second p-type region 22 with an even deeper p-type region, a hole channel, and a CS storage layer, a first CS storage layer 15, and a second CS storage layer 17.

[0105] During forward conduction, a forward voltage is applied to the gate trench 13 to form a MOS channel. Electrons from the n+ emitter region 11 are injected into the n- drift region 6, while holes are injected into the drift region from the p+ collector region 4. The deep p-type region is connected to the emitter to form a zero potential, reducing the electric field strength at the bottom of the trench. The deeper p-type region wraps around the bottom of the emitter trench, further optimizing the electric field distribution. Both of these factors allow the CS layer to increase its doping concentration without significantly affecting the device's breakdown voltage. The highly doped CS layer enhances the hole accumulation effect, reduces carrier recombination losses, and lowers the on-state voltage drop.

[0106] During turn-off, the gate voltage is removed, the MOS channel disappears, and electron extraction accelerates. The hole channel on the emitter trench side rapidly discharges the holes accumulated in the CS storage layer, shortening the turn-off time. In contrast, traditional IGBTs have a longer turn-off time because the CS storage layer hinders the flow of holes to the emitter. Adjusting the hole channel width, i.e., the distance between the CS storage layer and the trench, can balance the turn-off time and the on-state voltage drop: the larger the distance, the faster the holes are discharged and the shorter the turn-off time, but the hole accumulation effect is weakened, and the on-state voltage drop increases.

[0107] Under short-circuit conditions, high voltage and high current create a strong electric field, driving more holes to be discharged through the channel, reducing hole accumulation in the drift region, decreasing the conductivity modulation effect, preventing current surges, and improving short-circuit withstand capability. The deep p-type region and even deeper p-type region, together with FS layer 5, limit the electric field expansion, offsetting the negative impact of the highly doped CS layer on the electric field, ensuring that the device maintains a low on-state voltage drop under high blocking voltage.

[0108] Through innovative design and collaborative optimization, this structure breaks through the constraints of traditional devices in terms of withstand voltage, on-state voltage drop, and switching speed, achieving a significant improvement in overall performance.

[0109] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A novel RC-IGBT structure with a hole flow path and a good trade-off relationship, characterized in that, include: The device body (1) has a collector metal (3) at the bottom and a p+ collector region (4) at the top. An FS layer (5) is provided at the top of the p+ collector region (4). An n-drift region (6) is provided at the top of the FS layer (5). A gate trench (13) is provided at the top center of the n-drift region (6). An n+ emitter region (11) is provided near the top of the gate trench (13). A p+ contact region (12) is provided on the outside of the n+ emitter region (11). A second insulating layer (9) is provided at the top of the gate trench (13). A first emitter electrode (7) is provided on the outside of the second insulating layer (9). A p-base region (16) is provided in the middle of the outside of the gate trench (13). A second CS storage layer (17) is provided near the bottom of the outside of the gate trench (13). An emitter composite structure is provided on both sides inside the device body (1).

2. The novel RC-IGBT structure with a hole flow path and a good trade-off relationship according to claim 1, characterized in that: The emitter composite structure is a deep p-type structure, which includes: a first p-type region (2), which is located on both sides inside the device body (1); a first insulating layer (8), which is located on the outside of the first p-type region (2); a second emitter electrode (19), which is located on the outside of the first insulating layer (8); a third insulating layer (18), which is located on the outside of the second emitter electrode (19); a first CS storage layer (15), which is located on both sides of the first p-type region (2) near the bottom; and a channel mechanism is provided at one end of the first p-type region (2) away from the side wall of the device body (1).

3. A novel RC-IGBT structure with a hole flow path and a good trade-off relationship according to claim 2, characterized in that: The channel mechanism is a single-sided hole channel mechanism, which includes: a first emitter trench (14), the right side of which contacts the p-base region (16), and its top contacts the first insulating layer (8); and a second hole channel (21), which is located between the first emitter trench (14) and the first CS storage layer (15).

4. A novel RC-IGBT structure with a hole flow path and a good trade-off relationship according to claim 2, characterized in that: The channel mechanism is a double-sided hole channel mechanism, which includes: a third emitter trench (26), which is located inside the first p-type region (2) and its top is in contact with the first insulating layer (8); a first hole channel (10), which is located between the third emitter trench (26) and the first CS storage layer (15); and a fourth hole channel (25), which is located between the third emitter trench (26) and the p-base region (16).

5. A novel RC-IGBT structure with a hole flow path and a good trade-off relationship according to claim 1, characterized in that: The emitter composite structure is a deeper p-type structure, which includes: a second p-type region (22), which is located on both sides inside the device body (1); a second emitter trench (23), which is located inside the second p-type region (22); a third hole channel (24), which is located between the second emitter trench (23) and the p-base region (16); and an insulating mechanism is provided on the top of the second p-type region (22).

6. A novel RC-IGBT structure with a hole flow path and a good trade-off relationship according to claim 5, characterized in that: The insulation mechanism is a partially insulated mechanism, which includes: a fifth insulation layer (28), the bottom of which is in contact with the second emitter trench (23); a third emitter electrode (29), which is located outside the fifth insulation layer (28) and its bottom is in contact with the second p-type region (22); and a sixth insulation layer (27), which is located outside the third emitter electrode (29) and its bottom is in contact with the second p-type region (22).

7. A novel RC-IGBT structure with a hole flow path and a good trade-off relationship according to claim 5, characterized in that: The insulation mechanism is a fully insulating mechanism, which includes a fourth insulating layer (20), the top of the second p-type region (22) is in contact with the fourth insulating layer (20), and the top of the second emitter trench (23) is in contact with the fourth insulating layer (20).

8. A novel RC-IGBT structure with a hole flow path and a good trade-off relationship according to claim 1, characterized in that: There are two n+ emitter regions (11) symmetrically distributed on both sides of the gate trench (13), and there are two p+ contact regions (12) corresponding one-to-one with the n+ emitter regions (11). The upper ends of the n+ emitter regions (11) and p+ contact regions (12) are in contact with the first emitter electrode (7).

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