Transistor device

Abstract

Transistor devices and methods for manufacturing transistor devices are disclosed. The transistor device comprises a semiconductor body (100) and a plurality of transistor cells (1). Each transistor unit comprises a drift region (11), a main body region (12) and a source region (13); a gate electrode (21) connected to the gate node (G); and a field electrode (31) connected to the source node (S). The gate electrode (21) is dielectrically insulated from the body region (12) by a gate dielectric (22), and the gate electrode (21) is arranged in a first trench (23) extending from the first surface (101) into the semiconductor body (100). The field electrode (31) is dielectrically insulated from the drift region (11) by a high-k dielectric (32), and the field electrode (31) is arranged in the second trench (33). The second trench (33) extends from the first surface (101) into the semiconductor body (100) and is spaced apart from the first trench (23), and the field electrode (31) extends deeply into the semiconductor body (100) at least as deep as the first trench (23).

Description

Technical Field

[0001] The present disclosure relates generally to transistor devices, and in particular to silicon carbide (SiC) based transistor devices. Background Art

[0002] Silicon carbide (SiC) has a higher band gap than silicon (Si), so that SiC can withstand higher electric fields than silicon. Therefore, compared with a vertical transistor device based on silicon with the same voltage blocking capability, in a vertical transistor device based on SiC with a given voltage blocking capability, the length of the drift region can be reduced. Compared with silicon devices, the reduced length of the drift region causes a lower on-resistance of SiC devices. The reduction of on-resistance (which is the electrical impedance of a transistor device in the on state) causes lower conduction losses and is a continuous goal in the design of transistor devices.

[0003] A vertical SiC transistor device may be implemented with a trench gate electrode, which is a gate electrode arranged in a trench extending from a surface into a SiC semiconductor body. The trench gate electrode is dielectrically insulated from the semiconductor body by a gate dielectric.

[0004] High electric fields that may occur in SiC-based transistor devices may damage the gate dielectric. Conventional SiC-based transistor devices therefore include doped regions of a doping type complementary to the doping type of the drift region and connected to the source node (source electrode) of the transistor device. These doped regions are located below the gate trench and together with the drift region form a JFET that protects the gate dielectric from high electric fields in the blocking state of the transistor device.

[0005] Such doped regions, which may be referred to as JFET regions, may be formed using an implantation process. However, the implantation process for forming the JFET region may be expensive and require a thick implantation mask to be formed on top of the semiconductor body. Furthermore, due to the lateral spread of the implanted dopant atoms, the reduction of the cell pitch is limited. For example, the cell pitch is given by the center-to-center distance between adjacent gate trenches or adjacent JFET regions. Furthermore, a pn junction is formed between the drift region and the JFET region. Even in the on-state of the transistor device, such a pn junction involves a space charge region (depletion region), which reduces the width of the conductive path of the transistor device in the on-state. This limits the minimum possible cell pitch, even if a perfectly configured JFET region would be possible.

[0006] There therefore exists a need for improved SiC based transistor devices. Summary of the invention

[0007] One example relates to a transistor device. The transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes a drift region, a body region and a source region, a gate electrode connected to a gate node, and a field electrode connected to the source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and the gate electrode is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and the field electrode is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench. Further, the field electrode extends into the semiconductor body at least as deeply as the first trench.

[0008] Another example relates to a method. The method includes forming a plurality of transistor cells in a semiconductor body such that each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node, dielectrically insulated from the body region by a gate dielectric, and arranged in a first trench extending from a first surface into the semiconductor body; and a field electrode connected to the source node, dielectrically insulated from the drift region by a high-k dielectric, and arranged in a second trench extending from the first surface into the semiconductor body and spaced apart from the first trench. Forming the field electrode of each transistor cell includes forming the field electrode such that the field electrode extends deeper into the semiconductor body than the first trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles, and only the aspects necessary for understanding these principles are illustrated. The accompanying drawings are not to scale. The same reference characters in the accompanying drawings indicate the same features.

[0010] Figure 1 shows a vertical cross-sectional view of a transistor device having a plurality of transistor cells, each transistor cell comprising a gate electrode arranged in a first trench of a semiconductor body and a field electrode arranged in a second trench and dielectrically insulated from a drift region by a high-k dielectric;

[0011] Figure 2 shows a top view of a transistor device according to one example;

[0012] Figure 3 shows a top view of a transistor device according to another example;

[0013] Figure 4 showing a detailed view of a first trench and an adjacent second trench;

[0014] Figures 5 to 7 One example for connecting the body region of a transistor cell to the source electrode of a transistor device is illustrated;

[0015] Figure 8 Another example for connecting the body region to the source electrode is illustrated;

[0016] Fig. 9 A top view of a semiconductor body is shown and a diagram is provided for placing the semiconductor body in the Figure 2 An example of a gate electrode of the type illustrated in FIG. 5 connected to a gate pad of a transistor device;

[0017] Figures 10 to 13 The diagram shows Figure 8 Various modifications of transistor cells of the type illustrated in;

[0018] FIG. 14A to FIG. 14D illustrates one example of a method for forming a high-k dielectric and a field electrode in a second trench;

[0019] FIG. 15A to FIG. 15C One example of a method for forming a source electrode on top of a semiconductor body is illustrated;

[0020] 16A to 16H One example of a method for forming a gate dielectric and a gate electrode in a first trench of a semiconductor body is illustrated;

[0021] Fig.17 illustrates one example of a method for forming a doped region along a sidewall of a second trench;

[0022] FIG. 18A to FIG. 18B One example of a method for forming a high-k dielectric in a second trench spaced apart from a first surface of a semiconductor body is illustrated;

[0023] Fig.19 One example of a method for forming a deep current extension region is illustrated;

[0024] Fig. 20 The diagram shows the Fig.11 and Fig.12 An example of a method of a second groove of the type illustrated in FIG.

[0025] Fig.21 The voltage blocking capability of a transistor device depending on the cell pitch and on the relative dielectric constant of a high-k dielectric is illustrated;

[0026] Fig. 22 illustrates the dielectric field in the gate dielectric as a function of cell pitch; and

[0027] Fig.23 A vertical cross-sectional view of a transistor device according to another example is illustrated. DETAILED DESCRIPTION

[0028] In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and show examples of how the invention may be used and implemented for illustrative purposes. It is to be understood that the features of the various embodiments described herein may be combined with each other unless specifically stated otherwise.

[0029] Figure 1 A transistor device according to an example is shown. More specifically, Figure 1 A vertical cross-sectional view of a portion of a transistor device is shown. The transistor device comprises a semiconductor body 100 and a plurality of transistor cells 1. The semiconductor body 100 comprises a first surface 101 and a second surface 102. The second surface 102 is opposite to the first surface 101 and is spaced apart from the first surface 101 in a vertical direction z of the semiconductor body 100.

[0030] According to one example, the semiconductor body 100 is a single crystal semiconductor body. According to one example, the semiconductor body 100 includes single crystal silicon carbide (SiC). According to one example, the single crystal SiC is a single crystal SiC of 4H, 6H or 3H polytype. However, implementing the semiconductor body 100 using single crystal SiC is only an example. Other semiconductor materials, such as silicon (Si), may also be used.

[0031] Reference Figure 1 , each transistor cell comprises a drift region 11, a body region 12 and a source region 13. Each of the drift region 11, the body region 12 and the source region 13 is a doped semiconductor region within the semiconductor body 100. According to an example, the body region 12 adjoins both the source region 13 and the drift region 11, wherein the body region 12 is arranged between the source region 13 and the drift region 11. The source region 13 of each transistor cell 1 is connected to a source node S. According to an example (not shown in Figure 1 ), the body region 12 of the transistor cell is also connected to the source node S.

[0032] In the following, the body region 12, the source region 13 and the drift region 11 are referred to as “active device regions”. According to one example, the doping concentration of the active device region is selected from the following ranges: the drift region 11: 1E15 cm -3 and 1E17 cm -3 Between; Main area 12: 1E16 cm -3 and 1E18cm -3 Source region 13: higher than 1E19 cm -3 .

[0033] Further, each transistor cell 1 comprises a gate electrode 21 and a field electrode 31. The gate electrode 21 is arranged adjacent to the body region 12, is dielectrically insulated from the body region 12 by a gate dielectric 22, and is connected to a gate node G. Further, the gate electrode 21 is arranged in a first trench 23, which extends from the first surface 101 into the semiconductor body 100. According to an example, the gate electrode 21 extends essentially in a vertical direction z in the direction of the second surface 102. The first trench 23 is spaced apart from the second surface 102.

[0034] The field electrode 31 is arranged adjacent to the drift region 11, is dielectrically insulated from the drift region 11 by a field electrode dielectric 32, and is connected to the source node S. Further, the field electrode 31 is arranged in a second trench 33, which is spaced apart from the first trench 23. The second trench 33 extends from the first surface 101 into the semiconductor body 100. According to an example, the field electrode 31 extends essentially in a vertical direction z in the direction of the second surface 102. The second trench 33 is spaced apart from the second surface 102.

[0035] According to an example, the gate electrode 21 comprises a metal or a highly doped polycrystalline semiconductor material, such as, for example, polysilicon. Likewise, the field electrode 31 may comprise a metal or a highly doped polycrystalline semiconductor material, such as, for example, polysilicon.

[0036] In the following, the first trench 23 is also referred to as a gate trench. Furthermore, the second trench 33 is also referred to as a field electrode trench.

[0037] exist Figure 1 , only the gate node G and the source node S, the connection between the gate electrode 21 and the gate node G, the connection between the field electrode 31 and the source node S, and the connection between the source region 13 and the body region 12 and the source node S are schematically illustrated. The gate node and the source node can be implemented using conventional metallization, and the connection can be implemented using conventional wiring technology. An example for implementing such circuit nodes and connections is further explained below in this article.

[0038] Furthermore, in each transistor cell 1, the field electrode trench 33 including the field electrode 31 is spaced apart from the gate trench 23 including the gate electrode 21 in a lateral direction x of the semiconductor body 100. The lateral direction x is essentially perpendicular to the vertical direction z.

[0039] The field electrode 31 extends at least as deep into the semiconductor body 100 as the gate trench 23. That is, the dimension of the field electrode 31 in the vertical direction z of the semiconductor body 100 is at least equal to the dimension of the gate trench 23 in the vertical direction z. Figure 4 Further detailed explanation.

[0040] The field electrode dielectric 32 is a high-k dielectric. According to one example, this includes that the relative dielectric constant K of the field electrode dielectric 32 is higher than that of silicon dioxide (SiO 2 ) relative dielectric constant, silicon dioxide (SiO 2 ) has a relative dielectric constant of about 3.9, K SiO2 ≈3.9. According to an example, the material of the field electrode dielectric 32 is selected such that the relative permittivity K of the field electrode dielectric 32 is higher than 5, higher than 10, higher than 20 or even higher than 30. The relative permittivity of a high-k dielectric may also be referred to as K factor.

[0041] Examples for implementing the field electrode dielectric 32 include, but are not limited to, Al 2 O 3 (aluminum oxide), ZrO 2 (zirconia), HfO 2 (Hafnium oxide) or silicon-doped HfO 2 、AlN(aluminum nitride), AlSiO x (aluminum silicate), TiO 2 (Titanium oxide), Y 2 O 3 (Yttrium oxide) or Si 3 N 4 (Silicon nitride). The field electrode dielectric 32 may consist entirely of the same material, such as one of the materials explained previously. According to another example, the field electrode dielectric 32 comprises a layer stack having two or more different dielectric layers. At least one of these two or more layers may comprise one of the materials explained previously. Another of these two or more layers may comprise a low-k dielectric, such as SiO 2 .

[0042] According to one example, the gate dielectric 22 includes silicon dioxide (SiO 2 According to another example, the gate dielectric 22 comprises a high-k dielectric. The material of the high-k dielectric may be according to one of the examples explained herein before with reference to the field dielectric 32.

[0043] According to one example, the drift region 11 and the source region 13 are doped regions of a first doping type, and the body region 12 is a doped region of a second doping type complementary to the first doping type. The transistor device can be implemented as an N-type transistor device or as a P-type transistor device. In the N-type transistor device, the drift region 11 and the source region 13 are N-type regions and the body region 12 is a P-type region. In the P-type transistor device, the drift region 11 and the source region 13 are P-type regions and the body region 12 is an N-type region. Further, the transistor device can be implemented as an enhancement device or as a depletion device. In the enhancement device, the body region 12 of each transistor cell 1 is adjacent to the gate dielectric 22 of the corresponding transistor cell (as in Figure 1 In a depletion device, each transistor cell 1 includes, in addition to the body region 12, a channel region of the same doping type as the source region 13 between the body region 12 and the gate dielectric 22. However, such a channel region Figure 1 Not shown in the figure.

[0044] The transistor can be operated in a conventional manner by applying a drive voltage (gate-source voltage) between the gate node G and the source node S. Figure 1 When a driving voltage is applied between the gate node G and the source node S, the transistor device is in an on-state (conductive state), which causes a conductive channel in the body region 12 along the gate dielectric 22 between the source region 13 and the drift region 11 in each transistor cell 1. For example, when a positive driving voltage higher than the threshold voltage is applied between the gate node G and the source node S, the N-type transistor device is in an on-state.

[0045] In the on state, current can flow from the source node S to the drain node D via the source region 13, the conductive channel in the body region 12, and the drift region 11. Figure 1 The drain node D, which is only schematically illustrated in FIG. 1 , is electrically connected to the drift region 11 of each transistor cell 1. Figure 1 In the example illustrated in dashed lines in FIG. 1 , the drain node D is connected to the drift region 11 via the drain region 15. According to an example, the drain region 15 is of the same doping type as the drift region 11 and has a higher doping concentration. According to an example, the doping concentration of the drain region 15 is at least 100 times the doping concentration of the drift region 11.

[0046] In order to make the current more evenly distributed in the drift region 11 when the transistor device is in the on state, the drift region 11 may include a current extension region 14. The current extension region 14 is a part of the drift region 11 and has a higher doping concentration than the rest of the drift region 11. According to an example, the doping concentration of the current extension region 14 is between 3 times and 100 times the doping concentration of the rest of the drift region 11.

[0047] exist Figure 1 In the example illustrated in , in each transistor cell 1 , the current extension region 14 adjoins the body region 12 . However, this is only an example. It is also possible to implement the current extension region 14 in such a way that the current extension region 14 is spaced apart from the body region 12 in the vertical direction z.

[0048] Reference Figure 1 , a gate trench 23 with a gate electrode 21 may extend into the drift region 11. According to an example, as seen from the first surface 101, the current extension region 14 extends deeper into the semiconductor body 100 in the vertical direction z than the gate trench 23. Figure 1 As further illustrated in FIG. 1 , the current extension zone 14 may extend shallower into the semiconductor body 100 than the field electrode trench 33. However, this is only an example. According to another example (not illustrated), the current extension zone 14 extends deeper into the semiconductor body 100 in the vertical direction z than the field electrode trench 33, so that the current extension zone 14 surrounds the bottom of the field electrode trench 33.

[0049] When the conductive channel in the body region 12 is interrupted, the transistor device is in an off state. In the off state, when a voltage that reversely biases the PN junction between the body region 12 and the drift region 11 is applied between the drain node D and the source node S, a space charge region (depletion region) expands in the drift region 11. Such a depletion region is associated with an electric field.

[0050] In the absence Figure 1 In a transistor device with a field electrode 31 of the type illustrated in FIG. 1 , the maximum value of the electric field occurs in the drift region 11 close to the PN junction. For example, in the off state, if the potential of the gate electrode 21 is equal to the potential of the source region 13 and the body region 12, the electric field E in the gate dielectric 22 in the center of the bottom of the gate trench is 22 (where the field lines of the electric field are essentially perpendicular to the interface between the drift region 11 and the gate dielectric 22) is essentially given by:

[0051]

[0052] where ε 11 The relative dielectric constant (K factor) of the semiconductor material of the semiconductor body 100 is indicated, ε 22 The relative dielectric constant (K factor) of the dielectric material of the gate dielectric 22 is indicated, and E 11 2 shows the magnitude of the electric field in the region adjacent to the gate dielectric 22 in the drift region 11. The gate dielectric 22 may include silicon oxide (SiO 2), which has a relative dielectric constant of about 3.9. For example, silicon carbide has a relative dielectric constant of about 9.6. Therefore, if the semiconductor material of the semiconductor body 100 includes silicon carbide and the gate dielectric 22 includes silicon oxide, then according to equation (1), the dielectric field E in silicon oxide is 22 The electric field in the gate dielectric 22 may be significantly higher (approximately 2.5 times) than the dielectric field in the adjacent semiconductor material. This may have the effect that the electric field in the gate dielectric 22 may become higher than the critical electric field of the gate dielectric. This may cause degradation or damage to the gate dielectric 22.

[0053] The critical electric field of silicon carbide is between 2MV / cm and 3MV / cm. The critical electric field for intrinsic breakdown of silicon dioxide is between 8MV / cm and 10MV / cm, which is greater than 2.5 times the critical electric field of silicon carbide. However, due to imperfections in the manufacturing process of the gate dielectric 22, the critical electric field of the gate dielectric 22 may be less than the theoretical critical electric field of the material used to realize the gate dielectric 22. Therefore, in order to realize a reliable device, the electric field in the dielectric layer separating the gate electrode 21 from the drift region 11 should be less than twice the critical electric field of the material of the semiconductor body 100 and / or significantly less than the theoretical breakdown limit of the dielectric layer.

[0054] In accordance with Figure 1 In the transistor device 1, in the off state of the transistor device, the field electrode 31 connected to the source node S generates a space charge region (depletion region) in a section of the drift region 11 adjacent to the field electrode dielectric 32. As the voltage applied between the drain node D and the source node S increases, as seen from the field electrode dielectric 32, this depletion region starting from the field electrode dielectric 32 extends deeper into the drift region 11.

[0055] According to an example, the field electrode 31 of each transistor cell 1 is implemented such that the field electrode 31 depletes the drift region 11 in its entirety in the region adjacent to the gate dielectric 22 before the electric field reaches a magnitude that may damage the gate dielectric 21 due to the increased voltage between the drain node D and the source node S. In particular, the lateral distance between the first trench 23 and the second trench 33 and the vertical dimension of the field electrode 31 may be implemented in such a way that the field electrode 31 is able to deplete the drift region 11 and the region around the gate dielectric 22.

[0056] Referring to the above, the field electrode dielectric 32 is a high-k dielectric. The critical electric field of the high-k dielectric may be lower than that of a dielectric such as SiO 2However, due to the high K factor measured at the same field in the semiconductor drift region, the electric field in the field electrode dielectric 32 implemented with the high-k dielectric is lower than the electric field in the conventional field electrode dielectric including the low-k dielectric. Therefore, the field electrode dielectric 32 including the high-k dielectric is more robust than the gate dielectric 22 in terms of the electric field occurring in the drift region 11.

[0057] exist Figure 1 In FIG. 1 , several transistor units 1 of a transistor device are illustrated. As can be seen from Figure 1 As can be seen, two (or more) transistor cells may share an active device region 11, 12, 13, a gate electrode 21 or a field electrode 31. Figure 1 In the example illustrated in FIG. 1 , for example, the gate electrodes 21 of two adjacent transistor units 1 are formed by the same trench electrode. Furthermore, the field electrodes 31 of two (other) adjacent transistor units 1 are formed by the same trench electrode. Furthermore, as can be seen from Figure 1 As can be seen, the drift regions 11 of a plurality of transistor cells can be formed by one and the same doped region of the semiconductor body 100 . Likewise, the drain regions 15 of the transistor cells 1 can be formed by one and the same doped region of the semiconductor body 100 .

[0058] Figure 1 A vertical cross-sectional view of several transistor cells 1 is shown. Figure 1 In the horizontal plane of the plane of the cross-sectional plane AA shown in FIG. , the transistor unit 1 can be implemented in various ways. Figure 2 and Figure 3 Two different examples are explained. Figure 2 and Figure 3 In each of the EMBODIMENTS 1 and 2, reference numeral 2 denotes a gate structure, each of which includes a gate electrode 21 and a gate dielectric 22, wherein the gate electrode 21 and the gate dielectric 22 are not explicitly shown in these figures. Further, reference numeral 3 denotes a field electrode structure, each of which includes a field electrode 31 and a field electrode dielectric 32, wherein the field electrode 31 and the field dielectric 32 are not explicitly shown in these figures.

[0059] Reference Figure 2 , the transistor cell 1 can be implemented as an elongated transistor cell, which can also be referred to as a stripe cell. In this example, the gate structure 2 (with a gate electrode and a gate dielectric) and the field electrode structure 3 (with a field electrode and a field electrode dielectric) are elongated in the horizontal (lateral) direction of the semiconductor body 100. Similarly, the source region 13 and the body region 12 (these are elongated in the horizontal (lateral) direction of the semiconductor body 100). Figure 2The source region 13 and the body region 12 are elongated, wherein each source region 13 and the body region 12 are arranged between the gate structure 2 and the corresponding field electrode structure 3 .

[0060] Reference Figure 3 , the transistor cell 1 can be implemented as a hexagonal transistor cell. In this example, the gate structure 2 (having a gate electrode and a gate dielectric) has the shape of a hexagonal grid, wherein the source region 13 and the body region 12 (these are in Figure 3 The transistor cells 1 are formed in a hexagonal space defined by a hexagonal grid (outside the view in FIG. 1 ). In this example, each transistor cell 1 includes one field electrode structure 3 having a needle shape or a stacked shape.

[0061] Referring to the above, the semiconductor body 100 may include a single crystal SiC of the 4H polytype. In this example, the hexagonal gate structure 2 may be arranged within the crystal of the single crystal SiC semiconductor body so that the channel region between the gate dielectric 22 and the body region 12 is aligned to match the vertical crystal plane of the semiconductor body. This is beneficial in view of the reduction of the channel resistance.

[0062] It should be noted that implementing the transistor cell 1 as a hexagonal transistor cell by implementing the gate structure as a hexagonal grid is only an example. Other shapes of transistor cells 1 are also possible, such as implementing the transistor cell 1 as a rectangular transistor cell by implementing the gate structure 2 as a rectangular grid.

[0063] Figure 4 A vertical cross-sectional view of a portion of a transistor device is shown in more detail in order to explain some dimensions of the transistor cell 1. More specifically, in Figure 4 The portion of the transistor device illustrated in FIG. 1 includes a first trench 23, a second trench 33, a source region 13 and a body region 12 arranged between the first trench 23 and the second trench 33, a portion of the drift region 11, a portion of the optional drain region 15, and a portion of the optional current extension region 14. Figure 4 In the figure, d2 indicates the depth of the first trench 23, which is the dimension of the first trench 23 in the vertical direction z of the semiconductor body 100; d31 indicates the depth of the field electrode 31, which is the dimension of the field electrode 31 in the vertical direction z of the semiconductor body 100; w2 indicates the trench width of the first trench 23, which is the (shortest) lateral dimension of the first trench 23; w3 indicates the trench width of the second trench 33, which is the (shortest) lateral dimension of the second trench 33; s23 indicates the shortest distance between the first trench 23 and the second trench 33; and l11 indicates the length of the drift region 11, which is the dimension of the drift region 11 in the vertical direction z of the semiconductor body 100.

[0064] Referring to above, the field electrode 31 extends at least as deep into the semiconductor body 100 as the first trench 23 . Figure 4 , which includes that the depth d31 of the field electrode 31 is at least equal to the depth d2 of the first trench 23, d31 ≥ d2. According to an example, the depth d31 of the field electrode is between 1.0 and 2.5 times the depth d2 of the first trench 23, 1.0·d2≤d31≤2.5·d2. According to an example, the depth d31 of the field electrode is selected from between 0.8 micrometers (μm) and 2.5 micrometers.

[0065] According to one example, the groove width w2, w3 of each of the first groove 23 and the second groove 33 is selected from between 0.3 micrometers and 1.0 micrometers. The distance s23 between the first groove 23 and the second groove 33 can be selected from the same range as the groove width w2, w3. That is, the distance s23 can be selected from between 0.3 micrometers and 1.0 micrometers.

[0066] According to an example, the (shortest) distance between two adjacent second trenches 33 in the region of the gate structure 2 is selected from between 0.5 micrometers and 2 micrometers. Given a trench width between 0.3 micrometers and 1.0 micrometers, this is included in Figure 1 In a device of the type illustrated in FIG. 1 , the pitch p is between 0.8 (=0.5+2·0.15) microns and 3.0 (=2.0+2·0.5) microns. For example, the pitch p is the center-to-center distance between two adjacent second trenches 33 or two adjacent first trenches 31. As explained in further detail herein below, there are various examples of transistor devices in which the distance between two adjacent second trenches 33 under the gate structure 2 is shorter than in the region of the gate structure 2.

[0067] The voltage blocking capability of the transistor device depends, among other things, on the length l11 of the drift region 11. The length of the drift region 11 is essentially given by the (shortest) distance between the body region 12 and the drain region 15. According to one example, the length l11 of the drift region is selected from between 5 microns and 30 microns. SiC-based transistor devices can be implemented such that the voltage blocking capability is essentially equal to 100 V per 1 μm of drift region length (compared to silicon, where the voltage blocking capability is only about 10 V per 1 μm of drift region length).

[0068] Referring to above, the field electrode 31 , the source region 13 and optionally the body region 12 are connected to the source node S of the transistor device. Some examples for connecting the field electrode 31 , the source region 13 and the body region 12 to the source node S are explained below.

[0069] According to Figure 5In one example illustrated in FIG. 1 , the transistor device comprises a source metallization 41 on top of an insulating layer 43. The insulating layer 43 is formed on top of the first surface 101 of the semiconductor body 100 and electrically insulates the gate electrode 21 from the source metallization 41. The source metallization 41 is connected to a source node S or forms a source node S of the transistor device. Further, the transistor device comprises a conductive via 42, which extends through the insulating layer 43 and connects at least the field electrode 31 to the source metallization 41, and which may also be referred to as a source via 42. The “at least” in this case includes the via 42 connecting the field electrode 31 to the source metallization 41. Additionally, the source via 42 may connect the source region 13 directly to the source metallization 41. Alternatively, the source region 13 may be connected to the field electrode 31 (as further explained herein below) so that the source region 13 is indirectly connected to the source metallization 41 through the via 42.

[0070] In order to connect the body region 12 to the conductive vias 42, sections of the body region 12 may extend to the first surface 101 where they are connected to the conductive vias 42. Figure 6 , which shows a vertical cross-sectional view of a transistor device in a region where a segment of the body region 12 extends to the first surface 101 of the semiconductor body. Optionally, the segment of the body region extending to the first surface 101 has a higher doping concentration than the rest of the body region in order to achieve an ohmic contact between the body region 12 and the conductive via 42. Such a higher doped contact region is Figure 6 Reference numeral 16 is used for reference.

[0071] Figure 7 Shown in Figure 6 Horizontal cross-sectional view of a transistor device of the type illustrated in FIG. In the transistor device, the source regions 13 and the body regions 12 are alternately arranged in the lateral direction y along the first surface 101, so that the source regions 13 and the body regions 12 are alternately connected to the source vias 42. Figure 7 The vertical cross-sectional view in the vertical cross-sectional plane BB of the device illustrated in FIG. Figure 5 A vertical cross-sectional view is shown in FIG. Figure 7 The vertical cross-sectional view of the device illustrated in the vertical cross-sectional plane CC corresponds to the vertical cross-sectional view in FIG. Figure 6 Vertical cross-sectional view shown in FIG.

[0072] Figure 8 A vertical cross-sectional view of a portion of a transistor device according to another example is shown. Figure 1 , Figure 5 and Figure 6In the example illustrated in FIG. 1 , the high-k dielectric 32 does not extend to the first surface 101 but terminates in the semiconductor body 100 spaced apart from the first surface 101, so that the field electrode 31 adjoins the source region 13 and the body region 12 at the sidewalls of the second trench 33 and is electrically connected to the source region 13 and the body region 12. Optionally, a contact region 16 of the same doping type and more highly doped than the body region 12 is arranged between the field electrode 31 and the body region 12 in order to provide an ohmic contact between the field electrode 13 and the body region 12. The source via 42 is connected to the field electrode 31, so that the source via 42 is connected to the source region 13 and the body region 12 through the field electrode 31. As shown in FIG. Figure 8 As illustrated in the left part of , the source via 42 may be further connected to a portion of the source region 13 along the first surface 101 , so that the source via 42 is connected to the source region 13 both directly and through the field electrode 31 . However, this is only an example. Figure 8 As illustrated in the right part of , it is also possible that the source via 42 is connected only to the field electrode 31 , so that the source via 42 is connected to the source region 13 only through the field electrode 31 .

[0073] Fig. 9 A top view of a transistor device according to one example is shown. More specifically, Fig. 9 A top view of a semiconductor body 100 with a source metallization 41 is shown. Fig. 9 An example of gate structures 2 and their location under source metallization 41 is illustrated in dashed lines in FIG. In this example, the gate structure 2 under source metallization 41 extends beyond source metallization 41 and is connected to gate runner 52. Gate runner 52 is formed on top of insulating layer 43 and is connected to gate pad 51. Gate pad 51 is connected to gate node G or forms gate node G of a transistor device.

[0074] according to Fig. 9 The transistor device comprises only one source metallization 41. However, this is only an example. According to another example (not shown), the transistor device comprises several source metallizations and comprises two or more gate runners 52, each of which is connected to the source node S and each of which is connected to the gate pad 51.

[0075] Figures 10 to 13 The diagram shows Figure 1 Further examples of transistor devices of the type illustrated in FIG. Figures 10 to 13 Each of shows a vertical cross-sectional view of a portion of a transistor device.

[0076] exist Fig.10 The transistor device shown in the figure is based on Figure 8 The transistor device shown in the figure is Figure 8The transistor device illustrated in FIG. 1 differs in that the high-k dielectric 32 terminates spaced apart from the first surface 101 in the drift region 11. The drift region 11 is separated from the field electrode 31 by a doping region 17, which is of the same doping type as the body region 12 and is more highly doped than the body region 12. According to an example, the doping concentration of the doping region 17 is at least 10 times or at least 100 times the doping concentration of the body region 12.

[0077] According to one example, the doped region 17 not only separates the drift region 11 from the field electrode 31, but also (as in Fig.10 The doped region 17 is also arranged between the field electrode 31 and at least part of the body region 12 as shown in the figure. In this example, the doped region 17 provides an ohmic contact between the field electrode 31 and the body region 12.

[0078] Furthermore, the doped region 17 and the drift region 11 form a PN junction, so that in the blocking state of the transistor device, a depletion region (space charge region) can expand in the drift region 11 starting at the PN junction. Therefore, in addition to the field electrode structure 3 having the field electrode 31 and the high-k dielectric 32, the doped region 17 can also support the depletion of the drift region 11 around the gate dielectric 22, and thus help to protect the gate dielectric 22 from high electric fields in the blocking state of the transistor device. According to an example, the doping concentration of the doped region 17 is high enough so that the depletion region 17 cannot be completely depleted of charge carriers in the blocking state of the transistor device.

[0079] Reference Fig.10 , the doped region 17 may overlap the high-k dielectric 32. Further, according to an example, the doped region 17 extends deeper than the first trench 23 having the gate electrode 21 and the gate dielectric 22 in the vertical direction z.

[0080] Fig.11 Shown according to Fig.10 Modification of transistor devices. Fig.11 In the example illustrated in , the field electrode trench 33 is implemented such that the field electrode trench 33 widens below the bottom of the first trench 23, so that the adjacent second trench 33 forms a kind of bottleneck in the drift region 11 below the gate trench 23 with the gate electrode 21 and the gate dielectric 22. According to an example, the second trenches are implemented such that the shortest distance d33 in the lateral direction between two adjacent second trenches 33 is between 0.5 times and 2 times the trench width w2 of the first trench 23.

[0081] Narrowing the drift region 11 due to the widened field electrode trench 33 in the blocking state of the transistor device helps to deplete the drift region 11 in the region around the gate dielectric 22 and thus helps to protect the gate dielectric 22 from high electric fields.

[0082] It should be noted that the implementation Fig.11 A transistor device with a widened field electrode trench 33 of the type illustrated in FIG. Fig.11 1 , in which the high-k dielectric 32 ends in the drift region 11 and in which the field electrode 31 is separated from the drift region 11 by the doped region 17. In contrast, a widened field electrode trench 33 may also be used in a transistor device in which the high-k dielectric 32 extends to the first surface 101. This type of transistor device is Fig.12 Medium picture.

[0083] According to another example (not shown), the widened field electrode trench 33 is implemented in Figure 8 In a transistor device of the type illustrated in , the high-k dielectric 32 terminates in the body region 12 spaced apart from the first surface 101 .

[0084] Fig.13 A transistor device according to another example is shown. In this example, the field electrode trench 33 extends into the drain region 15 in the vertical direction z. The dimensions of the field electrode 31 may be as explained herein above. The section of the second trench 33 between the lower end of the field electrode 31 and the bottom of the second trench 33 is filled with a dielectric. According to an example, the dielectric between the lower end of the field electrode 31 and the bottom of the second trench 33 is a high-k dielectric of the same type as the high-k dielectric separating the field electrode 31 from the drift region 11.

[0085] In accordance with Fig.13 In the transistor device, since the high-k dielectric is arranged in the field electrode trench 33 between the bottom of the field electrode 31 and the bottom of the field electrode trench 33, the effective dielectric constant of the drift region 11 is higher than in a transistor device lacking such a high-k dielectric in the drift region 11 between the field electrode 31 and the drain region 15. Due to the increased dielectric constant, the drift region 11 can be implemented to have a higher doping concentration, so that the transistor device has a lower on-resistance without reducing the voltage blocking capability.

[0086] FIG. 14A to FIG. 14D The diagram shows the Figure 1 An example of a method for a transistor device of the type illustrated in FIG. More specifically, FIG. 14A to FIG. 14D A vertical cross-sectional view of a portion of a semiconductor body 100 is shown during different processing sequences. FIG. 14A to FIG. 14D The portion of the semiconductor body 100 illustrated in FIG. 1 comprises a gate trench 23 which is arranged between two adjacent field electrode trenches 33. It should be noted that FIG. 14A to FIG. 14DThe processing sequence illustrated in FIG. 1 and further explained herein below may occur on a wafer level. That is, multiple transistor devices may be formed simultaneously on a wafer, wherein the wafer is ultimately subdivided into individual transistor devices.

[0087] Fig.14A The semiconductor body 100 is shown after forming the gate structure 2 and after forming the field electrode trenches 33. An example for forming the gate structure 2 and the field electrode trenches 33 is referred to herein below. 16A to 16H Further explanation. According to an example, the gate structure 2 and the field electrode trench 33 are formed after forming the following doping regions: the doping regions form the source region 13 and the body region 12 in the completed transistor device. Forming these doping regions may include an implantation process in which dopant atoms are implanted into the semiconductor body 100 through the first surface 101.

[0088] Reference Fig. 14B The method includes forming a high-k dielectric layer 132. In the completed device, a portion of the high-k dielectric layer 132 forms a high-k dielectric 32 in the field electrode trench 33. Fig. 14B Forming the high-k dielectric layer 132 may include depositing the high-k dielectric layer 132 such that the high-k dielectric layer 132 covers surfaces (sidewalls and bottom) of the field electrode trenches 33 and covers the gate structure 2 and the first surface 101 of the semiconductor body 100 .

[0089] Reference Fig. 14C The method further comprises forming a field electrode layer 131. In the completed device, a portion of the field electrode layer 131 forms a field electrode 31 in the field electrode trench 33. Fig. 14C Forming the field electrode layer 131 may include depositing the field electrode layer 131 such that the field electrode layer 131 fills the field electrode trench 33 on top of the high-k dielectric layer 132 and covers the high-k dielectric layer 132 on top of the first surface 101 of the semiconductor body 100 and on top of the gate structure 2 .

[0090] Reference Fig.14D The method further comprises removing the field electrode layer 131 and the high-k dielectric layer 132 from above the first surface 101, whereby the high-k dielectric layer 132 remains in the field electrode trench 33 in which it forms the high-k dielectric 32, and whereby the field electrode layer 131 remains in the field electrode trench 33 on top of the high-k dielectric 32 in which it forms the field electrode 31. Removing the field electrode layer 131 and the high-k dielectric layer 132 from above the first surface 101 may comprise at least one of: an etching process; a polishing process, such as a CMP (chemical mechanical polishing) process, or the like.

[0091] FIG. 15A to FIG. 15COne example of a method for forming an insulating layer 43, a source metallization 41 and a source via 42 on top of a gate structure 2 is illustrated. FIG. 15A to FIG. 15B The method includes forming an insulating layer 43 so that the insulating layer 43 covers the gate structure 2 in those regions of the semiconductor body 100, forming a source metallization 41 on top of the semiconductor body 100. Forming the insulating layer 43 may include depositing the insulating layer 143 covering the entire first surface 101, and patterning the deposited insulating layer 143 so that the gate structure 2 is covered and at least part of the field electrode 31 is not covered. Patterning the deposited insulating layer may include using an etching mask 201 (which is Fig.15A The etching process is shown in dashed lines in FIG.

[0092] For illustration purposes only, Fig. 15B In the example shown in FIG. 4 , the insulating layer 43 is formed so that not only parts of the field electrode 31 but also parts of the source region 13 are not covered by the insulating layer 43. However, this is only an example. It is also possible to form the insulating layer 43 so that it completely covers the source region 13. In this example, for example, in the completed device the source region 13 is connected to the source metallization 41 via the field electrode 31, as in FIG. Figure 8 , Fig.10 and Fig.11 As shown in the figure.

[0093] Reference Fig. 15C , the method further comprises forming a source metallization 41 and a source via 42. This may comprise a processing step in which a metal layer is deposited on top of the insulating layer 43 and those sections of the first surface 101 not covered by the insulating layer 43. In this example, the metal layer forms the first metallization 41 and the source via 42 simultaneously.

[0094] 16A to 16H The diagram shows the Fig.14A An example of a method of forming a second trench 33 and a gate structure 2 of the type illustrated in FIG. 16A to 16H Each of shows a vertical cross-sectional view of a portion of the semiconductor body 100 during a different processing sequence.

[0095] Reference Fig.16A The method comprises forming the gate trench 23 and forming the partial field electrode trench 33' by the same etching process. Forming these trenches 23, 33' may comprise using an etching mask 202 formed on top of the first surface 101 (at Fig.16A Anisotropic etching process (shown in dashed lines in FIG. 5 ).

[0096] Reference Fig. 16BThe method further includes forming a gate dielectric layer 122. Portions of the gate dielectric layer 122 form the gate dielectric 22 in the completed transistor device. Forming the gate dielectric layer 122 may include depositing the gate dielectric layer 122 to cover the surfaces (bottom and sidewalls) of the gate trench 23 and portions of the field electrode trench 33' and to cover the first surface 101 of the semiconductor body 100. The material of the gate dielectric layer 122 corresponds to the desired material of the gate dielectric 22.

[0097] Reference Fig. 16C and Fig.16D The method further comprises removing the gate dielectric layer 122 from the partial field electrode trench 33 ′ and etching the partial field electrode trench 33 ′ deeper into the semiconductor body 100 to form the field electrode trench 33 .

[0098] Reference Fig. 16C , removing the gate dielectric layer 122 from the partial field electrode trench 33' may include forming a protective layer 203. The protective layer 203 covers those sections of the gate dielectric layer 122 that remain and does not cover those sections of the gate dielectric layer 122 that are to be removed. The protective layer 203 includes, for example, a photoresist and may be patterned using a conventional lithography process. For example, an etching process may be used to remove those sections of the gate dielectric layer 122 that are not covered by the protective layer 203.

[0099] Extending the partial field electrode trench 33' further into the semiconductor body 100 to form the field electrode trench 33 may include an etching process. According to an example, the protection layer 203 used in the process of partially removing the gate dielectric layer 122 is used as an etching mask in the process of etching the partial field electrode trench 33' deeper into the semiconductor body. However, this is only an example. It is also possible to use an etching mask other than a protection layer.

[0100] After forming the field electrode trenches 33 , the protection layer 203 is removed. Fig.16E The semiconductor body 100 is shown after removal of the protection layer 203 .

[0101] The method further includes forming a gate electrode 21 on top of the gate dielectric 22 in the gate trench 23. Fig.16F This may include depositing a gate electrode layer 121 over the entire arrangement, such that the gate electrode layer 121 fills the field electrode trenches 33 , fills the gate trenches 23 on top of the gate dielectric layer 122 and is formed over the first surface 101 of the semiconductor body 100 .

[0102] Reference Figure 16G, the method further includes a planarization process, wherein the gate electrode layer 121 and the portion of the gate dielectric layer 102 formed on top of the first surface 101 of the semiconductor body 100 are removed. The planarization process may include at least one of an etching process and a polishing process. Those sections of the gate dielectric layer 122 remaining in the gate trench 23 after the planarization process form the gate dielectric 22. Further, those sections of the gate electrode layer 121 remaining on top of the gate dielectric 22 in the gate trench 23 form the gate electrode 21.

[0103] The method further comprises removing the gate electrode layer 121 from the field electrode trench. This may comprise an etching process using an etching mask 204 covering the first surface 101 of the semiconductor body 100. Fig.16H 2 shows a semiconductor body 100 with an etching mask 204 and before an etching process. The gate electrode layer 121 is removed from the field electrode trench 23 during the etching process. Fig.14A The arrangement shown in the figure.

[0104] Fig.17 The diagram is used to form a reference Fig.10 An example of a method of explaining the type of doping region 17 is shown below. Fig.17 The formation of the doped region 17 may include a tilted implantation process, wherein dopant atoms are implanted into the sidewalls of the gate trench to form an implanted region 17'. The implanted region 17' defines the size and position of the doped region 17, wherein forming the doped region 17 based on the implanted region 17' includes an annealing process.

[0105] Reference Fig.17 , an implantation mask may be formed on top of the first surface 101 to prevent dopant atoms from being implanted into the first surface 101. The implantation mask may be the same as that in the reference Fig.16H The etching mask 204 is the same mask as used in the method explained.

[0106] exist Fig.17 In the process illustrated in FIG. 1 , the implantation region 17 ′ essentially extends in the vertical direction z to the first surface 101 . In this example, the source region 13 is separated from the doped region 17 and from the field electrode 31 . Thus, in this example, for example, the source region 13 is formed in a manner similar to that in FIG. 1 . Figure 5 The method shown in FIG. 4 is connected to the source via 42 at the first surface 101 .

[0107] This can be achieved in various ways Fig.10 doped regions 17 of the type illustrated in FIG. 1 , which are spaced apart from the first surface 101. According to one example, forming these regions 17 includes Fig.171 , which forms an implanted region 17' extending to the first surface 101. In addition to this first tilted implantation process in which dopant atoms of the second doping type are implanted, forming the doped region 17 may also include a second tilted implantation process in which dopant atoms of the first doping type are implanted into the trench sidewalls in a region adjacent to the first surface 101. The implantation dose in the second tilted implantation process may be equal to the implantation dose in the first tilted implantation process, so that in the region adjacent to the first surface 101, the two tilted implantation processes result in an effective doping concentration of zero and form a doped region 17 of the second doping type spaced apart from the first surface 101.

[0108] According to another example, a doping region 17 of a second doping type is formed in the semiconductor body 100 in a region spaced apart from the first surface 101 before forming the field electrode trenches 33. Forming the dopant region of the second doping type may include an implantation process. The field electrode trenches 33 are then formed to partially remove such doping regions of the second doping type, wherein the remaining portion of the dopant region formed before forming the field electrode trenches 33 forms the doping region 17.

[0109] FIG. 18A to FIG. 18B One example of a method for forming a recessed high-k dielectric 32 is illustrated, the recessed high-k dielectric 32 being a high-k dielectric that terminates spaced apart from the first surface 101 of the semiconductor body 100. Fig.18A , after forming the high-k dielectric layer 132, the method includes forming a protection layer 205 on top of those sections of the high-k dielectric layer 132 that should remain in the field electrode trenches 33. Forming the protection layer 205 may include depositing the protection layer over the entire semiconductor body 100 and etching back the protection layer so that the protection layer 205 remains only in those sections of the field electrode trenches 33 where the high-k dielectric layer 132 will be covered.

[0110] Reference Fig.18B , the method further includes removing the high-k dielectric layer 132 in those sections not covered by the protective layer 205. Removing the high-k dielectric layer 132 may include an etching process that selectively etches the high-k dielectric layer 132 relative to the semiconductor body 100. Finally, the protective layer 205 may be removed. Removing the protective layer 205 may include an etching process that selectively etches the protective layer 205 relative to the semiconductor body 100 and the high-k dielectric 32.

[0111] Referring to the above, the transistor device may include a current extension region 14 in the drift region 11, which helps to more evenly distribute the current (charge carriers) within the drift region 11, the current (charge carriers) being injected into the drift region 11 through the channel region along the gate dielectric 22. Forming the current extension region 14 may include an implantation process in which dopant atoms are implanted into the drift region 11 via the first surface 101, and an annealing process in which the implanted dopant atoms are activated. Alternatively, the current extension region 14 is formed in an epitaxial growth process during crystal growth of the semiconductor body 100.

[0112] Instead of or in addition to implanting dopant atoms via the first surface 101, dopant atoms may be implanted via the reference Fig.16A The bottom of the partial field electrode trench 33 ′ and the gate trench 23 formed in the explained process implants dopant atoms into the drift region 11 . Fig.19 An example of a process is illustrated in which dopant atoms are implanted in the drift region 11 via the bottom of the partial field electrode trenches 33' and the gate trenches 23. An implantation mask 206 formed on top of the first surface 101 protects the first surface 101 from implantation of dopant atoms therein.

[0113] Implanting dopant atoms forms an implantation region 14' below the bottom of the trenches 23, 33' in the drift region 11. By properly adjusting the implantation energy, the implantation region 14' can be formed adjacent to the trenches or can be formed spaced apart from the trenches 23, 33'. Forming the current extension region 14 based on the implantation region 14' includes an annealing process.

[0114] According to one example, as shown, dopant atoms are implanted only into the bottom of the trenches 23, 33'. In this example, several implantation regions 14' are formed, which are spaced apart from each other in the lateral direction of the semiconductor body 100. In SiC, there is no significant diffusion of the implanted dopant atoms during the annealing process. Therefore, in this example, the transistor device includes a plurality of current extension regions 14 spaced apart from each other in the lateral direction.

[0115] According to another example, a tilted implantation process is used to form the implantation regions 14'. In this example, the implantation regions 14' may be formed such that adjacent implantation regions 14' abut against each other. In this example, a continuous current extension region is formed after the annealing process.

[0116] Fig. 20One example of a method for forming field electrode trenches 33 that widen below gate trenches 23 is illustrated. Forming each of these trenches may include forming a portion of the trench using a conventional anisotropic etching process, covering the sidewalls of the first portion of the trench with a protective layer 207 and leaving the bottom of the trench uncovered by the protective layer 207, and performing an isotropic etching process that etches the trench deeper into the semiconductor body 100 in the vertical direction and in the lateral direction.

[0117] Fig.21 301 illustrates the voltage blocking capability of different transistor devices which are implemented in the same way and differ only in terms of the dielectric constant of the high-k dielectric 32 and the cell pitch p. For comparison reasons, curve 302 illustrates the voltage blocking capability as a function of the cell pitch p in a transistor device implemented with a low-k dielectric as field electrode dielectric. In this example, the low-k dielectric is silicon dioxide (SiO2) with a relative dielectric constant of 3.9. 2 ).

[0118] Curve 302 illustrates the voltage blocking capability depending on the cell pitch p in a transistor device implemented using a high-k dielectric 32 having a relative dielectric constant of 10, and curve 303 illustrates the voltage blocking capability in a transistor device implemented using a high-k dielectric 32 having a relative dielectric constant of 25.

[0119] If you can Fig.21 As can be seen, in each case, the voltage blocking capability decreases as the pitch p increases. Furthermore, the voltage blocking capability of the transistor device implemented with a low-k dielectric is significantly reduced below the voltage blocking capability of the transistor device with the same pitch but implemented with a high-k dielectric. In each case, the breakdown occurs below the field electrode trench 33.

[0120] Fig. 22 The diagram shows Fig.21 4. The magnitude of the electric field in the gate dielectric 22 depending on the cell pitch p for the same transistor device illustrated in FIG. 4. Curve 401 represents a transistor device implemented with a low-k dielectric, curve 402 represents a transistor device implemented with a high-k dielectric having a dielectric constant of K=10, and curve 403 represents a transistor device implemented with a high-k dielectric having a dielectric constant of K=25. As can be seen from Fig. 22 As can be seen, in each case, the electric field increases with increasing pitch p. Furthermore, at each pitch, the lower the dielectric constant, the higher the electric field.

[0121] Therefore, based on Fig.21 and Fig. 22 , we can see that according to Figure 1In the transistor device of and various modifications thereof explained herein, a high voltage blocking capability may be achieved by implementing transistor devices having field electrode structures 3 each including a field electrode 31 and a high-k dielectric 32 .

[0122] Fig.23 Shown according to Figure 1 In this example, each of the gate trenches 23 includes two different dielectrics, a gate dielectric 22 between the gate electrode 21 and portions of the body region 21, the source region 13, and the drift region 11, and a high-k dielectric 24 at the bottom of the gate trench 23 between the gate electrode 21 and the drift region 11. The high-k dielectric 24 is more robust than the gate dielectric 22 in view of high electric fields.

[0123] Some aspects of the transistor devices and methods explained above are briefly summarized below.

[0124] According to one example, a transistor device includes a semiconductor body and a plurality of transistor cells. Each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node; and a field electrode connected to a source node. The gate electrode is dielectrically insulated from the body region by a gate dielectric, and the gate electrode is arranged in a first trench extending from a first surface into the semiconductor body. The field electrode is dielectrically insulated from the drift region by a high-k dielectric, and the field electrode is arranged in a second trench. The second trench extends from the first surface into the semiconductor body and is spaced apart from the first trench, and the field electrode extends into the semiconductor body at least as deeply as the first trench.

[0125] The field electrode may extend deeper into the semiconductor body than the first trench. The field electrode may be dielectrically insulated from the body region and the source region by a high-k dielectric. The field electrode may be electrically connected to the body region and the source region in the second trench.

[0126] Each transistor cell may include a doped region of the same doping type as the body region, wherein the doped region adjoins the body region and the field electrode and extends along the high-k dielectric into the drift region.

[0127] The transistor device may further include a source electrode electrically connected to the body region, the source region and the field electrode of the plurality of transistor cells, wherein the source electrode is connected to a source node or forms a source node of the transistor device. The transistor device may further include a drain region, wherein each of the drift regions in the plurality of transistor cells is arranged between the drain region and the body region of the corresponding transistor cell.

[0128] Each transistor cell may comprise a current extension region in the drift region, wherein the current extension region is more highly doped than the rest of the drift region.

[0129] According to one example, the second trenches of the plurality of transistor cells are spaced apart from the drain region. According to another example, the second trenches of the plurality of transistor cells extend along the drift region into the drain region.

[0130] According to an example, the first trench is implemented such that in a region below the first trench arranged between two adjacent second trenches, a distance between adjacent second trenches is shorter than in a region of the first trenches.

[0131] The relative permittivity of the high-k dielectric may be higher than that of silicon dioxide. According to one example, the relative permittivity is higher than 5, higher than 10, or higher than 20.

[0132] According to an example, a dimension of the field electrode in the vertical direction of the semiconductor body is between 1.0 and 2.5 times the depth of the first trench. For example, a dimension of the field electrode in the vertical direction of the semiconductor body is between 0.8 micrometers and 2.5 micrometers. For example, a distance between adjacent second trenches is between 0.5 micrometers and 2 micrometers.

[0133] According to one example, the semiconductor body is a SiC semiconductor body.

[0134] According to another example, a method for forming a transistor device includes forming a plurality of transistor cells in a semiconductor body such that each transistor cell includes: a drift region, a body region, and a source region; a gate electrode connected to a gate node, the gate electrode being dielectrically insulated from the body region by a gate dielectric and being arranged in a first trench extending from a first surface into the semiconductor body; and a field electrode connected to the source node, the field electrode being dielectrically insulated from the drift region by a high-k dielectric and being arranged in a second trench extending from the first surface into the semiconductor body and spaced apart from the first trench. Forming the field electrode of each transistor cell includes forming the field electrode such that the field electrode extends deeper into the semiconductor body than the first trench.

[0135] According to an example, the field electrode is formed after forming the gate dielectric and the gate electrode.

Claims

1. A transistor device comprising a semiconductor body (100) and a plurality of transistor cells (1), wherein each transistor cell comprises: A drift region (11), a body region (12) and a source region (13); a gate electrode (21) connected to a gate node (G); as well as a field electrode (31), which is connected to the source node (S), wherein the gate electrode (21) is dielectrically insulated from the body region (12) by a gate dielectric (22), and the gate electrode (21) is arranged in a first trench (23) extending from the first surface (101) into the semiconductor body (100), wherein the field electrode (31) is dielectrically insulated from the drift region (11) by a high-k dielectric (32), and the field electrode (31) is arranged in the second trench (33), wherein the second trench (33) extends from the first surface (101) into the semiconductor body (100) and is spaced apart from the first trench (23), and The field electrode (31) extends at least as deep into the semiconductor body (100) as the first trench (23).

2. The transistor device according to claim 1, The field electrode (31) extends deeper into the semiconductor body (100) than the first trench (23).

3. The transistor device according to claim 1, The field electrode (31) is dielectrically insulated from the body region (12) and the source region (13) by a high-k dielectric (32).

4. The transistor device according to claim 1, The field electrode (31) is electrically connected to the body region (12) and the source region (13) in the second trench (33).

5. The transistor device according to claim 4, wherein each transistor cell (1) further comprises: a doping region (17) of the same doping type as the main region (12), The doped region (17) adjoins the body region (12) and the field electrode (31) and extends into the drift region (11) along the high-k dielectric (32).

6. The transistor device according to any one of the preceding claims, further comprising: a source electrode (41) electrically connected to the body region (12), the source region (13) and the field electrode (31) of the plurality of transistor cells, Wherein the source electrode (41) is connected to a source node (S) or forms a source node (S) of the transistor device.

7. The transistor device according to any one of the preceding claims, further comprising: a drain region (15), Each of the drift regions (11) in the plurality of transistor cells (1) is arranged between a drain region (15) and a body region (12) of the corresponding transistor cell (1).

8. The transistor device according to any one of the preceding claims, wherein each transistor cell (1) further comprises: A current spreading region (14) in the drift region (11), wherein the current spreading region (14) is more highly doped than the rest of the drift region (11).

9. A transistor device according to claim 7 or claim 8, The second trenches (33) of the plurality of transistor units (1) are spaced apart from the drain region (15).

10. A transistor device according to claim 7 or claim 8, The second trenches (33) of the plurality of transistor units (1) extend along the drift region (11) into the drain region (15).

11. A transistor device according to any one of the preceding claims, In a region below a first trench (23) arranged between two adjacent second trenches (33), the distance between adjacent second trenches (33) is shorter than in the region of the first trenches (23).

12. A transistor device according to any one of the preceding claims, wherein the relative permittivity of the high-k dielectric is higher than the relative permittivity of silicon dioxide.

13. The transistor device of claim 12, wherein the relative dielectric constant is higher than 5, higher than 10 or higher than 20.

14. The transistor device according to any one of claims 1 to 13, wherein a dimension (d3) of the field electrode (31) in a vertical direction (z) of the semiconductor body (100) is between 1.0 and 2.5 times the depth (d2) of the first trench (23).

15. The transistor device according to any one of claims 1 to 13, wherein a dimension (d3) of the field electrode (31) in a vertical direction (z) of the semiconductor body (100) is between 0.8 micrometers and 2.5 micrometers.

16. A transistor device according to any one of the preceding claims, wherein the distance between adjacent second trenches (33) is between 0.5 micrometers and 2 micrometers.

17. The transistor device according to any of the preceding claims, wherein the semiconductor body (100) is a SiC semiconductor body.

18. A method comprising: A plurality of transistor cells (1) are formed in a semiconductor body (100) such that each transistor cell comprises: A drift region (11), a body region (12) and a source region (13); a gate electrode (21) connected to a gate node (G), dielectrically insulated from the body region (12) by a gate dielectric (22), and arranged in a first trench (23) extending from the first surface (101) into the semiconductor body (100); and a field electrode (31), which is connected to the source node (S), is dielectrically insulated from the drift region (11) by a high-k dielectric (32), and is arranged in a second trench (33) extending from the first surface (101) into the semiconductor body (100) and is spaced apart from the first trench (23), Wherein forming the field electrode (31) of each transistor cell (1) comprises forming the field electrode (31) such that the field electrode (31) extends deeper into the semiconductor body (100) than the first trench (23).

19. The method according to claim 18, The field electrode (31) is formed after forming the gate dielectric (22) and the gate electrode (21).

Images