A JTE terminal structure for silicon carbide power devices and its fabrication method

Abstract

This invention provides a JTE termination structure for a silicon carbide power device and its fabrication method. The P-JTE region of the silicon carbide power device JTE termination structure is arranged in a stepped shape within the N- epitaxial layer, with its left side contacting the right surface of the P+ region. This invention significantly reduces the surface JTE concentration and creates an internal gradient of JTE charge by constructing a stepped multi-region JTE structure with an unconventional charge gradient. This structure can effectively reduce the peak electric field at the device surface while ensuring a wide dose injection window, avoiding additional leakage current at the surface, reducing the risk of premature breakdown at the surface, and improving the reverse breakdown voltage reliability of the device. Furthermore, this invention combines conventional injection and ballistic injection to achieve the desired JTE structure, avoiding the cumbersome steps of multiple epitaxial and injection processes in conventional manufacturing methods, thus reducing process costs and cycle time.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a silicon carbide power device JTE terminal structure and its fabrication method. Background Technology

[0002] With energy and environmental issues receiving increasing attention, society demands higher efficiency from power electronic systems and places higher requirements on the performance of power semiconductor devices. Today, silicon-based power devices are widely used in many fields. However, as silicon power device development nears maturity and the inherent material properties of silicon limit their performance to meet the growing demands of high-power applications, their performance is no longer sufficient. Compared to traditional silicon-based semiconductor materials, silicon carbide (SiC) materials, with their large bandgap, strong critical breakdown electric field, and high thermal conductivity, are particularly suitable for fabricating high-voltage, high-power power electronic devices.

[0003] In the fabrication of high-voltage SiC power devices, junction extension technology (JTE) structures are often used to extend the depletion region of the main junction, thereby alleviating the concentration of electric field at the edge of the main junction and thus improving and stabilizing the breakdown voltage. Compared with field limiting rings (FLRs), JTE terminations have advantages such as simple fabrication and high design size tolerance, and are widely used in the fabrication of high-voltage, especially ultra-high-voltage, SiC power devices. Generally, a single-concentration doped JTE (i.e., a single-region JTE) has a narrow figure-of-figure doping window to achieve a high breakdown voltage, making the device breakdown voltage extremely sensitive to interference from the SiC / SiO2 interface charge. Therefore, designers often adopt the multi-region effect concept to construct multi-region JTEs with varying lateral charge gradients to significantly improve the figure-of-figure window and solve the breakdown voltage transgression problem caused by interface charge. However, since most JTE terminations are "surface terminations," meaning the depletion region terminates at the surface of the SiC material, the presence of a high surface electric field often leads to the degradation of the device's breakdown characteristics and a decrease in the device's breakdown voltage stability.

[0004] Therefore, it is urgent to conduct design optimization research on the JTE structure of silicon carbide power devices to ensure the stability of the reverse blocking characteristics of the devices. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a silicon carbide power device JTE termination structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention provides a silicon carbide power device JTE termination structure comprising: a substrate 1, an N-epitaxial layer 2, a P-JTE region 3, a P+ region 4, a passivation layer 5, an anode 6, and a cathode 7;

[0007] In this configuration, the N-epitaxial layer 2 is disposed on the substrate 1, the P+ region 4 is disposed on one side of the N-epitaxial layer 2, the anode 6 is disposed on the P+ region 4, the passivation layer 5 is disposed on the N-epitaxial layer 2, the P-JTE region 3 is disposed in a stepped shape inside the N-epitaxial layer 2, and its left side is in contact with the right surface of the P+ region 4, its right side is not in contact with the inner surface of the N-epitaxial layer 2, its upper surface is in contact with the lower surface of the passivation layer 5, and the cathode 7 is disposed on the reverse side of the substrate 1.

[0008] Secondly, the present invention provides a method for fabricating a JTE termination structure for a silicon carbide power device, comprising:

[0009] S100, Obtain substrate 1, and generate N-epi-epi-layer 2 on substrate 1;

[0010] S200, a silicon dioxide layer is deposited on the N-epitaxial layer 2, and photoresist is spin-coated on the silicon dioxide layer and then one end of the silicon dioxide is etched away. Ion implantation is performed from top to bottom into the N-epitaxial layer 2 in the etched area to form a P+ region 4 at one end of the N-epitaxial layer 2.

[0011] S300, silicon dioxide is regrown at the etched end to re-form a silicon dioxide layer, and photoresist is spin-coated on both sides of the silicon dioxide layer. In the middle region, etching is performed from top to bottom until the upper surface of the N-epitaxial layer 2 is reached. From the upper surface, ion implantation with different energies is performed multiple times into the N-epitaxial layer 2 from top to bottom to form a P-JTE region 3 with multiple steps.

[0012] Among them, the injection junction depth of P-JTE region 3 is greater than that of P+ region 4;

[0013] S400, the silicon dioxide layer is etched away, and a passivation layer 5 is formed on the N-epitaxial layer 2 so that the passivation layer 5 covers part of the P+ region 4 and the upper surface of the N-epitaxial layer 2;

[0014] S500, an anode 6 is formed by covering an anode metal on the P+ region 4 and a cathode 7 is formed by covering a cathode metal on the reverse side of the substrate 1.

[0015] Beneficial effects:

[0016] 1. This invention introduces the electric field concentration point into the N-epitaxial layer, effectively reducing the surface peak electric field in the device terminal region, reducing the surface leakage current induced by the strong electric field under high reverse bias voltage, reducing the risk of premature breakdown of the device, and improving the reverse withstand voltage reliability of the device.

[0017] 2. The inverted JTE termination structure of this invention can broaden the figure of merit dose window, enhance process robustness, and improve the stability of reverse breakdown voltage of the device.

[0018] 3. From a manufacturing perspective, this invention can achieve the required JTE structure by combining conventional injection and ballistic injection, avoiding the cumbersome steps of multiple epitaxy and injection in conventional manufacturing methods, thus reducing process costs and cycle time.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the JTE terminal structure of a silicon carbide power device provided by the present invention;

[0021] Figures 2a-2i This is a schematic diagram of the process for fabricating a silicon carbide power device JTE terminal structure using the first ion implantation method provided by the present invention;

[0022] Figure 2j-Figure 2l This is a schematic diagram of the process for fabricating a JTE terminal structure for a silicon carbide power device using the second ion implantation method provided by the present invention;

[0023] Figure 3 This is an AI ion implantation concentration-implantation depth curve;

[0024] Figure 4 This is a schematic diagram of surface electric field intensity and location;

[0025] Figure 5 This is a schematic diagram of breakdown voltage-JTE dose. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0027] refer to Figure 1 As shown, the present invention provides a silicon carbide power device JTE termination structure comprising: a substrate 1, an N-epitaxial layer 2, a P-JTE region 3, a P+ region 4, a passivation layer 5, an anode 6, and a cathode 7;

[0028] In this configuration, the N-epitaxial layer 2 is disposed on the substrate 1, the P+ region 4 is disposed on one side of the N-epitaxial layer 2, the anode 6 is disposed on the P+ region 4, the passivation layer 5 is disposed on the N-epitaxial layer 2, the P-JTE region 3 is disposed in a stepped shape inside the N-epitaxial layer 2, and its left side is in contact with the right surface of the P+ region 4, its right side is not in contact with the inner surface of the N-epitaxial layer 2, its upper surface is in contact with the lower surface of the passivation layer 5, and the cathode 7 is disposed on the reverse side of the substrate 1.

[0029] In this design, substrate 1 is a silicon carbide substrate with N-type doping and nitrogen or phosphorus as the doping element; the concentration of the N-epitaxial layer 2 is 5 × 10⁻⁶. 13 cm-3 ~2×10 16 cm -3 The thickness ranges from 5 to 200 μm, and the doping element is nitrogen or phosphorus. The number of steps in P-JTE region 3 is n, with n ranging from 2 to 10. The depth d1 of the first step JTE ranges from 0.4 to 1.5 μm; the depth variation Δdi between adjacent steps from the second to the nth step ranges from 0.1 to 0.6 μm. In each step of P-JTE region 3, the JTE doping concentration is 1 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The doping element is aluminum.

[0030] It is worth noting that the depth change of adjacent steps can be a constant change or a variable change.

[0031] Combination Figures 2a to 2l This invention provides a method for fabricating a JTE terminal structure for a silicon carbide power device, comprising:

[0032] S100, Obtain substrate 1, and generate N-epi-epi-layer 2 on substrate 1;

[0033] S200, a silicon dioxide layer 103 is deposited on the N-epitaxial layer 2, and photoresist 104 is spin-coated on the silicon dioxide layer 103. Then, one end of the silicon dioxide is etched away, and ion implantation is performed from top to bottom into the N-epitaxial layer 2 in the etched area to form a P+ region 4 at one end of the N-epitaxial layer 2.

[0034] This invention introduces the electric field concentration point into the N-epitaxial layer, effectively reducing the surface peak electric field in the device terminal region, reducing surface leakage current induced by strong electric field under high reverse bias voltage, reducing the risk of premature breakdown of the device, and improving the reverse withstand voltage reliability of the device.

[0035] S300, silicon dioxide is regrown at the etched end to re-form a silicon dioxide layer, and photoresist is spin-coated on both sides of the silicon dioxide layer. In the middle region, etching is performed from top to bottom until the upper surface of the N-epitaxial layer 2 is reached. From the upper surface, ion implantation with different energies is performed multiple times into the N-epitaxial layer 2 from top to bottom to form a P-JTE region 3 with multiple steps.

[0036] In this invention, P-JTE region 3 is an inverted JTE termination structure. This inverted JTE termination structure widens the figure-of-fact dose window, enhances process robustness, and improves the stability of the device's reverse breakdown voltage. The dose range at the 3300V breakdown voltage target reaches 1.4 × 10⁻⁶. 13 cm -2 It is 7 times that of a single-region JTE and 0.4 × 10⁻⁶ higher than that of a traditional three-order JTE structure.13 cm -2 Meanwhile, a breakdown voltage closer to that of an ideal planar junction was achieved, with a maximum breakdown efficiency of 99%. This demonstrates that the inverted JTE is better compatible with breakdown voltage and process tolerance, and this structure is suitable for devices of any voltage level.

[0037] S400, the silicon dioxide layer is etched away, and a passivation layer 5 is formed on the N-epitaxial layer 2 so that the passivation layer 5 covers part of the P+ region 4 and the upper surface of the N-epitaxial layer 2;

[0038] S500, an anode 6 is formed by covering an anode metal on the P+ region 4 and a cathode 7 is formed by covering a cathode metal on the reverse side of the substrate 1.

[0039] This invention combines ballistic ion implantation with conventional ion implantation to construct a step-shaped multi-region JTE structure with an unconventional charge gradient, significantly reducing the surface JTE concentration and creating an internal JTE charge gradient. This structure effectively reduces the peak electric field at the device surface while maintaining a wide dose implantation window, avoiding additional leakage current at the surface, reducing the risk of premature breakdown at the surface, and improving the reverse breakdown voltage reliability of the device. Furthermore, from a manufacturing perspective, this invention combines conventional and ballistic implantation to achieve the desired JTE structure, avoiding the cumbersome steps of multiple epitaxial and implantation processes in conventional manufacturing methods, thus reducing process costs and time.

[0040] In an optional embodiment of the present invention, S200 includes:

[0041] S210, a silicon dioxide layer 103 is deposited on the N-epitaxial layer 2, such as Figure 2a As shown;

[0042] S220, spin-coating photoresist 104 onto silicon dioxide layer 103, such as Figure 2b As shown, one end of the silicon dioxide is then etched away to form the first ion implantation mask layer, as shown. Figure 2c As shown;

[0043] S230, Al ions are implanted into the N-epitaxial layer 2 from top to bottom in the etched area to form a P+ region 4 at one end of the N-epitaxial layer 2, such as... Figure 2d As shown; the Al ion implantation energy ranges from 10 keV to 800 keV;

[0044] S240, the first ion implantation mask layer is cleaned out.

[0045] In an optional embodiment of the present invention, S300 includes:

[0046] S310, silicon dioxide is regrown at the etched end to re-form a silicon dioxide layer 103;

[0047] S320, photoresist 106 is spin-coated on both sides of the newly formed silicon dioxide layer 103, as follows: Figure 2e As shown, the opening is achieved through photolithography and dry etching, followed by etching from top to bottom in the middle region until the upper surface of the N-epitaxial layer 2 is reached to form a second ion implantation mask layer. Figure 2f As shown, in the area etched in the middle, ion implantation with different energies is performed multiple times from top to bottom into the N-epitaxial layer 2 using two ion implantation methods, thereby forming a P-JTE region 3 in the N-epitaxial layer 2 where the JTE charge in the step changes from top to bottom or from left to right.

[0048] In one optional embodiment of the present invention, the first ion implantation method in S320 includes:

[0049] S321a, Al ion implantation was performed on JTE 1-3 at an implantation tilt angle of -4° and an energy of 500keV-800keV to form the bottom terminal region 107, as shown. Figure 2g As shown; cleaning removes the second ion implantation mask layer;

[0050] S322a, a third ion implantation mask layer is prepared on the surface of the N-epitaxial layer 2, and Al ion implantation is performed on JTE 1-2 at an implantation tilt angle of -4° and an energy of 300keV-500keV to form the intermediate layer terminal region 108, as shown. Figure 2h As shown;

[0051] S323a, the third ion implantation mask layer is cleaned and removed. A fourth ion implantation mask layer is then prepared on the surface of the N-epitaxial layer 2. Al ion implantation is performed on JTE 1 at an implantation tilt angle of -4° and an energy of 100keV to 300keV, and at an implantation tilt angle of 0° and an energy of 10keV to 100keV, respectively, ultimately forming the uppermost terminal region, as shown below. Figure 2i As shown;

[0052] It is worth noting that: an injection angle of -4° is ballistic injection, and an injection angle of 0° is conventional injection.

[0053] S324a, clean and remove the fourth ion implantation mask layer, and use high temperature annealing to activate the implanted ions to form a P-JTE region 3 in the N-epipolar layer 2 where the JTE charge changes from top to bottom within the step;

[0054] Among them, the bottommost terminal region, the middle terminal region, and the topmost terminal region form the P-JTE region 3 in which the JTE charge changes from top to bottom within the step.

[0055] In an optional embodiment of the present invention, the second ion implantation method in S320 includes:

[0056] S321b, the JTE 1 region was subjected to four ion implantations at high, medium, and low energies of 500keV–800keV, 300keV–500keV, 100keV–300keV, and 10keV–100keV respectively to form the leftmost terminal region 111, as shown. Figure 2j As shown; cleaning removes the second ion implantation mask layer;

[0057] S322b, a third ion implantation mask layer is prepared on the surface of N-epitaxial layer 2, and then JTE 2 is subjected to two ion implantations at medium and high energies of 500keV-800keV and 300keV-500keV to form an intermediate terminal region, as shown. Figure 2k As shown; cleaning removes the third ion implantation mask layer;

[0058] S323b, a fourth ion implantation mask layer is prepared on the surface of N-epitaxial layer 2. Finally, JTE 3 is subjected to a high-energy ion implantation of 500keV~800keV to form the rightmost terminal region, as shown. Figure 2l As shown;

[0059] S324b, clean and remove the fourth ion implantation mask layer, and use high temperature annealing to activate the implanted ions to form a P-JTE region 3 in the N-epipolar layer 2 where the JTE charge changes from left to right within the step;

[0060] Among them, the leftmost terminal region, the middle terminal region, and the rightmost terminal region form the P-JTE region 3 in which the JTE charge changes from left to right within the step.

[0061] It is worth noting that although the two ion implantation methods are different, the JTE charge on the steps in the P-JTE region 3 formed is highest on the leftmost side when viewed from left to right, and also highest on the bottom layer when viewed from bottom to top. This makes the P-JTE region 3 of the present invention different from the existing structure, presenting a structure with inverted JTE charge.

[0062] In an optional embodiment of the present invention, S500 includes:

[0063] S510, Ti, Ni or Al metal is deposited on P+ region 4 by magnetron sputtering or electron beam evaporation to form anode 6, and then rapid thermal annealing (RTA) is used to form ohmic contact;

[0064] S520, Ni metal is deposited on the reverse side of substrate 1 by magnetron sputtering or electron beam evaporation to form cathode 7, and then rapid thermal annealing (RTA) is used to form ohmic contacts.

[0065] This invention provides a JTE termination structure for a silicon carbide power device and its fabrication method. The JTE termination structure includes a substrate, an N-epitaxial layer, a P-JTE region, a P+ region, a passivation layer, an anode, and a cathode. The P-JTE region is arranged in a stepped shape within the N-epitaxial layer, with its left side contacting the right surface of the P+ region. This invention significantly reduces the surface JTE concentration and creates an internal gradient of JTE charge by constructing a stepped multi-region JTE structure with an unconventional charge gradient. This structure can effectively reduce the peak electric field on the device surface while ensuring a wide dose injection window, avoiding additional leakage current at the surface, reducing the risk of premature breakdown at the surface, and improving the reverse breakdown voltage reliability of the device. Furthermore, this invention combines conventional injection and ballistic injection to achieve the desired JTE structure, avoiding the cumbersome steps of multiple epitaxial and injection processes in conventional manufacturing methods, thus reducing process costs and cycle time.

[0066] The advantages of the structure of this invention are illustrated below through experimental results.

[0067] refer to Figure 3 , Figure 3 The JTE1 doping concentration is 7.5 × 10⁻⁶. 16 cm -3 The JTE2 doping concentration is 7.2 × 10⁻⁶. 16 cm -3 The JTE3 doping concentration is 4.5 × 10⁻⁶. 16 cm -3 AI ion implantation concentration-implantation depth curve at that time. Figure 3 The vertical axis represents the AI ​​ion implantation concentration, and the horizontal axis represents the implantation depth. Figure 3 It is known that the structure of the present invention achieves a JTE structure opposite to the traditional third-order JTE by implanting Al ions with four groups of different energies / doses / tilts, with the Gaussian peak concentration position (i.e. step edge) being 0.8 μm at the maximum implantation energy of 700 keV. The d1, d2, and d3 are 0.8, 0.4, and 0.2 μm, respectively.

[0068] refer to Figure 4 , Figure 4 This is a schematic diagram of the surface electric field intensity and its location. Figure 4 The horizontal axis represents the electric field position, and the vertical axis represents the surface electric field intensity. Figure 4 As can be seen from the surface electric field intensity-location, compared with the traditional third-order JTE, the inverted JTE structure reduces the maximum surface peak electric field intensity by 24%. The low surface electric field can avoid additional leakage current at the surface, reduce the risk of hard breakdown of the device at the surface, and improve the breakdown application reliability of the device.

[0069] refer to Figure 5 , Figure 5This is a schematic diagram of breakdown voltage-JTE dose. Figure 5 The horizontal axis represents the JTE dose, and the vertical axis represents the breakdown voltage. From Figure 5 As can be seen from this, the merit dose window for single-region JTE is only about 0.2 × 10⁻⁶. 13 cm -2 The proposed inverted JTE terminal structure can broaden the figure of merit dose window, achieving a dose range of 1.4 × 10⁻⁶ at a target withstand voltage of 3300 V. 13 cm -2 It is 7 times that of a single-zone JTE, and 0.4 × 10⁻⁶ higher than that of a traditional three-order JTE structure. 13 cm -2 It can be seen that the proposed inverted JTE structure is an effective termination technology that is compatible with breakdown voltage and process tolerance.

[0070] It is worth noting that the terms "first" and "second" in this invention are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0071] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A JTE termination structure for a silicon carbide power device, characterized in that, include: Substrate (1), N-epitaxial layer (2), P-JTE region (3), P+ region (4), passivation layer (5), anode (6) and cathode (7); The N-epitaxial layer (2) is disposed on the substrate (1), the P+ region (4) is disposed on one side of the N-epitaxial layer (2), the anode (6) is disposed on the P+ region (4), the passivation layer (5) is disposed on the N-epitaxial layer (2), the anode (6) is disposed on the P+ region (4), the P-JTE region (3) is disposed in a stepped shape inside the N-epitaxial layer (2), and its left side contacts the right surface of the P+ region (4), its right side does not contact the upper surface of the N-epitaxial layer (2), and its upper surface contacts the lower surface of the passivation layer (5). The cathode (7) is disposed on the reverse side of the substrate (1). The number of steps in the P-JTE region (3) is n, and the value of n is in the range of 2 to 10. The depth of the first step JTE is... d The value of 1 ranges from 0.4 to 1.5 μm; the value of Δdi, the depth change between adjacent steps from the second step to the nth step, ranges from 0.1 to 0.6 μm; the depth of the first step JTE is greater than the depth of the P+ region (4), and the bottom surfaces of the first step JTE to the nth step JTE are flush.

2. The JTE termination structure for silicon carbide power devices according to claim 1, characterized in that, The substrate (1) is a silicon carbide substrate, doped with N-type, and the doping element is nitrogen or phosphorus; the concentration of the N-epitaxial layer (2) is 5×10⁻⁶. 13 cm -3 ~2×10 16 cm -3 The thickness is 5~200um, and the doping element is nitrogen or phosphorus.

3. The JTE termination structure for silicon carbide power devices according to claim 1, characterized in that, In each step of the P-JTE region (3), the JTE doping concentration is 1×10⁻⁶. 16 cm -3 ~1×10 18 cm -3 The doping element is aluminum.

4. A method for fabricating a JTE termination structure for a silicon carbide power device, characterized in that, The method for fabricating the JTE termination structure of the silicon carbide power device as described in any one of claims 1 to 3 includes: S100, Obtain a substrate (1) and generate an N-epitaxial layer (2) on the substrate (1). S200, a silicon dioxide layer is deposited on the N-epipolar layer (2), and photoresist is spin-coated on the silicon dioxide layer and then one end of the silicon dioxide is etched away. Ion implantation is performed from top to bottom into the N-epipolar layer (2) in the etched area to form a P+ region (4) at one end of the N-epipolar layer (2). S300, silicon dioxide is regrown at the etched end to re-form a silicon dioxide layer, and photoresist is spin-coated on both sides of the silicon dioxide layer. In the middle region, etching is performed from top to bottom until the upper surface of the N-epitaxial layer (2) is reached. From the upper surface, ion implantation with different energies is performed multiple times into the N-epitaxial layer (2) to form a P-JTE region (3) with multiple steps. The injection junction depth of the P-JTE region (3) is greater than that of the P+ region (4); S400, etch away the silicon dioxide layer and form a passivation layer (5) on the N-epitaxial layer (2) so that the passivation layer (5) covers a portion of the P+ region (4) and the upper surface of the N-epitaxial layer (2); S500, an anode (6) is formed by covering an anode metal on the P+ region (4) and a cathode (7) is formed by covering a cathode metal on the reverse side of the substrate (1).

5. The method for fabricating the JTE terminal structure of the silicon carbide power device according to claim 4, characterized in that, S200 includes: S210, a silicon dioxide layer is deposited on the N-epitaxial layer (2); S220, spin-coating photoresist onto the silicon dioxide layer and then etching away one end of the silicon dioxide to form a first ion implantation mask layer; S230, Al ions are implanted into the N-epitaxial layer (2) from top to bottom in the etched area to form a P+ region (4) at one end of the N-epitaxial layer (2); wherein the Al ion implantation energy is 10keV to 800keV; S240, the first ion implantation mask layer is cleaned out.

6. The method for fabricating the JTE terminal structure of the silicon carbide power device according to claim 4, characterized in that, The S300 includes: S310, regrowing silicon dioxide at the etched end to re-form a silicon dioxide layer. S320, spin-coat photoresist on both sides of the newly formed silicon dioxide layer, and then etch from top to bottom in the middle region until the upper surface of the N-epitaxial layer (2) is reached to form a second ion implantation mask layer; in the middle etched area, ion implantation with different energies is performed multiple times from top to bottom into the N-epitaxial layer (2) using two ion implantation methods, thereby forming a P-JTE region (3) in the N-epitaxial layer (2) where the JTE charge changes from top to bottom within the step.

7. The method for fabricating the JTE termination structure of the silicon carbide power device according to claim 6, characterized in that, The first ion implantation method in S320 includes: S321a, Al ion implantation was performed on JTE 1~3 at an implantation tilt angle of -4° and an energy of 500keV~800keV to form the bottom terminal region; the second ion implantation mask layer was removed by cleaning. S322a, a third ion implantation mask layer is prepared on the surface of the N-epipolar layer (2), and Al ion implantation is performed on JTE 1~2 at an implantation tilt angle of -4° and an energy of 300keV~500keV to form an intermediate layer terminal region; S323a, clean and remove the third ion implantation mask layer, prepare the fourth ion implantation mask layer on the surface of the N-epipolar layer (2), and perform Al ion implantation on JTE 1 at an implantation tilt angle of -4° and an energy of 100keV~300keV and an implantation tilt angle of 0° and an energy of 10keV~100keV respectively, and finally form the uppermost terminal region; S324a, clean and remove the fourth ion implantation mask layer, and use high temperature annealing to activate the implanted ions to form a P-JTE region (3) in the N-epipolar layer (2) where the ion energy changes from top to bottom. Among them, the bottommost terminal region, the middle terminal region and the topmost terminal region form a P-JTE region (3) in which the JTE charge changes from top to bottom within the step.

8. The method for fabricating the JTE termination structure of the silicon carbide power device according to claim 6, characterized in that, The second ion implantation method in S320 includes: S321b, the JTE 1 region was subjected to four ion implantations at high, medium and low energies of 500keV~800keV, 300keV~500keV, 100keV~300keV and 10keV~100keV respectively to form the leftmost terminal region; the second ion implantation mask layer was removed by cleaning. S322b, a third ion implantation mask layer is prepared on the surface of the N-epitaxial layer (2), and then JTE 2 is ion implanted twice with medium and high energies of 500keV~800keV and 300keV~500keV to form an intermediate terminal region; the third ion implantation mask layer is then cleaned and removed; S323b, a fourth ion implantation mask layer is prepared on the surface of the N-epitaxial layer (2), and finally, JTE 3 is ion implanted once with a high energy of 500keV~800keV to form the rightmost terminal region; S324b, clean and remove the fourth ion implantation mask layer, and use high temperature annealing to activate the implanted ions to form a P-JTE region (3) in the N-epipolar layer (2) where the JTE charge changes from left to right within the step. Among them, the leftmost terminal region, the middle terminal region and the rightmost terminal region form a P-JTE region (3) in which the JTE charge changes from left to right within the step.

9. The method for fabricating the JTE terminal structure of the silicon carbide power device according to claim 4, characterized in that, The S500 includes: S510, Ti or Ni or Al metal is deposited on the P+ region (4) by magnetron sputtering or electron beam evaporation to form an anode (6), and then rapid thermal annealing (RTA) is used to form an ohmic contact; S520, Ni metal is deposited on the reverse side of the substrate (1) by magnetron sputtering or electron beam evaporation to form a cathode (7), and then rapid thermal annealing (RTA) is used to form an ohmic contact.

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