Method of forming semiconductor device

Abstract

A method of forming a metal gate structure of a stacked multi-gate device is provided. A method according to an embodiment of the present disclosure includes: depositing a titanium nitride (TiN) layer over a channel region including a bottom channel layer and a top channel layer; depositing a dummy filling layer to cover the side wall of the bottom channel layer; after depositing the dummy filling layer, selectively forming a barrier layer above the TiN layer along the side wall of the top channel layer; selectively removing the dummy filling layer to release the bottom channel layer; selectively depositing a first work function metal layer to wrap each of the bottom channel layers; forming a gate isolation layer over the top surface of the first work function metal layer; removing the barrier layer; releasing the top channel layer; and selectively depositing a second work function metal layer to wrap each of the top channel layers. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as IC technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, and multi-gate devices have become popular and promising candidate devices for high-performance and low-leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the top and sidewalls of the "fin" extending from the substrate of the gate wrapping semiconductor material). MBC transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on both sides or multiple sides. Because its gate structure surrounds the channel region, MBC transistors can also be referred to as gate-around transistors (SGTs) or full-ring gate (GAA) transistors. The channel region of an MBC transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives the MBC transistor alternative names, such as nanosheet transistor or nanowire transistor.

[0004] As the semiconductor industry further develops to sub-10 nanometer (nm) technology process nodes pursuing higher device density, higher performance and lower cost, challenges from manufacturing and design issues have led to stacked device structure configurations, such as complementary field effect transistors (C-FETs), in which n-type multi-gate transistors and p-type multi-gate transistors are vertically stacked one above the other. N-type multi-gate transistors and p-type multi-gate transistors may require different work function metal layers. It may be challenging to selectively form the work function layer type without causing undesirable damage to surrounding structures. Therefore, although existing gate formation processes for stacked devices are generally sufficient to meet their intended purposes, they are not satisfactory in all aspects. Summary of the invention

[0005] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: depositing a titanium nitride (TiN) layer over a channel region including a bottom channel layer and a top channel layer above the bottom channel layer; depositing a dummy filling layer to cover the sidewalls of the bottom channel layer; after depositing the dummy filling layer, selectively forming a barrier layer over the titanium nitride layer along the sidewalls of the top channel layer; selectively removing the dummy filling layer to release the bottom channel layer; selectively depositing a first work function metal layer to wrap each of the bottom channel layers; forming a gate isolation layer above a top surface of the first work function metal layer; removing the barrier layer; releasing the top channel layer; and selectively depositing a second work function metal layer to wrap each of the top channel layers.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: receiving a workpiece, the workpiece comprising: a substrate; a fin rising from the substrate; a bottom channel member disposed above the fin; an intermediate dielectric layer disposed above the bottom channel member; a top channel member disposed above the intermediate dielectric layer; a gate dielectric layer disposed above the surface of the bottom channel member and the top channel member; a first plurality of plug layers interlaced with the bottom channel member; and a second plurality of plug layers interlaced with the top channel member; depositing a titanium-containing dielectric layer on the sidewalls of the bottom channel member, the sidewalls of the first plurality of plug layers, the sidewalls of the intermediate dielectric layer, the sidewalls of the bottom channel member, and the sidewalls of the second plurality of plug layers. layer; depositing a dummy filling layer over the workpiece so that the top surface of the dummy filling layer is substantially coplanar with the bottom surface of the intermediate dielectric layer; after depositing the dummy filling layer, selectively forming a barrier layer over the titanium-containing layer along the sidewalls of the top channel component; selectively removing the dummy filling layer, the titanium-containing layer not covered by the barrier layer, and the first plurality of plug layers to release the bottom channel component; selectively depositing a first work function metal layer to wrap each of the bottom channel components; forming a gate isolation layer over the top surface of the first work function metal layer; removing the barrier layer; selectively removing the second plurality of plug layers to release the top channel component; and selectively depositing a second work function metal layer to wrap each of the top channel components.

[0007] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: depositing a titanium-containing layer over a channel region including a bottom channel member and a top channel member over the bottom channel member; forming a top hard mask on a top surface of the titanium-containing layer; after forming the top hard mask, depositing a first dummy-filling layer to cover the titanium-containing layer along the sidewalls of the bottom channel member; after depositing the first dummy-filling layer, selectively forming a barrier layer to cover the titanium-containing layer along the sidewalls of the top channel member; selectively removing the first dummy-filling layer to release the bottom channel member; selectively depositing a first work function metal layer to wrap each of the bottom channel members; after selectively depositing the first work function metal layer, forming a gate isolation layer over the first work function metal layer and the top hard mask; after forming the gate isolation layer, removing the top hard mask; removing the barrier layer; releasing the top channel member; and selectively depositing a second work function metal layer to wrap each of the top channel members. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart of a method 100 for forming a gate structure of a C-FET device according to one or more aspects of an embodiment of the present disclosure is shown.

[0010] Figures 2 to 21 According to one or more aspects of the present disclosure, Figure 1 A partial cross-sectional view of a workpiece undergoing various manufacturing processes in a method.

[0011] Fig. 22 It shows that one or more aspects of the embodiments of the present disclosure can be used with Figure 1 Exemplary self-assembly precursors for use in method 100.

[0012] Fig.23 The mechanism for binding of a self-assembled precursor to a titanium-containing surface according to one or more aspects of an embodiment of the present disclosure is schematically illustrated. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to limit the disclosed embodiments. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0014] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, when "about," "approximately," etc. are used to describe a value or a range of values, as understood by one of ordinary skill in the art, the terms are intended to include values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the value, the value or range of values ​​encompasses a reasonable range that includes the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing material layers known to one of ordinary skill in the art is + / - 15%.

[0016] A stacked multi-gate device refers to a semiconductor device comprising a bottom multi-gate device and a top multi-gate device stacked above the bottom multi-gate device. When the bottom multi-gate device and the top multi-gate device have different conductivity types, the stacked multi-gate device can be a complementary field effect transistor (C-FET). The multi-gate device in the C-FET can be a FinFET or a nanosheet / nanowire transistor. In order to optimize the threshold voltage of the bottom multi-gate device and the top multi-gate device, different work function metal layers are deposited around the bottom active area of ​​the bottom multi-gate device and the top active area of ​​the top multi-gate device. When the surface of the top active area is substantially free of the first work function metal layer, it may be challenging to selectively deposit the first work function metal layer above the bottom active area.

[0017] The disclosed embodiment provides a method for forming different work function metal layers to join the active area of ​​a stacked multi-gate device. In an exemplary embodiment of a stacked multi-gate device including a nanosheet / nanowire transistor, a gate dielectric layer is deposited above the surface of a bottom channel member and a top channel member. A first plurality of dielectric plug layers are formed to plug the intervals between the bottom channel members, and a second plurality of dielectric plug layers are formed to plug the intervals between the top channel members. A titanium-containing dummy pad is formed above the sidewalls of the bottom channel member, the first plurality of dielectric plug layers, the second plurality of dielectric plug layers, and the top channel member. A dummy filling layer is formed to cover the dummy pad above the bottom channel member. A self-assembled precursor is then used to form a barrier layer above the dummy pad not covered by the dummy filling layer. The self-assembled precursor is configured to bond to titanium on the dummy pad so that the barrier layer is formed only on the surface of the dummy pad. After selectively removing the dummy filling layer and the first plurality of dielectric plug layers, the bottom channel member is released. In the case where the barrier layer covers the dummy pad, a first work function metal layer is selectively deposited to wrap the bottom channel member. The use of the barrier layer reduces or eliminates the need to etch back excess first work function metal layer over the top channel component. Subsequently, a second work function metal layer is deposited to wrap around the top channel component.

[0018] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 for forming a semiconductor device according to various aspects of an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the embodiments of the present disclosure to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 21 Describing method 100, Figures 2 to 21 1 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages according to an embodiment of the method 100. Because the workpiece 200 will be manufactured into a semiconductor device 200 at the end of the manufacturing process, the workpiece 200 may be referred to as a semiconductor device 200 as the context requires. In addition, throughout the present application and across different embodiments, the same reference numerals represent the same components having the same structure and composition unless otherwise specified. The source / drain region may refer to a source or a drain, individually or collectively depending on the context.

[0019] refer to Figure 1 and Figure 2, method 100 includes block 102, wherein a superlattice structure 204 is formed over a substrate 202. In an embodiment, substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include a buried insulating layer, such as a buried silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Although not explicitly shown in the figures, substrate 202 may include an n-type well region and a p-type well region for fabricating transistors of different conductivity types. When present, each of the n-type well and the p-type well is formed in substrate 202 and includes a doping profile. The n-type well may include a doping profile of an n-type dopant, such as phosphorus (P) or arsenic (As). The p-type well may include a doping profile of a p-type dopant, such as boron (B). The doping in the n-type well and the p-type well may be formed using ion implantation or thermal diffusion and may be considered part of substrate 202. For ease of reference, substrate 202 and structures formed thereon during method 100 may be referred to as workpiece 200.

[0020] In addition to the substrate 202, the workpiece 200 also includes a bottom silicon layer 208B above the substrate 202. In frame 102, the bottom silicon layer 208B and the superlattice structure 204 are deposited on the substrate 202 using an epitaxial process. Suitable epitaxial processes include vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The superlattice structure 204 includes a plurality of channel layers 208 interlaced with a plurality of sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 may have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si) and the sacrificial layers 206 are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layer 206 allows the sacrificial layer 206 to be selectively removed or recessed without substantially damaging the channel layers 208. The sacrificial layers 206 and the channel layers 208 are alternately deposited one after another to form the superlattice structure 204 .

[0021] The channel layer 208 in the bottom portion of the superlattice structure 204 will provide a channel member for the bottom nanosheet / nanowire transistor, and the channel layer 208 in the top portion of the superlattice structure 204 will provide a channel member for the top nanosheet / nanowire transistor. The term "channel member" is used herein to represent any material portion of a channel having nanoscale dimensions and having an elongated shape in a transistor, regardless of the cross-sectional shape of the portion. The channel member can be in the form of a nanowire, nanosheet, or other nanostructure, and can have a circular, elliptical, racetrack-shaped, rectangular, or square cross-section. For ease of reference, the superlattice structure 204 can be vertically divided into a bottom portion 204B and a top portion 204T above the bottom portion 204B, wherein the intermediate sacrificial layer 206M is sandwiched in the middle. The intermediate sacrificial layer 206M and the other sacrificial layers can have different germanium contents. In some embodiments, the germanium content of the intermediate sacrificial layer 206M can be greater than the germanium content of the other sacrificial layers 206, so that the entire intermediate sacrificial layer 206M can be selectively removed during the formation of the internal spacer groove.

[0022] It should be pointed out that Figure 2 The superlattice structure 204 in includes six (6) layers of channel layers 208 interlaced with six (6) layers of sacrificial layers 206 (including middle sacrificial layer 206M), which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of channel layers 208 may be included in the superlattice structure 204 and distributed between the bottom portion and the top portion 204T. The number of layers depends on the desired number of channel members for the top nanosheet / nanowire transistor and the bottom nanosheet / nanowire transistor. In some embodiments, the number of channel layers 208 in the superlattice structure 204 can be between 4 and 10. The thickness of the channel layers 208 and the sacrificial layers 206 can be selected based on device performance considerations of the bottom nanosheet / nanowire transistor, the top nanosheet / nanowire transistor, and the C-FET as a whole.

[0023] refer to Figure 1 and Figure 3 , the method 100 includes a block 104, where a fin structure 210 is formed from a portion of the superlattice structure 204 and the substrate 202. In some embodiments, the superlattice structure 204, the bottom silicon layer 208B, and the portion of the substrate 202 are patterned to form the fin structure 210. For patterning purposes, a hard mask layer may be deposited over the superlattice structure 204. The hard mask layer may be a single layer or multiple layers. In one example, the hard mask layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. Figure 3As shown in , the fin structure 210 extends vertically from the substrate 202 in the Z direction and extends longitudinally in the Y direction. The fin structure 210 can be patterned using a suitable process including a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines lithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is smaller than that obtainable using a single, direct lithography process. For example, in one embodiment, a material layer is formed above the substrate and patterned using a lithography process. Spacers are formed next to the patterned material layer using a self-alignment process. The material layer is then removed, and then the remaining spacers or mandrels can be used as an etching mask to etch the superlattice structure 204, the bottom silicon layer 208B, and the substrate 202 to form the fin structure 210. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0024] Although in Figure 3 It is not explicitly shown, but after the fin structure 210 is formed, an isolation feature 212 is formed around the fin structure 210 to separate the fin structure 210 from an adjacent fin structure 210. The isolation feature 212 may also be referred to as a shallow trench isolation (STI) feature 212. In an exemplary process, a dielectric material for the isolation feature is deposited over the workpiece 200 (including the fin structure 210) using CVD, sub-atmospheric pressure CVD (SACVD), flowable CVD (FCVD), spin coating, and / or other suitable processes. Then, the deposited dielectric material is planarized and recessed to form the isolation feature 212. As shown in FIG. Figure 3 As shown in , the fin-shaped structure rises above the isolation feature 212. The dielectric material used for the isolation feature may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. Figure 3 In the embodiment shown in , the isolation features 212 completely cover the sidewalls of the fin structure 210 and only cover a portion of the sidewalls of the bottom silicon layer 208B of the fin structure 210 .

[0025] refer to Figure 1 and Figure 4, the method 100 includes a frame 106, in which a dummy gate stack 214 is formed above the channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or a gate-last process) is used, in which the dummy gate stack 214 is used as a reserved position for a functional gate structure. Other processes and configurations are also possible. In order to form the dummy gate stack 214, a dummy dielectric layer 213, a dummy gate electrode layer 215, and a gate top hard mask layer 217 are deposited above the workpiece 200. The deposition of these layers may include the use of low pressure CVD (LPCVD), CVD, plasma enhanced CVD (PECVD), PVD, ALD, thermal oxidation, electron beam evaporation or other suitable deposition techniques or combinations thereof. The dummy dielectric layer 213 may include silicon oxide, the dummy gate electrode layer 215 may include polysilicon, and the gate top hard mask layer 217 may be a multilayer including silicon oxide and silicon nitride. Using photolithography and etching processes, the gate top hard mask layer 217 is patterned. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. The etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. Like the fin structure 210, the dummy gate stack 214 may also be patterned using double patterning or multiple patterning techniques. Thereafter, the patterned gate top hard mask 217 is used as an etching mask, and then the dummy dielectric layer 213 and the dummy gate electrode layer 215 are etched to form the dummy gate stack 214. The dummy gate stack 214 extends longitudinally in the X direction to wrap over the fin structure 210 and is bonded to the isolation feature 212. The portion of the fin structure 210 located below the dummy gate stack 214 defines the channel region 210C. The channel region 210C and the dummy gate stack 214 also define a source / drain region 210SD that does not vertically overlap the dummy gate stack 214. The channel region 210C is disposed between the two source / drain regions 210SD along the Y direction.

[0026] refer to Figure 1 and Figure 4, the method 100 includes a frame 108, in which the source / drain region 210SD of the fin structure 210 is recessed to form a source / drain recess. The operation in frame 108 may include forming at least one gate spacer layer 216 above the sidewall of the dummy gate stack 214 before recessing the source / drain region 210SD. In some embodiments, forming at least one gate spacer layer 216 includes depositing one or more dielectric layers above the workpiece 200. In an exemplary process, one or more dielectric layers are conformally deposited using CVD, SACVD, or ALD. The one or more dielectric layers may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, and / or a combination thereof. After depositing at least one gate spacer layer 216, the workpiece 200 is etched in an anisotropic etching process to form a source / drain recess above the source / drain region 210SD. The etching process in frame 108 may be a dry etching process or a suitable etching process. The exemplary dry etching process may be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, NF3, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gas and / or plasma and / or a combination thereof. The sidewalls of the sacrificial layer 206 and the channel layer 208 in the channel region 210C are exposed in the source / drain recesses.

[0027] refer to Figure 1 and Figure 4, the method 100 includes a block 110, in which an inner spacer feature 218 is formed. In block 110, the sacrificial layer 206 exposed in the source / drain recess is selectively and partially recessed to form the inner spacer recess, while the exposed channel layer 208 is substantially not etched. The intermediate sacrificial layer 206M may be completely removed during the formation of the inner spacer recess (due to its large germanium content). In an embodiment where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 may include a SiGe oxidation process and subsequent SiGe oxide removal. In this embodiment, the SiGe oxidation process may include the use of ozone (O3). In some other embodiments, the selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the extent to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. The selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process may include using hydrogen fluoride (HF) or ammonium hydroxide (NH4OH). After forming the inner spacer recess, an inner spacer material layer is deposited over the workpiece 200 (including in the inner spacer recess). In addition, as Figure 4 As shown in , an inner spacer material layer may also be deposited in the space left by selectively removing the middle sacrificial layer 206M. The inner spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. The deposited inner spacer material layer is then etched back to remove excess inner spacer material layer above the sidewalls of the gate spacer layer and the channel layer 208, thereby forming an inner spacer feature 218 and an intermediate dielectric layer 220, as shown in FIG. Figure 4 In some embodiments, the etch-back process in block 110 may be a dry etch process, which includes using oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I), other suitable gases and / or plasma and / or combinations thereof.

[0028] refer to Figure 1 and Figure 4, the method 100 includes block 112, in which a source / drain feature 224 is formed over the source / drain region 210SD. The operations in block 112 may include: depositing a bottom source / drain feature 224B; depositing a bottom contact etch stop layer (CESL) 226 and a bottom interlayer dielectric (ILD) 228; depositing an etch stop layer (ESL) over the bottom CESL 226 and the bottom ILD layer 228; depositing a top source / drain feature 224T; and depositing a top CESL and a top ILD layer. For ease of reference, the bottom source / drain feature 224B and the top source / drain feature 224T may be collectively referred to as the source / drain feature 224.

[0029] The bottom source / drain feature 224B is formed above the source / drain region 210SD. Before depositing the bottom source / drain feature 224B, a sidewall barrier (not shown) may be deposited over the workpiece 200 to cover the sidewalls of the channel layer 208 formed by the top portion 204T of the superlattice structure 204. The sidewall barrier is formed of a dielectric material such as silicon oxide or silicon nitride so that it blocks epitaxial formation on the sidewalls of the channel layer 208. In the absence of a sidewall barrier, epitaxial growth from the top channel layer 208 may merge to block satisfactory formation of the bottom source / drain feature 224B. After forming the sidewall barrier, the bottom source / drain feature 224B may be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process may use gaseous and / or liquid precursors that interact with the components of the substrate 202 and the channel layer 208. The sidewall blocking layer (due to its dielectric composition) blocks the bottom source / drain feature 224B from forming on the sidewalls of the channel layer 208 formed by the top portion 204T of the superlattice structure 204. Figure 4 As shown in , the deposited bottom source / drain feature 224B is in physical contact with (or adjacent to) the channel layer 208 formed by the bottom portion 204B of the superlattice structure 204. Depending on the design, the bottom source / drain feature 224B can be n-type or p-type. In the depicted embodiment, the bottom source / drain feature 224B is a p-type source / drain feature and can include silicon germanium (SiGe) doped with a p-type dopant, such as boron (B). In these depicted embodiments, the bottom source / drain feature 224B can include boron-doped silicon germanium (SiGe:B).

[0030] Still reference Figure 4, CESL 226 and bottom ILD layer 228 are deposited over bottom source / drain features 224B. Bottom CESL 226 may include silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by CVD, ALD, plasma enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In some embodiments, bottom CESL 226 is first conformally deposited on workpiece 200, and then bottom ILD layer 228 is deposited over bottom CESL 226 by spin coating, FCVD, CVD, or other suitable deposition techniques. Bottom ILD layer 228 may include materials such as ethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. In some embodiments, after forming the bottom ILD layer 228, the workpiece 200 may be annealed to improve the integrity of the bottom ILD layer 228. The bottom CESL 226 and the bottom ILD layer 228 are etched back to the exposed sidewalls of the top channel layer 208 formed by the top portion 204T of the superlattice structure 204. It should be noted that the barrier layer may also be removed during the etching back of the bottom CESL 226 and the bottom ILD layer 228.

[0031] Then, an etch stop layer (ESL) 230 is deposited over the bottom CESL 226 and the bottom ILD layer 228. The ESL 230 may include silicon nitride or silicon oxynitride and is in direct contact with the top surfaces of the bottom CESL 226 and the bottom ILD layer 228. The ESL 230 may be deposited using ALD, CVD, or a suitable method. Etching back may be performed using a dry etchant or a wet etchant to expose the sidewalls of the top channel layer 208 formed by the top portion 204T of the superlattice structure 204. The bottom ILD layer 228 and the bottom CESL 226 provide a flat top surface. The ESL 230 is deposited on the flat top surface. Figure 4 As shown in , the ESL 230 may be in direct contact with at least one of the internal spacer components 218 .

[0032] The top source / drain component 224T is formed above the ESL 230. The top source / drain component 224T can be formed using an epitaxial process, such as VPE, UHV-CVD, MBE, and / or other suitable processes. The epitaxial growth process can use gaseous and / or liquid precursors that interact with the components of the top channel layer 208 formed by the top portion 204T of the superlattice structure 204. The epitaxial growth of the top source / drain component 224T can occur from the exposed sidewalls of the top channel layer 208. The deposited top source / drain component 224T is in physical contact (or adjacent) with the channel layer 208 formed by the top portion 204T of the superlattice structure 204. Depending on the design, the top source / drain component 224T can be n-type or p-type. In the depicted embodiment, the top source / drain component 224T is an n-type source / drain component and can include silicon (Si) doped with an n-type dopant (such as phosphorus (P)). In the depicted embodiments, the top source / drain features 224T can include phosphorus-doped silicon (Si:P).

[0033] Although not explicitly shown in the drawings, the top CESL and the top ILD layer are deposited over the top source / drain features 224T. The top CESL is similar to the bottom CESL 226. It may include silicon nitride, silicon oxynitride, and / or other materials known in the art, and may be formed by CVD, ALD, plasma enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. The top ILD layer is deposited on the top CESL. The top ILD layer is similar to the bottom ILD layer 228. It may include materials such as ethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, after forming the top ILD layer, the workpiece 200 may be annealed to improve the integrity of the top ILD layer. To remove excess material and expose the top surface of the dummy gate stack 214 , a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed.

[0034] refer to Figure 1 and Figure 5, the method 100 includes a block 114, in which the channel member 2080 is released. The operations in block 114 may include removing the dummy gate stack 214 and releasing the channel layer 208 as the channel member 2080. Removing the dummy gate stack 214 may include one or more etching processes that are selective to the material in the dummy gate stack 214. For example, removing the dummy gate stack 214 may be performed using a selective wet etch, a selective dry etch, or a combination thereof. After removing the dummy gate stack 214, the channel region 210C ( Figure 4 The sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 210C are exposed. Thereafter, the sacrificial layer 206 in the channel region 210C is selectively removed to release the channel layer 208 as a channel member 2080. Figure 5 , channel member 2080 includes bottom channel member 2080B below intermediate dielectric layer 220 and top channel member 2080T above intermediate dielectric layer 220. Here, because the size of channel member 2080 is nanometer-scale, channel member 2080 may also be referred to as nanostructure. Selective removal of sacrificial layer 206 may be achieved by selective dry etching, selective wet etching or other selective etching processes. In certain embodiments, selective wet etching includes APM etching (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In some other embodiments, selective removal includes SiGe oxidation and subsequent silicon germanium oxide removal. For example, oxidation may be provided by ozone cleaning, and then silicon germanium oxide may be removed by an etchant such as NH4OH.

[0035] refer to Figure 1 and Figure 5, method 100 includes frame 116, wherein a gate dielectric layer 232 is deposited to wrap the channel member 2080. Although not explicitly shown in the drawings, before depositing the gate dielectric layer 232, an interfacial layer is first formed over the exposed surface of the channel member 2080 and the substrate 202. That is, the interfacial layer exists at the interface between the gate dielectric layer 232 and the channel member 2080 and between the gate dielectric layer 232 and the substrate 202. In some embodiments, the interfacial layer includes silicon oxide and can be formed in a pre-cleaning process. An exemplary pre-cleaning process can include using RCA SC-1 (ammonia, hydrogen peroxide and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide and water). The gate dielectric layer 232 is then deposited over the interfacial layer using ALD, CVD and / or other suitable methods. The gate dielectric layer 232 is formed of a high-k dielectric material. As used and described herein, high-k dielectric materials include those having a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide (~3.9). The gate dielectric layer 232 may include hafnium oxide. Alternatively, the gate dielectric layer 232 may include other high-K dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. It should be noted that because the intermediate dielectric layer 220 contacts the top surface of the topmost bottom channel component 2080B and the bottom surface of the bottommost top channel component 2080T, the interface layer and the gate dielectric layer 232 do not extend along the top surface of the topmost bottom channel component 2080B and the bottom surface of the bottommost top channel component 2080T. Figure 5 As shown in the figure, the gate dielectric layer 232 is also deposited on the sidewalls of the fin structure formed by the bottom silicon layer 208B and the top surface of the isolation feature 212. In some embodiments not explicitly shown in the figures, a silicon (Si) capping layer can be deposited over the gate dielectric layer 232 to expand the process window and protect the gate dielectric layer 232.

[0036] refer to Figure 1 and Figure 5, the method 100 includes a frame 118, wherein a dielectric plug 233 is formed to fill the space between the channel members 2080. In order to be able to easily and completely remove any dummy filling material, the space between the channel members 2080 is filled with a dielectric plug 233. The dielectric plug 233 is formed with a material that can be selectively removed without substantially damaging the gate dielectric layer 232. In some embodiments, the dielectric plug 233 includes aluminum oxide that can be selectively removed using ammonium hydroxide (NH4OH) or hydrofluoric acid (HF). In order to form the dielectric plug 233, an aluminum oxide layer is deposited over the workpiece 200 to fill the space between the channel members 2080. Then, an anisotropic etching process is performed to remove excess aluminum oxide outside the space between the channel members 2080. The anisotropic etching process can be a dry etching process, which includes the use of oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I), other suitable gases and / or plasmas and / or combinations thereof.

[0037] refer to Figure 1 and Figure 5 , the method 100 includes a block 120, in which a dummy liner 234 is formed along the sidewalls of the channel member 2080 and the dielectric plug 233, and a top hard mask 236 is formed over a top surface of the dummy liner 234. The dummy liner 234 is used to protect the channel member 2080 from being damaged during subsequent operations that result in the formation of a gate structure. To introduce etch selectivity, the dummy liner 234 includes a metal nitride, such as titanium nitride (TiN) or tantalum nitride (TaN). In the depicted embodiment, the dummy liner 234 includes titanium nitride (TiN) and may be referred to as a titanium-containing liner 234. The dummy liner 234 may be deposited using ALD, and as shown in FIG. Figure 5 As shown in FIG, the dummy liner 234 is deposited on the gate dielectric layer 232 and on the sidewalls of the dielectric plug 233 along the sidewalls of the channel member 2080. The dummy liner 234 is also deposited on the gate dielectric layer 232, which is disposed on the sidewalls of the fin structure formed by the bottom silicon layer 208B and on the top surface of the isolation feature 212. That is, the dummy liner 234 is separated from the bottom silicon layer 208B and the isolation feature 212 by the gate dielectric layer 232. In addition, the dummy liner 234 is also deposited on the gate dielectric layer 232 disposed on the topmost top channel member 208T.

[0038] After depositing the dummy liner 234, a top hard mask 236 is formed on the dummy liner 234 disposed above the channel member 2080. In some embodiments, the top hard mask 236 includes silicon nitride. In an exemplary process for forming the top hard mask 236, a bottom anti-reflective coating (BARC) is deposited over the workpiece 200 to fill the spaces between the fin-shaped structures. A planarization process is then performed to expose the top surface of the dummy liner 234 disposed along the top surface of the topmost top channel member 208T. Then, a hard mask layer is deposited and patterned on the BARC layer to form a top hard mask 236 above the channel member 2080. After patterning the hard mask layer, the BARC layer is removed by ashing.

[0039] refer to Figure 1 and Figure 6 , the method 100 includes block 122, in which a first dummy fill 237 is formed to cover the bottom channel member 2080B. In some embodiments, the first dummy fill 237 may include silicon oxide and may be deposited using flowable CVD (FCVD). To improve the integrity of the first dummy fill 237, the operation in block 122 may include an annealing process at a temperature between about 350° C. and about 500° C.

[0040] refer to Figure 1 and Figure 7 , method 100 includes block 124, where a barrier layer 238 is formed on the dummy liner 234 along the sidewalls of the top channel member 2080T. In the case where the first dummy filler 237 covers the bottom channel member 2080B, the barrier layer 238 is selectively formed on the dummy liner 234. In some embodiments, the barrier layer 238 can be a self-assembled monolayer (SAM) deposited by ALD using a titanium-binding precursor. The molecules of the titanium-binding precursor can include a head group and a hydrocarbon tail group that bind to the titanium in the titanium-containing liner 234. Now referring to Fig. 22 Examples of titanium-binding precursors include hexylphosphonic acid (HPA) ( Fig. 22 (A) in), dodecylphosphonic acid (DDPA) ( Fig. 22 (B)), octadecylphosphonic acid (ODPA) ( Fig. 22 (C), 16-phosphonohexadecanoic acid (PHDA) ( Fig. 22 (D)), 12-mercaptododecylphosphonic acid (MDPA) ( Fig. 22 (E)), 12-pentafluorophenoxydodecylphosphonic acid (PFPA) ( Fig. 22 (F)) or 11-hydroxyundecylphosphonic acid (HUPA) ( Fig. 22 Each of these examples includes a phosphonic acid moiety. Fig.23The phosphonic acid moiety has several bonding modes with titanium on the dummy pad 234. For example, the phosphonic acid moiety can have a monodentate bond ( Fig.23 (1) in), and the bridging bidentate bond between two titanium atoms ( Fig.23 (2) or (3) in), and the bridging tridentate bond with three titanium atoms ( Fig.23 (4)) and the chelated bidentate bond with a single titanium atom ( Fig.23 (5) in ). Figure 7 As shown in FIG. 2 , barrier layer 238 is selectively deposited along the exposed sidewalls of dummy liner 234, which extend along the sidewalls of top channel member 2080T. In some embodiments, barrier layer 238 may be approximately 1000 mm thick. Peace between.

[0041] refer to Figure 1 and Figure 8 , method 100 includes frame 126, wherein the first dummy filler 237 is removed to release the bottom channel member 2080B. The operation in frame 126 includes selectively removing the first dummy filler 237 and selectively removing the dielectric plug 233 not covered by the barrier layer 238. In some embodiments, the first dummy filler 237 is removed using a dry etching process using a fluorine-containing gas (F2, NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6) or a mixture thereof. The dielectric plug 233 can be removed using an aqueous solution of ammonium hydroxide or hydrofluoric acid (HF) or diluted HF. In some optional embodiments, with the barrier layer 238 in place, the first dummy filler 237 can be etched away using hydrofluoric acid (HF) or diluted HF. In one embodiment, the dielectric plug 233 and the first dummy filler 237 can be selectively removed using hydrofluoric acid (HF) or diluted HF. With the first dummy fill 237 and the dielectric plug 233 removed, the bottom channel member 2080B is released again.

[0042] refer to Figure 1 and Fig. 9, method 100 includes frame 128, wherein a first work function layer 240 is deposited to wrap each of the bottom channel member 2080B. In the case of releasing the bottom channel member 2080B, the first work function layer 240 is deposited to wrap each of the bottom channel member 2080B. Depending on the design of the semiconductor device, the first work function layer 240 can be an n-type work function layer or a p-type work function layer. The first work function layer 240 can include a single layer or optionally a multilayer structure, such as various combinations of metal layers with a selected work function to enhance device performance. In the depicted embodiment, the first work function layer 240 is a p-type work function layer, and can include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium silicide (ZrSi2), molybdenum silicide (MoSi2), tantalum silicide (TaSi2), nickel silicide (NiSi2), other p-type work function materials or combinations thereof. In one embodiment, the first work function layer 240 includes titanium nitride (TiN). The first work function layer 240 can be deposited using ALD. It is observed that the tail groups of the barrier layer 238 hinder the deposition of the first work function layer 240 thereon. Therefore, only a moderate etch back may be required to remove the excess first work function layer 240. The etch back may also remove the first work function layer 240 deposited on the top hard mask 236. Fig. 9 In some embodiments shown in , after etching back, the top surface of the first work function layer 240 can be higher than the top surface of the topmost bottom channel component 2080B, but lower than the top surface of the intermediate dielectric layer 220. That is, the top surface of the first work function layer 240 remains lower than the bottom surface of the bottommost top channel component 2080T or flush with the bottom surface of the bottommost top channel component 2080T. It should be noted that the first work function layer 240 is spaced apart from the bottom channel component 2080B by the interface layer and the gate dielectric layer 232. It should be noted that the first work function layer 240 does not completely wrap the topmost bottom channel component 2080B because the top surface of the topmost bottom channel component 2080B is covered by the intermediate dielectric layer 220.

[0043] refer to Figure 1 and Figures 10 to 15 , the method 100 includes box 130, in which a gate isolation layer 242 is formed above the top surface of the first work function layer 240. Depending on the design, the bottom channel member 2080B and the top channel member 2080T can be activated simultaneously or separately. When the former is desired, the first work function layer 240 and the second work function layer 250 to be deposited are in direct contact without any intervening isolation layer to form a common gate. When the latter is desired, the gate isolation layer 242 is deposited on the first work function layer 240 to provide a split gate structure. When such a gate isolation layer 242 is desired, the operations in box 130 are implemented. Reference Fig.10First, a gate isolation material 242 is conformally deposited over the workpiece 200. Due to the presence of the barrier layer 238 that blocks the deposition of the gate isolation material 242, little or no gate isolation material 242 is deposited on the dummy liner 234. Fig.10 As shown in , the gate isolation material 242 can be deposited on the top surface of the first work function layer 240 and the top surface of the top hard mask 236. In some embodiments, the gate isolation material 242 includes a nitrogen-containing dielectric material such as silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon nitride oxide. In one embodiment, the gate isolation material 242 includes silicon nitride. The gate isolation material 242 can be deposited using ALD.

[0044] Reference now Fig.11 After the gate isolation material 242 is deposited, a second dummy fill 244 is deposited over the workpiece 200 (including over the gate isolation material 242, the barrier layer 238, and the top hard mask 236). In other words, the second dummy fill 244 wraps around the top channel member 2080T. The composition of the second dummy fill 244 is different from the composition of the first dummy fill 237. In some embodiments, the second dummy fill 244 includes a BARC material including silicon (Si), oxygen (O), carbon (C), and hydrogen (H), while the first dummy fill 237 includes silicon oxide. Then refer to Fig.12 The second dummy fill 244 is then etched back to expose the top hard mask 236 and the gate isolation material 242 on the top hard mask 236. In some embodiments, both the hard mask 236 and the gate isolation material 242 are formed of silicon nitride and can be selectively removed using a wet etch using phosphoric acid (H3PO4), such as Fig.13 As shown in . Fig.14 After removing the top hard mask 236, the second dummy filler 244 is removed by ashing or selective etching. The gate isolation material 242 remaining on the top surface of the first work function layer 240 can now be referred to as a gate isolation layer 242. Fig.15 In some embodiments shown in , the workpiece 200 may include a first region I and a second region II. In the first region I, the first work function layer 240 is electrically isolated from the second work function layer 250 by the gate isolation layer 242, while in the second region II, the first work function layer 240 and the second work function layer 250 are in direct and electrical contact with each other. If the second region II is covered by, for example, a BARC layer, the workpiece 200 may include a first region I and a second region II. Figures 10 to 14 The process shown in FIG. Fig.15 The gate isolation layer 242 in.

[0045] refer to Figure 1 and Fig.16, the method 100 includes a frame 132, wherein the top channel member 2080T is released. In frame 132, the dielectric plugs 233 interlaced with the top channel member 2080T are removed using an aqueous solution of ammonium hydroxide. With the dielectric plugs 233 removed, the top channel member 2080T is again released. It should be noted that the interface layer and the gate dielectric layer 232 remain on the surface of the top channel member 2080T.

[0046] refer to Figure 1 and Fig.17 , the method 100 includes a frame 134, wherein a second work function layer 250 is deposited to wrap each of the top channel member 2080T. In the case of releasing the top channel member 2080T, a second work function layer 250 is deposited to wrap each of the top channel member 2080T. Depending on the design of the semiconductor device, the second work function layer 250 can be an n-type work function layer or a p-type work function layer. The second work function layer 250 can include a single layer or optionally a multilayer structure, such as various combinations of metal layers with a selected work function to enhance device performance. In the depicted embodiment, the second work function layer 250 is an n-type work function layer, and can include titanium (Ti), aluminum (Al), silver (Ag), manganese (Mn), zirconium (Zr), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), other n-type work function materials or combinations thereof. In one embodiment, the second work function layer 250 includes titanium aluminum (TiAl). The second work function layer 250 can be deposited using ALD. Fig.17 In some embodiments shown in , after depositing the second work function layer 250, a glue layer and a gate capping layer can be deposited on the second work function layer 250. The glue layer can include titanium nitride (TiN), and the gate capping layer can include tungsten (W). After depositing the glue layer and the gate capping layer, a CMP process can be used to planarize the workpiece 200 to remove excess material and provide a flat top surface. It should be noted that the second work function layer 250 does not completely wrap the bottommost top channel component 2080T because the bottom surface of the bottommost top channel component 2080T is covered by the intermediate dielectric layer 220.

[0047] refer to Figure 1 and Figures 18 to 21 , the method 100 includes block 136, in which a gate contact via 260 is formed to couple to the gate structure 255. After planarization in block 134, an interlayer dielectric (ILD) layer 252 is deposited over the workpiece 200 by spin coating, FCVD, CVD, or other suitable deposition techniques, such as Fig.18As shown in . The ILD layer 252 may include materials such as ethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. Fig.19 , a gate contact opening 254 is formed through the ILD layer 252 to expose a portion of the second work function layer 250 (or a glue layer or gate capping layer deposited therein). The formation of the gate contact opening 254 may include a dry etching process using an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas (e.g., CF3I), other suitable gases and / or plasmas and / or combinations thereof. Reference Fig. 20 , a via glue layer 256 is blanket deposited over the workpiece 200 (including over the ILD layer 252 and the gate contact opening 254). In some embodiments, the via glue layer 256 may include titanium nitride (TiN) and may be deposited using ALD. Fig.21 In the embodiment of the present invention, a metal filler 260 is deposited over the workpiece 200, and the workpiece 200 is planarized to remove excess via glue layer 256 and metal filler 260, thereby forming a gate contact via 262 extending through the ILD layer 252. In some embodiments, the metal filler 260 may include tungsten (W) and may be deposited using ALD or CVD. The gate contact via 262 includes the via glue layer 256 and the metal filler 260.

[0048] In one exemplary aspect, the disclosed embodiments relate to a method. The method includes: depositing a titanium nitride (TiN) layer over a channel region including a bottom channel layer and a top channel layer above the bottom channel layer; depositing a dummy filling layer to cover the sidewall of the bottom channel layer; after depositing the dummy filling layer, selectively forming a barrier layer over the TiN layer along the sidewall of the top channel layer; selectively removing the dummy filling layer to release the bottom channel layer; selectively depositing a first work function metal layer to wrap each of the bottom channel layers; forming a gate isolation layer over a top surface of the first work function metal layer; removing the barrier layer; releasing the top channel layer; and selectively depositing a second work function metal layer to wrap each of the top channel layers.

[0049] In some embodiments, during the selective deposition of the first work function metal layer, little or no first work function metal layer is deposited on the barrier layer. In some embodiments, one of the bottom channel layers is stacked above another, and before the TiN layer is deposited, the bottom channel layer is interlaced with the first plurality of dielectric plug layers, and one of the top channel layers is stacked above another, and before the TiN layer is deposited, the top channel layer is interlaced with the second plurality of dielectric plug layers. In some embodiments, the selective removal includes selectively removing the first plurality of dielectric plug layers. In some instances, releasing the top channel layer includes selectively removing the second plurality of dielectric plug layers. In some embodiments, the first plurality of dielectric plug layers and the second plurality of dielectric plug layers include aluminum oxide. In some embodiments, the method further includes: depositing a top hard mask on the TiN layer above the channel region before depositing the dummy fill layer. In some embodiments, the selective formation of the barrier layer includes depositing a self-assembled precursor on the TiN layer not covered by the dummy fill layer, and the self-assembled precursor is configured to form a monodentate bond, a bridging bidentate bond, a bridging tridentate bond, or a chelated bidentate bond with titanium on the TiN layer. In some embodiments, the self-assembly precursor comprises a phosphonic acid functional head group and a tail group comprising a hydrocarbon chain. In some examples, the self-assembly precursor comprises hexylphosphonic acid (HPA), dodecylphosphonic acid (DDPA), octadecylphosphonic acid (ODPA), 16-phosphonohexadecanoic acid (PHDA), 12-mercaptododecylphosphonic acid (MDPA), 12-pentafluorophenoxydodecylphosphonic acid (PFPA) or 11-hydroxyundecylphosphonic acid (HUPA).

[0050] In another exemplary aspect, the disclosed embodiments are directed to a method. The method includes: receiving a workpiece, the workpiece including: a substrate; a fin rising from the substrate; a bottom channel member disposed above the fin; an intermediate dielectric layer disposed above the bottom channel member; a top channel member disposed above the intermediate dielectric layer; a gate dielectric layer disposed above a surface of the bottom channel member and the top channel member; a first plurality of plug layers interlaced with the bottom channel member; and a second plurality of plug layers interlaced with the top channel member; depositing a titanium-containing layer over sidewalls of the bottom channel member, sidewalls of the first plurality of plug layers, sidewalls of the intermediate dielectric layer, sidewalls of the bottom channel member, and sidewalls of the second plurality of plug layers; and depositing a titanium-containing layer over the workpiece. A dummy filling layer is deposited so that the top surface of the dummy filling layer is substantially coplanar with the bottom surface of the intermediate dielectric layer; after depositing the dummy filling layer, selectively forming a barrier layer over the titanium-containing layer along the sidewalls of the top channel component; selectively removing the dummy filling layer, the titanium-containing layer not covered by the barrier layer, and the first plurality of plug layers to release the bottom channel component; selectively depositing a first work function metal layer to wrap each of the bottom channel components; forming a gate isolation layer over the top surface of the first work function metal layer; removing the barrier layer; selectively removing the second plurality of plug layers to release the top channel component; and selectively depositing a second work function metal layer to wrap each of the top channel components.

[0051] In some embodiments, the titanium-containing layer includes titanium nitride. In some embodiments, the selective formation of the barrier layer includes depositing a self-assembly precursor on the titanium-containing layer not covered by the dummy filling layer. The self-assembly precursor is configured to form a monodentate bond, a bridging bidentate bond, a bridging tridentate bond, or a chelated bidentate bond with the titanium on the titanium-containing layer. In some embodiments, the self-assembly precursor includes hexylphosphonic acid (HPA), dodecylphosphonic acid (DDPA), octadecylphosphonic acid (ODPA), 16-phosphonyl hexadecanoic acid (PHDA), 12-mercaptododecylphosphonic acid (MDPA), 12-pentafluorophenoxydodecylphosphonic acid (PFPA) or 11-hydroxyundecylphosphonic acid (HUPA). In some instances, the first work function metal layer includes titanium nitride (TiN), and the second work function metal layer includes titanium aluminide (TiAl).

[0052] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: depositing a titanium-containing layer over a channel region including a bottom channel member and a top channel member above the bottom channel member; forming a top hard mask on a top surface of the titanium-containing layer; after forming the top hard mask, depositing a first dummy filling layer to cover the titanium-containing layer along the sidewall of the bottom channel member; after depositing the first dummy filling layer, selectively forming a barrier layer to cover the titanium-containing layer along the sidewall of the top channel member; selectively removing the first dummy filling layer to release the bottom channel member; selectively depositing a first work function metal layer to wrap each of the bottom channel members; after selectively depositing the first work function metal layer, forming a gate isolation layer over the first work function metal layer and the top hard mask; after forming the gate isolation layer, removing the top hard mask; removing the barrier layer; releasing the top channel member; and selectively depositing a second work function metal layer to wrap each of the top channel members.

[0053] In some embodiments, removing the top hard mask includes: depositing a second dummy fill layer over the gate isolation layer and the barrier layer; etching back the second dummy fill layer to expose the top hard mask; removing the top hard mask; and removing the second dummy fill layer after removing the top hard mask. In some embodiments, the composition of the first dummy fill layer is different from the composition of the second dummy fill layer. In some instances, selectively forming a barrier layer includes depositing a self-assembled precursor on a titanium-containing layer not covered by the first dummy fill layer. The self-assembled precursor is configured to form a monodentate bond, a bridging bidentate bond, a bridging tridentate bond, or a chelated bidentate bond with titanium on the titanium-containing layer. In some embodiments, the self-assembled precursor includes hexylphosphonic acid (HPA), dodecylphosphonic acid (DDPA), octadecylphosphonic acid (ODPA), 16-phosphonohexadecanoic acid (PHDA), 12-mercaptododecylphosphonic acid (MDPA), 12-pentafluorophenoxydodecylphosphonic acid (PFPA) or 11-hydroxyundecylphosphonic acid (HUPA).

[0054] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: depositing a titanium nitride (TiN) layer over a channel region including a bottom channel layer and a top channel layer over the bottom channel layer; depositing a dummy filling layer to cover the sidewalls of the bottom channel layer; After depositing the dummy filling layer, selectively forming a barrier layer over the titanium nitride layer along the sidewalls of the top channel layer; selectively removing the dummy filling layer to release the bottom channel layer; selectively depositing a first work function metal layer to wrap each of the bottom channel layers; forming a gate isolation layer above a top surface of the first work function metal layer; removing the barrier layer; releasing the top channel layer; as well as A second work function metal layer is selectively deposited to wrap each of the top channel layers.

2. The method according to claim 1, wherein: During the selective deposition of the first work function metal layer, little or no first work function metal layer is deposited on the barrier layer.

3. The method according to claim 1, in, The bottom channel layers are stacked one above the other and prior to depositing the titanium nitride layer, and the bottom channel layers are interleaved with a first plurality of dielectric plug layers, The top channel layers are stacked one above the other and prior to depositing the titanium nitride layer, and the top channel layers are interleaved with a second plurality of dielectric plug layers.

4. The method according to claim 3, wherein: The selectively removing includes selectively removing the first plurality of dielectric plug layers.

5. The method according to claim 3, wherein: Releasing the top channel layer includes selectively removing the second plurality of dielectric plug layers.

6. The method according to claim 3, wherein: The first plurality of dielectric plug layers and the second plurality of dielectric plug layers include aluminum oxide.

7. The method according to claim 1, further comprising: Prior to depositing the dummy fill layer, a top hard mask is deposited on the titanium nitride layer over the channel region.

8. The method according to claim 1, in, Selectively forming the barrier layer includes depositing a self-assembly precursor on the titanium nitride layer not covered by the dummy filling layer, Wherein, the self-assembly precursor is configured to form a monodentate bond, a bridging bidentate bond, a bridging tridentate bond or a chelated bidentate bond with the titanium on the titanium nitride layer.

9. A method of forming a semiconductor device, comprising: A workpiece is received, the workpiece comprising: substrate; a fin rising from the substrate; a bottom channel member disposed above the fin; an intermediate dielectric layer disposed above the bottom channel member; a top channel member disposed above the intermediate dielectric layer; a gate dielectric layer disposed over surfaces of the bottom channel member and the top channel member; a first plurality of plug layers interleaved with the bottom channel member; and a second plurality of plug layers interleaved with the top channel member; depositing a titanium-containing layer over sidewalls of the bottom channel member, sidewalls of the first plurality of plug layers, sidewalls of the intermediary dielectric layer, sidewalls of the bottom channel member, and sidewalls of the second plurality of plug layers; depositing a dummy fill layer over the workpiece such that a top surface of the dummy fill layer is substantially coplanar with a bottom surface of the intermediate dielectric layer; After depositing the dummy fill layer, selectively forming a barrier layer over the titanium-containing layer along sidewalls of the top channel member; selectively removing the dummy fill layer, the titanium-containing layer not covered by the barrier layer, and the first plurality of plug layers to release the bottom channel member; selectively depositing a first work function metal layer to wrap around each of the bottom channel members; forming a gate isolation layer above a top surface of the first work function metal layer; removing the barrier layer; selectively removing the second plurality of plug layers to release the top channel member; and A second work function metal layer is selectively deposited to wrap around each of the top channel members.

10. A method of forming a semiconductor device, comprising: depositing a titanium-containing layer over a channel region including a bottom channel member and a top channel member over the bottom channel member; forming a top hard mask on a top surface of the titanium-containing layer; After forming the top hard mask, depositing a first dummy fill layer to cover the titanium-containing layer along sidewalls of the bottom channel member; After depositing the first dummy-fill layer, selectively forming a barrier layer to cover the titanium-containing layer along sidewalls of the top channel member; selectively removing the first dummy fill layer to release the bottom channel member; selectively depositing a first work function metal layer to wrap around each of the bottom channel members; After selectively depositing the first work function metal layer, forming a gate isolation layer over the first work function metal layer and the top hard mask; After forming the gate isolation layer, removing the top hard mask; removing the barrier layer; releasing the top channel member; as well as A second work function metal layer is selectively deposited to wrap around each of the top channel members.

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