Photoelectric conversion apparatus, imaging system, and mobile apparatus

Abstract

The invention discloses a photoelectric conversion apparatus, an imaging system, and a mobile apparatus. There is provided a photoelectric conversion device including: a first substrate having a first surface; photodiodes disposed in the first substrate and each having a first region and a second region, the first region generating signal charges by photoelectrically converting incident light, and the second region receiving the signal charges moved from the first region; a first isolation region disposed at a first depth in the first substrate and including a first portion extending in a first direction so as to isolate the second regions from each other; and a second isolation region disposed in the first substrate at a second depth deeper than the first depth from the first surface and including a second portion extending in a second direction intersecting the first direction in a plan view so as to isolate the first regions from each other, and the first portion and the second portion partially overlap each other in the plan view.

Description

[0001] This application is a divisional application of the Chinese invention patent application with application number 202010105808.1, application date February 20, 2020, and titled "Photoelectric conversion equipment, imaging system and mobile device". Technical Field

[0002] The present invention relates to a photoelectric conversion device, an imaging system and a mobile device. Background Art

[0003] Avalanche diodes are known that can detect weak light at the level of a single photon by using avalanche (electron avalanche) multiplication. Japanese Patent Application Publication No. 2018-157387 discloses an imaging device configured such that multiple avalanche diodes are arranged in a single pixel.

[0004] In addition, an image sensor having a plurality of photoelectric conversion units for image plane phase difference autofocus in each pixel is known. In such an image sensor, when the subject has a stripe pattern or the like in which parallax is unlikely to occur, the accuracy of autofocus may be reduced. Japanese Patent Application Publication No. 2011-53519 discloses a technology for improving focus detection accuracy by using two alignment directions of focus detection pixels.

[0005] In a photoelectric conversion device using a photodiode disclosed in Japanese Patent Application Publication No. 2018-157387 or Japanese Patent Application Publication No. 2011-53519, a desired function may differ depending on the position in the thickness direction of a semiconductor substrate on which the photodiode is formed. However, neither Japanese Patent Application Publication No. 2018-157387 nor Japanese Patent Application Publication No. 2011-53519 considers focusing on the relationship between the position in the thickness direction of the substrate and the function. Summary of the invention

[0006] The present invention is directed to providing a photoelectric conversion apparatus, an imaging system, and a moving device which can optimize the structure of a photodiode in consideration of the position in the thickness direction of a substrate.

[0007] According to one aspect of the present invention, a photoelectric conversion device is provided, comprising: a first substrate having a first surface; a plurality of photodiodes arranged in the first substrate, and each photodiode having a first region and a second region, the first region generating a signal charge by photoelectrically converting incident light, and the second region receiving the signal charge moved from the first region; a first isolation region, arranged in the first substrate at a first depth and including a first portion extending in a first direction so as to isolate a second region of one of the plurality of photodiodes from a second region of another of the plurality of photodiodes; and a second isolation region, arranged in the first substrate at a second depth deeper than the first depth relative to the first surface, and including a second portion extending in a second direction intersecting the first direction in a plan view so as to isolate a first region of one of the plurality of photodiodes from a first region of another of the plurality of photodiodes, and a portion of the first portion and a portion of the second portion overlap each other in a plan view.

[0008] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic cross-sectional view of an avalanche diode according to the first embodiment.

[0010] Figure 2A , Figure 2B and Figure 2C is a schematic plan view of an avalanche diode according to the first embodiment.

[0011] Figure 3A and Figure 3B is a potential diagram of the avalanche diode according to the first embodiment.

[0012] Figure 4A , Figure 4B and Figure 4C is a schematic plan view showing an example of pixel arrangement.

[0013] Figure 5A and Figure 5B is a schematic plan view in which partitions are overlapped for illustration.

[0014] Figure 6 is a block diagram of a photoelectric conversion device according to a second embodiment.

[0015] Figure 7 is a block diagram of a pixel according to the second embodiment.

[0016] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Fig.8F are a schematic plan view and a schematic cross-sectional view of an avalanche diode according to a second embodiment.

[0017] Fig. 9 is a schematic plan view in which partitions are overlapped for illustration.

[0018] Fig.10 is a schematic cross-sectional view of a photoelectric conversion device according to a third embodiment.

[0019] Fig.11 is a schematic cross-sectional view of a photoelectric conversion apparatus according to a fourth embodiment.

[0020] Fig.12 is a block diagram of a photoelectric conversion device according to a fifth embodiment.

[0021] Fig.13 is an equivalent circuit diagram of a pixel according to the fifth embodiment.

[0022] Fig.14 is a schematic plan view of a photodiode according to a fifth embodiment.

[0023] Fig.15 is a schematic cross-sectional view of a photodiode according to a fifth embodiment.

[0024] Fig.16 is a schematic cross-sectional view of a photodiode according to a fifth embodiment.

[0025] Fig.17 is a schematic cross-sectional view of a photodiode according to a fifth embodiment.

[0026] Fig.18 is a schematic plan view of a pixel according to the fifth embodiment.

[0027] Fig.19A , Fig.19B and Fig.19C is a schematic diagram showing a first example of the arrangement of semiconductor regions according to the fifth embodiment.

[0028] Fig. 20A , Fig. 20B and Fig. 20C is a schematic diagram showing a second example of the arrangement of the semiconductor regions according to the fifth embodiment.

[0029] Fig.21A and Fig.21B is a schematic plan view showing an arrangement example of pixels according to the fifth embodiment.

[0030] Fig. 22 is a schematic plan view of a pixel according to a sixth embodiment.

[0031] Fig.23 is a schematic plan view showing an arrangement example of pixels according to the sixth embodiment.

[0032] Fig.24 is a schematic plan view of a pixel according to a modification example of the sixth embodiment.

[0033] Fig.25 is a schematic plan view of a pixel according to a seventh embodiment.

[0034] Fig.26 is a schematic plan view of a pixel according to a modification example of the seventh embodiment.

[0035] Fig. 27 is a schematic cross-sectional view of an avalanche diode according to an eighth embodiment.

[0036] Fig.28A and Fig.28B is a schematic perspective view of an avalanche diode according to an eighth embodiment.

[0037] Fig.29 is a schematic plan view of a photodiode according to a ninth embodiment.

[0038] Fig.30 is a schematic cross-sectional view of a photodiode according to a ninth embodiment.

[0039] Fig.31 is a schematic plan view of a photodiode according to a tenth embodiment.

[0040] Fig.32 is a schematic cross-sectional view of a photodiode according to a tenth embodiment.

[0041] Fig.33 is a schematic perspective view of a photodiode according to a tenth embodiment.

[0042] Fig.34 is a schematic plan view of a pixel according to a tenth embodiment.

[0043] Fig.35 is a schematic plan view showing the arrangement of a semiconductor region according to an eleventh embodiment.

[0044] Fig.36 is a schematic cross-sectional view of a photodiode according to an eleventh embodiment.

[0045] Fig.37 is a schematic perspective view of a photodiode according to an eleventh embodiment.

[0046] Fig.38A , Fig.38B , Fig.38C , Fig.38Dand Fig.38E is a schematic plan view showing an arrangement example of pixels according to the twelfth embodiment.

[0047] Fig.39 is a block diagram of an imaging system according to a thirteenth embodiment.

[0048] Fig.40A and Fig.40B is a block diagram of an imaging system and a moving device according to a fourteenth embodiment. DETAILED DESCRIPTION

[0049] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. First embodiment

[0050] A photoelectric conversion device according to a first embodiment will be described. As an example, the photoelectric conversion device of the present embodiment is assumed to be an imaging device for capturing an image. The photoelectric conversion device of the present embodiment has one or more pixels, and each pixel includes one or more avalanche diodes. The conductivity type of the charge used as a signal charge in a pair of charges generated by the avalanche diode is referred to as a first conductivity type. In addition, the conductivity type opposite to the first conductivity type is referred to as a second conductivity type.

[0051] Figure 1 1 is a schematic cross-sectional view of an avalanche diode according to the present embodiment. The avalanche diode of the present embodiment is arranged in a semiconductor substrate 15 (first substrate). The semiconductor substrate 15 has a first face and a second face opposite to the first face. For example, the first face is the front face of the semiconductor substrate 15, and the second face is the back face of the semiconductor substrate 15. In the present embodiment, the direction from the first face to the second face is referred to as the depth direction. On the front side of the semiconductor substrate 15, a gate electrode of a transistor, a multilayer wiring structure, etc. are arranged.

[0052] Each of the isolation portion 16A and the isolation portion 16B is a region that electrically isolates semiconductor regions from each other. Each of the isolation portion 16A and the isolation portion 16B may be an insulating isolation region formed by local oxidation of silicon (LOCOS), shallow trench isolation (STI), deep trench isolation (DTI), etc. In addition, each of the isolation portion 16A and the isolation portion 16B may be a PN isolation region formed by a PN junction between a P-type semiconductor region and an N-type semiconductor region.

[0053] like Figure 1As shown in FIG. 1 , a region surrounded by an isolation portion 16A serving as a first isolation region is formed in a semiconductor substrate 15. A first semiconductor region 71 of a first conductivity type and a second semiconductor region 76 are arranged in a region surrounded by the isolation portion 16A. In addition, a region surrounded by an isolation portion 16B serving as a second isolation region is formed in the semiconductor substrate 15. A third semiconductor region 74, a fourth semiconductor region 72 of a second conductivity type, and a fifth semiconductor region 75 are arranged in a region surrounded by the isolation portion 16B. In addition, a contact plug 77 arranged to contact the first semiconductor region 71 is provided on a first face of the semiconductor substrate 15. The contact plug 77 serves as a terminal of an avalanche diode.

[0054] The first semiconductor region 71, the second semiconductor region 76, and the isolation portion 16A are arranged at a depth X (a first depth). The first semiconductor region 71 and the second semiconductor region 76 are arranged in a direction perpendicular to the depth direction ( Figure 1 The second semiconductor region 76 is arranged between the first semiconductor region 71 and the isolation portion 16A.

[0055] Herein, the expression that, for example, the first semiconductor region 71, the second semiconductor region 76, and the isolation portion 16A are arranged at the depth X means that the region having the highest (peak) impurity concentration injected into the inside of the semiconductor substrate 15 is at the depth X. However, this does not mean that the peak is identical to the depth X in a strict sense, and a case where the peak is shifted from the depth X due to a design error, a manufacturing error, etc. is also included in the state where the peak is arranged at the depth X.

[0056] The third semiconductor region 74 and the fourth semiconductor region 72 are arranged at a depth Y deeper than the depth X relative to the first surface. The fifth semiconductor region 75 is arranged at a depth Z (second depth) deeper than the depth Y relative to the first surface. The isolation portion 16B is arranged at the depth Y and the depth Z. The third semiconductor region 74 and the fourth semiconductor region 72 are in contact with each other in a direction perpendicular to the depth direction. The fourth semiconductor region 72 is arranged between the third semiconductor region 74 and the isolation portion 16B. The fifth semiconductor region 75 and the isolation portion 16B are in contact with each other in a direction perpendicular to the depth direction.

[0057] Figure 2A , Figure 2B and Figure 2C is a schematic plan view of an avalanche diode according to the present embodiment. Figure 2A , Figure 2B and Figure 2C Schematic plan views at depth X, depth Y and depth Z are shown respectively.

[0058] like Figure 2AAs shown, the first semiconductor region 71 is included in the second semiconductor region 76 at a depth X. In addition, the second semiconductor region 76 is included in the isolation portion 16A. Note that Figure 2A The distance R in denoted by φ indicates the distance between the first semiconductor region 71 and the isolation portion 16A.

[0059] like Figure 2B As shown, the third semiconductor region 74 is included in the fourth semiconductor region 72 at a depth Y. In addition, the fourth semiconductor region 72 is included in the isolation portion 16B. Figure 2C As shown, the fifth semiconductor region 75 is included at a depth Z in the isolation portion 16B.

[0060] like Figure 1 , Figure 2A , Figure 2B and Figure 2C As shown, the first semiconductor region 71 overlaps with at least a portion of the third semiconductor region 74 in a plan view. In addition, the third semiconductor region 74 and the fourth semiconductor region 72 overlap with at least a portion of the fifth semiconductor region 75 in a plan view. Furthermore, the second semiconductor region 76 overlaps with at least a portion of the fourth semiconductor region 72 in a plan view. Here, the shape of the isolation portion 16A and the shape of the isolation portion 16B are different from each other in a plan view.

[0061] Figure 3A and Figure 3B is a graph showing one example of the potential of the avalanche diode according to the present embodiment. Figure 3A Shown along Figure 1 The potential distributions of the lines JK and GH in the cross-sectional view are shown. Figure 3B Shown along Figure 1 The potential distribution of the line AB and the line CD of the cross-sectional view is shown. The potential in the semiconductor region changes according to the potential applied to the contact plug 77. Figure 3A and Figure 3B The potential shown is the potential when the potential is supplied so that the reverse bias voltage is applied to the avalanche diode. The potential is supplied from a power supply voltage line provided outside the avalanche diode via a circuit such as a quench circuit. In addition, the level of the potential is set so that avalanche multiplication occurs in the avalanche diode.

[0062] exist Figure 3A In FIG. 1 , the dotted line 20 represents the potential distribution along the line GH, and the solid line 21 represents the potential distribution along the line JK. Each of these potentials indicates the potential of electrons as signal charges. Note that when the signal charges are holes, the relationship between the higher potential and the lower potential will be reversed. The depths X, Y, Z, and W on the horizontal axis are related to the depths in FIG. Figure 1The depths of the positions shown with corresponding reference marks correspond to those of the positions shown with corresponding reference marks. Figure 3A Reference symbols X, Y and Z in the figure represent Figure 1 The depths X, Y, and Z are shown in FIG. In addition, the depth W is a depth between the depth Y and the depth Z.

[0063] Will describe Figure 3A Each level of the potential in the fourth semiconductor region 72. The XH level represents the potential of the fourth semiconductor region 72. The H level represents the potential of the third semiconductor region 74. The M level represents the potential of the second semiconductor region 76. The L level represents the potential of the first semiconductor region 71. Note that, although the potential of the second semiconductor region 76 is lower than the potential of the third semiconductor region 74 in this example, this may be the opposite. In addition, although the potential of the third semiconductor region 74 is lower than the potential of the fourth semiconductor region 72 in this example, these potentials may be the same. In addition, although the potential of the first semiconductor region 71 is lower than the potential of the second semiconductor region 76 in this example, these potentials may be the same.

[0064] The potential along the line GH represented by the dotted line 20 will be described. The potential is between the XH level and the H level at the depth Z. The potential gradually decreases as the depth changes from the depth Z to the depth W. The potential then gradually increases as the depth changes from the depth W to the depth Y, and reaches the XH level at the depth Y. In addition, the potential gradually decreases as the depth changes from the depth Y to the depth X. The potential reaches the M level near the depth X.

[0065] The potential along the line JK represented by the solid line 21 passing through the avalanche diode will be described. The potential is between the XH level and the H level at the depth Z. The potential gradually decreases as the depth changes from the depth Z to the depth Y, and the slope of the potential increases near the depth Y. The potential then reaches the H level at the depth Y. The potential decreases sharply as the depth changes from the depth Y to the depth X. That is, a steep potential gradient is formed between the depth Y and the depth X. The potential reaches the L level at the depth X.

[0066] The potentials along the line GH and the line JK are substantially the same at the depth Z. In addition, a potential gradient is formed at positions along the line GH and the line JK near the depth Z, which gradually decreases as the depth approaches the first surface side of the semiconductor substrate 15. Therefore, due to the potential gradient, the charge generated in the semiconductor region inside the pixel by the incident light moves toward the first surface side.

[0067] Along the line JK, a potential gradient is formed that slightly decreases as the depth approaches the first surface side of the semiconductor substrate 15 as the depth changes from the depth W to the depth Y. As a result, the charge moves to the first surface side. On the other hand, along the line GH, a potential gradient is formed that slightly increases as the depth approaches the first surface side of the semiconductor substrate 15 as the depth changes from the depth W to the depth Y. This potential gradient serves as a potential barrier that prevents the charge from moving to the first surface. This potential barrier (the fourth semiconductor region 72) suppresses the charge from moving from the fifth semiconductor region 75 to the second semiconductor region 76. In contrast, since the potential gradient in the horizontal direction from the position of the line GH to the line JK is small, in the process of moving to the first surface within the range from the depth W to the depth Y, the charge located near the line GH is promoted to move to the portion near the line JK.

[0068] The charges that have moved to the portion near the region indicated by the line JK are accelerated by the steep potential gradient (i.e., the strong electric field formed in the range from the depth Y to the depth X). The charges accelerated by the strong electric field reach the first semiconductor region 71. In this way, avalanche multiplication occurs in the region from the depth Y to the depth X near the line JK. In contrast, the region indicated by the line GH has a potential distribution in which avalanche multiplication is less likely to occur than in the region from the depth Y to the depth X along the line JK.

[0069] One example of realizing such a structure may be a configuration in which the difference between the potential of the first semiconductor region 71 and the potential of the third semiconductor region 74 is greater than the difference between the potential of the second semiconductor region 76 and the potential of the fourth semiconductor region 72. With such a potential structure, a configuration in which avalanche multiplication occurs in the avalanche diode is realized. In addition, in this configuration, the reduction in sensitivity due to the presence of a portion where avalanche multiplication is less likely to occur is reduced for the following reason.

[0070] The potential of the third semiconductor region 74 is lower than the potential of the fourth semiconductor region 72. Therefore, the fourth semiconductor region 72 serves as a potential barrier that prevents signal charges from existing in the fifth semiconductor region 75. Thus, signal charges existing in a region included in the fifth semiconductor region 75 and overlapping with the fourth semiconductor region 72 or the third semiconductor region 74 are promoted to move to the first semiconductor region 71 via the third semiconductor region 74, and the charges are collected, thereby reducing sensitivity reduction.

[0071] Figure 3A 1 shows the potential structure when the third semiconductor region 74 is a P-type semiconductor region. However, even when the third semiconductor region 74 is an N-type semiconductor region, the relationship of the potential at the depth Y does not change for the line GH and the line JK, respectively. That is, at the depth Y, the potential along the line GH is higher than the potential along the line JK.

[0072] In addition, although Figure 3A The potential structure when the second semiconductor region 76 is an N-type semiconductor region is shown, but even in the case of a P-type semiconductor region, the relationship of the potential at the depth Y does not change for the line GH and the line JK, respectively. That is, at the depth Y, the potential along the line GH is higher than the potential along the line JK.

[0073] Note that since the charges generated in each portion of the fifth semiconductor region 75 move to a portion near the region indicated by line JK and cause avalanche multiplication, the sensitivity of a single pixel is approximately proportional to the area in a plan view of the fifth semiconductor region 75 included in the isolation portion 16B.

[0074] exist Figure 3B , the dotted line 22 represents the potential distribution along the line CD, that is, at the depth Y, and the solid line 23 represents the potential distribution along the line AB, that is, at the depth X. Since the meanings of the XH level, H level, M level and L level are the same as Figure 3A are the same as those in , so their description will be omitted.

[0075] The potential represented by the dotted line 22 varies between the XH level and the H level according to the horizontal position. The potential near the third semiconductor region 74 is low. The potential represented by the solid line 23 varies between the XH level and the L level according to the horizontal position. More specifically, the distribution makes the potential gradually decrease as the horizontal position changes from the isolation portion 16A to the first semiconductor region 71. The potential of the second semiconductor region 76 located between the isolation portion 16A and the first semiconductor region 71 changes slightly from the isolation portion 16A to the first semiconductor region 71. This potential distribution can be achieved by injecting impurities so that the impurity concentration of the second semiconductor region 76 is relatively low.

[0076] In the present embodiment, the second semiconductor region 76 is arranged between the isolation portion 16A and the first semiconductor region 71, and the isolation portion 16A and the first semiconductor region 71 are spaced apart from each other by a constant distance R. Thus, the electric field intensity due to the difference between the potential of the isolation portion 16A and the potential of the first semiconductor region 71 can be lower than the electric field intensity due to the difference between the potential of the first semiconductor region 71 and the potential of the third semiconductor region 74. Therefore, this suppresses the situation where the noise caused by the tunnel effect is caused by avalanche multiplication occurring at the PN junction between the isolation portion 16A and the first semiconductor region 71.

[0077] As described above, the isolation section 16A arranged at the depth X defines an avalanche region (second region) where avalanche multiplication due to signal charge occurs. In addition, the isolation section 16B arranged at the depth Z defines a sensitivity region (first region) where signal charge is generated by photoelectric conversion of incident light. As described above, in terms of reducing noise caused by the tunnel effect, the isolation section 16A at the depth X is designed to ensure the distance R between the isolation section 16A and the first semiconductor region 71 to a certain extent. In contrast, the isolation section 16B at the depth Z is designed by adjusting the shape, area, etc., so as to have the desired sensitivity level and desired position of the sensitivity region of each pixel. As discussed above, since the shape of the avalanche region and the shape of the sensitivity region have different design constraints, different shapes may be optimal for each shape. Thus, in the present embodiment, the shape of the isolation section 16A and the shape of the isolation section 16B are different from each other in a plan view. Therefore, a photoelectric conversion device with improved layout flexibility is provided, and the shape of the avalanche region and the shape of the sensitivity region can be designed to be suitable for the shape of each property.

[0078] As an example of a configuration in which the shape of the isolation portion 16A and the shape of the isolation portion 16B are different from each other, the area included in the isolation portion 16A and the area included in the isolation portion 16B may be different from each other. For example, for a pixel intended to increase sensitivity, the area included in the isolation portion 16B may be designed to be larger than the area included in the isolation portion 16A, so that the isolation portion 16B may be arranged to overlap with a portion of an adjacent pixel. As described above, in the avalanche diode of the present embodiment, the signal charge present in the fifth semiconductor region 75 is easily moved to the first semiconductor region 71 via the third semiconductor region 74. Therefore, since the signal charge generated in the fifth semiconductor region 75 is collected in the first semiconductor region 71, avalanche multiplication similarly occurs even when the area included in the isolation portion 16B is designed to be larger than the area included in the isolation portion 16A. Figure 4A , Figure 4B and Figure 4C An example of a configuration in which the area included in the isolation section 16B of some pixels is increased is shown.

[0079] Figure 4A , Figure 4B and Figure 4C 1 is a schematic plan view showing an example of a pixel arrangement in which the area included in the isolation section 16B is larger than the area included in the isolation section 16A in some pixels. Figure 4A is a schematic plan view at depth X, Figure 4B is a schematic plan view at a depth Y, and Figure 4C is a schematic plan view at depth Z. Figure 4A , Figure 4B and Figure 4C As shown, a plurality of pixels arranged in the semiconductor substrate 15 are arranged to form a plurality of rows and a plurality of columns. Figure 4A , Figure 4B and Figure 4C , four rows and four columns of a plurality of pixels are extracted and shown.

[0080] like Figure 4A As shown, the first semiconductor region 71 is included in the second semiconductor region 76 at a depth X. In addition, the second semiconductor region 76 is included in the isolation portion 16A. The minimum distance between the first semiconductor region 71 and the isolation portion 16A is the distance R in all pixels.

[0081] like Figure 4B As shown, the third semiconductor region 74 is included in the fourth semiconductor region 72 at a depth Y. In addition, the fourth semiconductor region 72 is included in the isolation portion 16B. Figure 4C As shown, the fifth semiconductor region 75 is included in the isolation portion 16B at a depth Z. Figure 4C The characters "red", "green", and "blue" written in the fifth semiconductor region 75 indicate that the corresponding pixels are red pixels, green pixels, and blue pixels, respectively. The red pixel, the green pixel, and the blue pixel are pixels on which red filters, green filters, and blue filters are respectively set. In the present embodiment, the red pixel, the green pixel, and the blue pixel form a Bayer arrangement.

[0082] like Figure 4C As shown, in the present embodiment, the area included in the isolation portion 16B of the green pixel is larger than the area included in the pixels of other colors. To achieve this, the isolation portion 16B of the green pixel is arranged to protrude to the outside relative to the isolation portion 16A between the adjacent red pixel and the adjacent blue pixel in a plan view. In other words, the shape of the isolation portion 16A and the shape of the isolation portion 16B are different from each other in a plan view. Thus, the area of ​​the sensitivity region of the green pixel can be wider than the area of ​​the sensitivity region of the pixels of other colors, and the sensitivity of the green pixel can be greater. Since the human eye is more sensitive to green than to red or blue, as shown in FIG. Figure 4C As shown in , when the area of ​​the sensitivity region of the green pixel is larger than the area of ​​the sensitivity region of the red pixel or the blue pixel, the basic image quality can be improved.

[0083] Note that for certain design requirements, color pixels other than green pixels may be larger. That is, in other words in a more general manner, the areas of the sensitivity regions surrounded by the isolation portion 16B may be different from each other with respect to the two avalanche diodes included in the photoelectric conversion device. In addition, the two avalanche diodes may be rewritten as a first avalanche diode having sensitivity to incident light of a first color and a second avalanche diode having sensitivity to incident light of a second color different from the first color.

[0084] refer to Figure 5A and Figure 5B , the positional relationship between the isolation portion 16A and the isolation portion 16B will be described in more detail. Figure 5A yes Figure 4A The isolation portion 16A and Figure 4B The isolation portion 16B is overlapped for illustration in a schematic plan view. Figure 5B FIG. 1 is an enlarged view of the intersection W of the isolation portion 16A and the isolation portion 16B. Figure 5B As shown, the isolation portion 16A includes a first portion P1 extending in the x1 direction (first direction). In addition, the isolation portion 16B includes a second portion P2 extending in the x2 direction (second direction) intersecting the x1 direction in a plan view. In this case, a portion of the first portion P1 and a portion of the second portion P2 overlap each other in an overlapping portion P3 in a plan view.

[0085] As described above, according to the present embodiment, the shape of the isolation portion 16A isolating the avalanche regions from each other and the shape of the isolation portion 16B isolating the sensitivity regions from each other are different from each other in a plan view. More specifically, a portion of the first portion P1 of the isolation portion 16A and a portion of the second portion P2 of the isolation portion 16B overlap each other in an overlapping portion P3 in a plan view. Thus, a photoelectric conversion device having improved layout flexibility is provided.

[0086] In addition, according to the present embodiment, the fourth semiconductor region 72 used as the third isolation region is arranged so as to isolate a portion of the region between the avalanche region and the sensitivity region. Thus, since the signal charge existing in the fifth semiconductor region 75 is promoted to move to the first semiconductor region 71 via the third semiconductor region 74, the sensitivity is improved.

[0087] Although in the description of the present embodiment, the bias voltage applied to the avalanche diode is controlled to have a state where avalanche multiplication occurs, it is not limited to this, and the bias voltage may be controllable to have a state where avalanche multiplication does not occur. In other words, the avalanche diode of the present embodiment can operate in two types of modes: an accumulation mode for accumulating signal charges in the sensitivity region and a readout mode for reading out the signal charges accumulated in the sensitivity region. Here, the accumulation mode is a mode in which a first bias voltage is applied to the avalanche diode, and the first bias voltage is controlled to a state in which avalanche multiplication does not occur. The charge generated by photoelectric conversion when the avalanche diode is in the accumulation mode is accumulated in the sensitivity region. The readout mode is a mode in which a second bias voltage different from the first bias voltage is applied to the avalanche diode, and the second bias voltage is controlled to a state in which avalanche multiplication occurs. By controlling the avalanche diode in two types of modes in this way, it is possible to implement an operation of accumulating signal charges in a predetermined period of time in the sensitivity region, and then reading out a signal according to the signal charges accumulated in the predetermined period of time. Second embodiment

[0088] A photoelectric conversion device according to a second embodiment will be described. In the description of this embodiment, features having the same functions as those of the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof may be omitted or simplified.

[0089] Figure 6 1 is a block diagram of the photoelectric conversion device 10 according to the present embodiment. The photoelectric conversion device 10 has a pixel unit 106 , a control pulse generating unit 109 , a horizontal scanning circuit 104 , a column circuit 105 , a signal line 107 , an output circuit 108 , and a vertical scanning circuit 103 .

[0090] The pixel unit 106 has a plurality of pixels 100 arranged to form a plurality of rows and columns. Each pixel 100 includes a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 converts light entering the photoelectric conversion device 10 into an electrical signal. The pixel signal processing unit 102 outputs the electrical signal to the column circuit 105 via a signal line 107.

[0091] The vertical scanning circuit 103 supplies a control pulse for driving each pixel 100 pixel by pixel row based on a control pulse supplied from the control pulse generating unit 109. A logic circuit such as a shift register, an address decoder, etc. may be used for the vertical scanning circuit 103. A signal line 107 is arranged for each column of the pixel unit 106. The signal line 107 transmits a signal output from the pixel 100 selected by the vertical scanning circuit 103 to the column circuit 105.

[0092] The signals of each pixel 100 are input to the column circuit 105 via the signal line 107. The column circuit 105 performs predetermined processing on the input signal. The predetermined processing may include processing such as noise removal and amplification of the input signal and processing of converting the processed signal into a form to be output externally. In order to realize this function, the column circuit 105 has, for example, a parallel to serial converter circuit.

[0093] The horizontal scanning circuit 104 sequentially supplies control pulses for outputting signals processed in the column circuit 105 to the output circuit 108, column by column, to the column circuit 105. The output circuit 108 is formed of a buffer amplifier, a differential amplifier, etc. The output circuit 108 outputs the signal output from the column circuit 105 to a storage unit or a signal processing unit outside the photoelectric conversion device 10.

[0094] Although in Figure 6 The arrangement of the pixels 100 in the pixel unit 106 is a two-dimensional matrix, but the arrangement is not limited thereto. For example, in the pixel unit 106, a plurality of pixels 100 may be arranged one-dimensionally. In addition, only a single pixel 100 may be included in the pixel unit 106. In addition, the vertical scanning circuit 103, the horizontal scanning circuit 104, and the column circuit 105 may be divided into a plurality of blocks, and the blocks of the pixel unit 106 may be arranged so as to correspond to the above-mentioned blocks of the vertical scanning circuit 103, the horizontal scanning circuit 104, and the column circuit 105. In addition, the horizontal scanning circuit 104 and the column circuit 105 may be divided into blocks corresponding to respective pixel columns.

[0095] It is not essential to provide the function of the pixel signal processing unit 102 in each of all pixels 100 within the pixel unit 106, and for example, a single pixel signal processing unit 102 may be shared by a plurality of pixels 100. In this case, the pixel signal processing unit 102 performs processing on signals output from the plurality of pixels 100 in sequence.

[0096] In addition, Figure 6 In the embodiment, the semiconductor substrate 15 including the pixel array in which the photoelectric conversion element 101 is two-dimensionally arranged and the semiconductor substrate including the elements other than the above may be separate semiconductor substrates. Thus, the ratio of the area of ​​the photoelectric conversion element 101 to the chip area can be increased, and the sensitivity of the photoelectric conversion element 101 is improved. In this case, the photoelectric conversion device 10 may have a stacked structure in which a plurality of semiconductor substrates are attached to each other.

[0097] As an example of such a configuration, the pixel signal processing unit 102 may be provided on a semiconductor substrate different from the semiconductor substrate 15 on which the photoelectric conversion element 101 is formed. In this case, the photoelectric conversion element 101 and the pixel signal processing unit 102 are electrically connected to each other via a connection wiring provided for each pixel 100. The vertical scanning circuit 103, the horizontal scanning circuit 104, the signal line 107, and the column circuit 105 may be similarly provided on a semiconductor substrate different from the photoelectric conversion element 101, and the same advantages are obtained.

[0098] Figure 7 is an example of a block diagram of the pixel 100 according to the present embodiment. Figure 7 In the embodiment of the present invention, one pixel 100 has a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 has a photoelectric conversion unit 201 and a control unit 202.

[0099] The photoelectric conversion unit 201 generates a charge pair by photoelectric conversion according to incident light. An avalanche diode is used as the photoelectric conversion unit 201. The anode of the photoelectric conversion unit 201 is connected to a potential line through which a potential VL is supplied. The cathode of the photoelectric conversion unit 201 is connected to one end of the control unit 202. The other end of the control unit 202 is connected to a potential line through which a potential VH higher than the potential VL is supplied.

[0100] With such a configuration, a reverse bias potential that can cause avalanche multiplication is applied between the anode and cathode of the photoelectric conversion unit 201. Once photoelectric conversion is performed in response to incident light with such a reverse bias potential applied, the generated charge causes avalanche multiplication and an avalanche current occurs.

[0101] Note that when a reverse biased potential is supplied to the photoelectric conversion unit 201 and the potential difference between the anode and the cathode is greater than the breakdown voltage, the avalanche diode is in Geiger mode operation. A photodiode that quickly detects weak signals at the level of a single photon by using Geiger mode operation is a single photon avalanche diode (SPAD).

[0102] In addition, when the potential difference between the anode and cathode of the photoelectric conversion unit 201 is greater than or equal to the potential difference that causes avalanche multiplication of the charge generated in the photoelectric conversion unit 201 and is less than or equal to the breakdown voltage, the avalanche diode is in linear mode. An avalanche diode that performs light detection in linear mode is called an avalanche photodiode (APD). In the present embodiment, the photoelectric conversion unit 201 can operate as any of the above-mentioned avalanche diodes. Note that the potential difference that causes avalanche multiplication is about 6V or more.

[0103] The control unit 202 has a function of replacing the change in the avalanche current generated in the photoelectric conversion unit 201 with a voltage signal. In addition, the control unit 202 is used as a load circuit (quenching circuit) when performing signal amplification by avalanche multiplication. The load circuit performs a quenching operation to change the voltage supplied to the photoelectric conversion unit 201 and suppress avalanche multiplication. For example, the control unit 202 may include a resistor element or an active quenching circuit. The active quenching circuit is a circuit that actively suppresses avalanche multiplication by detecting an increase in the avalanche current and performing feedback control.

[0104] The pixel signal processing unit 102 has a waveform shaping unit 203, a counter circuit 204, and a selector circuit 206. The waveform shaping unit 203 shapes the voltage change caused by the signal at the single photon level and outputs a pulse signal. The pulse signal indicates the incidence of a photon. For example, Figure 7 As shown, an inverter circuit is used in the waveform shaping unit 203. Figure 7 An example of using a single inverter as the waveform shaping unit 203 is shown, but the waveform shaping unit 203 may be a circuit in which a plurality of inverters are connected in series, or may be other circuits as long as the circuit has a waveform shaping effect.

[0105] The pulse signal output from the waveform shaping unit 203 is counted by the counter circuit 204. For example, an N-bit counter (N is a positive integer) is set in the counter circuit 204, and the N-bit counter can count the input pulse signal up to a maximum of about 2 to the Nth power and hold the counted value. The signal obtained by counting is held in the counter circuit 204 as a signal indicating the detection result of the incident light. In addition, the control pulse pRES is supplied to the counter circuit 204 from the vertical scanning circuit 103 via the drive line 207. The counter circuit 204 resets the held signal in response to the control pulse pRES being input.

[0106] The control pulse pSEL is supplied from the vertical scanning circuit 103 to the selector circuit 206 via the driving line 208. The selector circuit 206 switches the electrical connection or disconnection between the counter circuit 204 and the signal line 107 based on the control pulse pSEL. For example, a transistor, a buffer circuit for outputting a signal to the outside of the pixel, or the like can be used for the selector circuit 206.

[0107] When the pixel unit 106 has a configuration in which a plurality of pixels 100 are arranged in a matrix, the capture operation may be a rolling shutter operation or a global electronic shutter operation. For example, the rolling shutter operation is realized by sequentially resetting the value counted by the counter circuit 204 row by row and sequentially outputting the signal held in the counter circuit 204 row by row.

[0108] In addition, the global electronic shutter operation is realized by simultaneously resetting the values ​​counted by the counter circuit 204 on all pixel rows and sequentially outputting the signals held by the counter circuit 204 row by row. Note that when the global electronic shutter operation is applied, it is desirable to provide a switching member using a switch or the like so as to be able to switch whether counting is performed by the counter circuit 204.

[0109] FIG. 8A to FIG. 8F It is shown Figure 6 and Figure 7 A schematic plan view and a schematic cross-sectional view of an example of a configuration in which two avalanche diodes are arranged diagonally inside a substantially square area. A plurality of avalanche diodes of the photoelectric conversion device 10 are arranged in a matrix forming a plurality of rows and a plurality of columns, wherein FIG. 8A to FIG. 8F The two avalanche diodes shown in are defined as one unit. Fig. 8A is a schematic plan view at depth X, Figure 8B is a schematic plan view at a depth Y, and Figure 8C is a schematic plan view at depth Z. In addition, Fig.8D is a schematic cross-sectional view taken along line SL1-SL1', Fig. 8E is a schematic cross-sectional view taken along line SL2-SL2', and Fig.8F is a schematic cross-sectional view taken along line SL3 - SL3 ′.

[0110] like Fig. 8A As shown, the two first semiconductor regions 71 are respectively contained in the two second semiconductor regions 76 at the depth X. In addition, the two second semiconductor regions 76 are respectively contained in different parts of the isolation portion 16A. The first semiconductor region 71 and the isolation portion 16A are arranged so that the distance between the first semiconductor region 71 and the isolation portion 16A is the distance R in all directions. In other words, the first semiconductor region 71 is arranged so that the distance between the first semiconductor region 71 and the isolation portion 16A is the largest. The two first semiconductor regions 71 are arranged on the diagonal of the square formed by the isolation portion 16A. The isolation portion 16A is arranged to extend in a diagonal direction (a direction different from any direction in the rows and columns formed by the avalanche diodes) between the two first semiconductor regions 71 so as to diagonally isolate the two second semiconductor regions 76. In this way, when the two avalanche diodes are arranged in a square area, the distance R can be increased by arranging the first semiconductor region 71 on the diagonal. Thus, the distance R can be about 1.17 times the distance in the case where the two first semiconductor regions 71 are arranged in the horizontal direction.

[0111] like Figure 8BAs shown, each third semiconductor region 74 is included in each fourth semiconductor region 72 at a depth Y. In addition, the fourth semiconductor region 72 is included in the isolation portion 16B.

[0112] like Figure 8C As shown, the two fifth semiconductor regions 75 are respectively included in different parts of the isolation portion 16B at a depth Z. The isolation portion 16B is arranged to extend in the vertical direction between the two fifth semiconductor regions 75 so as to isolate the two second semiconductor regions 76 from each other in the horizontal direction. Figure 8C , the position of the microlens ML that guides the incident light to the two fifth semiconductor regions 75 is shown by a dotted line. The positions of the two fifth semiconductor regions 75 are arranged symmetrically about the center position of the microlens ML in the horizontal direction. That is, the two avalanche diodes of this embodiment have two sensitivity regions that are optically conjugate with one microlens ML. Thus, the signals obtained from the two avalanche diodes can be used as signals for phase difference autofocusing.

[0113] refer to Fig. 9 , the positional relationship between the isolation portion 16A and the isolation portion 16B will be described in more detail. Fig. 9 yes Fig. 8A The isolation portion 16A and Figure 8B The isolation portion 16B is overlapped for illustration in a schematic plan view. Fig. 9 As shown, the isolation portion 16A includes a first portion P1 extending in the x1 direction (first direction). In addition, the isolation portion 16B includes a second portion P2 extending in the x2 direction (second direction) intersecting the x1 direction in a plan view. In this case, a portion of the first portion P1 and a portion of the second portion P2 overlap each other in an overlapping portion P3 in a plan view.

[0114] As described above, in the present embodiment, a portion of the isolation portion 16A isolating the two first semiconductor regions 71 from each other and a portion of the isolation portion 16B isolating the two fifth semiconductor regions 75 from each other intersect each other in a plan view. That is, the shape of the isolation portion 16A and the shape of the isolation portion 16B are different from each other in a plan view. More specifically, a portion of the first portion P1 of the isolation portion 16A and a portion of the second portion P2 of the isolation portion 16B overlap each other in an overlapping portion P3 in a plan view. Thus, a photoelectric conversion device 10 having improved layout flexibility is provided, and the shape of the avalanche region and the shape of the sensitivity region can be designed to be suitable for the respective characteristics.

[0115] More specifically, the isolation section 16A of the present embodiment is arranged to extend in the diagonal direction so that the distance R is maximum when two avalanche diodes are arranged in a square area. In contrast, since the sensitivity regions need to be arranged symmetrically in the horizontal direction in the drawing in consideration of the direction in which the phase difference for phase difference autofocus is obtained, the isolation section 16B of the present embodiment is arranged to extend in the vertical direction. In other words, since the required characteristics and design constraints are different for the isolation section 16A defining the avalanche region and the isolation section 16B defining the sensitivity region, these regions are designed to have different shapes from each other. In this way, by making the shape of the isolation section 16A and the shape of the isolation section 16B different from each other, it is possible to achieve the effect of reducing the noise caused by the tunnel effect caused by the increased distance R, and to achieve the need to obtain a signal for phase difference autofocus. In addition, since the distance R can be increased by arranging two avalanche diodes diagonally inside the square area, when the maximum value of the distance R is constrained, the size of the pixel can be reduced by adopting the configuration of the present embodiment. Thus, the number of pixels can be increased, and the advantage of improved image quality can be obtained.

[0116] Note that, although each peripheral shape of the isolating portion 16A and the isolating portion 16B is a square in the present embodiment, the peripheral shape is not limited thereto. For example, each peripheral shape of the isolating portion 16A and the isolating portion 16B may be a rectangle (including a square), and two avalanche diodes may be arranged inside the rectangular area. Also in this case, the isolating portion 16A is arranged to extend in the diagonal direction so that the distance R when the two avalanche diodes are arranged is maximized. Third embodiment

[0117] A photoelectric conversion device according to a third embodiment will be described. In the description of this embodiment, features having the same functions as those of the first embodiment or the second embodiment are denoted by the same reference numerals, and detailed descriptions thereof may be omitted or simplified.

[0118] The photoelectric conversion device of the present embodiment is an apparatus in which the photoelectric conversion device of the second embodiment is applied to a back-illuminated photoelectric conversion device. Fig.10 is a schematic cross-sectional view of a photoelectric conversion device according to the present embodiment. Fig.10 The color filter CF1 and the color filter CF2 and the micro lens ML are added along Fig. 8A , Figure 8B and Figure 8C 1-1 ' is a schematic cross-sectional view of the embodiment of the present invention. Fig.10 As shown, the color filters CF1 and CF2 and the microlens ML are arranged on the second surface side of the semiconductor substrate 15 .

[0119] The incident light sequentially passes through the microlens ML and the color filter CF1 or the color filter CF2, and is received from the second surface side of the semiconductor substrate 15. The color filter CF1 and the color filter CF2 transmit light of different colors from each other. The microlens ML is shared by two avalanche diodes, and the light passing through the microlens ML is guided to either of the two avalanche diodes. Note that although Fig.10 One microlens ML is arranged in association with two avalanche diodes, but the arrangement is not limited thereto. That is, one microlens ML may be arranged to correspond to two or more avalanche diodes.

[0120] As described above, the photoelectric conversion device of this embodiment is a back-illuminated type in which the second surface opposite to the first surface provided with the wiring layer is a light receiving surface. Therefore, in the photoelectric conversion device of this embodiment, the sensitivity is further improved compared with the case of the front-illuminated type. Fourth embodiment

[0121] A photoelectric conversion device according to a fourth embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to third embodiments are denoted by the same reference numerals, and detailed descriptions thereof may be omitted or simplified.

[0122] The photoelectric conversion device of the present embodiment is an apparatus in which the photoelectric conversion device of the third embodiment is applied to a stacked-type photoelectric conversion device. Fig.11 is a schematic cross-sectional view of a photoelectric conversion device according to the present embodiment. Fig.11 Color filters CF1 and CF2, micro lenses ML, and semiconductor substrate 17 are added along Fig. 8A , Figure 8B and Figure 8C 1-1 '. In the same manner as in the third embodiment, the color filter CF1 and the color filter CF2 and the microlens ML are arranged on the second face side of the semiconductor substrate 15. In addition, the semiconductor substrate 17 is bonded to the first face side of the semiconductor substrate 15 via the bonding interface 18, and is mechanically and electrically connected to the semiconductor substrate 15. A signal processing circuit such as the pixel signal processing unit 102 that processes a signal output from the avalanche diode is included in the semiconductor substrate 17.

[0123] As described above, the photoelectric conversion device of the present embodiment is a stacked type in which the semiconductor substrate 15 (first substrate) and the semiconductor substrate 17 (second substrate) are stacked in addition to being a back-illuminated type as in the third embodiment. The avalanche diode is arranged in the semiconductor substrate 15, and the signal processing circuit is arranged in the semiconductor substrate 17. Thus, compared with the case where the avalanche diode and the signal processing circuit are arranged in a single substrate, the sensitivity region of the avalanche diode can be wide, and the sensitivity is further improved. Fifth embodiment

[0124] A photoelectric conversion device according to a fifth embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to fourth embodiments are marked with the same reference numerals, and their detailed descriptions may be omitted or simplified. Unlike the first to fourth embodiments, the photoelectric conversion device of this embodiment is an image sensor having a photodiode that does not use avalanche multiplication. The photoelectric conversion device of this embodiment has not only a function of outputting a signal for capturing, but also a function of outputting a signal for image plane phase difference autofocusing.

[0125] Fig.12 is a block diagram of a photoelectric conversion device 60 according to the present embodiment. The photoelectric conversion device 60 has a pixel unit 61, a control pulse generating unit 109, a horizontal scanning circuit 104, a column circuit 105, a signal line 107, an output circuit 108, and a vertical scanning circuit 103. Since the configurations of the control pulse generating unit 109, the horizontal scanning circuit 104, the column circuit 105, the signal line 107, the output circuit 108, and the vertical scanning circuit 103 are substantially the same as those of the second embodiment, description thereof will be omitted.

[0126] The pixel unit 61 has a plurality of pixels 600 arranged to form a plurality of rows and columns. Each pixel 600 has a photodiode that converts incident light into an electrical signal.

[0127] Fig.13 6 is an example of an equivalent circuit diagram of a pixel 600 according to the present embodiment. The pixel 600 has photoelectric conversion units PD1 and PD2, transfer transistors M1A and M1B, a reset transistor M2, an amplifying transistor M3, and a selecting transistor M4. Each of these transistors may be an N-channel MOS transistor. A control signal PTX1 is input to the gate of the transfer transistor M1A from the vertical scanning circuit 103. A control signal PTX2 is input to the gate of the transfer transistor M1B from the vertical scanning circuit 103. A control signal PRES is input to the gate of the reset transistor M2 from the vertical scanning circuit 103. A control signal PSEL is input to the gate of the selecting transistor M4 from the vertical scanning circuit 103.

[0128] Each of the photoelectric conversion units PD1 and PD2 generates and accumulates charges by photoelectric conversion according to incident light. Each of the photoelectric conversion units PD1 and PD2 is not an avalanche diode as described in the first to fourth embodiments, but a typical photodiode that does not use avalanche amplification. Each anode of the photoelectric conversion units PD1 and PD2 is connected to a ground potential line. The cathode of the photoelectric conversion unit PD1 is connected to the source of the transfer transistor M1A. The cathode of the photoelectric conversion unit PD2 is connected to the source of the transfer transistor M1B.

[0129] The connection node of the drains of the transfer transistors M1A and M1B, the source of the reset transistor M2, and the gate of the amplifier transistor M3 forms a floating diffusion FD. The drain of the reset transistor M2 and the drain of the amplifier transistor M3 are connected to a power supply potential line having a potential VDD. The source of the amplifier transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the signal line 107. The signal line 107 is connected to a current source (not shown).

[0130] When the control signal PRES is controlled to a high level and the reset transistor M2 is turned on, the potential of the floating diffusion FD is reset. When the control signal PTX1 is controlled to a high level and the transfer transistor M1A is turned on, the charge accumulated in the photoelectric conversion unit PD1 is transferred to the floating diffusion FD. When the control signal PTX2 is controlled to a high level and the transfer transistor M1B is turned on, the charge accumulated in the photoelectric conversion unit PD2 is transferred to the floating diffusion FD. When the control signal PSEL is controlled to a high level and the selection transistor M4 is turned on, the amplifier transistor M3 and the current source connected to the signal line 107 form a source follower circuit. At this time, a voltage according to the potential of the floating diffusion FD is output to the signal line 107.

[0131] With such a configuration, the photoelectric conversion device of this embodiment can independently output signals based on the charges accumulated in the two photoelectric conversion units PD1 and PD2. In addition, the photoelectric conversion device of this embodiment can sum the charges accumulated in the two photoelectric conversion units PD1 and PD2 and output a signal based on the sum.

[0132] Fig.14 is a schematic plan view of a photodiode according to the present embodiment. Fig.14 1 shows the positional relationship between the microlens ML forming a part of the photodiode and the two N-type semiconductor regions 601. Fig.14 , the position of the microlens ML that guides incident light to the two N-type semiconductor regions 601 is shown by a dotted line. Fig.14 The two N-type semiconductor regions 601 are respectively connected to Fig.13The positions of the two N-type semiconductor regions 601 are arranged symmetrically about the center position of the microlens ML in the horizontal direction. That is, the two photodiodes of this embodiment have two sensitivity regions that are optically conjugate with one microlens ML. Therefore, the signals obtained from the two photodiodes can be used as signals for image plane phase difference autofocus.

[0133] Fig.15 is a schematic cross-sectional view of a photodiode according to the present embodiment. Fig.15 Schematically shows the Fig.14 The photodiodes of the present embodiment are arranged in a semiconductor substrate 15 (first substrate). The semiconductor substrate 15 has a first surface and a second surface opposite to the first surface. For example, the first surface is the front surface of the semiconductor substrate 15, and the second surface is the back surface of the semiconductor substrate 15. In the present embodiment, the direction from the first surface to the second surface is referred to as the depth direction. On the front side of the semiconductor substrate 15, gate electrodes of transistors, multilayer wiring structures, etc. are arranged. On the back side of the semiconductor substrate 15, microlenses ML corresponding to the two photodiodes are arranged.

[0134] like Fig.15 As shown, a P-type semiconductor region 604 and a region surrounded by the P-type semiconductor region 604 are formed in a semiconductor substrate. N-type semiconductor regions 601, 602, and 603 are arranged in the region surrounded by the P-type semiconductor region 604.

[0135] The N-type semiconductor region 602 is arranged at a depth D1 (first depth). The N-type semiconductor region 603 is arranged at a depth D2 deeper than the depth D1 relative to the first surface. The N-type semiconductor region 601 is arranged at a depth D3 (second depth) deeper than the depth D2 relative to the first surface. The N-type semiconductor region 602 and the N-type semiconductor region 603 are in contact in the depth direction, and the N-type semiconductor region 603 and the N-type semiconductor region 601 are in contact in the depth direction.

[0136] Fig.16 is a schematic cross-sectional view of a photodiode according to the present embodiment. Fig.16 It is used for Fig.15 The same cross section shows a more detailed view of the structure of the P-type semiconductor region 604. The P-type semiconductor region 604 includes regions 604a, 604b, 604c, 604d, 604e, and 604f.

[0137] The region 604a is arranged to surround the N-type semiconductor regions 601, 602, and 603 from the depth D1 to the depth D3. The region 604a serves as an isolation region between adjacent pixels.

[0138] The region 604 b (first isolation region) is arranged between the two N-type semiconductor regions 602 at the depth D1 . The region 604 b serves as an isolation region between the two N-type semiconductor regions 602 .

[0139] The region 604 c (second isolation region) is arranged between the two N-type semiconductor regions 601 at the depth D3 . The region 604 c serves as an isolation region between the two N-type semiconductor regions 601 .

[0140] The region 604d (third isolation region) is arranged to contact the N-type semiconductor region 601 and the N-type semiconductor region 602 in the depth direction. The region 604d isolates the other parts except for a part of the region between the N-type semiconductor region 601 and the N-type semiconductor region 602 (the part where the N-type semiconductor region 603 is arranged) from each other. In other words, the N-type semiconductor region 601 and the N-type semiconductor region 602 are connected via the N-type semiconductor region 603.

[0141] The region 604e is arranged on the first surface side of the two N-type semiconductor regions 602 and the region 604b. The region 604f is arranged on the second surface side of the two N-type semiconductor regions 601 and the region 604c.

[0142] Once light enters the back side of the semiconductor substrate 15 via the microlens ML, electrons appear in the N-type semiconductor region 601 by photoelectric conversion. That is, the N-type semiconductor region 601 serves as a sensitivity region (first region) of the photoelectric conversion device. These electrons (signal charges) move to the N-type semiconductor region 602 via the N-type semiconductor region 603. That is, the N-type semiconductor region 602 serves as an accumulation region (second region) in which the charges of the photoelectric conversion device are accumulated. The N-type semiconductor region 603 (third region) corresponds to the transfer path of the electrons from the N-type semiconductor region 602 to the N-type semiconductor region 601. In order to achieve this, it is desired that the potential of the electrons monotonically increases on the transfer path of the electrons from the N-type semiconductor region 602 to the N-type semiconductor region 601.

[0143] Fig.17 is a schematic cross-sectional view of a photodiode according to the present embodiment. Fig.17 It is aimed at Fig.15 and Fig.16The same cross section shows a diagram of a structure for transferring charges in more detail. The semiconductor substrate 15 includes a semiconductor region 605 forming a floating diffusion portion FD. In addition, each gate electrode 606 of the transfer transistors M1A and M1B is arranged on the first surface at a position corresponding to the P-type semiconductor region 604 between the N-type semiconductor region 602 and the semiconductor region 605. By controlling the voltage of the gate electrode 606, the charge accumulated in the semiconductor region 602 can be transferred to the semiconductor region 605. Note that although Fig.17 The two semiconductor regions 605 are shown as separate regions, but as Fig.13 As shown, Fig.17 The two semiconductor regions 605 in may be nodes which are electrically connected to each other and have the same potential.

[0144] Fig.18 is a schematic plan view of a pixel 600 according to the present embodiment. Fig.18 Shows Fig.13 An example of a specific layout of the circuit of pixel 600 is shown in FIG. Fig.18 The semiconductor region and the position of the microlens ML where the photodiode, transistor, etc. are formed are shown. Fig.18 The gate electrodes 606 of the transfer transistors M1A and M1B, the gate electrode 607 of the reset transistor M2, the gate electrode 608 of the amplification transistor M3, and the gate electrode 609 of the selection transistor M4 are shown. Fig.18 Wiring WL connecting these components to each other is also shown.

[0145] The gate electrodes 606 of the transfer transistors M1A and M1B are arranged in a plan view between the N-type semiconductor region 602 and the semiconductor region 605. The semiconductor region 605 is connected to the semiconductor region 610 forming the main electrode of the reset transistor M2 and the gate electrode 608 of the amplification transistor M3 via the wiring WL. The wiring WL is connected to the gate electrodes 606, 607, and 609, and a control signal is input from the vertical scanning circuit 103 to the gate electrodes 606, 607, and 609 via the wiring WL.

[0146] Wiring WL serving as a power supply potential line having a potential VDD is connected to a semiconductor region 611 forming main electrodes of the reset transistor M2 and the amplifier transistor M3. Wiring WL serving as a signal line 107 for externally outputting a signal voltage is connected to a semiconductor region 612 forming a main electrode of the selection transistor M4.

[0147] In the present embodiment, the N-type semiconductor region 601 and the N-type semiconductor region 602 are connected via the N-type semiconductor region 603. Thus, the N-type semiconductor region 601 and the N-type semiconductor region 602 may have shapes different from each other in a plan view. In addition, since the N-type semiconductor region 601 and the N-type semiconductor region 602 may be designed independently of each other with respect to their positional relationship, various specific forms of positional relationships may exist between the N-type semiconductor region 601 and the N-type semiconductor region 602. Two types of arrangement examples of the N-type semiconductor region 601 and the N-type semiconductor region 602 will be described.

[0148] Fig.19A , Fig.19B and Fig.19C is a schematic diagram showing a first example of the arrangement of semiconductor regions according to the present embodiment. Fig.19A 601, 602, and 603, a semiconductor region 605, and a gate electrode 606. Fig.19A As shown, each of the N-type semiconductor region 601 and the N-type semiconductor region 602 has a rectangular parallelepiped shape extending in the depth direction of the drawing sheet. That is, the N-type semiconductor region 601 and the N-type semiconductor region 602 extend in the same direction.

[0149] Fig.19B 601, 602, and 603, a semiconductor region 605, and a gate electrode 606. Fig.19B As shown, all the N-type semiconductor regions 601 and the N-type semiconductor regions 602 extend in the vertical direction of the drawing. In other words, the two N-type semiconductor regions 601 are arranged adjacent to each other in the horizontal direction of the drawing, and the two N-type semiconductor regions 602 are also arranged adjacent to each other in the horizontal direction of the drawing. In such a configuration, since the N-type semiconductor regions 601 from which charges are generated by photoelectric conversion are arranged at positions spaced apart in the horizontal direction, a signal for image plane phase difference autofocus can be obtained that can mainly detect parallax in the horizontal direction. Fig.19B , the direction of phase difference detection is indicated by arrow 613.

[0150] Fig.19C 604b serving as an isolation region between the N-type semiconductor regions 602 and the region 604c serving as an isolation region between the N-type semiconductor regions 601 in a plan view. Fig.19C As shown, both the region 604b and the region 604c extend in the vertical direction of the drawing.

[0151] Fig. 20A , Fig. 20B and Fig. 20C is a schematic diagram showing a second example of the arrangement of the semiconductor region according to the present embodiment. Fig.19A , Fig.19B and Fig.19C The main difference lies in the arrangement of the semiconductor region 601 .

[0152] like Fig. 20A As shown, each N-type semiconductor region 602 has a rectangular parallelepiped shape extending in the depth direction of the drawing, and each N-type semiconductor region 601 has a rectangular parallelepiped shape extending in the horizontal direction of the drawing. That is, the N-type semiconductor region 601 and the N-type semiconductor region 602 extend in directions orthogonal to each other in a plan view, that is, in different directions.

[0153] like Fig. 20B As shown, each N-type semiconductor region 602 extends in the vertical direction of the drawing, and each N-type semiconductor region 601 extends in the horizontal direction of the drawing. In other words, the two N-type semiconductor regions 601 are arranged adjacent to each other in the vertical direction of the drawing, and the two N-type semiconductor regions 602 are arranged adjacent to each other in the horizontal direction of the drawing. In such a configuration, since the N-type semiconductor regions 601 from which charges are generated by photoelectric conversion are arranged at positions spaced apart in the vertical direction, a signal for image plane phase difference autofocusing that can mainly detect parallax in the vertical direction can be obtained. Fig. 20B , the direction of phase difference detection is indicated by arrow 614.

[0154] Fig. 20C 604b serving as an isolation region between the N-type semiconductor regions 602 and the region 604c serving as an isolation region between the N-type semiconductor regions 601 in a plan view. Fig. 20C As shown, region 604b extends in the vertical direction of the drawing, and region 604c extends in the horizontal direction of the drawing. That is, region 604b and region 604c extend in directions orthogonal to each other in the plan view, that is, in different directions.

[0155] Fig.21A and Fig.21B is a schematic plan view showing an arrangement example of the pixels 600 . Fig.21A Shows Fig.19A , Fig.19B and Fig.19C 1 and 2. An example in which the pixels 600 of the first example are arranged in a matrix. In this example, an arrow 613 indicating the direction of phase difference detection is oriented in the horizontal direction. Fig.21B Shows Fig. 20A , Fig. 20B and Fig. 20C00 is an example in which the pixels 600 of the second example are arranged in a matrix. In this example, an arrow 614 indicating the direction of phase difference detection is oriented in the vertical direction.

[0156] As described above, each pixel 600 of the present embodiment has an N-type semiconductor region 602 arranged at a depth D1 and an N-type semiconductor region 601 arranged at a depth D3 deeper than the depth D1 relative to the first surface. In the case where the N-type semiconductor region 601 has a sufficient thickness, most of the light received from the second surface side is absorbed by the N-type semiconductor region 601 and does not reach the N-type semiconductor region 602. Thus, the N-type semiconductor region 601 serves as a sensitive region for generating charges from incident light by photoelectric conversion. The charges generated in the N-type semiconductor region 601 move to the N-type semiconductor region 602 via the N-type semiconductor region 603 and accumulate in the N-type semiconductor region 602. That is, the N-type semiconductor region 602 serves as an accumulation region for accumulating charges generated by photoelectric conversion.

[0157] In this way, the N-type semiconductor region 601 and the N-type semiconductor region 602 are located at different positions in the thickness direction of the substrate, and therefore have different functions from each other. Therefore, the plan view shapes of the N-type semiconductor region 601 and the N-type semiconductor region 602 can be designed to be different according to the purpose. From another point of view, the region 604b used as the isolation region between the N-type semiconductor regions 602 and the region 604c used as the isolation region between the N-type semiconductor regions 601 can be designed to have different shapes in a plan view.

[0158] exist Fig.19B and Fig.21A In the first example, two N-type semiconductor regions 601 are arranged adjacent to each other in the horizontal direction of the drawing, and a signal for image plane phase difference autofocus that can mainly detect parallax in the horizontal direction can be obtained. This design is more useful when the subject has a pattern close to a vertical stripe pattern. In contrast, in Fig. 20B and Fig.21BIn the second example, two N-type semiconductor regions 601 are arranged adjacent to each other in the vertical direction of the drawing, and a signal for image plane phase difference autofocusing that can mainly detect parallax in the vertical direction can be obtained. This design is more useful when the subject has a pattern close to a horizontal stripe pattern. In this way, by changing the shape of the N-type semiconductor region 601 used as the sensitivity region in consideration of the expected subject characteristics, different detection directions can be provided in image plane phase difference autofocusing. In the above two examples, the N-type semiconductor region 602 used as the accumulation region has the same design. In addition, between the two examples, the designs of the gate electrode 606, the semiconductor region 605, the wiring WL, etc. can also be the same. That is, since the design of parts other than the sensitivity region can be common without depending on the shape of the accumulation region, the design is simplified.

[0159] As described above, according to the present embodiment, a photoelectric conversion device can be provided that can optimize the structure of the photodiode that outputs a signal for image plane phase difference autofocus in consideration of the position in the thickness direction of the substrate. Thus, a photoelectric conversion device that can output a signal in an appropriate parallax detection direction according to the shape of the subject is provided.

[0160] Note that even in the case of a circuit configuration using a typical photodiode as in this embodiment, a structure in which a first substrate on which a photodiode is arranged and a second substrate on which a signal processing circuit is arranged are stacked can be applied in the same manner as in the fourth embodiment. In this case, the area of ​​the sensitivity region of the photodiode can be wider, and the sensitivity is further improved. Sixth embodiment

[0161] The photoelectric conversion device according to the sixth embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to fifth embodiments will be marked with the same reference numerals, and their detailed descriptions may be omitted or simplified. The photoelectric conversion device of this embodiment is a modified example of the arrangement of the pixel 600 described in the fifth embodiment.

[0162] Fig. 22 is a schematic plan view of a pixel according to the present embodiment. Fig. 22 4 pixels of two rows by two columns are shown, and the arrangement of N-type semiconductor regions 601 and 603, semiconductor region 605, gate electrode 606, and microlens ML is shown. Fig.19B and Fig. 20B The arrangement of the N-type semiconductor region 602 is the same, so Fig. 22 The illustration is omitted.

[0163] exist Fig. 22In the upper left pixel of FIG. 1 , two N-type semiconductor regions 601 (the first photodiode group corresponding to the first microlens ML) are connected to Fig. 20B In the same way as in the vertical direction of the drawing, they are arranged adjacent to each other. Fig. 22 In the pixels adjacent to the upper left pixel of the image (the upper right pixel and the lower left pixel), two N-type semiconductor regions 601 (the second photodiode group corresponding to the second microlens ML) are connected to the pixel adjacent to the upper left pixel of the image. Fig.19B are arranged adjacent to each other in the horizontal direction of the drawing in the same manner.

[0164] Fig.23 is a schematic plan view showing an arrangement example of the pixels 600 . Fig.23 Shows a repeated arrangement Fig. 22 An example of four pixels of two rows by two columns defined as one unit is shown in FIG. In this example, with respect to the orientation of arrows 613 and 614 indicating the direction of phase difference detection, the horizontal direction and the vertical direction are repeated alternately.

[0165] In this embodiment, the pixel unit 61 includes Fig.19B The first example shown in FIG. 1 can mainly detect pixels of parallax in the horizontal direction and in Fig. 20B The second example shown in FIG. 6 shows two pixels that can mainly detect parallax in the vertical direction. Therefore, multiple pairs of signals for image plane phase difference autofocus with different detection directions can be obtained. This enables accurate focus detection with less reliance on the shape of the subject from the plurality of pixels 600 of the pixel unit 61. For example, when the subject has a stripe pattern, stable focus detection accuracy can be obtained regardless of the direction of the stripes. As described above, in the present embodiment, a photoelectric conversion device that can implement focus detection according to various situations is provided.

[0166] Note that although in the above example, the combination of the orientations of arrows 613 and 614 indicating the direction of phase difference detection is a combination of only two types of directions, the horizontal direction and the vertical direction, a combination of two types of directions other than the above may be adopted, or a combination of three or more types of directions may be adopted. Fig.24 is a schematic plan view of a pixel according to a modification of this embodiment. Fig.24 As shown, when the shapes of the two N-type semiconductor regions 601 are triangles adjacent to each other in a diagonal direction, the direction of phase difference detection indicated by arrow 615 may be a diagonal direction. Fig.24 The pixel 600 having the configuration is included in the pixel unit 61, and signals for image plane phase difference autofocusing can be obtained in more detection directions. Seventh embodiment

[0167] The photoelectric conversion device according to the seventh embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to sixth embodiments will be marked with the same reference numerals, and their detailed descriptions may be omitted or simplified. The photoelectric conversion device of this embodiment is a modification of the arrangement of the pixel 600 described in the fifth and sixth embodiments.

[0168] Fig.25 is a schematic plan view of a pixel according to the present embodiment. Fig.25 With Fig. 22 Four pixels of two rows by two columns are shown in the same manner, and the arrangement of N-type semiconductor regions 601 and 603, semiconductor region 605, and gate electrode 606 is shown. Note that the illustration of microlens ML is omitted. In addition, Fig.25 2 shows the arrangement of color filters CFR, CFG, and CFB provided in association with each pixel. Fig.10 In the same manner as in , it is arranged between the microlens ML and the second surface of the semiconductor substrate.

[0169] The color filter CFR is a color filter that transmits red light, and one color filter CFR is set in four pixels of two rows by two columns. The color filter CFG is a color filter that transmits green light, and two color filters CFG are set in four pixels of two rows by two columns. The color filter CFB is a color filter that transmits blue light, and one color filter CFB is set in four pixels of two rows by two columns. Fig.25 The arrangement scheme of the color filters CFR, CFG, and CFB is called a Bayer arrangement, however, this is an example and another arrangement scheme may be adopted. Hereinafter, pixels provided with the color filters CFR, CFG, and CFB may be referred to as red pixels, green pixels, and blue pixels, respectively.

[0170] like Fig.25 As shown, in this embodiment, Fig.19B The pixels that can mainly detect parallax in the horizontal direction shown in the first example are green pixels, and Fig. 20B The pixel that can mainly detect the parallax in the vertical direction shown in the second example is a red pixel or a blue pixel. In this way, in the present embodiment, pixels for different detection directions have color filters of different colors.

[0171] Since the focus can be detected more accurately when the colors are not mixed in the comparison of the signal for the image plane phase difference autofocus, it is desirable that the color is the same in each detection direction. Therefore, in the present embodiment, the arrangement of the color filters is set so that the pixels for different detection directions have color filters of different colors. Therefore, according to the present embodiment, even with a photoelectric conversion device set for color image capture, accurate focus detection can be performed.

[0172] Note that in Fig.25 In the configuration of, although each signal output from the red pixel, the green pixel, and the blue pixel can be used for the image plane phase difference autofocus, the signals of all these colors may be used or the signals of one or two of these colors may be used. Since the light absorption rate of the silicon substrate is higher for green than for red or blue, the green pixel has a higher sensitivity than the other pixels. Therefore, it is desirable that at least the signal output from the green pixel is used for the image plane phase difference autofocus.

[0173] Fig.25 The association relationship of the N-type semiconductor region 601 and the arrangement of the color filter in FIG. 1 is an example, and another association relationship may be adopted. Fig.26 is a schematic plan view of a pixel according to a modification example of the present embodiment. Fig.26 The arrangement of the N-type semiconductor region 601 is different from that of the modified example. Fig.25 Specifically, one of the two green pixels is Fig.19B The first example shown in FIG. 1 can mainly detect the pixel of the parallax in the horizontal direction, and the other is Fig. 20B The second example shown in FIG. 1 can mainly detect the pixels of parallax in the vertical direction. In such a configuration, the signal output from the green pixel with high sensitivity can be used for focus detection in both detection directions. Note that the signal output from one or both of the red pixel and the blue pixel can be further used for focus detection. Eighth embodiment

[0174] The photoelectric conversion device according to the eighth embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to seventh embodiments will be marked with the same reference numerals, and their detailed descriptions may be omitted or simplified. The photoelectric conversion device of this embodiment is an example in which the photodiode of the pixel 600 described in the fifth embodiment is replaced by an avalanche diode. The detailed structure of the avalanche diode, the operation of avalanche multiplication, etc. are the same as those described in the first embodiment.

[0175] Fig. 276 is a schematic cross-sectional view of an avalanche diode according to the present embodiment. The semiconductor substrate 15 of the present embodiment has a semiconductor region 616, which is used as a region for collecting charges from the N-type semiconductor regions 601 and 602 and is used as a terminal for obtaining a signal. The semiconductor region 616 is a portion corresponding to the first semiconductor region 71 of the first embodiment. In addition, in the cross-sectional structure of the pixel 600 of the present embodiment, neither the gate electrode 606 having a charge transfer function nor the semiconductor region 605 forming the floating diffusion portion FD of the fifth to seventh embodiments is provided.

[0176] Fig.28A and Fig.28B is a schematic plan view showing the arrangement of the N-type semiconductor regions 601 , 602 , and 603 and the semiconductor region 616 . Fig.28A is with reference Fig.19A The first example described corresponds to an example of an arrangement. Fig.28A In the configuration, you can Fig.19A In the same manner as the configuration, a signal for image plane phase difference autofocusing can be obtained that can mainly detect parallax in the horizontal direction. In addition, Fig.28B is with reference Fig. 20A The second example described corresponds to an example of an arrangement. Fig.28B In the configuration, you can Fig. 20A In the same manner, a signal for image plane phase difference autofocusing can be obtained by mainly detecting parallax in the depth direction.

[0177] Therefore, as in the present embodiment, when each photodiode is an avalanche diode that performs an avalanche multiplication operation, the same structure as that of the fifth to seventh embodiments can also be achieved. That is, a photoelectric conversion device is provided that can optimize the structure of the avalanche diode in consideration of the position in the thickness direction of the substrate. Ninth embodiment

[0178] A photoelectric conversion device according to a ninth embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to eighth embodiments will be labeled with the same reference numerals, and their detailed descriptions may be omitted or simplified. The photoelectric conversion device of this embodiment is an example in which a deep trench isolation (DTI) structure is used as an element isolation region between pixels of the pixel 600 described in the fifth embodiment.

[0179] Fig.29 is a schematic plan view of a photodiode according to the present embodiment, and Fig.30 is a schematic cross-sectional view of a photodiode according to the present embodiment. Fig.29 and Fig.30 The photodiode of the fifth embodiment Fig.14 , Fig.15 The difference between the photodiode of FIG. 1 and FIG. 2 is that a DTI structure 617 is added. Fig.29 As shown, the DTI structure 617 is arranged in a grid shape so as to surround the two N-type semiconductor regions 601 in a plan view. Fig.30 As shown, the DTI structure 617 is arranged in the side portions of the N-type semiconductor regions 601 and 602 .

[0180] Once electrons are generated in the N-type semiconductor region 601 in response to incident light, crosstalk caused by the transfer of electrons to adjacent pixels over the potential barrier of the P-type semiconductor region 604 may occur. In the case of a pixel configuration capable of capturing a color image, this crosstalk may cause color mixing. In addition, when the N-type semiconductor region 601 is so thick that the incident light from the second surface is unlikely to reach the N-type semiconductor region 602, this crosstalk may be significant. Therefore, in the present embodiment, a DTI structure 617 having good insulating properties is arranged in the side of the N-type semiconductor regions 601 and 602 as the transfer path of electrons to adjacent pixels, thereby reducing the impact of crosstalk. It is desirable that the DTI structure 617 is formed to reach substantially the same depth as the N-type semiconductor region 601 so as to be arranged at least on the side of the N-type semiconductor region 601 where electrons are generated. Tenth embodiment

[0181] A photoelectric conversion device according to a tenth embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to ninth embodiments will be denoted by the same reference numerals, and their detailed descriptions may be omitted or simplified. The photoelectric conversion device of this embodiment is a photoelectric conversion device in which the number of photodiodes corresponding to one microlens ML in the pixel 600 described in the fifth embodiment is reduced to one.

[0182] Fig.31 is a schematic plan view of a photodiode according to the present embodiment. Fig.32 is a schematic cross-sectional view of a photodiode according to the present embodiment. Fig.33 is a schematic perspective view of a photodiode according to the present embodiment. Fig.34 is a schematic plan view of a pixel according to this embodiment. Figure 31 to Figure 34 Only one N-type semiconductor region 602 (the third photodiode group corresponding to the third microlens ML) is provided in the pixel 600. In addition, the shape of the N-type semiconductor region 601 is deformed so as to substantially cover the entire microlens ML. Fig.14 , Fig.15 The characteristics of etc. are different.

[0183] like Fig.31 and Fig.32 As shown in FIG. 6 , only one N-type semiconductor region 602 is arranged on the left side of the pixel 600. Fig.31 and Fig.32 As shown, the N-type semiconductor region 601 is arranged so as to substantially cover the entire microlens ML. Fig.33 and Fig.34 As shown in FIG. 1 , since one N-type semiconductor region 602 is arranged, only one N-type semiconductor region 603 is arranged. Although the number of gate electrodes 606 may also be one, as shown in FIG. Fig.33 and Fig.34 As shown, it can be Fig.18 The two gate electrodes 606 are arranged in the same manner in order to maintain the symmetry of the arrangement.

[0184] The pixel 600 of this embodiment is not used to obtain a signal for image plane phase difference autofocusing, but is used to obtain a signal for capture. The single N-type semiconductor region 601 of this embodiment has an area approximately twice that of the fifth embodiment, and can generate twice the electrons of the fifth embodiment. Therefore, the sensitivity of a single output signal is approximately twice as high. In addition, since the number of gate electrodes 606 that need to be driven during readout is one, faster readout is achieved.

[0185] As described above, according to the present embodiment, a photoelectric conversion device that can perform fast and high-sensitivity capture is provided. The pixel 600 of the present embodiment is useful in the use of an electronic viewfinder or the like that requires fast and high-sensitivity capture. Fig.12 When some of the plurality of pixels 600 in the pixel unit 61 are used as the pixels 600 of the present embodiment, a reduced image for an electronic viewfinder can be quickly acquired with high sensitivity. Eleventh Embodiment

[0186] The photoelectric conversion device according to the eleventh embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to tenth embodiments will be marked with the same reference numerals, and their detailed descriptions may be omitted or simplified. The photoelectric conversion device of this embodiment is a photoelectric conversion device in which the shapes of the two N-type semiconductor regions 601 in the pixel 600 described in the fifth embodiment are different.

[0187] Fig.35 is a schematic plan view showing the arrangement of semiconductor regions according to the present embodiment. Fig.36 is a schematic cross-sectional view of a photodiode according to the present embodiment. Fig.37 is a schematic perspective view of a photodiode according to the present embodiment. Figure 35 to Figure 37 The pixel 600 of the fifth embodiment Fig.15 , Fig.19A , Fig.19B, Fig.19C The pixel of FIG. 60 is different in that the two N-type semiconductor regions 601 have shapes and areas different from each other.

[0188] like Fig.35 and Fig.36 As shown in FIG. 1 , the shapes and areas of the two N-type semiconductor regions 601 in the plan view and the cross-sectional view are different from each other. Fig.37 As shown, the two N-type semiconductor regions 601 have shapes and volumes different from each other.

[0189] At the pixel 600 far from the center of the pixel unit 61, light that has passed through the optical system of an imaging system such as a camera enters the imaging surface diagonally. Since the angle of the incident light affects the accuracy of the image plane phase difference autofocus, in order to reduce this influence, there is a scheme for arranging the microlens ML by shifting the optical axis from the center of the pixel 600. In this case, considering the shift of the optical axis of the microlens ML, it is desirable to shift the position of the N-type semiconductor region 601 as the sensitivity region from the center to have a different shape thereof. In such an arrangement, the areas of the two N-type semiconductor regions 601 are different from each other in a plan view.

[0190] In the present embodiment, since the shapes of the two N-type semiconductor regions 601 can be different from each other, the shapes of the two N-type semiconductor regions 601 can be appropriately designed in consideration of the position of the microlens ML inside the pixel unit 61 or the position of the coordinates. Thus, the accuracy of the image plane phase difference autofocusing is improved within a wide range inside the pixel unit 61. Alternatively, the range in which the image plane phase difference autofocusing can be performed inside the pixel unit 61 is expanded. It is noted that since the angle of the incident light to the pixel 600 gradually changes depending on the coordinates (image height) inside the pixel unit 61, in view of this change, it is desirable to gradually change the shapes of the N-type semiconductor regions 601 together according to the coordinates (image height) inside the pixel unit 61.

[0191] As described above, according to the present embodiment, the shapes of the two N-type semiconductor regions 601 are made different, thereby providing a photoelectric conversion device with improved accuracy of image plane phase difference autofocusing. Twelfth Embodiment

[0192] A photoelectric conversion device according to a twelfth embodiment will be described. In the description of this embodiment, features having the same functions as those of the first to eleventh embodiments will be labeled with the same reference numerals, and their detailed descriptions may be omitted or simplified. In this embodiment, a modification in which the arrangement scheme of the pixel 600 described in the fifth to seventh embodiments is changed in various ways will be described.

[0193] Fig.38A , Fig.38B, Fig.38C , Fig.38D and Fig.38E is a schematic plan view showing an arrangement example of pixels according to the present embodiment. Fig.38E Shown in Fig.38A , Fig.38B , Fig.38C and Fig.38D Legend used in .

[0194] Specifically, in Fig.38A , Fig.38B , Fig.38C and Fig.38D , the pattern in the square frame representing the pixel 600 indicates whether the pixel 600 is a red pixel, a green pixel, or a blue pixel. In other words, this pattern represents the colors of the color filters CFR, CFG, and CFB provided on the pixel 600. Fig.38A , Fig.38B , Fig.38C and Fig.38D As shown, the color arrangement of the pixels 600 forms a Bayer arrangement in which the same arrangement is repeated, in which four pixels of two rows by two columns are defined as one unit.

[0195] The orientation of the line added in the pattern inside the square frame representing the pixel 600 indicates the orientation of the region 604c of the P-type semiconductor region 604 that isolates the two N-type semiconductor regions 601 from each other. In other words, the shapes of the two figures obtained by dividing the square with lines schematically represent the shapes of the two N-type semiconductor regions 601. Fig.38E As written in , the isolation scheme in which two N-type semiconductor regions 601 are arranged adjacent to each other in the horizontal direction is called horizontal isolation. The isolation scheme in which two N-type semiconductor regions 601 are arranged adjacent to each other in the vertical direction is called vertical isolation. The isolation scheme in which two N-type semiconductor regions 601 are arranged adjacent to each other in the direction between the lower left and the upper right is called the first diagonal isolation. The isolation scheme in which two N-type semiconductor regions 601 are arranged adjacent to each other in the direction between the upper left and the lower right is called the second diagonal isolation. These isolation directions correspond to the phase difference detection direction in the image plane phase difference autofocus.

[0196] exist Fig.38A In the example of FIG. 1 , the pixels 600 on the first and second rows have horizontal separation, and the pixels 600 on the third and fourth rows have vertical separation. The fifth to eighth rows also have the same arrangement. In this way, in Fig.38A In the example, every four rows repeat the same arrangement, and four rows including two rows isolated horizontally and two rows isolated vertically are defined as one unit.

[0197] exist Fig.38BIn the example of , the pixels 600 on the first and second rows have an arrangement of repeating horizontal isolation and first diagonal isolation, and the pixels 600 on the third and fourth rows have an arrangement of repeating second diagonal isolation and vertical isolation. The fifth to eighth rows also have the same arrangement. In this way, in Fig.38B In the example of , the same arrangement is repeated, wherein four rows by four columns including horizontal isolation, vertical isolation, first diagonal isolation, and second diagonal isolation are defined as one unit.

[0198] exist Fig.38C In the example of FIG. 5 , the pixels 600 on the first row have horizontal separation, and the pixels 600 on the second row have vertical separation. The third row and subsequent rows have an arrangement that repeats the above. In this way, in FIG. Fig.38C In the example of , the same arrangement is repeated every two rows, where two rows including one row of horizontal isolation and one row of vertical isolation are defined as one unit. In this arrangement, a red pixel and a green pixel adjacent to the red pixel in the horizontal direction have horizontal isolation, and a blue pixel and a green pixel adjacent to the blue pixel in the horizontal direction have vertical isolation. In this way, the color and isolation direction of the pixel can be associated so that pixels of some colors have regular isolation directions.

[0199] exist Fig.38D In the example of , the red pixels on the first row have horizontal isolation, and the green pixels on the first row have vertical isolation. In addition, the green pixels on the second row have vertical isolation, and the blue pixels on the second row have a repeated arrangement of the first diagonal isolation or the second diagonal isolation. The third row and subsequent rows have an arrangement that repeats the above. In this way, in Fig.38D In the example of , the same arrangement is repeated, where two rows by four columns including horizontal isolation, vertical isolation, first diagonal isolation, and second diagonal isolation are defined as one unit. In this arrangement, each green pixel and each red pixel adjacent to each blue pixel in the horizontal direction have horizontal isolation, and each green pixel adjacent to each red pixel in the horizontal direction has vertical isolation. Each blue pixel has first diagonal isolation or second diagonal isolation. In this way, the color and isolation direction of the pixel can be associated so that pixels of some colors have regular isolation directions.

[0200] As described above, in this embodiment, by including pixels 600 in various isolation directions in the pixel unit 61, signals for image plane phase difference autofocusing in various detection directions can be obtained.

[0201] Note that in FIG. 38A to FIG. 38EIn the example of , the color of pixel 600 may be a color other than red, green, or blue. For example, the color of pixel 600 may be cyan, magenta, and yellow as complementary colors, or may be white. In addition, pixel 600 may be an infrared pixel having an infrared filter that transmits infrared light and blocks visible light.

[0202] In addition, the arrangement of the pixels 600 is not limited to the Bayer arrangement, but may be other arrangements. For example, an arrangement in which red pixels, green pixels, and blue pixels are arranged in the same row or column may be used, a hexagonal arrangement in which hexagonal pixels are arranged may be used, or a staggered arrangement in which pixel groups including rectangles or the like defined as one unit are each offset by half a pitch and arranged. In addition, some pixels 600 may be replaced with the pixel 600 in which the number of photodiodes of the eleventh embodiment is one. Thirteenth Embodiment

[0203] An imaging system according to a thirteenth embodiment will be described. The imaging system of this embodiment has the photoelectric conversion device of any one of the first to twelfth embodiments. The imaging system refers to a device for capturing a still image or a moving image, such as a digital still camera, a digital video camera, a mobile phone digital camera, etc.

[0204] Fig.39 100 is a block diagram of an imaging system according to a thirteenth embodiment. The imaging system has a lens unit 1001, a lens driving device 1002, a shutter 1003, a shutter driving device 1004, a photoelectric conversion device 1005, an imaging signal processing circuit 1006, and a timing generation unit 1007. The imaging system also has a memory unit 1008, a general control / operation unit 1009, a storage medium control interface (I / F) unit 1010, a storage medium 1011, an external I / F unit 1012, and a light measuring device 1013.

[0205] The lens unit 1001 is a component that captures an optical image of a subject on the photoelectric conversion device 1005. The lens driving device 1002 is a device that drives the lens unit 1001. The lens driving device 1002 performs zoom control, focus control, aperture control, etc. by driving the lens unit 1001. The shutter 1003 is an optical member that blocks incident light, and a mechanical shutter can be used, for example. In addition, the shutter 1003 can also have an aperture function. The shutter driving device 1004 performs control of opening / closing of the shutter 1003, etc.

[0206] The photoelectric conversion device 1005 is a photoelectric conversion device of any one of the first to twelfth embodiments, and converts an optical image of a subject captured by the lens unit 1001 into an image signal to obtain an image signal. The imaging signal processing circuit 1006 is a circuit that performs various corrections, data compression, etc. on the image signal output from the photoelectric conversion device 1005. The timing generation unit 1007 is a circuit that outputs various timing signals to the photoelectric conversion device 1005 and the imaging signal processing circuit 1006.

[0207] The general control / operation unit 1009 is a control circuit that performs various operations and controls of the entire imaging system. The memory unit 1008 is a storage device for temporarily storing image data output from the imaging signal processing circuit 1006. The storage medium control I / F unit 1010 is an interface for performing storage or reading on the storage medium 1011. The storage medium 1011 is a removable storage medium such as a semiconductor memory, and is used for storage or reading of image data. The external I / F unit 1012 is an interface for providing various information, captured images, etc. from the outside, and can be a communication interface for communicating with other information processing devices such as a computer, or can be a user interface such as a display device.

[0208] Next, the operation at the time of capturing when the imaging system is a digital still camera with a ranging function will be described. In response to the main power of the imaging system being turned on, the power supply for controlling the imaging system and the power supply for capturing that supplies power to the imaging signal processing circuit 1006, etc. are turned on in sequence.

[0209] In response to the user pressing a release button (not shown), the photoelectric conversion device 1005 acquires an image signal, and the general control / operation unit 1009 performs a distance measurement operation based on the data of the image signal and calculates the distance to the subject based on the result of the distance measurement operation. The lens driving device 1002 then drives the lens unit 1001 based on the calculated distance to determine whether focusing is successful, and if focusing is unsuccessful, performs focus adjustment by performing a process of driving the lens unit 1001 again. The distance measurement operation may be an operation performed by a dedicated distance measurement device (not shown) in addition to the operation using the image signal acquired by the photoelectric conversion device 1005.

[0210] Once focusing is confirmed, the imaging system starts a capture operation. After the capture operation is completed, the image signal output from the photoelectric conversion device 1005 is processed in the imaging signal processing circuit 1006 and written to the memory unit 1008 under the control of the general control / operation unit 1009. The imaging signal processing circuit 1006 performs rearrangement, addition, etc. of data. The data stored in the memory unit 1008 is stored in the storage medium 1011 via the storage medium control I / F unit 1010 under the control of the general control / operation unit 1009. In addition, such data can be input into a computer or the like via the external I / F unit 1012. The computer can perform processing such as image editing on the data output from the imaging system.

[0211] The imaging system of the present embodiment has the photoelectric conversion device of any one of the first embodiment to the twelfth embodiment. Therefore, according to the present embodiment, a higher quality imaging system is provided. Fourteenth Embodiment

[0212] An imaging system and a moving device according to a fourteenth embodiment will be described. Fig.40A and Fig.40B is a diagram showing the configuration of the imaging system 300 and the mobile device according to the present embodiment.

[0213] Fig.40A An example of an imaging system 300 related to a vehicle-mounted camera is shown. The imaging system 300 has a photoelectric conversion device 310. The photoelectric conversion device 310 of this embodiment is the photoelectric conversion device described in any one of the first to twelfth embodiments described above. The imaging system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the photoelectric conversion device 310 and a parallax calculation unit 314 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the photoelectric conversion device 310. In addition, the imaging system 300 has a distance measurement unit 316 that calculates the distance to an object based on the calculated parallax and a collision determination unit 318 that determines whether there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 314 and the distance measurement unit 316 are examples of a distance information acquisition unit that acquires distance information about the distance to an object. That is, the distance information is information about parallax, defocus amount, distance to an object, and the like. The collision determination unit 318 can determine the possibility of collision using any distance information. The distance information acquisition unit can be implemented by specially designed hardware or can be implemented by a software module. In addition, the distance information acquisition unit may be implemented by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or may be implemented by a combination thereof.

[0214] The imaging system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, steering angle, etc. In addition, the imaging system 300 is connected to the control ECU 330, which is a control device that outputs a control signal for causing the vehicle to generate a braking force based on the determination result of the collision determination unit 318. In addition, the imaging system 300 is also connected to the alarm device 340, which issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, when the possibility of collision is high as a determination result of the collision determination unit 318, the control ECU 330 performs vehicle control to avoid collision or reduce damage by applying brakes, retracting the accelerator, suppressing engine power, etc. The alarm device 340 warns the user by emitting a sound alarm such as a sound, displaying alarm information on a display of a car navigation system, etc., providing vibration to a seat belt or a steering wheel, etc.

[0215] In the present embodiment, an area around the vehicle, such as a front area or a rear area, is captured by using the imaging system 300 . Fig.40B An example of the arrangement of the imaging system 300 when the front area of ​​the vehicle (capture area 350) is captured is shown. The vehicle information acquisition device 320 sends an instruction to the imaging system 300 or the photoelectric conversion device 310. This configuration can further improve the ranging accuracy.

[0216] Although an example of control for avoiding a collision with another vehicle is described above, the embodiment may be applied to an automatic driving control for following another vehicle, an automatic driving control for not exiting a lane, and the like. In addition, the imaging system 300 is not limited to vehicles such as the subject vehicle, and may be applied to movable devices (mobile devices) such as ships, airplanes, or industrial robots, for example. In addition, the imaging system 300 may be widely applied to devices utilizing object recognition such as an intelligent transportation system (ITS), and is not limited to mobile devices. Modified Embodiment

[0217] The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any embodiment is added to another embodiment or an example in which a part of the configuration of any embodiment is replaced by a part of the configuration of another embodiment is one of the embodiments of the present invention.

[0218] In addition, the devices or systems shown in the above-mentioned thirteenth embodiment and fourteenth embodiment are configuration examples of devices or systems to which the photoelectric conversion device of the present invention can be applied. Therefore, the devices or systems to which the photoelectric conversion device of the present invention can be applied are not limited to Fig.39 , Fig.40A or Fig.40B Configuration shown.

[0219] In addition, for example, the conductivity type of the semiconductor region shown in the first embodiment to the twelfth embodiment may be changed, and for example, all the conductivity types may be reversed. Figure 4A , Figure 4B , Figure 4C , Figure 6 , Fig.12 or FIG. 38A to FIG. 38E The pixel arrangement shown in Figure 7 or Fig.13 The circuit configuration inside the pixel and the like shown in are examples, and a different pixel arrangement or a different circuit configuration may be employed.

[0220] The embodiments of the present invention may also be implemented by a computer of a system or device that reads out and executes computer executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more completely referred to as a "non-transitory computer-readable storage medium") to perform the functions of one or more of the above-described embodiments and / or includes one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing the functions of one or more of the above-described embodiments, and by a method executed by a computer of a system or device, for example, by reading out and executing computer executable instructions from a storage medium to perform the functions of one or more of the above-described embodiments and / or controlling one or more circuits to perform the functions of one or more of the above-described embodiments. The computer may include one or more processors (e.g., a central processing unit (CPU), a microprocessing unit (MPU)), and may include a network of separate computers or separate processors to read out and execute computer executable instructions. The computer executable instructions may be provided to the computer, for example, from a network or a storage medium. The storage medium may include, for example, a hard disk, a random access memory (RAM), a read-only memory (ROM), a storage device of a distributed computing system, an optical disk (such as a compact disk (CD), a digital versatile disk (DVD), or a Blu-ray disk (BD)) TM ), one or more of a flash memory device, a memory card, etc. Other embodiments

[0221] The embodiments of the present invention may also be implemented by providing software (program) for executing the functions of the above embodiments to a system or device via a network or various storage media, and a computer or a central processing unit (CPU) or a microprocessing unit (MPU) of the system or device reads and executes the program.

[0222] While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded broad interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims

1. A photoelectric conversion device, characterized in that: The photoelectric conversion device comprises: A first substrate having a first surface and a second surface opposite to the first surface; a plurality of photodiodes arranged in the first substrate and each having a first region of a first conductivity type that generates signal charge by photoelectrically converting incident light received from the second face side and a second region of the first conductivity type that overlaps at least a portion of the first region in a plan view; a first microlens arranged on the second face side in association with a first photodiode group including two or more photodiodes among the plurality of photodiodes; and a second microlens disposed on the second face side in association with a second photodiode group including two or more photodiodes different from the photodiodes included in the first photodiode group among the plurality of photodiodes, wherein the plurality of second regions are arranged in the first substrate at a first depth, wherein the plurality of first regions are arranged in the first substrate at a second depth relative to the first surface that is deeper than the first depth, Among them, the photoelectric conversion equipment includes: a first path for moving signal charges from only one of the plurality of first regions to only one of the plurality of second regions, and a second path for moving the signal charge from only another first region among the plurality of first regions to only another second region among the plurality of second regions, wherein a semiconductor region of a second conductivity type opposite to the first conductivity type is arranged between the one first region among the plurality of first regions and the another second region among the plurality of second regions, wherein the semiconductor region of the second conductivity type is arranged between the other first region among the plurality of first regions and the one second region among the plurality of second regions, wherein a shape of a first region and a shape of a second region included in the first photodiode group are different from each other in a plan view, wherein the first region included in the first photodiode group extends longer in the first direction than the first region included in the second photodiode group in a plan view, and Here, the first region included in the second photodiode group extends longer than the first region included in the first photodiode group in a second direction intersecting the first direction in a plan view.

2. The photoelectric conversion device according to claim 1, further comprising: a first isolation region disposed at a first depth and including a first portion extending in a first direction so as to isolate a second region of one of the plurality of photodiodes included in the first photodiode group from a second region of another of the plurality of photodiodes included in the first photodiode group; as well as A second isolation region is arranged at a second depth and includes a second portion, which extends in a second direction intersecting the first direction in a plan view so as to isolate a first region of one photodiode among the multiple photodiodes included in the first photodiode group from a first region of another photodiode among the multiple photodiodes included in the first photodiode group. 3 . The photoelectric conversion device according to claim 1 , further comprising a floating diffusion to which charges are transferred from each of the plurality of second regions of the first photodiode group. 4 . The photoelectric conversion device according to claim 1 , further comprising a third region arranged between the first region and the second region so as to be in contact with the first region and the second region.

5. The photoelectric conversion device according to claim 4, wherein The potential of the signal charge in the third region increases monotonically along the path from the first region to the second region.

6. The photoelectric conversion device according to claim 1 or 2, wherein: Shapes of the plurality of first regions included in the first photodiode group are different from each other in a plan view.

7. The photoelectric conversion device according to claim 1 or 2, wherein: Areas of the plurality of first regions included in the first photodiode group are different from each other in a plan view.

8. The photoelectric conversion device according to claim 1 or 2, wherein: The area of ​​the first region included in the first photodiode group and the area of ​​the first region included in the second photodiode group are the same in a plan view.

9. The photoelectric conversion device according to claim 1 or 2, wherein: The photodiodes included in the first photodiode group are sensitive to incident light of a first color, and the photodiodes included in the second photodiode group are sensitive to incident light of a second color different from the first color. 10 . The photoelectric conversion device according to claim 1 , further comprising a deep trench isolation structure isolating the first photodiode group and the second photodiode group from each other. 11 . The photoelectric conversion device according to claim 1 , further comprising a third microlens arranged on the second face side in association with a third photodiode group including only one photodiode among the plurality of photodiodes.

12. The photoelectric conversion device according to claim 1 or 2, wherein: The second region receives the signal charges moved from the first region.

13. The photoelectric conversion device according to claim 1, further comprising a third region arranged between the first region and the second region so as to be in contact with the first region and the second region, in, Each of the first region, the second region, and the third region has a first conductivity type.

14. The photoelectric conversion device according to claim 13, further comprising: a first isolation region disposed at a first depth and including a first portion extending in a first direction so as to isolate a second region of one of the plurality of photodiodes from a second region of another of the plurality of photodiodes; as well as a second isolation region disposed in the first substrate at a second depth and including a second portion extending in a second direction intersecting the first direction in a plan view so as to isolate a first region of one of the plurality of photodiodes from a first region of another of the plurality of photodiodes, Each of the first portion and the second portion has a second conductivity type different from the first conductivity type.

15. An imaging system, characterized in that: The imaging system comprises: The photoelectric conversion device according to any one of claims 1 to 14; and The signal processing unit is configured to process a signal output from the photoelectric conversion device.

16. A mobile device, characterized in that: The mobile device comprises: The photoelectric conversion device according to any one of claims 1 to 14; a distance information acquisition unit configured to acquire distance information about a distance to a subject from a parallax image based on a signal from the photoelectric conversion device; and The control unit is configured to control the mobile device based on the distance information.

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