Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a manufacturing method thereof and a photovoltaic module. The solar cell comprises a semiconductor substrate and a first semiconductor layer, and a first surface of the semiconductor substrate comprises a first region, a transition region and a second region; the first semiconductor layer covers the first region; the first area and the transition area comprise a plurality of first pyramids, the first pyramid adjacent to the second area in the transition area is an edge pyramid, and the edge pyramid extends towards the second area to form a suspended brim part; the first edge, close to the second area, of the first semiconductor layer is arranged on the edge pyramid, and an undercut structure is arranged between the first edge of the first semiconductor layer and the edge pyramid. In the using process, a part of light is reflected to the brim part from the second area and is reflected to the second area through the brim part to be absorbed and utilized by the semiconductor substrate, and the light absorption rate is improved. The first edge of the first semiconductor layer is supported by the brim portion, which can prevent the first edge of the first semiconductor layer from collapsing.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] Solar cells are now being used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells use the photovoltaic principle to generate carriers, and then use electrodes to lead the carriers out, thereby facilitating the effective use of electrical energy.

[0003] However, currently, a portion of the light irradiated to the solar cell will be reflected back into the environment, affecting the photoelectric conversion efficiency of the solar cell. Summary of the invention

[0004] The purpose of the present application is to provide a solar cell and a manufacturing method thereof, and a photovoltaic module to improve the light absorption rate and photoelectric conversion efficiency of the solar cell, while preventing the first edge of the first semiconductor layer from collapsing and deforming.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell, comprising:

[0007] A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other, wherein the first surface includes a first region, a transition region, and a second region arranged adjacent to each other in sequence along a first direction;

[0008] A first semiconductor layer, the first semiconductor layer covers the first region;

[0009] The first region and the transition region include a plurality of first pyramids, wherein the first pyramid in the transition region adjacent to the second region is an edge pyramid, and the edge pyramid extends toward the second region to form a suspended brim portion;

[0010] A first edge of the first semiconductor layer close to the second region is disposed on the edge pyramid, and an undercut structure is provided between the first edge of the first semiconductor layer and the edge pyramid.

[0011] By adopting the above technical solution, during the actual use of the solar cell, a portion of the light is reflected from the second area to the brim portion. Since the brim portion forms a suspended structure toward the second area, the light reflected to the brim portion will be reflected again to the second area to be absorbed and utilized by the semiconductor substrate, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery. In addition, the brim portion forms a suspended structure toward the second area, so that the distance between the edge of the brim portion away from the first area and the first semiconductor layer can be larger, avoiding the defects of the edge of the brim portion from approaching the first semiconductor layer, thereby reducing defect recombination. In addition, the first edge of the first semiconductor layer extends to the side of the brim portion away from the semiconductor substrate, or in other words, the first edge of the first semiconductor layer extends to the upper side of the brim portion, so that the first edge of the first semiconductor layer is supported by the brim portion, which can prevent the first edge of the first semiconductor layer from collapsing at the edge of the transition area.

[0012] In one implementation, along the first direction, the width of the brim portion is less than or equal to 200 nm; and / or, along the first direction, the depth of the undercut structure is less than or equal to 100 nm. In this technical solution, the width of the brim portion and the depth of the undercut structure are set within a reasonable range, while ensuring the carrier collection efficiency of the first semiconductor layer, preventing the first edge of the first semiconductor layer from collapsing.

[0013] In one implementation, along the first direction, the edge of the brim portion close to the second region is closer to the second region than the first edge. In this way, the first edge of the first semiconductor layer is located entirely on the upper side of the brim portion, thereby improving the stability of the brim portion supporting the first edge of the first semiconductor layer and further preventing the first edge of the first semiconductor layer from collapsing.

[0014] In one implementation, along the extension direction of the first semiconductor layer, the side of the first edge close to the semiconductor substrate extends in a wave shape. This arrangement allows the first edge of the first semiconductor layer to better wrap the side wall of the edge pyramid, and also appropriately increases the overall extension length of the first semiconductor layer, thereby increasing the carrier transmission path and area in the first semiconductor layer, which is beneficial to reducing contact resistance.

[0015] In one implementation, the brim has at least one raised bottom edge on the side facing the semiconductor substrate, which can improve the overall strength of the brim and further prevent the brim itself and the first edge of the first semiconductor layer from collapsing.

[0016] In one implementation, the second region includes a plurality of second pyramids, and an average height of the second pyramids is greater than an average height of the first pyramids; and / or,

[0017] The height of the first pyramid ranges from 500nm to 3000nm; and / or,

[0018] The height of the second pyramid ranges from 800nm ​​to 5000nm.

[0019] By adopting this technical solution, the first pyramids in the first region and the transition region are smaller, which is beneficial to improving the formation quality of the first semiconductor layer in the first region and the transition region, thereby improving the passivation effect; in addition, the second pyramids in the second region are larger, which can fully reflect light, improve the light trapping effect, and increase the utilization rate of light. The larger second pyramid makes it easier for light to be reflected to the brim and then reflected back to the position of the second pyramid by the brim.

[0020] In one implementation, the solar cell further includes a passivation layer, which covers the side of the first semiconductor layer facing away from the semiconductor substrate and the second region; the passivation layer wraps the brim portion and fills the undercut structure. In this technical solution, the passivation layer can be formed on the entire first surface, the passivation layer has a grooved region, and the first electrode passes through the grooved region of the passivation layer to make ohmic contact with the first semiconductor layer. On the one hand, the passivation layer can protect the surface of the cell and prevent water vapor or oxygen from penetrating into the interior of the cell, thereby avoiding performance degradation of the cell due to oxidation or hydrolysis; on the other hand, the provision of the passivation layer can improve the utilization of light and reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell.

[0021] In one implementation, the passivation layer is a single-layer structure; or, the passivation layer is a double-layer structure; or, the passivation layer includes one or more of silicon nitride, silicon oxide, aluminum oxide, or phosphate glass.

[0022] In one implementation, the second region is formed as a groove structure that is recessed toward the second surface relative to the first region; when the second semiconductor layer is arranged in the groove structure, the existence of the groove structure can at least partially offset the electrode structure that is electrically in contact with the first semiconductor layer and the second semiconductor layer, respectively, along the thickness direction of the semiconductor substrate, which is beneficial to suppressing leakage.

[0023] A prism inclined toward the first region is formed in the transition region. The prism is a polyhedral structure, which is beneficial to increase the specific surface area of ​​the groove side wall surface and further reduce the surface reflectivity of the transition region.

[0024] In one implementation, the angle between the prism and the first surface is between 50° and 60°. The inclination angle of the prism is controlled between 50° and 60°, which can effectively improve the reflection utilization rate of light, increase the light reflected by the prism to the cover glass or the back plate and then reflected back to the cell, so as to improve the photoelectric conversion efficiency.

[0025] In one implementation, the projection width of the prism on the first surface is 1-8 μm. The projection width on the first surface is controlled to be small, which can effectively reduce the proportion of the prism on the first surface and increase the proportion of the second area, thereby increasing the incident area of ​​light and thus improving the utilization rate of light. In addition, by reasonably controlling the inclination angle of the prism and the projection width on the first surface, the first absorption of light by the second area can be improved while improving the secondary utilization of light.

[0026] In one implementation, the solar cell further includes a second semiconductor layer, the second semiconductor layer covers at least a portion of the second surface of the semiconductor substrate, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer.

[0027] In one implementation, the solar cell further includes a second semiconductor layer, the second semiconductor layer covers at least a portion of the second region, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer.

[0028] In one implementation, the first semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell further includes a first interface layer located on a side of the first semiconductor layer close to the semiconductor substrate;

[0029] The second semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell also includes a second interface layer located on a side of the second semiconductor layer close to the semiconductor substrate.

[0030] A method for manufacturing a solar cell, comprising:

[0031] A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface comprises a first region, a transition region and a second region which are arranged adjacent to each other in sequence along a first direction;

[0032] Performing texturing on the semiconductor substrate so that at least the first surface of the semiconductor substrate forms a first pyramid-shaped texturing surface;

[0033] forming a first semiconductor layer on a first surface of the semiconductor substrate;

[0034] A portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region. The first pyramid in the transition region adjacent to the second region is an edge pyramid. The edge pyramid extends toward the second region to form a suspended brim portion, so that a first edge of the first semiconductor layer close to the second region is arranged on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid.

[0035] In the solar cell structure formed by the above-mentioned manufacturing method, a portion of the light is reflected from the second area to the brim portion. Since the brim portion forms a suspended structure toward the second area, the light reflected to the brim portion will be reflected again to the second area to be absorbed and utilized by the semiconductor substrate, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery. In addition, the brim portion forms a suspended structure toward the second area, so that the distance between the edge of the brim portion away from the first area and the first semiconductor layer can be larger, avoiding defects at the edge of the brim portion from approaching the first semiconductor layer, thereby reducing defect recombination. In addition, the first edge of the first semiconductor layer extends to the side of the brim portion away from the semiconductor substrate, or in other words, the first edge of the first semiconductor layer extends to the upper side of the brim portion, so that the first edge of the first semiconductor layer is supported by the brim portion, which can prevent the first edge of the first semiconductor layer from collapsing at the edge of the transition area.

[0036] In one implementation, a portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, a first pyramid in the transition region adjacent to the second region is an edge pyramid, the edge pyramid extends toward the second region to form a suspended brim portion, a first edge of the first semiconductor layer close to the second region is disposed on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid, including:

[0037] Forming a mask layer on a side of the first semiconductor layer away from the semiconductor substrate and performing patterning;

[0038] removing the first semiconductor layer not covered by the mask layer;

[0039] The area of ​​the semiconductor substrate not covered by the mask layer is textured so that the second area presents a second pyramid-shaped texture surface, and the first pyramid adjacent to the second area in the transition area is an edge pyramid, which extends toward the second area to form a suspended brim portion, so that the first edge of the first semiconductor layer close to the second area is arranged on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid.

[0040] In one implementation, a portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, a first pyramid in the transition region adjacent to the second region is an edge pyramid, and the edge pyramid extends toward the second region to form a suspended brim portion, so that a first edge of the first semiconductor layer close to the second region is disposed on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid, the method for manufacturing a solar cell further includes:

[0041] forming a passivation layer on the second region of the first surface and on a side of the first semiconductor facing away from the semiconductor substrate;

[0042] Grooving a portion of the passivation layer corresponding to the first region;

[0043] forming a second semiconductor layer on the second surface, the conductivity type of the second semiconductor layer being opposite to that of the first semiconductor layer;

[0044] A first electrode is formed in the grooved region of the passivation layer, and a second electrode is formed on the side of the second semiconductor layer away from the semiconductor substrate. In this way, a double-sided solar cell is formed according to the technical solution.

[0045] In one implementation, a portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, a first pyramid in the transition region adjacent to the second region is an edge pyramid, and the edge pyramid extends toward the second region to form a suspended brim portion, so that a first edge of the first semiconductor layer close to the second region is disposed on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid, the method for manufacturing a solar cell further includes:

[0046] forming a second semiconductor layer at least in a second region of the first surface, the second semiconductor layer and the first semiconductor layer having opposite conductivity types;

[0047] forming a passivation layer on the first surface of the semiconductor substrate;

[0048] A first electrode is formed in a region of the passivation layer corresponding to the first region, and a second electrode is formed in a region of the passivation layer corresponding to the second semiconductor layer.

[0049] In one implementation, selectively etching a portion of the semiconductor substrate corresponding to the second region to remove the first semiconductor layer in the second region includes:

[0050] The portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, and at the same time, the surface of the second region is recessed relative to the first region in the direction from the second surface to the first surface to form a groove structure.

[0051] A photovoltaic assembly comprises a plurality of solar cells as described in any one of the above items, or comprises a plurality of solar cells formed by any one of the above manufacturing methods.

[0052] Compared with the prior art, the beneficial effects of the photovoltaic module provided in the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0054] Figure 1 A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0055] Figure 2 Another partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0056] Figure 3 A local SEM image of a solar cell provided in an embodiment of the present application;

[0057] Figure 4 A top view SEM image of a solar cell provided in an embodiment of the present application;

[0058] Figure 5 A side view of a first edge of a solar cell provided in an embodiment of the present application;

[0059] Figure 6 A side view of a brim portion of a solar cell provided in an embodiment of the present application;

[0060] Figure 7 A side view of a first edge and a brim portion of a solar cell provided in an embodiment of the present application;

[0061] Figure 8 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 1 ;

[0062] Fig. 9 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 2 ;

[0063] Fig.10 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 3 ;

[0064] Fig.11 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 4 ;

[0065] Fig.12 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 5 ;

[0066] Fig.13A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 6 ;

[0067] Fig.14 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 7 ;

[0068] Fig.15 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 8 ;

[0069] Fig.16 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 9 ;

[0070] Fig.17 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 10 ;

[0071] Fig.18 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 10 one;

[0072] Fig.19 A schematic longitudinal cross-sectional view of the structure of a back contact cell during the manufacturing process provided in an embodiment of the present application Figure 10 two.

[0073] Reference numerals:

[0074] 1-semiconductor substrate, 1a-first region, 1b-transition region, 1c-second region, 1d-prism, 1e-brim portion, 1f-bottom edge, 2-first semiconductor layer, 2a-undercut structure, 2b-first edge, 3-passivation layer, 4-first electrode, 5-second semiconductor layer, 6-transparent conductive layer, 7-second electrode, 8-first pyramid, 9-second pyramid, 10-first interface layer, 11-mask layer, 12-second interface layer. DETAILED DESCRIPTION

[0075] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0076] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0077] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0078] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0079] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0080] See also Figure 1-Figure 4 The solar cell provided in the embodiment of the present application includes a semiconductor substrate 1, a first semiconductor layer 2 and a second semiconductor layer 5. The semiconductor substrate 1 has a first surface and a second surface arranged opposite to each other, and the first surface includes a first region 1a, a transition region 1b and a second region 1c arranged in sequence along a first direction, and the transition region 1b is located between the first region 1a and the second region 1c, and the transition region 1b connects the first region 1a and the second region 1c. The first semiconductor layer 2 covers the first region 1a, that is, along a direction parallel to the first surface of the semiconductor substrate 1, the first semiconductor layer 2 is formed in the first region 1a.

[0081] Moreover, the first region 1a and the transition region 1b of the first surface include a plurality of first pyramids 8, that is, the first region 1a and the transition region 1b of the first surface are both first pyramid-type velvet surfaces. Since the pyramid-type velvet surface can cause the incident light to be reflected and refracted multiple times on the surface, the advancing direction of the incident light in the semiconductor substrate 1 is changed, the optical path is extended, a light trapping effect is generated, and the generation of photogenerated carriers is increased. Therefore, when the first region 1a and the transition region 1b are the first pyramid-type velvet surfaces, it is beneficial for more light to be refracted from the first region 1a and the transition region 1b of the first surface into the semiconductor substrate 1 and absorbed and utilized by the semiconductor substrate 1, which is beneficial for improving the photoelectric conversion efficiency of the back contact battery.

[0082] The first pyramid 8 adjacent to the second region 1c in the transition region 1b is an edge pyramid, that is, the edge pyramid is adjacent to the second region 1c. Figure 3 As shown, the edge pyramid extends toward the second region 1c to form a suspended brim portion 1e, and the brim portion 1e is a part of the edge pyramid, that is, the brim portion 1e forms a suspended structure close to the edge of the second region 1c.

[0083] Furthermore, the first edge 2b of the first semiconductor layer 2 close to the second region 1c is arranged on the edge pyramid, and an undercut structure 2a is provided between the first edge 2b of the first semiconductor layer 2 and the edge pyramid. The undercut structure 2a extends from the upper side to the lower side of the first edge 2b of the first semiconductor layer 2, and finally extends to the side wall of the edge pyramid close to the second region 1c. Specifically, the first semiconductor layer 2 covers at least one side of the brim portion 1e close to the first region 1a and the top of the brim portion 1e. The first edge 2b of the first semiconductor layer 2 is supported by the edge pyramid.

[0084] By adopting the above technical solution, during the actual use of the solar cell, a portion of the light is reflected from the second region 1c to the brim portion 1e. Since the brim portion 1e forms a suspended structure toward the second region 1c, the light reflected to the brim portion 1e will be reflected again to the second region 1c to be absorbed and utilized by the semiconductor substrate 1, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery. In addition, the brim portion 1e forms a suspended structure toward the second region 1c, so that the distance between the edge of the brim portion 1e away from the first region 1a and the first semiconductor layer 2 can be larger, avoiding the defects at the edge of the brim portion 1e from approaching the first semiconductor layer 2, thereby reducing defect recombination. In addition, the first edge 2b of the first semiconductor layer 2 extends to the side of the brim portion 1e away from the semiconductor substrate 1, or in other words, the first edge 2b of the first semiconductor layer 2 extends to the upper side of the brim portion 1e, so that the first edge 2b of the first semiconductor layer 2 is supported by the brim portion 1e, which can prevent the first edge 2b of the first semiconductor layer 2 from collapsing at the edge of the transition region 1b.

[0085] It should be noted that the first region 1a, transition region 1b and second region 1c of the first surface of the semiconductor substrate 1 are all virtual boundaries. The first region 1a is a region for forming the first electrode 4; the transition region 1b is a region from the edge of the first electrode 4 to the edge pyramid; and the second region 1c is a portion of the first surface excluding the first region 1a and the transition region 1b.

[0086] In some embodiments, along the first direction, the width of the brim portion 1e is less than or equal to 200nm, or in other words, the width of the brim portion 1e suspended along the first direction is less than or equal to 200nm. Considering that along the first direction, if the width of the brim portion 1e is too large, the brim portion 1e will block a portion of the light irradiated to the second area 1c, thereby affecting the absorbance of the solar cell, resulting in a decrease in the photoelectric conversion efficiency; if the width of the brim portion 1e is too small along the first direction, the stability of the brim portion 1e supporting the first edge 2b of the first semiconductor layer 2 is reduced, which easily causes the first edge 2b of the first semiconductor layer 2 to collapse. In view of the above situation, in this technical solution, the width of the brim portion 1e is set within a reasonable range to ensure the absorbance of the solar cell while preventing the first edge 2b of the first semiconductor layer 2 from collapsing.

[0087] Illustratively, along the first direction, the width of the brim portion 1e is 200 nm, 180 nm, 150 nm, 120 nm, 100 nm, 80 nm, 50 nm, 20 nm or 10 nm.

[0088] In addition, along the first direction, the depth of the bottom cut structure 2a is less than or equal to 100nm. That is, the width of the bottom cut structure 2a suspended along the first direction is less than or equal to 100nm. It should be noted that the bottom cut structure refers to the etching liquid etching a certain layer between two layer structures during the etching process to form a gradually retracted edge shape. On the one hand, if the depth of the bottom cut structure 2a is too large along the first direction, the first semiconductor layer 2 is likely to exceed the brim portion 1e, causing the first edge 2b of the first semiconductor layer 2 to collapse; on the other hand, if the depth of the bottom cut structure 2a is too small along the first direction, it may cause the area of ​​the first semiconductor layer 2 to be small, affecting the carrier collection efficiency; Combining the above two aspects, in the present technical solution, the depth of the bottom cut structure 2a is set within a reasonable range, while ensuring the carrier collection efficiency of the first semiconductor layer 2, preventing the first edge 2b of the first semiconductor layer 2 from collapsing.

[0089] Illustratively, along the first direction, the depth of the undercut structure 2 a is 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, 20 nm or 10 nm.

[0090] In another embodiment, along the first direction, the edge of the brim portion 1e close to the second region 1c is closer to the second region 1c than the first edge 2b. In this way, the first edge 2b of the first semiconductor layer 2 is entirely located on the upper side of the brim portion 1e, thereby improving the stability of the brim portion 1e supporting the first edge 2b of the first semiconductor layer 2 and further preventing the first edge 2b of the first semiconductor layer 2 from collapsing.

[0091] like Figure 3 As shown, the brim portion 1e has at least one raised bottom edge 1f on the side facing the semiconductor substrate 1. In other words, the bottom side of the brim portion 1e has at least one raised bottom edge 1f. This arrangement can improve the overall strength of the brim portion 1e and further prevent the brim portion 1e itself and the first edge 2b of the first semiconductor layer 2 from collapsing.

[0092] like Figure 5-Figure 7 As shown, along the extension direction of the first semiconductor layer 2, the side of the first edge 2b close to the semiconductor substrate 1 extends in a wavy shape. That is, the lower side of the first edge 2b of the first semiconductor layer 2 appears to extend along the wavy line as a whole. Such a configuration makes the first edge 2b of the first semiconductor layer 2 better wrap the side wall of the edge pyramid, and in addition, the overall extension length of the first semiconductor layer 2 is appropriately increased, thereby increasing the transmission path and area of ​​carriers in the first semiconductor layer 2, which is conducive to reducing the contact resistance.

[0093] In some embodiments, the second region 1c includes multiple second pyramids 9, that is, the second region 1c is a second pyramid velvet surface. Because the velvet surface has a light-trapping function, when the second region 1c of the semiconductor substrate 1 is a velvet surface, the reflectivity of the light-facing surface can be reduced, which is beneficial for more light to be refracted from the light-facing surface into the semiconductor substrate 1 and absorbed and utilized by the semiconductor substrate 1, thereby improving the photoelectric conversion efficiency of the back-contact battery.

[0094] Furthermore, the average height of the second pyramid 9 is greater than the average height of the first pyramid 8, that is, the average height of the second pyramid 9 in the second region 1c is greater than the average height of the first pyramid 8 in the first region 1a. With this technical solution, the first pyramid 8 in the first region 1a and the transition region 1b is smaller, which is beneficial to improving the formation quality of the first semiconductor layer 2 in the first region 1a and the transition region 1b, thereby improving the passivation effect; in addition, the second pyramid 9 in the second region 1c is larger, which can fully reflect light, improve the light trapping effect, increase the utilization rate of light, and the larger second pyramid 9 makes it easier for light to be reflected to the brim portion 1e, and then reflected back to the position of the second pyramid 9 by the brim portion 1e.

[0095] It can be understood that in the process of measuring the second pyramid 9 and the average height of the second pyramid 9, if the measured area is too small, the heights of the second pyramid 9 and the second pyramid 9 cannot be accurately obtained by measuring only the base area of ​​the pyramid. Therefore, the measured area should at least include the complete pyramid. Preferably, the measured area should be greater than or equal to 5*5μm. 2 .

[0096] The height of the first pyramid 8 ranges from 500 nm to 3000 nm. Exemplarily, the height of the first pyramid 8 is 500 nm, 800 nm, 1000 nm, 1200 nm, 1500 nm, 1800 nm, 2000 nm, 2200 nm, 2500 nm, 2800 nm or 3000 nm.

[0097] The height of the second pyramid 9 ranges from 800nm ​​to 5000nm. Exemplarily, the height of the second pyramid 9 is 800nm, 1000nm, 1200nm, 1500nm, 1800nm, 2000nm, 2200nm, 2500nm, 2800nm, 3000nm, 3200nm, 3500nm, 3800nm, 4000nm, 4200nm, 4500nm, 4800nm, or 5000nm, etc.

[0098] In the actual application process, the embodiment of the present invention does not specifically limit the material of the semiconductor substrate 1. The semiconductor substrate 1 can be a substrate of any semiconductor material such as a silicon substrate, a silicon germanium substrate, a germanium substrate or a gallium arsenide substrate. In terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0099] It can be understood that the first surface of the semiconductor substrate 1 can correspond to the backlight side of the solar cell, and the second surface of the semiconductor substrate 1 can correspond to the light-facing side of the solar cell; or, the first surface of the semiconductor substrate 1 can correspond to the light-facing side of the solar cell, and the second surface of the semiconductor substrate 1 can correspond to the backlight side of the solar cell.

[0100] In some implementations, the solar cell further includes a passivation layer 3, which covers the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1 and the second region 1c; the passivation layer 3 wraps the brim portion 1e and fills the undercut structure 2a. In this technical solution, the passivation layer 3 can be formed on the entire first surface, the passivation layer 3 has a grooved area, and the first electrode 4 passes through the grooved area of ​​the passivation layer 3 to make ohmic contact with the first semiconductor layer 2. On the one hand, the passivation layer 3 can protect the surface of the cell and prevent water vapor or oxygen from penetrating into the interior of the cell, thereby avoiding performance degradation of the cell due to oxidation or hydrolysis; on the other hand, the provision of the passivation layer 3 can improve the utilization of light and reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell.

[0101] Furthermore, according to actual needs, the passivation layer 3 may be a single-layer structure or a multi-layer structure. In the case where the passivation layer 3 is a multi-layer structure, the passivation layer 3 may be a double-layer structure, a triple-layer structure, etc.

[0102] In terms of material, the passivation layer 3 may include one or more of silicon nitride (SiNx, x can be any value), silicon oxide, aluminum oxide (AlOx, x can be any value) or phosphate glass (PSG, Phosphosilicate Glass). Exemplarily, the passivation layer 3 includes a phosphate glass layer and a silicon nitride layer stacked in sequence, and the silicon nitride layer is located on the side of the phosphate glass layer away from the semiconductor substrate 1; or, the passivation layer 3 includes an aluminum oxide layer and a silicon nitride layer stacked in sequence, wherein the silicon nitride layer is located on the side of the aluminum oxide layer away from the semiconductor substrate 1.

[0103] As for the thickness of the passivation layer 3, it can be set according to the actual application scenario. For example, the thickness of the passivation layer 3 is 50nm, 60nm, 80nm, 100nm, 120nm, 150nm, etc.

[0104] In other embodiments, Figure 2-Figure 4 As shown, the second region 1c is formed as a groove structure that is recessed toward the second surface relative to the first region 1a, that is, the second region 1c is lower than the first region 1a and the transition region 1b of the first surface to form a groove structure. In the case where the second semiconductor layer 5 is disposed in the groove structure, the presence of the groove structure can at least partially stagger the electrode structures that are electrically in contact with the first semiconductor layer 2 and the second semiconductor layer 5, respectively, along the thickness direction of the semiconductor substrate 1, which is beneficial to suppressing leakage.

[0105] Furthermore, a prism 1d inclined toward the first region 1a is formed in the transition region 1b, and the prism 1d is also formed on the side wall of the groove structure. A plurality of prisms 1d can be connected to the bottom prism 1f of the brim portion 1e. The prism 1d is a polyhedral structure, which is conducive to increasing the specific surface area of ​​the groove side wall surface and further reducing the surface reflectivity of the transition region 1b.

[0106] See also Figure 2 The inclination angles of the multiple prisms 1d are basically close, and the angle α between them and the first surface is between 50°-60°, preferably 53°-56°, for example, 53°, 54°, 55°, 56°. Setting the inclination angles of the prisms 1d in this way can effectively improve the reflection utilization rate of light, increase the light reflected by the prisms to the cover glass or the back plate and then reflected back to the cell, so as to improve the photoelectric conversion efficiency. Specifically, when the light is irradiated to the second area for the first time, it will be reflected, and the reflected light part will change the outgoing ray path through the multiple prisms 1d, and the special inclination angles of the multiple prisms 1d make the light with the changed outgoing ray path irradiate the cover glass or the back plate of the photovoltaic module at a large angle, and it is easier to reflect back to the first surface of the cell, thereby realizing the second utilization of the light.

[0107] See also Figure 4 , the projection width d of the multiple prisms 1d on the first surface is 1-8μm. A projection width d that is too small (for example, less than 1μm) will cause residues in the second region 1c when the first semiconductor layer 2 is removed, which is not conducive to the passivation effect; a projection width d that is too large (for example, greater than 8μm) will cause the projection area of ​​the prism 1d to be too large, squeezing the area of ​​the second region 1c (the second region 1c is the main absorption area of ​​light). Controlling the projection width of the multiple prisms 1d on the first surface to be smaller can effectively reduce the proportion of the prisms on the first surface and increase the proportion of the second region, thereby increasing the incident area of ​​light and improving the utilization rate of light. In addition, by reasonably controlling the inclination angle of the prism and the projection width on the first surface, it is possible to improve the initial absorption of light by the second region while improving the secondary utilization of light.

[0108] It should be noted that the solar cell provided in the embodiment of the present application may be a double-sided solar cell or a back-contact solar cell.

[0109] In the case where the solar cell is a bifacial solar cell, the bifacial solar cell may be a PREC (Passivated Emitter Rear Cell) solar cell, a TOPCon (Tunnel Oxide Passivated Contact) solar cell or a HIT (Heterojunction with Intrinsic Thin-layer) solar cell.

[0110] In the case where the solar cell is a back-contact solar cell, the back-contact solar cell can be a HTBC (Heterojunction Tunnel Oxide Passivated Contact Back Contact) solar cell, an HBC (Heterojunction Back Contact) solar cell, a TBC (Tunnel Oxide Passivated Contact Back Contact) or an HPBC (Hybrid Passivated Back Contact) solar cell, or the back-contact solar cell can also be a hybrid cell formed by combining an HJT solar cell, a TOPCon solar cell, an IBC solar cell, etc.

[0111] In the case where the solar cell is a bifacial solar cell, the second semiconductor layer 5 covers at least a portion of the second surface of the semiconductor substrate 1, and the second semiconductor layer 5 has an opposite conductivity type to the first semiconductor layer 2, so as to collect and extract electrons and holes respectively, thereby facilitating the formation of photocurrent. In this technical solution, the first semiconductor layer 2 and the second semiconductor layer 5 are respectively located on the first surface and the second surface of the semiconductor substrate 1.

[0112] In the case where the solar cell is a back-contact solar cell, the solar cell further includes a second semiconductor layer 5, the second semiconductor layer 5 covers at least a portion of the second region 1c, and the second semiconductor layer 5 has an opposite conductivity type to the first semiconductor layer 2, so as to respectively collect and extract electrons and holes, thereby facilitating the formation of photocurrent. In this technical solution, the first semiconductor layer 2 and the second semiconductor layer 5 are both located on the first surface of the semiconductor substrate 1.

[0113] In the above embodiments, the conductivity type of the first semiconductor layer 2 may be N-type, in which case the conductivity type of the second semiconductor layer 5 is P-type; or the conductivity type of the first semiconductor layer 2 may be P-type, in which case the conductivity type of the second semiconductor layer 5 is N-type.

[0114] Among them, the materials of the first semiconductor layer 2 and the second semiconductor layer 5 can be silicon (Si), germanium (Ge), silicon carbide (SiCx) or gallium arsenide (GaAs) and the like. Taking the case where the materials of the first semiconductor layer 2 and the second semiconductor layer 5 are both silicon (Si) as an example, the second semiconductor layer 5 can include one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. In addition, the first semiconductor layer 2 can be doped polycrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first semiconductor layer 2 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is conducive to improving the photoelectric conversion efficiency of the back contact battery. Of course, the first semiconductor layer 2 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The first semiconductor layer 2 can be additionally formed on the semiconductor substrate 1 by deposition technology, or it can be formed in the semiconductor substrate 1 by diffusion, ion implantation, etc.

[0115] In some embodiments, the solar cell may further include a first interface layer 10, which is located at least between the first semiconductor layer 2 and the semiconductor substrate 1. In this case, the passivation contact structure composed of the first interface layer 10 and the first semiconductor layer 2 has an excellent interface passivation effect, and can achieve selective collection of carriers, reduce the carrier recombination rate in the region where the first semiconductor layer 2 is formed on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the back contact cell. The material and thickness of the first interface layer 10 can be set according to the material of the first semiconductor layer 2 and actual needs, and are not specifically limited here.

[0116] Among them, the material of the above-mentioned first interface layer 10 can be determined according to the material of the first semiconductor layer 2. For example: when the first semiconductor layer 2 includes a doped polysilicon layer, the first interface layer 10 is a tunneling oxide layer; in this way, the first semiconductor layer 2 and the first interface layer 10 form a tunneling oxide layer passivation contact, and the tunneling oxide layer passivation technology can form a tunneling film between the first electrode 4 and the semiconductor substrate 1, isolating the first electrode 4 from contacting the semiconductor substrate 1, reducing contact recombination losses, and electrons can tunnel through the film without affecting current transfer. At the same time, passivation can bend the surface energy band, reduce the surface recombination loss of the silicon wafer, and effectively improve the front passivation and metal contact problems. For another example: when the first semiconductor layer 2 includes a doped amorphous silicon layer, the first interface layer 10 includes an intrinsic amorphous silicon layer. Secondly, the embodiment of the present invention does not specifically limit the material of the first interface layer 10.

[0117] In some embodiments, the back contact cell may further include a second interface layer 12, which is located at least between the second semiconductor layer 5 and the semiconductor substrate 1. The projection of the second interface layer 12 on the semiconductor substrate 1 may overlap with the projection of the second semiconductor layer 5 on the semiconductor substrate 1. In this case, the passivation contact structure composed of the second interface layer 12 and the second semiconductor layer 5 can realize the selective collection of carriers and reduce the carrier recombination rate in the area where the second semiconductor layer 5 is formed on the first surface of the semiconductor substrate 1. The material and thickness of the second interface layer 12 can be set according to the material of the second semiconductor layer 5 and actual needs, and are not specifically limited here. For example: when the material of the second semiconductor layer 5 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer 12 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon layer.

[0118] As for the thickness of the second interface layer 12, since the thickness of the second interface layer 12 will affect its own transmission resistance and passivation effect, and further affect the forward leakage loss and reverse breakdown voltage of the back contact battery, the thickness of the second interface layer 12 can be determined according to the requirements of the forward leakage loss and reverse breakdown voltage of the back contact battery in the actual application scenario, and no specific limitation is made here.

[0119] In the above embodiment, the thickness of the first interface layer 10 can be set according to the material of the second semiconductor layer 5 and actual needs, and is not specifically limited here. Exemplarily, the thickness of the first interface layer 10 is 1nm to 5nm, for example, the thickness of the first interface layer 10 is 1nm, 2nm, 3nm, 4nm or 5nm. The thickness of the second interface layer 12 can be set according to the material of the second semiconductor layer 5 and actual needs, and is not specifically limited here. Exemplarily, the thickness of the second interface layer 12 is 1nm to 5nm, for example, the thickness of the second interface layer 12 is 1nm, 2nm, 3nm, 4nm or 5nm.

[0120] In addition, the embodiment of the present invention does not specifically limit the thickness of the first semiconductor layer 2 and the second semiconductor layer 5, the doping concentration of impurities in the first semiconductor layer 2, and the doping concentration of impurities in the second semiconductor layer 5, as long as they can be applied to the back contact battery provided in the embodiment of the present invention.

[0121] Exemplarily, the thickness of the first semiconductor layer 2 may be greater than or equal to 80 nm and less than or equal to 160 nm. For example, the thickness of the first semiconductor layer 2 may be 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm or 160 μm. The thickness of the second semiconductor layer 5 may be greater than or equal to 5 nm and less than or equal to 50 nm. For example, the thickness of the second semiconductor layer 5 may be 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 40 nm or 50 nm, etc.

[0122] In other embodiments, when the solar cell is a bifacial cell, the second semiconductor layer 5 covers at least a portion of the second surface of the semiconductor substrate 1, and a transparent conductive layer 6 may be provided on the side of the second semiconductor layer 5 away from the semiconductor substrate 1. Specifically, when the second semiconductor layer 5 is one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, a transparent conductive layer 6 may be provided on the side of the first semiconductor layer 2 away from the semiconductor substrate 1. The transparent conductive layer 6 has a high electrical conductivity and can timely guide the collected carriers to reduce the carrier recombination rate. When the first semiconductor layer 2 is doped polycrystalline silicon, a transparent conductive layer 6 may be provided on the side of the first semiconductor layer 2 away from the semiconductor substrate 1, or a transparent conductive layer 6 may not be provided.

[0123] The material of the transparent conductive layer 6 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide.

[0124] The present invention provides a method for manufacturing a back contact battery. Figures 8 to 19 The manufacturing process is described in detail with reference to the cross-sectional view of the operation shown in FIG. 1 . Specifically, the manufacturing method of the back contact battery includes the following steps:

[0125] S100: providing a semiconductor substrate 1, wherein the semiconductor substrate 1 has a first surface and a second surface opposite to each other; the first surface comprises a first region 1a, a transition region 1b, and a second region 1c which are arranged adjacent to each other in sequence along a first direction;

[0126] The material of the semiconductor substrate 1, and the ranges of the first region 1a, the transition region 1b, and the second region 1c on the first surface side can be referred to above and will not be described in detail here.

[0127] Before this step, the semiconductor substrate 1 can also be placed in a polishing and cleaning machine to remove the cut damage layer of the semiconductor substrate 1 using a polishing liquid. In addition, in this step, the morphology of the first surface and the second surface of the semiconductor substrate 1 after polishing and cleaning can be adjusted by adjusting parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step can be omitted.

[0128] S200: texturing the semiconductor substrate 1 so that at least the first surface of the semiconductor substrate 1 forms a first pyramid-shaped texture surface;

[0129] In the actual manufacturing process, Figure 8 As shown, the pyramid-shaped suede surface can be formed on the first surface, the second surface and the side surface of the semiconductor substrate 1, or the pyramid-shaped suede surface can be formed only on the first surface.

[0130] S300: forming a first semiconductor layer 2 on a first surface of a semiconductor substrate 1;

[0131] In the actual manufacturing process, Fig. 9 As shown, the first semiconductor layer 2 can be formed on the first surface, the second surface and the side surface of the semiconductor substrate 1, or the first semiconductor layer 2 can be formed on the first surface as a whole layer. Fig.10 As shown, a mask layer 11 is formed on the side of the first semiconductor layer 2 away from the semiconductor substrate 1. The material of the mask layer 11 can be silicon nitride, and the mask layer 11 can be formed by LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), etc. Then, as Fig.11 As shown, the mask layer 11 is selectively etched to remove the portion of the mask layer 11 corresponding to the second region 1c, and retain the portion of the mask layer 11 corresponding to the first region 1a.

[0132] It should be noted that, in the case where the solar cell further includes a first interface layer 10, in this step, deposition and etching processes may be used to form the first interface layer 10 before forming the first semiconductor layer 2. Then, a mask layer 11 is formed, and under the masking effect of the mask layer 11, laser etching or wet chemical process or other etching methods are used to remove the first semiconductor layer 2 and the first interface layer 10 corresponding to the second region 1c, and the first semiconductor layer 2 and the first interface layer 10 corresponding to the first region 1a and the transition region 1b are retained.

[0133] In this step, the first semiconductor layer 2 and the first interface layer 10 can be realized by LPCVD, PECVD, PVD (Physical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), etc. When the first interface layer 10 is an oxide tunneling layer, the oxide tunneling layer can be formed by the above-mentioned method, and can also be generated by a high-temperature reaction of oxygen with the first surface of the semiconductor substrate 1, or the oxide tunneling layer can also be generated by a wet chemical method, such as the reaction of silicon with ozone, the oxidation reaction of silicon with nitric acid, etc. to generate the oxide tunneling layer.

[0134] It should be noted that the material of the first interface layer 10 can be referred to above and will not be described in detail here.

[0135] The thickness of the first interface layer 10 may be 1 nm to 4 nm, for example, 1 nm, 1.4 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, etc.

[0136] The mask layer 11 may be formed, for example, by LPCVD or PECVD. In some examples, the material of the first mask layer 11 may include silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbide, or intrinsic silicon.

[0137] S400: Selectively etching a portion of the semiconductor substrate 1 corresponding to the second region 1c to remove the first semiconductor layer 2 in the second region 1c. The first pyramid 8 adjacent to the second region 1c in the transition region 1b is an edge pyramid. The edge pyramid extends toward the second region 1c to form a suspended brim portion 1e, so that the first edge 2b of the first semiconductor layer 2 close to the second region 1c is set on the edge pyramid, and a bottom cut structure 2a is formed between the first edge 2b of the first semiconductor layer 2 and the edge pyramid.

[0138] Then as Fig.12 As shown, the first semiconductor layer 2 is selectively etched to remove the portion of the first semiconductor layer 2 corresponding to the second region 1c, and retain the portion of the first semiconductor layer 2 corresponding to the first region 1a and the transition region 1b, thereby completing the patterning of the first semiconductor layer 2. In this step, the first semiconductor layer 2 can be formed into a poly-finger. Fig.13 As shown, the mask layer 11 is removed.

[0139] When the first semiconductor layer 2 is selectively etched, the wet etching solution can also texture the semiconductor substrate 1, and the first pyramid 8 adjacent to the second area 1c in the transition area 1b is an edge pyramid, and the edge pyramid extends toward the second area 1c to form a suspended brim 1e, and the brim 1e is a part of the edge pyramid, that is, the edge of the brim 1e close to the second area 1c forms a suspended structure. In addition, the first edge 2b of the first semiconductor layer 2 close to the second area 1c is arranged on the edge pyramid, and there is an undercut structure 2a between the first edge 2b of the first semiconductor layer 2 and the edge pyramid. The undercut structure 2a extends from the upper side of the first edge 2b of the first semiconductor layer 2 to the lower side, and finally extends to the side wall of the edge pyramid close to the second area 1c. Specifically, the first semiconductor layer 2 at least covers one side of the brim 1e close to the first area 1a and the top of the brim 1e. The first edge 2b of the first semiconductor layer 2 is supported by the edge pyramid.

[0140] In the solar cell structure formed by the above manufacturing method, a part of the light is reflected from the second area 1c to the brim 1e. Since the brim 1e forms a suspended structure toward the second area 1c, the light reflected to the brim 1e will be reflected again to the second area 1c and absorbed and utilized by the semiconductor substrate 1, which is beneficial to improve the photoelectric conversion efficiency of the back contact battery. In addition, the brim 1e forms a suspended structure toward the second area 1c, so that the distance between the edge of the brim 1e away from the first area 1a and the first semiconductor layer 2 can be larger, avoiding the defects at the edge of the brim 1e from approaching the first semiconductor layer 2, thereby reducing defect recombination. In addition, the first edge 2b of the first semiconductor layer 2 extends to the side of the brim 1e away from the semiconductor substrate 1, or in other words, the first edge 2b of the first semiconductor layer 2 extends to the upper side of the brim 1e, so that the first edge 2b of the first semiconductor layer 2 is supported by the brim 1e, which can prevent the first edge 2b of the first semiconductor layer 2 from collapsing at the edge of the transition area 1b.

[0141] In the above embodiment, step S400 may specifically include:

[0142] S401: forming a mask layer 11 on a side of the first semiconductor layer 2 facing away from the semiconductor substrate 1 and performing patterning;

[0143] like Fig.11 As shown, the mask layer 11 is selectively etched to remove the portion of the mask layer 11 corresponding to the second region 1c, and retain the portion of the mask layer 11 corresponding to the first region 1a.

[0144] S402: removing the first semiconductor layer 2 not covered by the mask layer 11;

[0145] like Fig.12As shown, the first semiconductor layer 2 is selectively etched to remove the portion of the first semiconductor layer 2 corresponding to the second region 1c, and retain the portion of the first semiconductor layer 2 corresponding to the first region 1a and the transition region 1b, thereby completing the patterning of the first semiconductor layer 2. In this step, the first semiconductor layer 2 can be formed into a poly-finger.

[0146] When selectively etching the first semiconductor layer 2, the etching solution can also texturize the area of ​​the semiconductor substrate 1 not covered by the mask layer 11, so that the second area 1c presents a second pyramid-shaped texturized surface, and the first pyramid 8 adjacent to the second area 1c in the transition area 1b is an edge pyramid, and the edge pyramid extends toward the second area 1c to form a suspended brim portion 1e, so that the first edge 2b of the first semiconductor layer 2 close to the second area 1c is set on the edge pyramid, and a bottom cut structure 2a is formed between the first edge 2b of the first semiconductor layer 2 and the edge pyramid.

[0147] Next, the area of ​​the semiconductor substrate 1 not covered by the mask layer 11 is textured again, so that the edge pyramid extends toward the second area 1c to form a suspended brim portion 1e, and an undercut structure 2a is formed between the first edge 2b of the first semiconductor layer 2 and the edge pyramid.

[0148] By adopting the above-mentioned manufacturing method and the two-time texturing method, the edge pyramid is finally extended toward the second area 1c to form a suspended brim portion 1e, and a bottom cut structure 2a is formed between the first edge 2b of the first semiconductor layer 2 and the edge pyramid, thereby improving the light utilization rate of the solar cell and preventing the first edge 2b of the first semiconductor layer 2 from collapsing.

[0149] In some embodiments, after step S400, the method further includes:

[0150] S501: forming a passivation layer 3 on the second region 1c of the first surface and on a side of the first semiconductor facing away from the semiconductor substrate 1;

[0151] like Fig.14 As shown, in this step, a passivation layer 3 is formed at least on the second region 1c of the first surface and on the side of the first semiconductor away from the semiconductor substrate 1. In the actual manufacturing process, the passivation layer 3 can be formed on both the first surface and the second surface. The thickness, number of layers and material of the passivation layer 3 can be referred to above and will not be repeated here.

[0152] S601: Grooving a portion of the passivation layer 3 corresponding to the first region 1a;

[0153] Next, if Fig.15 As shown, a groove is formed in a portion of the passivation layer 3 corresponding to the first region 1 a . Specifically, the groove can be formed by using a laser process, and the grooved region is used to form the first electrode 4 .

[0154] S701: forming a second semiconductor layer 5 on the second surface, wherein the conductivity type of the second semiconductor layer 5 is opposite to that of the first semiconductor layer 2;

[0155] By adopting the above technical solution, a double-sided solar cell is formed in steps S501 to S701.

[0156] like Fig.16 As shown, after step S601 and before step S701 , the side surface of the semiconductor substrate 1 and the passivation layer 3 formed on the second surface need to be removed, and the first semiconductor layer 2 and the first interface layer 10 on the second surface of the semiconductor substrate 1 also need to be removed.

[0157] like Fig.17 As shown, in this step, the second semiconductor layer 5 can be formed only on the second surface of the semiconductor substrate 1, or on the second surface and the side of the semiconductor substrate 1. In the case where the solar cell also includes a second interface layer 12, before forming the second semiconductor layer 5, the second interface layer 12 is first formed, and the second semiconductor layer 5 is formed on the side of the second interface layer 12 away from the semiconductor substrate 1. In the actual manufacturing process, the second semiconductor layer 5 can be formed by chemical vapor deposition and doping processes.

[0158] S801 : forming a first electrode 4 in the grooved region of the passivation layer 3 , and forming a second electrode 7 on a side of the second semiconductor layer 5 facing away from the semiconductor substrate 1 .

[0159] In this step, when the second surface of the solar cell further includes a transparent conductive layer 6, as Fig.18 As shown, before forming the second electrode 7 , a transparent conductive layer 6 may be formed on the surface of the second semiconductor layer 5 facing away from the semiconductor substrate 1 .

[0160] In the actual manufacturing process, the transparent conductive layer 6 can be formed by PVD, and a laser process can be used to open an opening that penetrates the transparent conductive layer 6. Exemplarily, the thickness of the transparent conductive layer 6 can be greater than or equal to 10 nm and less than or equal to 500 nm; preferably, the thickness of the transparent conductive layer 6 is greater than or equal to 50 nm and less than or equal to 200 nm.

[0161] The material of the transparent conductive layer 6 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide and indium hydroxide. The transparent conductive layer 6 may be a single-layer film or a laminated film.

[0162] Finally, a process such as screen printing, electroplating or evaporation can be used to form a first electrode 4 in the grooved region of the passivation layer 3 and a second electrode 7 on a side of the second semiconductor layer 5 facing away from the semiconductor substrate 1 .

[0163] The first electrode 4 and the second electrode 7 can be made of silver, copper, aluminum, or alloys thereof. The first electrode 4 and the second electrode 7 can be the same or different.

[0164] In some other embodiments, after step S400, the method further includes:

[0165] S502: forming a second semiconductor layer 5 at least in the second region 1c of the first surface; the second semiconductor layer 5 and the first semiconductor layer 2 have opposite conductivity types;

[0166] In this step, a second semiconductor layer 5 may be formed on the entire first surface of the semiconductor substrate 1, and then a portion of the second semiconductor layer 5 may be removed by laser or wet etching to expose a portion of the first semiconductor layer 2. The second semiconductor layer 5 and the first semiconductor layer 2 have opposite conductivity types.

[0167] In the actual manufacturing process, chemical vapor deposition and doping processes can be used to form the second semiconductor layer 5 disposed entirely on the first surface. Then, laser etching and other processes are used to remove the portion of the second semiconductor layer 5 located above at least a portion of the first semiconductor layer 2 under the masking action of the corresponding mask layer 11 or mask.

[0168] S602: forming a passivation layer 3 on a first surface of the semiconductor substrate 1;

[0169] In this step, a passivation layer 3 is formed at least on the first surface. The thickness, number of layers and material of the passivation layer 3 can be referred to above and will not be described in detail here.

[0170] S702 : forming a first electrode 4 in a region of the passivation layer 3 corresponding to the first region, and forming a second electrode 7 in a region of the passivation layer 3 corresponding to the second semiconductor layer 5 .

[0171] In this step, grooves may be formed in the portion of the passivation layer 3 corresponding to the first semiconductor layer 2 and the portion corresponding to the second semiconductor layer 5. Specifically, a laser process may be used to form grooves in the passivation layer 3. Then, a process such as screen printing, electroplating or evaporation may be used to form a first electrode 4 in the grooved region corresponding to the first semiconductor layer 2, and a second electrode 7 in the grooved region of the passivation layer 3 corresponding to the second semiconductor layer 5.

[0172] Alternatively, the first electrode 4 may pass through the passivation layer 3 to make ohmic contact with the first semiconductor layer 2 by means of a burn-through method. Similarly, the second electrode 7 may pass through the passivation layer 3 to make ohmic contact with the second semiconductor layer 5 by means of a burn-through method.

[0173] The first electrode 4 and the second electrode 7 can be made of silver, copper, aluminum, or alloys thereof. The first electrode 4 and the second electrode 7 can be the same or different.

[0174] In step S400, the portion of the semiconductor substrate 1 corresponding to the second region 1c is selectively etched to remove the first semiconductor layer 2 in the second region 1c, and at the same time, the surface of the second region 1c is recessed relative to the first region 1a in the direction of the second surface along the direction from the second surface to the first surface, thereby forming a groove structure. In the actual manufacturing process, the portion of the semiconductor substrate 1 corresponding to the second region 1c can be etched under the masking effect of the mask layer 11 and by a wet chemical process, so that the surface of the second region 1c is lower than the surface of the first region 1a in the direction from the second surface to the first surface, thereby forming a groove structure.

[0175] In addition, the present application also provides a photovoltaic assembly, which includes a plurality of solar cells provided in any of the above embodiments, or includes a plurality of solar cells formed by the method for manufacturing a solar cell provided in any of the above embodiments. Compared with the prior art, the beneficial effects of the photovoltaic assembly provided in the embodiment of the present application are the same as the beneficial effects of the above solar cell and the method for manufacturing a solar cell, and will not be described in detail here.

[0176] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0177] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface arranged opposite to each other, wherein the first surface includes a first region, a transition region, and a second region arranged adjacent to each other in sequence along a first direction; a first semiconductor layer, wherein the first semiconductor layer covers the first region; The first region and the transition region include a plurality of first pyramids, wherein the first pyramid in the transition region adjacent to the second region is an edge pyramid, and the edge pyramid extends toward the second region to form a suspended brim portion; A first edge of the first semiconductor layer close to the second region is disposed on the edge pyramid, and an undercut structure is provided between the first edge of the first semiconductor layer and the edge pyramid.

2. The solar cell according to claim 1, characterized in that: Along the first direction, the width of the brim portion is less than or equal to 200 nm; and / or, Along the first direction, the depth of the undercut structure is less than or equal to 100 nm.

3. The solar cell according to claim 1, characterized in that Along the first direction, an edge of the brim portion close to the second region is closer to the second region than the first edge.

4. The solar cell according to claim 1, characterized in that Along the extension direction of the first semiconductor layer, a side of the first edge close to the semiconductor substrate extends in a wave shape.

5. The solar cell according to claim 1, characterized in that: The brim portion has at least one raised bottom edge on a side facing the semiconductor substrate.

6. The solar cell according to claim 1, characterized in that The second region includes a plurality of second pyramids, and an average height of the second pyramids is greater than an average height of the first pyramids; and / or, The height of the first pyramid ranges from 500nm to 3000nm; and / or, The height of the second pyramid ranges from 800nm ​​to 5000nm.

7. The solar cell according to claim 1, characterized in that The solar cell further includes a passivation layer, which covers the side of the first semiconductor layer facing away from the semiconductor substrate and the second region; the passivation layer wraps the brim portion and fills the undercut structure.

8. The solar cell according to claim 7, characterized in that: The passivation layer is a single-layer structure; or, the passivation layer is a double-layer structure; or, the passivation layer includes one or more of silicon nitride, silicon oxide, aluminum oxide or phosphate glass.

9. The solar cell according to claim 1, characterized in that: The second region is formed into a groove structure that is recessed relative to the first region toward the second surface; Prisms inclined toward the first region are formed in the transition region.

10. The solar cell according to claim 9, characterized in that: The angle between the prism and the first surface is between 50° and 60°.

11. The solar cell according to claim 9, characterized in that: The projection width of the prism on the first surface is 1-8 μm.

12. The solar cell according to claim 1, characterized in that The solar cell further includes a second semiconductor layer, which covers at least a portion of the second surface of the semiconductor substrate, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer.

13. The solar cell according to claim 1, characterized in that The solar cell further includes a second semiconductor layer, the second semiconductor layer covers at least a portion of the second region, and the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer.

14. The solar cell according to claim 12 or 13, characterized in that: The first semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell further includes a first interface layer located on a side of the first semiconductor layer close to the semiconductor substrate; The second semiconductor layer includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon; the solar cell also includes a second interface layer located on a side of the second semiconductor layer close to the semiconductor substrate.

15. A method for manufacturing a solar cell, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other; the first surface comprises a first region, a transition region and a second region which are arranged adjacent to each other in sequence along a first direction; Performing texturing on the semiconductor substrate so that at least a first surface of the semiconductor substrate forms a first pyramid-shaped texturing surface; forming a first semiconductor layer on a first surface of the semiconductor substrate; A portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, a first pyramid in the transition region adjacent to the second region is an edge pyramid, and the edge pyramid extends toward the second region to form a suspended brim portion, so that a first edge of the first semiconductor layer close to the second region is arranged on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid.

16. The method for manufacturing a solar cell according to claim 15, characterized in that: The method comprises: selectively etching a portion of the semiconductor substrate corresponding to the second region to remove the first semiconductor layer in the second region, wherein the first pyramid in the transition region adjacent to the second region is an edge pyramid, and the edge pyramid extends toward the second region to form a suspended brim portion, so that a first edge of the first semiconductor layer close to the second region is arranged on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid, comprising: forming a mask layer on a side of the first semiconductor layer away from the semiconductor substrate and performing patterning; removing the first semiconductor layer not covered by the mask layer; The area of ​​the semiconductor substrate not covered by the mask layer is textured so that the second area presents a second pyramid-shaped texture surface, the first pyramid adjacent to the second area in the transition area is an edge pyramid, and the edge pyramid extends toward the second area to form a suspended brim portion, so that the first edge of the first semiconductor layer close to the second area is arranged on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid.

17. The method for manufacturing a solar cell according to claim 15, characterized in that: The portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, the first pyramid in the transition region adjacent to the second region is an edge pyramid, the edge pyramid extends toward the second region to form a suspended brim portion, a first edge of the first semiconductor layer close to the second region is arranged on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid, the method for manufacturing a solar cell further comprises: forming a passivation layer on the second region of the first surface and on a side of the first semiconductor facing away from the semiconductor substrate; Grooving a portion of the passivation layer corresponding to the first region; forming a second semiconductor layer on the second surface, wherein the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; A first electrode is formed in the groove region of the passivation layer, and a second electrode is formed on a side of the second semiconductor layer facing away from the semiconductor substrate.

18. The method for manufacturing a solar cell according to claim 15, characterized in that: The portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, the first pyramid in the transition region adjacent to the second region is an edge pyramid, the edge pyramid extends toward the second region to form a suspended brim portion, a first edge of the first semiconductor layer close to the second region is arranged on the edge pyramid, and an undercut structure is formed between the first edge of the first semiconductor layer and the edge pyramid, the method for manufacturing a solar cell further comprises: forming a second semiconductor layer at least in a second region of the first surface, wherein the conductivity type of the second semiconductor layer is opposite to that of the first semiconductor layer; forming a passivation layer on the first surface of the semiconductor substrate; A first electrode is formed in a region of the passivation layer corresponding to the first region, and a second electrode is formed in a region of the passivation layer corresponding to the second semiconductor layer.

19. The method for manufacturing a solar cell according to claim 15, characterized in that: Selectively etching a portion of the semiconductor substrate corresponding to the second region to remove the first semiconductor layer in the second region, comprising: The portion of the semiconductor substrate corresponding to the second region is selectively etched to remove the first semiconductor layer in the second region, and at the same time, the surface of the second region is recessed relative to the first region in the direction from the second surface to the first surface to form a groove structure.

20. A photovoltaic module, characterized in that: The method comprises a plurality of solar cells according to any one of claims 1 to 14, or comprises a plurality of solar cells formed by the manufacturing method according to any one of claims 15 to 19.

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