Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, and relates to the technical field of photovoltaics. The solar cell comprises a silicon wafer, and the silicon wafer comprises a light facing surface and a backlight surface. The light-facing surface of the silicon wafer is provided with a first suede structure, and at least partial area of the backlight surface of the silicon wafer is provided with a second suede structure; the included angle between the side wall of the second suede structure and the first plane is a first included angle, the included angle between the side wall of the first suede structure and the first plane is a second included angle, the first included angle is larger than the second included angle, and the difference value between the first included angle and the second included angle ranges from 2 degrees to 20 degrees. According to the invention, the incident angle is relatively large when light reaches the backlight surface, and the transmission loss is relatively reduced. When the light reflected in the backlight surface reaches the light-facing surface, the incident angle is large, so that less light escapes from the front surface. Through the relevance design of the first suede structure and the second suede structure, the front escape loss and the back transmission loss of the solar cell can be minimized, and the current and the efficiency of the solar cell can be improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, in particular to a solar cell and a photovoltaic module. Background Art

[0002] The light conversion effect and output current of solar cells are greatly affected by the surface structure of silicon wafers. In the process of preparing solar cells, a velvet structure is usually prepared on the surface of silicon wafers to reduce the reflection loss of incident light.

[0003] At present, in order to improve production efficiency, velvet structures of similar size are usually prepared on the light-facing side and the backlight side of the silicon wafer. Alternatively, in order to improve the absorption and utilization rate of long-wave light by solar cells, the backlight side of the silicon wafer can be set as a polished surface.

[0004] However, preparing velvet structures of similar sizes on the light-facing and back-light sides of the silicon wafer will result in large long-wave transmission losses. Setting the back-light side of the silicon wafer as a polished surface can effectively reduce the transmission loss of long-wave light, but it also increases the escape loss of long-wave light on the light-facing side of the solar cell to a certain extent. In other words, the light trapping effect in current solar cells is poor. Summary of the invention

[0005] The present invention provides a solar cell and a photovoltaic module, aiming to solve the problem of poor light trapping effect in existing solar cells.

[0006] A first aspect of the present invention provides a solar cell, comprising a silicon wafer, the silicon wafer comprising: a light-facing surface and a backlight surface;

[0007] The light-facing surface of the silicon wafer has a first velvet structure, and at least a portion of the backlight surface of the silicon wafer has a second velvet structure;

[0008] The included angle between the side wall of the second suede structure and the first plane is a first included angle, and the included angle between the side wall of the first suede structure and the first plane is a second included angle;

[0009] The first plane is perpendicular to the thickness direction of the silicon wafer;

[0010] The first angle is greater than the second angle, and a difference between the first angle and the second angle is 2° to 20°.

[0011] In the silicon wafer of the solar cell of the present application, the first angle is greater than the second angle, and the difference between the first angle and the second angle is 2° to 20°. When the light reaches the backlight surface, the incident angle is relatively large, so the transmission loss will be relatively reduced. At the same time, the incident angle of the light reflected from the backlight surface when reaching the light-facing surface is also relatively large, so less escape from the front will occur. In summary, through the associative design of the above-mentioned first velvet structure and the second velvet structure, the front escape loss and the back transmission loss of the silicon wafer and the solar cell can be minimized, which can effectively improve the current and efficiency of the solar cell.

[0012] Optionally, the difference between the first angle and the second angle is 3.5° to 10°.

[0013] Optionally, the area of ​​the second velvet structure accounts for a proportion of greater than or equal to 10% of the area of ​​the backlight surface of the silicon wafer.

[0014] Optionally, the backlight surface of the silicon wafer is divided into a first conductive region, a second conductive region, and an isolation region located between the first conductive region and the second conductive region;

[0015] The second velvet structure is located in the isolation area.

[0016] Optionally, both the first conductive region and the second conductive region have a polishing structure; or,

[0017] One of the first conductive region and the second conductive region is a P-type conductive region, and the other is an N-type conductive region. The P-type conductive region has a polished structure, and the N-type conductive region has a velvet structure.

[0018] Optionally, the second velvet structure is only located in the isolation region, and the area of ​​the second velvet structure occupies 10% to 40% of the area of ​​the backlight surface of the silicon wafer.

[0019] Optionally, the second angle is 45° to 70°, and the first angle is 50° to 80°.

[0020] Optionally, the first angle is 51.5° to 70°.

[0021] Optional,

[0022] The height of the first velvet structure is 0.2 μm to 10 μm; and / or,

[0023] The width of the first velvet structure is 0.14 μm to 20 μm; and / or,

[0024] The height of the second velvet structure is 0.2 μm to 10 μm; and / or,

[0025] The second texture structure has a width of 0.07 μm to 19 μm.

[0026] Optionally, the height of the first velvet structure is 0.8 μm to 3 μm; and / or,

[0027] The width of the first velvet structure is 0.58 μm to 6 μm; and / or,

[0028] The height of the second velvet structure is 0.8 μm to 3 μm; and / or,

[0029] The second texture structure has a width of 0.28 μm to 5.6 μm.

[0030] Optionally, the first velvet structure includes: a plurality of first-type pyramidal structures, and the second velvet structure includes: a plurality of second-type pyramidal structures; the dimensions of the first-type pyramidal structures and the dimensions of the second-type pyramidal structures both include: height and / or width, and the height direction is parallel to the thickness direction of the silicon wafer;

[0031] The plurality of second-type pyramidal structures include pyramidal structures of at least two sizes.

[0032] Optionally, the solar cell further comprises:

[0033] A first carrier transport layer and a second carrier transport layer are located on the silicon wafer; one of the first carrier transport layer and the second carrier transport layer is an N-type carrier transport layer, and the other is a P-type carrier transport layer.

[0034] Optionally, the first carrier transport layer includes: a first doping layer and a first passivation layer that are stacked; the first passivation layer is closer to the silicon wafer; the first passivation layer includes: a tunneling oxide layer or an intrinsic amorphous silicon layer;

[0035] The second carrier transport layer includes: a second doping layer and a second passivation layer which are stacked; the second passivation layer is closer to the silicon wafer; the second passivation layer includes: a tunneling oxide layer or an intrinsic amorphous silicon layer; the first doping layer and the second doping layer have different doping types.

[0036] Optionally, the first carrier transport layer is located on the backlight side of the silicon wafer, and the second carrier transport layer is located on the light-facing side of the silicon wafer.

[0037] A second aspect of the present invention provides a photovoltaic assembly, comprising: a plurality of any of the aforementioned solar cells.

[0038] The above-mentioned solar cells and photovoltaic modules have the same or similar beneficial effects, and will not be described in detail here to avoid repetition. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0040] Figure 1 A schematic diagram of the optical path of a silicon wafer in a solar cell of the related art is shown;

[0041] Figure 2 A comparison diagram showing the light absorption and transmission results of a silicon wafer in a solar cell of the related art;

[0042] Figure 3 A schematic diagram showing the optical path of a silicon wafer in a solar cell of another related technology is shown;

[0043] Figure 4 A comparison diagram showing light absorption and transmission results of a silicon wafer in a solar cell of another related technology;

[0044] Figure 5 A schematic diagram of the optical path of a silicon wafer in a solar cell of the present application is shown;

[0045] Figure 6 A comparison diagram of light absorption and transmission results of a silicon wafer in a solar cell of the present application is shown;

[0046] Figure 7 A schematic diagram showing the structure of a silicon wafer in a solar cell of the present application is shown;

[0047] Figure 8 A schematic diagram showing the structure of a silicon wafer in another solar cell of the present application is shown;

[0048] Figures 9 to 11 The schematic diagrams of the structures of three solar cells of the present application are shown.

[0049] Description of Figure Numbers:

[0050] 100-silicon wafer, 110-light-facing side of the silicon wafer, 120-backlight side of the silicon wafer, 1-second velvet structure, 111-height of the first velvet structure, 112-width of the first velvet structure, 121-height of the second velvet structure, 122-width of the second velvet structure, 3-first carrier transport layer, 4-second carrier transport layer. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] The present application provides a solar cell, which comprises a silicon wafer, Figure 1 , Figure 3 and Figure 5 In the figure, the upper surface is the light-facing surface of the silicon wafer 100, the lower surface is the backlight surface of the silicon wafer 100, the thick straight line arrows are all schematic diagrams of the transmitted light path, and the thin straight line arrows are all schematic diagrams of the reflected light path. Figure 1 , Figure 3 and Figure 5 In the embodiment, the thickness of the silicon wafers 100 is the same, for example, the thickness of the silicon wafers 100 is 155 μm (micrometer). Figure 2 , Figure 4 and Figure 6 Respectively refers to Figure 1 , Figure 3 , Figure 5 The silicon wafers in the figure are respectively used in the same type of solar cells, and the ratios of light absorbed by the silicon wafer 100, light escaping from the light-facing front side of the silicon wafer 100, and light transmitted from the back side of the silicon wafer 100 are obtained under the same test conditions. Figure 2 , Figure 4 and Figure 6 In the figure, the horizontal axis refers to the wavelength of light in nm, and the vertical axis refers to the corresponding ratio. Figure 2 , Figure 4 and Figure 6 In the figure, the curves with rectangles refer to the proportion of light absorbed by the silicon wafer 100, the curves with circles refer to the proportion of light escaping from the light-facing side of the silicon wafer 100, that is, the front side, and the curves with triangles refer to the proportion of light passing through the backlight side of the silicon wafer 100, that is, the back side. Figure 2 , Figure 4 and Figure 6 In the figure, the current density corresponding to the bulk silicon absorption refers to the maximum current density that the corresponding solar cell can reach, the current density corresponding to the front escape refers to the current density lost by the corresponding solar cell due to the light escaping from the front, and the current density corresponding to the back transmission refers to the current density lost by the corresponding solar cell due to the light transmitted from the back. The first plane is perpendicular to the thickness direction of the silicon wafer. For example, refer to Figure 5 The middle line L is a schematic diagram of the first plane, which may not be a part of the outer surface of the silicon wafer, but may be a cross section of the silicon wafer, which is perpendicular to the thickness direction of the silicon wafer.

[0053] Specifically, refer to Figure 1 and Figure 2 The light-facing side and the back-facing side of the silicon wafer 100 of the solar cell are prepared with velvet structures of similar size, and the entire light-facing side of the silicon wafer 100 has a relatively uniform velvet structure, and the entire back-facing side of the silicon wafer 100 has a relatively uniform velvet structure, that is, Figure 1 The first angle between the sidewall of the velvet structure on the backlight side of the silicon wafer 100 and the first plane perpendicular to the thickness direction of the silicon wafer 100 is equal to the second angle between the sidewall of the velvet structure on the light-facing side of the silicon wafer 100 and the first plane, and both are 54.74°. Figure 1 After the light enters the silicon wafer 100 from the light-facing side, it reaches the backlight side from the inside of the silicon wafer 100. The incident angle of the light on the velvet structure surface of the backlight side is very small, so it is more likely to be transmitted. Figure 2 Most of the light with wavelength greater than or equal to 900nm is transmitted from the backlight side of the silicon wafer, so the transmission loss (also called back transmission) is very large. Figure 2 , Figure 1 In the solar cell corresponding to the silicon wafer, the current density lost due to the light transmitted through the back side is large, reaching 3.48mA / cm 2 (milliamperes per square centimeter), refer to Figure 1 , the incident angle of the light reflected internally to the light-facing surface is larger, so the front escape loss is smaller, that is Figure 2 Compared with the light transmitted from the backlight side of the silicon wafer, less light escapes from the light-facing side of the silicon wafer. The current density lost by the light escaping from the front side is small, which is 0.32mA / cm 2 Therefore, there is a problem of poor light trapping effect due to excessive transmission loss, which is referred to Figure 2 , Figure 1 The maximum current density that a solar cell corresponding to a silicon wafer can achieve is only 40.49 mA / cm 2 .

[0054] Reference Figure 3 and Figure 4 ,and Figure 1 and Figure 2 The only difference is that the entire backlight surface of the silicon wafer 100 is set as a polished surface. Figure 3 , relative to Figure 1 When light reaches the backlight surface, the incident angle is large, so it is more likely to be internally reflected, and the amount of light transmitted is relatively small. Figure 4 , Figure 3 In the solar cell corresponding to the silicon wafer, the current density lost due to the light transmitted through the back side is small, which is 0.71mA / cm 2 , but refer to Figure 3When the internally reflected light reaches the light-facing surface again, it is easier to escape from the light-facing surface due to the smaller incident angle. Therefore, the escape loss from the light-facing surface is larger. Figure 4 Compared with the light transmitted from the backlight side of the silicon wafer, more light escapes from the light-facing side of the silicon wafer. The current density lost by the light escaping from the front side is large, reaching 2.62mA / cm 2 That is, although the backlight transmission loss is small, the escape loss to the light side is large, and the overall optical loss is large. Although it can effectively reduce the transmission loss of long-wave light, it also increases the escape loss of long-wave light on the light side of the solar cell to a certain extent. Figure 4 , Figure 3 The maximum current density that a solar cell corresponding to a silicon wafer can achieve is only 41.15 mA / cm 2 .

[0055] Regarding the above Figure 1 , Figure 2 , Figure 3 and Figure 4 For technical issues shown, refer to Figures 5 to 11 The present invention provides a solar cell, which includes a silicon wafer 100. The silicon wafer 100 includes: a light-facing surface and a backlight surface. The light-facing surface refers to a surface located on the light-facing side 110 of the silicon wafer 100, and the backlight surface refers to a surface located on the backlight side 120 of the silicon wafer 100. As mentioned above, the silicon wafer also includes: a first plane perpendicular to the thickness direction of the silicon wafer 100. During normal operation of the solar cell, the side of the silicon wafer 100 that mainly receives light is the light-facing side, and the backlight side 120 is opposite to the light-facing side 110. The light-facing surface of the silicon wafer 100 has a first velvet structure, and at least a portion of the backlight surface of the silicon wafer 100 has a second velvet structure. Figures 5 to 11 In the embodiment, the thickness direction of the silicon wafer 100 is the vertical direction, the first angle α between the sidewall of the second velvet structure and the first plane is greater than the second angle θ between the sidewall of the first velvet structure and the first plane, and the difference between the first angle α and the second angle θ is 2° to 20°. More specifically, refer to Figure 5 ,and Figure 1 and Figure 2 The only difference is that the first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ is 2° to 20°. Figure 6 ,and Figure 1 and Figure 2 The only difference is that the first angle α is 58.24°, which is greater than the second angle θ of 54.74°, and the difference between the two is 3.5°. Figure 5 , when the light reaches the backlight surface, the incident angle is relatively large, so the transmission loss will be relatively reduced, refer to Figure 6 , Figure 5In the solar cell corresponding to the silicon wafer, the current density lost due to the light transmitted through the back side is small, which is 0.889mA / cm 2 At the same time, refer to Figure 5 , the incident angle of the light reflected from the backlight surface when it reaches the light-facing surface is also relatively large, so less light will escape from the front side. Figure 6 Less light escapes from the light-facing side of the silicon wafer, and the current density lost by the light escaping from the front side is also smaller, only 0.77 mA / cm 2 In summary, the design of the correlation between the first velvet structure and the second velvet structure can minimize the front escape loss and the back transmission loss of the silicon wafer 100 and the solar cell, that is, relative to Figure 2 Basically, back transmission begins to occur in the wavelength range greater than or equal to 900nm, and the back transmission accounts for a large proportion, and relative to Figure 4 , positive escape begins to occur in the band range less than or equal to 1000nm, and the positive escape accounts for a large proportion. Figure 6 In this application, the front escape and back transmission basically begin to occur in the wavelength range greater than or equal to 1000nm, and the proportion of the front escape and back transmission in the wavelength range greater than or equal to 1000nm is also small, which can effectively improve the current and efficiency of the solar cell. Figure 6 , Figure 5 The maximum current density that the solar cell corresponding to the silicon wafer can achieve is 41.92mA / cm 2 .

[0056] comprehensive Figures 1 to 6 It can be inferred that, when other conditions are the same, the present application only increases the above-mentioned first angle α so that the first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ is 2° to 20°, which not only reduces the light escaping from the front, but also reduces the light transmitted from the back, and fully increases the internal reflection, that is, increases the light absorbed by the silicon wafer, reduces the current density lost due to the light escaping from the front, and also reduces the current density lost due to the light transmitted from the back, that is, takes into account the current density lost due to the light escaping from the front and the current density lost due to the light transmitted from the back, thereby increasing the current density of the solar cell as a whole, and can effectively improve the current and efficiency of the solar cell.

[0057] It should be noted that the first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ can be selected in the range of 2° to 20°. For example, the difference between the first angle α and the second angle θ can be 2°, 3°, 5°, 8°, 10°, 11°, 11.5°, 12°, 15°, 17°, 18°, 19°, or 20°.

[0058] The first velvet structure may include a number of first-class pyramidal structures, and the second velvet structure may include a number of second-class pyramidal structures. The first-class pyramidal structure may be a quasi-pyramid structure, a quasi-cone structure, a quasi-pyramid structure with a truncated top, a quasi-cone structure with a truncated top, etc. The second-class pyramidal structure may be a quasi-pyramid structure, a quasi-cone structure, a quasi-pyramid structure with a truncated top, a quasi-cone structure with a truncated top, etc. On the same silicon wafer, whether the shapes of the first-class pyramidal structure and the second-class pyramidal structure are similar is not specifically limited. The first-class pyramidal structure and the second-class pyramidal structure may include: a cone surface, a cone top and a bottom contour line, and the cone surface is located between the cone top and the bottom contour line. For the quasi-pyramid structure and the quasi-cone structure, the cone top here may be a vertex, and for the quasi-pyramid structure with a truncated top and the quasi-cone structure with a truncated top, the cone top here may be a surface. The first-class pyramidal structure and the second-class pyramidal structure may be positive-class pyramidal structures or inverted-class pyramidal structures. Figures 5 to 11 As shown, the apex of the positive pyramidal structure is further away from the geometric center of the silicon wafer 100 than the bottom contour line. The apex of the inverted pyramidal structure is closer to the geometric center of the silicon wafer 100 than the bottom contour line. The first angle between the sidewall of the second velvet structure and the first plane here may refer to the arithmetic mean of the angles between the cone surfaces of multiple second-type pyramidal structures in the second velvet structure and the first plane, and the multiple may refer to greater than or equal to 2. For example, the first angle between the sidewall of the second velvet structure and the first plane perpendicular to the thickness direction of the silicon wafer 100 may refer to the arithmetic mean of the angles between the cone surfaces of 5 second-type pyramidal structures in the second velvet structure and the first plane. The second angle between the sidewall of the first velvet structure and the first plane here may refer to the arithmetic mean of the angles between the cone surfaces of multiple first-type pyramidal structures in the first velvet structure and the first plane, and the multiple may refer to greater than or equal to 2. For example, the second angle between the side wall of the first velvet structure and the first plane may refer to the arithmetic mean of the angles between the cone surfaces of the four first-type pyramidal structures in the first velvet structure and the first plane. Here, in the process of determining the first angle and the second angle, whether the arithmetic mean of the angles between the specifically selected second-type pyramidal structures in the second velvet structure and the first plane is equal to the arithmetic mean of the angles between the specifically selected first-type pyramidal structures in the first velvet structure and the first plane is not specifically limited, and the two may be equal or unequal.

[0059] Here, at least part of the backlight surface of the silicon wafer 100 has a second velvet structure, which can be understood as the ratio of the area of ​​the second velvet structure to the area of ​​the backlight surface of the silicon wafer 100 is greater than 0 and less than or equal to 100%. Fig.11 The area S1 of the second velvet structure refers to the area of ​​the projection of the second velvet structure on the aforementioned first plane, and the area S2 of the backlight surface of the silicon wafer 100 refers to the area of ​​the projection of the backlight surface of the silicon wafer 100 on the aforementioned first plane. Figure 5 and Figure 7 , the area of ​​the second velvet structure accounts for 100% of the area of ​​the backlight surface of the silicon wafer 100. Figures 8 to 11 , the ratio of the area of ​​the second velvet structure 1 to the area of ​​the backlight surface of the silicon wafer 100 is greater than 0 and less than 100%. In the case where the ratio of the area of ​​the second velvet structure 1 to the area of ​​the backlight surface of the silicon wafer 100 is greater than 0 and less than 100%, whether the remaining part of the backlight surface of the silicon wafer 100 is provided with a velvet structure is not specifically limited. In the case where the ratio of the area of ​​the second velvet structure 1 to the area of ​​the backlight surface of the silicon wafer 100 is greater than 0 and less than 100% and the remaining part of the backlight surface of the silicon wafer 100 is provided with a velvet structure, the size of the velvet structure provided on the remaining part of the backlight surface of the silicon wafer 100 can be equal to or different from the size of the velvet structure on the light-facing surface, and there is no specific limitation on this. For example, Figure 8 In the embodiment, the ratio of the area of ​​the second velvet structure 1 to the area of ​​the backlight surface of the silicon wafer 100 is greater than 0 and less than 100%, and the velvet structure is set on the remaining part of the backlight surface of the silicon wafer 100. The size of the velvet structure set on the remaining part of the backlight surface of the silicon wafer 100 is equal to the size of the velvet structure on the light-facing surface. In this way, the preparation processes of the velvet structure on the remaining part of the backlight surface of the silicon wafer 100 and the velvet structure on the light-facing surface can be compatible, and the process is simple.

[0060] It should be noted that the total number of the first type pyramidal structures in the first velvet structure is not specifically limited, the total number of the second type pyramidal structures in the second velvet structure is not specifically limited, and the relative size relationship between the two is not specifically limited.

[0061] Optionally, the first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ is 3.5° to 10°. Specifically, as mentioned above, the first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ is 2° to 20°, which has achieved a good balance between back transmission and front escape, so that the solar cell has a certain degree of optical gain. The first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ is 3.5° to 10°. This is on the premise of ensuring a good balance between back transmission and front escape, while taking into account the difficulty of process implementation and process time. For example, if the difference between the first angle α and the second angle θ is less than 3.5°, the process difficulty may be greater, and if the difference between the first angle α and the second angle θ is greater than 10°, it may take a long time to form the first velvet structure and the second velvet structure. In other words, when the first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ is 3.5° to 10°, three factors are considered at the same time: not only can a good balance between back transmission and front escape be ensured, but the corresponding process difficulty can also be lower and the process time is less.

[0062] It should be noted that the first angle α is greater than the second angle θ, and the difference between the first angle α and the second angle θ can be selected in the range of 3.5° to 10°. For example, the difference between the first angle α and the second angle θ can be 3.5°, 4°, 5°, 6°, 6.5°, 6.75°, 7°, 8°, 9°, 10°, 8.5°, 7.9°, or 5.4°.

[0063] Optionally, the second angle θ is 45° to 70°, and the first angle α is 50° to 80°. The second angle is compatible with existing processes, and the size of the first angle α is relatively appropriate, achieving a good balance between back transmission and front escape. Moreover, the light trapping effect of the light-facing surface is also good.

[0064] For example, the second angle θ may be 45°, 50°, 55°, 60°, 57.5°, 61°, 64°, 65°, 69°, or 70°.

[0065] For example, the first angle α may be 50°, 55°, 72°, 63°, 57.5°, 60°, 62°, 65°, 79°, 70°, or 80°.

[0066] It should be noted that, in the process of setting the first angle and the second angle, it is necessary to ensure that the first angle is greater than the second angle, and the difference between the first angle and the second angle is 2° to 20°.

[0067] The optional angle is 51.5° to 70°, which is more compatible with the existing texturing process and achieves a good balance between back transmission and front escape. Moreover, the light trapping effect on the light-facing side is also better.

[0068] For example, the first angle α may be 51.5°, 53°, 58°, 52°, 55°, 54°, 57°, 58°, 60°, 63°, or 70°.

[0069] Optionally, the area S1 of the second velvet structure accounts for a ratio greater than or equal to 10% of the area S2 of the backlight surface of the silicon wafer 100. That is, the area S1 of the second velvet structure accounts for a ratio greater than or equal to 10% of the area S2 of the backlight surface of the silicon wafer 100 and less than or equal to 100%. The area S1 of the second velvet structure accounts for a relatively large proportion, which has a better balancing effect on back transmission and front escape.

[0070] For example, the ratio of the area S1 of the second velvet structure to the area S2 of the backlight surface of the silicon wafer 100 can be 10%, 15%, 20%, 30%, 40%, 50%, 60%, 65%, 70%, 80%, 90%, or 100%.

[0071] Optional, see Fig. 9 and Fig.10 The backlight surface of the silicon wafer 100 is divided into a first conductive area, a second conductive area and an isolation area between the first conductive area and the second conductive area, and a second velvet structure 1 is provided on the isolation area. Fig. 9 and Fig.10 In the backlight surface of the silicon wafer 100, the left side of the second velvet structure 1 is the first conductive area, and the right side of the second velvet structure 1 is the second conductive area. In the solar cell, the first conductive area will be provided with a first carrier transport layer 3, and the second conductive area will be provided with a second carrier transport layer 4, that is to say, the solar cell is a back contact solar cell, and the light-facing surface of the back contact solar cell is not blocked by the grid line, and has a higher conversion efficiency. The first angle α of the second velvet structure 1 is larger (the cone top is sharper), and the first conductive area and the second conductive area are relatively flat, which is conducive to forming a better quality passivation structure, and the performance of the back contact solar cell can be further improved. For example, the first conductive area and the second conductive area are relatively flat, which is conducive to forming a better quality passivation contact structure, and the passivation contact structure is usually not required to be formed on the isolation area, and the isolation area has a second velvet structure 1. Of the first carrier transport layer 3 and the second carrier transport layer 4, one is an N-type carrier transport layer, and the other is a P-type carrier transport layer.

[0072] Optional, see Fig. 9 , the first conductive region and the second conductive region both have a polished structure, the first conductive region and the second conductive region are flatter, which is conducive to forming a passivation structure with better quality, and can further improve the performance of the back contact solar cell. For example, the first conductive region and the second conductive region are flatter, which is conducive to forming a passivation contact structure with better quality, and the passivation contact structure is usually not required to be formed on the isolation region, and the isolation region has a second velvet structure 1. In the above embodiment, the isolation region has a second velvet structure 1 to achieve a good balance between back transmission and front escape, and at the same time, it can ensure that the P region and N region of the back contact solar cell have the best passivation contact effect.

[0073] Optional, see Fig.10 One of the first conductive region and the second conductive region is a P-type conductive region, and the other is an N-type conductive region. The P-type conductive region has a polished structure, and the N-type conductive region has a velvet structure. A P-type carrier transport layer can be subsequently formed on the P-type conductive region with the polished structure, and an N-type carrier transport layer can be formed on the N-type conductive region with the velvet structure. Specifically, when the conductive region corresponding to the P-type carrier transport layer is a velvet structure, the quality of the passivation contact structure is difficult to guarantee. Therefore, the conductive region corresponding to the P-type carrier transport layer is a polished structure that is smoother, which is conducive to forming high-quality passivation contact, and can further improve the performance of the back-contact solar cell.

[0074] Optionally, the second velvet structure is only located in the isolation area, and the area S1 of the second velvet structure 1 accounts for 10% to 40% of the area S2 of the backlight surface of the silicon wafer 100. Specifically, the backlight surface of the silicon wafer 100 is divided into a first conductive area, a second conductive area, and an isolation area between the first conductive area and the second conductive area. The second velvet structure 1 is only located in the isolation area, and the area S1 of the isolation area or the second velvet structure 1 accounts for 10% to 40% of the area S2 of the backlight surface of the silicon wafer 100. The area S1 of the isolation area accounts for a relatively appropriate proportion, and the dead area formed is relatively small. That is, this embodiment can achieve a good balance between the back transmission and the front escape of the battery cell by only adjusting the surface structure of the isolation area and the area proportion of the isolation area, and has a relatively small dead area.

[0075] For example, the second velvet structure is only located in the isolation area, and the ratio of the area S1 of the second velvet structure to the area S2 of the backlight surface of the silicon wafer 100 can be 10%, 11%, 15%, 20%, 25%, 28%, 30%, 32%, 35%, 37%, or 40%.

[0076] Optional, see Figures 7 to 11 The dimensions of the first velvet structure include: height 111 and width 112, and the dimensions of the second velvet structure include: height 121 and width 122, the height direction is parallel to the thickness direction of the silicon wafer 100, and the height direction is perpendicular to the width direction. The height 111 of the first velvet structure is the distance between the highest point of the first velvet structure and the lowest point of the first velvet structure in the thickness direction of the silicon wafer 100, and the height 111 of the first velvet structure is 0.2μm to 10μm, so that the light trapping effect on the light surface is better.

[0077] For example, the height 111 of the first textured structure may be 0.2 μm, 0.5 μm, 0.9 μm, 1 μm, 1.2 μm, 1.5 μm, 3 μm, 2 μm, 5 μm, 5.1 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0078] The first velvet structure includes a plurality of first-class pyramidal structures. The height 111 of the first velvet structure may refer to the distance between the highest point of the first-class pyramidal structure and the lowest point of the first-class pyramidal structure in the thickness direction of the silicon wafer 100. For a pyramidal structure or a cone-like structure, the highest point here is the top of the cone. For a pyramidal structure or a cone-like structure with the top cut off, the highest point here may be the geometric center of the surface farthest from its bottom contour line. The arithmetic mean of the distance between the highest point of a plurality of first-class pyramidal structures in the first velvet structure and the lowest point of the first-class pyramidal structure in the thickness direction of the silicon wafer 100 may be taken. The plurality may refer to greater than or equal to 2. For example, the height 111 of the first velvet structure may be the arithmetic mean of the distance between the highest point and the lowest point of four first-class pyramidal structures in the first velvet structure in the thickness direction of the silicon wafer 100.

[0079] The first velvet structure includes a plurality of first-class pyramidal structures. The width 112 of the first velvet structure refers to the maximum size of the first-class pyramidal structure in the direction perpendicular to the thickness direction of the silicon wafer 100. It can be the arithmetic mean of the maximum sizes of a plurality of first-class pyramidal structures in the first velvet structure in the direction perpendicular to the thickness direction of the silicon wafer 100. The plurality can refer to greater than or equal to 2. For example, the width 112 of the first velvet structure can be the arithmetic mean of the maximum sizes of three first-class pyramidal structures in the first velvet structure in the direction perpendicular to the thickness direction of the silicon wafer 100. Optionally, the width 112 of the first velvet structure is 0.14 μm to 20 μm. The width 112 of the first velvet structure is more appropriate, and the light trapping effect on the light surface is better.

[0080] For example, the width 112 of the first texture structure may be 0.14 μm, 0.5 μm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 10.07 μm, 14 μm, 16 μm, 15 μm, 19 μm, or 20 μm.

[0081] Optional, see Figures 7 to 11 The height 121 of the second velvet structure is the distance between the highest point of the second velvet structure and the lowest point of the second velvet structure in the thickness direction of the silicon wafer 100. The height 121 of the second velvet structure is 0.2 μm to 10 μm, so the light trapping effect of the backlight surface is better.

[0082] For example, the height 121 of the second textured structure may be 0.2 μm, 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 3 μm, 2 μm, 5 μm, 5.1 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0083] The second velvet structure includes a plurality of second-type pyramidal structures. The height 121 of the second velvet structure may refer to the distance between the highest point of the second-type pyramidal structure and the lowest point of the second-type pyramidal structure in the thickness direction of the silicon wafer 100, and may be the arithmetic mean of the distances between the highest point of a plurality of second-type pyramidal structures in the second velvet structure and the lowest point of the second-type pyramidal structure in the thickness direction of the silicon wafer 100. The plurality may refer to greater than or equal to 2. For example, the height 121 of the second velvet structure may be the arithmetic mean of the distances between the highest point and the lowest point of 5 second-type pyramidal structures in the second velvet structure in the thickness direction of the silicon wafer 100.

[0084] The second velvet structure includes a plurality of second-type pyramidal structures. The width 122 of the second velvet structure refers to the maximum size of the second-type pyramidal structure in the direction perpendicular to the thickness direction of the silicon wafer 100. It can be the arithmetic mean of the maximum sizes of a plurality of second-type pyramidal structures in the second velvet structure in the direction perpendicular to the thickness direction of the silicon wafer 100. The plurality can refer to greater than or equal to 2. For example, the width 122 of the second velvet structure can be the arithmetic mean of the maximum sizes of three second-type pyramidal structures in the second velvet structure in the direction perpendicular to the thickness direction of the silicon wafer 100. Optionally, the width 122 of the second velvet structure is 0.07 μm to 19 μm, which is more appropriate and has a better light trapping effect on the backlight surface.

[0085] For example, the width 122 of the second texture structure may be 0.07 μm, 0.1 μm, 0.14 μm, 0.5 μm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, 12 μm, 10.07 μm, 14 μm, 16 μm, 15 μm, or 19 μm.

[0086] Here, in the process of determining the height of the first velvet structure and the height of the second velvet structure, whether the number of the second type of pyramidal structures selected from the second velvet structure is equal to the number of the first type of pyramidal structures selected from the first velvet structure is not specifically limited, and they may be equal or unequal. In the process of determining the width of the first velvet structure and the width of the second velvet structure, whether the number of the second type of pyramidal structures selected from the second velvet structure is equal to the number of the first type of pyramidal structures selected from the first velvet structure is not specifically limited, and they may be equal or unequal.

[0087] Furthermore, the height 111 of the first velvet structure is 0.8 μm to 3 μm, which not only has a good light trapping effect, but also has better compatibility with the existing velvet process. For example, the height 111 of the first velvet structure can be 0.8, 0.92 μm, 1 μm, 1.3 μm, 1.5 μm, 1.9 μm, 2 μm, 2.5 μm, 2.1 μm, 3 μm, 1.9 μm.

[0088] Furthermore, the width 112 of the first velvet structure is 0.58 μm to 6 μm, which not only has a good light trapping effect, but also has better compatibility with the existing velvet process. For example, the width 112 of the first velvet structure can be 0.58, 0.95 μm, 1 μm, 1.7 μm, 1.5 μm, 2.9 μm, 2 μm, 2.5 μm, 3.3 μm, 3 μm, 4 μm, 4.5 μm, 6 μm, 3.29 μm, 5 μm, 5.5 μm.

[0089] Furthermore, the height 121 of the second velvet structure is 0.8 μm to 3 μm, which not only has a good light trapping effect, but also has better compatibility with the existing velvet process. For example, the height 121 of the second velvet structure can be 0.8, 0.92 μm, 1 μm, 1.3 μm, 1.5 μm, 1.9 μm, 2 μm, 2.5 μm, 2.1 μm, 3 μm, 1.9 μm.

[0090] Furthermore, the width 122 of the second velvet structure is 0.28 μm to 5.6 μm, which not only has a good light trapping effect, but also has better compatibility with the existing velvet process. For example, the width 122 of the second velvet structure can be 0.28, 0.5, 0.95 μm, 1 μm, 1.7 μm, 1.5 μm, 2.9 μm, 2 μm, 2.5 μm, 3.3 μm, 3 μm, 4 μm, 4.5 μm, 5.6 μm, 3.29 μm, 5 μm, 5.5 μm.

[0091] Optional, optional, reference Figures 7 to 11 The first velvet structure includes: a plurality of first-class pyramidal structures, and the second velvet structure includes: a plurality of second-class pyramidal structures. The dimensions of the first-class pyramidal structure include: height and width, and the dimensions of the second-class pyramidal structure include: height and width. The height direction is parallel to the thickness direction of the silicon wafer 100, and the height direction is perpendicular to the width direction. The plurality of second-class pyramidal structures include: pyramidal structures of at least two sizes, and the plurality of second-class pyramidal structures may include: pyramidal structures of at least two heights, or the plurality of second-class pyramidal structures may include: pyramidal structures of at least two widths, or the plurality of second-class pyramidal structures may include: pyramidal structures of at least two widths and heights. The shapes of the second-class pyramidal structures in the second velvet structure are flexible and diverse.

[0092] In the present application, the preparation method of any of the aforementioned silicon wafers 100 is not limited. For example, the silicon wafer 100 may be firstly textured, and the light-facing surface and the backlight surface may form the same texture structure, and then a mask layer such as an oxide layer may be grown on both sides of the silicon wafer, and then the mask layer of at least a portion of the backlight surface may be removed, and the velvet structure of at least a portion of the backlight surface that is not protected by the mask layer may be further etched using an alkaline solution with an additive, thereby preparing the silicon wafer. For example, the mask layer is an oxide layer, and the mask layer of at least a portion of the backlight surface may be pickled by acid such as HF (hydrofluoric acid). For another example, different texture liquids may be used to texture the light-facing surface and the backlight surface of the silicon wafer 100 separately. For another example, different texture durations may be used to texture the light-facing surface and the backlight surface of the silicon wafer 100 separately. For another example, different texture durations and different texture liquids may be used to texture the light-facing surface and the backlight surface of the silicon wafer 100 separately. It should be noted that when the area S1 of the second velvet structure occupies less than 100% of the area of ​​the backlight surface of the silicon wafer 100, the surface morphology of the second velvet structure and the remaining part of the backlight surface of the silicon wafer 100 also needs to be prepared separately, and no specific limitation is made to this.

[0093] It should be noted that the second velvet structure on the backlight surface of the silicon wafer 100 can be a continuous whole, or can be composed of a number of spaced parts, and this is not specifically limited.

[0094] Reference Figures 9 to 11 The solar cell of the present application also includes: a first carrier transport layer 3 and a second carrier transport layer 4 located on the silicon wafer 100, and one of the first carrier transport layer 3 and the second carrier transport layer 4 is an N-type carrier transport layer and the other is a P-type carrier transport layer.

[0095] Optionally, the first carrier transport layer 3 includes: a first doped layer and a first passivation layer arranged in stacked manner, the first passivation layer is closer to the silicon wafer 100, the first passivation layer includes: a tunneling oxide layer or an intrinsic amorphous silicon layer, the second carrier transport layer 4 includes: a second doped layer and a second passivation layer arranged in stacked manner, the second passivation layer is closer to the silicon wafer 100, the first doped layer and the second doped layer have different doping types, one is N-type doping and the other is P-type doping, thereby forming a contact passivation structure, further improving the conversion efficiency of the solar cell.

[0096] Reference Fig. 9 and Fig.10Optionally, the backlight surface of the silicon wafer 100 is divided into a first conductive region, a second conductive region, and an isolation region between the first conductive region and the second conductive region, and the isolation region has a second velvet structure 1. Reference may be made to the aforementioned related records, and no further description is given to avoid repetition. The first carrier transport layer 3 is located on the first conductive region, and the second carrier transport layer 4 is located on the second conductive region, forming a back-contact solar cell. The light-facing surface of the back-contact solar cell has a higher conversion efficiency because there is no grid line blocking it.

[0097] Reference Fig.11 Optionally, the first carrier transport layer 3 is located on the backlight side of the silicon wafer 100, and the second carrier transport layer 4 is located on the light-facing side of the silicon wafer 100, forming a double-sided solar cell with flexible and diverse cell types.

[0098] It should be noted that, when the first carrier transport layer 3 is located on the backlight surface of the silicon wafer 100 and the second carrier transport layer 4 is located on the light-facing surface of the silicon wafer 100, the second velvet structure can be located at any position of the backlight surface. For example, the second velvet structure can be located in the middle or edge position of the backlight surface, where the middle position is closer to the geometric center of the backlight surface, and the edge position is farther away from the geometric center of the backlight surface than the middle position.

[0099] The solar cell has the corresponding beneficial effects of any of the aforementioned silicon wafers, and the relevant parts of the two can be referenced to each other, which will not be described here in order to avoid repetition.

[0100] The present application also provides a photovoltaic assembly, including: a plurality of any of the aforementioned solar cells, the photovoltaic assembly having the corresponding beneficial effects of any of the aforementioned solar cells, which will not be described again here to avoid repetition.

[0101] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0102] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon wafer, wherein the silicon wafer comprises a light-facing surface and a backlight surface; The light-facing surface of the silicon wafer has a first velvet structure, and at least a portion of the backlight surface of the silicon wafer has a second velvet structure; The included angle between the side wall of the second suede structure and the first plane is a first included angle, and the included angle between the side wall of the first suede structure and the first plane is a second included angle; The first plane is perpendicular to the thickness direction of the silicon wafer; The first angle is greater than the second angle, and a difference between the first angle and the second angle is 2° to 20°.

2. The solar cell according to claim 1, characterized in that The difference between the first angle and the second angle is 3.5° to 10°.

3. The solar cell according to claim 1, characterized in that The ratio of the area of ​​the second velvet structure to the area of ​​the backlight surface of the silicon wafer is greater than or equal to 10%.

4. The solar cell according to claim 1, characterized in that The backlight surface of the silicon wafer is divided into a first conductive area, a second conductive area, and an isolation area between the first conductive area and the second conductive area; The second velvet structure is located in the isolation area.

5. The solar cell according to claim 4, characterized in that: The first conductive region and the second conductive region both have a polished structure; or, One of the first conductive region and the second conductive region is a P-type conductive region, and the other is an N-type conductive region. The P-type conductive region has a polished structure, and the N-type conductive region has a velvet structure.

6. The solar cell according to any one of claims 4, characterized in that: The second velvet structure is only located in the isolation area, and the area of ​​the second velvet structure occupies 10% to 40% of the area of ​​the backlight surface of the silicon wafer.

7. The solar cell according to claim 1, characterized in that The second angle is 45° to 70°, and the first angle is 50° to 80°.

8. The solar cell according to claim 1, characterized in that The height of the first velvet structure is 0.8 μm to 3 μm; and / or, The width of the first velvet structure is 0.58 μm to 6 μm; and / or, The height of the second velvet structure is 0.8 μm to 3 μm; and / or, The second texture structure has a width of 0.28 μm to 5.6 μm.

9. The solar cell according to claim 1, characterized in that: The first velvet structure includes: a plurality of first-type pyramidal structures, and the second velvet structure includes: a plurality of second-type pyramidal structures; the dimensions of the first-type pyramidal structures and the dimensions of the second-type pyramidal structures both include: height and / or width, and the height direction is parallel to the thickness direction of the silicon wafer; The plurality of second-type pyramidal structures include pyramidal structures of at least two sizes.

10. A solar cell according to any one of claims 1 to 9, characterized in that: Also includes: A first carrier transport layer and a second carrier transport layer are located on the silicon wafer; one of the first carrier transport layer and the second carrier transport layer is an N-type carrier transport layer, and the other is a P-type carrier transport layer.

11. The solar cell according to claim 10, characterized in that The first carrier transport layer includes: a first doping layer and a first passivation layer which are stacked; the first passivation layer is closer to the silicon wafer; the first passivation layer includes: a tunneling oxide layer or an intrinsic amorphous silicon layer; The second carrier transport layer includes: a second doping layer and a second passivation layer which are stacked; the second passivation layer is closer to the silicon wafer; the second passivation layer includes: a tunneling oxide layer or an intrinsic amorphous silicon layer; the first doping layer and the second doping layer have different doping types.

12. The solar cell according to claim 10, characterized in that: The first carrier transport layer is located on the backlight side of the silicon wafer, and the second carrier transport layer is located on the light-facing side of the silicon wafer.

13. A photovoltaic module, characterized in that: include: A solar cell as claimed in any one of claims 1 to 12.

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