Micro-LED structure with improved pixel stability and manufacturing method thereof

Abstract

The present invention discloses a Micro-LED structure for improving pixel stability and a manufacturing method thereof, wherein the structure comprises: a driving substrate including an anode reflective electrode, a Micro-LED tube core located on the driving substrate, and the bottom of the Micro-LED tube core is connected to the top of the anode reflective electrode; the Micro-LED tube core comprises a hole-type conductive layer, an optimization layer, a light-emitting functional layer, an electron-type conductive layer arranged in sequence from bottom to top, a passivation layer wrapping the side wall of the anode reflective electrode and the side wall of the Micro-LED tube core, and a cathode electrode located on the Micro-LED tube core; and a microlens located on the driving substrate, on the cathode electrode, and wrapping the side wall of the passivation layer. The Micro-LED chip prepared by the method of the present invention has a stable pixelization process, good side wall quality of the pixel, and high spatial uniformity of the pixel.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a Micro-LED structure for improving pixel stability and a manufacturing method thereof. Background Art

[0002] Micro-LED made of semiconductor materials has the characteristics of self-luminescence, small chip size and high integration. Compared with LCD and OLED, its brightness, resolution, energy consumption, response speed, thermal stability and other indicators are more advantageous. At the same time, the emergence of Micro-LED has promoted the rapid development of augmented reality (AR), virtual reality (VR), head-up display (HUD), and wearable display devices. For the application of near-eye display scenes, the pixel pitch of Micro-LED chips should be less than 10μm. At the same time, based on the requirements of production capacity and cost in mass production, wafer-bonded vertical structure Micro-LED chips have excellent prospects. Small-sized, vertical-structured Micro-LEDs require large etching depth, high line width accuracy, and stable sidewall quality. Therefore, the key is to optimize the Micro-LED structure and pixel etching process.

[0003] At present, the mainstream process for realizing Micro-LED pixel mesas is top-down, that is, using dry etching (ICP etching) or wet etching. Among them, the etched film layer may include metal, dielectric and GaN-based semiconductor, the etching thickness is in the μm order, and the etching target line width is generally less than 10 μm. At the same time, most of the film layer in the etching process is transparent, which makes the regulation of the etching stage more difficult, and because the sidewalls are exposed during the etching process, etching byproducts such as metal particles will also cause sidewall leakage. In addition, for deep etching, the uniformity of etching space is difficult to control, and both the pixel line width and the mesas height are affected by it.

[0004] In summary, deep etching is an important part of the current Micro-LED structural design and pixel process preparation technologies, but there is a lack of means and methods to solve the above problems. Generally, the solution is to reduce the etching rate or etch in steps. However, for requirements such as pixel line width, sidewall morphology and full-chip uniformity, traditional etching optimization methods are obviously difficult to achieve high indicators, and pixel stability is poor. Summary of the invention

[0005] Technical purpose: In view of the defects in the prior art, the present invention discloses a Micro-LED structure and a manufacturing method for improving pixel stability. By introducing an optimization layer combined with a specifically regulated ICP etching process, the pixelation process of the Micro-LED device is more stable, and side wall contamination during the pixelation process can be avoided, effectively reducing the reverse leakage of the Micro-LED and improving the reliability of the device.

[0006] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0007] A Micro-LED structure for improving pixel stability includes: a driving substrate including an anode reflective electrode, a Micro-LED tube core located on the driving substrate, and the bottom of the Micro-LED tube core is connected to the top of the anode reflective electrode; the Micro-LED tube core includes a hole type conductive layer, an optimization layer, a light-emitting functional layer, an electron type conductive layer arranged in sequence from bottom to top, a passivation layer wrapping the side wall of the anode reflective electrode and the side wall of the Micro-LED tube core, and a cathode electrode located on the Micro-LED tube core; a microlens located on the driving substrate, on the cathode electrode, and wrapping the side wall of the passivation layer.

[0008] The present invention also provides a method for manufacturing a Micro-LED structure for improving pixel stability, comprising the following steps:

[0009] Step 1: growing a nucleation layer, a transition buffer layer, an electron type conductive layer material, a light emitting functional layer material, an optimization layer material and a hole type conductive layer material on the surface of the substrate from bottom to top in sequence to form an epitaxial full-structure thin film;

[0010] Step 2: evaporating metal on the surface of the hole-type conductive layer material and the surface of the driving substrate to form an anode reflective electrode material;

[0011] Step 3, removing the substrate in the epitaxial full-structure film to expose the nucleation layer in the epitaxial full-structure film;

[0012] Step 4: performing the first step of ICP etching, including: removing the nucleation layer and the transition buffer layer, performing pixel etching on the epitaxial full-structure film, etching the electronic type conductive layer material and the light-emitting functional layer material into several unconnected parts according to the pixel position, and forming the electronic type conductive layer and the light-emitting functional layer;

[0013] Step 5: forming a protective dielectric layer on and above the side wall of the electronic type conductive layer and the side wall of the light emitting functional layer, and forming a second step etching mask on the side wall and top of the protective dielectric layer;

[0014] Step 6: performing a second ICP etching, including: etching the non-pixel area of ​​the optimization layer, the hole type conductive layer, and the anode reflective electrode with the assistance of the second etching mask to achieve isolation between pixels; after etching, the optimization layer, the hole type conductive layer, and the anode reflective electrode are formed;

[0015] Step 7: forming a passivation layer on the sidewalls of the electronic type conductive layer, the sidewalls of the light emitting functional layer, the sidewalls of the optimization layer, the sidewalls of the hole type conductive layer, and the sidewalls of the anode reflective electrode, and forming a cathode electrode on the passivation layer and the electronic type conductive layer;

[0016] Step eight: forming a microlens on the driving substrate, the side wall of the passivation layer, and the cathode electrode.

[0017] Beneficial effects:

[0018] (1) The method of the present invention can be implemented by traditional epitaxial and etching processes and equipment. The electron blocking layer in the traditional epitaxial structure is designed as a process optimization layer. No new gas source needs to be introduced in the epitaxial process. By combining etching gases and finely controlling etching parameters, basic ICP etching equipment can achieve matching between the process and the optimized layer. Compared with the deep etching process in traditional Micro-LED preparation, this method does not add additional process steps, has a simple process, and is easy to apply in the actual production process.

[0019] (2) The design and introduction of the optimization layer that matches the ICP etching in the present invention has the following advantages: 1) It can improve the uniformity of the entire chip during the pixelation etching process. Due to the introduction of the self-stop layer, the etching non-uniformity between the center and the edge will be eliminated, thereby avoiding the subsequent non-uniformity of the light emission of the Micro-LED device; 2) The optimized ICP etching process makes the first step of the etching process more stable, reduces side wall contamination, and avoids the possibility of side wall leakage caused by processes such as etching electrode metal, thereby improving the stability and reliability of the Micro-LED device; 3) The introduction of the optimization layer can also block electrons, avoid electron leakage, and improve quantum efficiency.

[0020] (3) By introducing an optimized layer combined with a specifically regulated ICP etching process, the pixelation process of the Micro-LED device preparation is more stable, side wall contamination during the pixelation process can be avoided, the reverse leakage of the Micro-LED is effectively reduced, and the reliability of the device is improved. At the same time, the uniformity of the entire chip can also be effectively improved. This method has the beneficial characteristics of simple process implementation, significant effect improvement, and easy mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of Micro-LED structure to improve pixel stability;

[0022] Figure 2 Schematic diagram of epitaxial full-structure film with the introduction of optimized layers;

[0023] Figure 3 It is a schematic diagram of the structure that will undergo etching process after bonding;

[0024] Figure 4 Schematic diagram of removing the epitaxial full-structure thin film substrate;

[0025] Figure 5 Schematic diagram of etching and removing the nucleation layer and transition buffer layer;

[0026] Figure 6 This is a schematic diagram of the device pixel structure after the first step of etching;

[0027] Figure 7 It is a schematic diagram of the structure after the pixel protection medium is grown;

[0028] Figure 8 It is a schematic diagram of the structure after the second step ICP etching process;

[0029] Fig. 9 It is a schematic diagram of the structure after the passivation layer and the cathode electrode are prepared;

[0030] Fig.10 Schematic diagram of the Micro-LED structure formed after microlens preparation.

[0031] Among them, 101 is a substrate, 102 is a nucleation layer, 103 is a transition buffer layer, 104 is an electronic type conductive layer material, 104' is an electronic type conductive layer, 105 is a light-emitting functional layer material, 105' is a light-emitting functional layer, 106 is an optimization layer material, 106' is an optimization layer, 107 is a hole type conductive layer material, and 107' is a hole type conductive layer; 201 is a driving substrate, 202 is an anode reflective electrode material, and 202' is an anode reflective electrode; 301 is a protective dielectric layer; 302 is a second step etching mask, 401 is a passivation layer, 402 is a cathode electrode, and 403 is a microlens. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] An embodiment of the present invention is further explained and illustrated below in conjunction with the accompanying drawings.

[0034] As attached Figure 1 As shown, a Micro-LED structure for improving pixel stability in this embodiment includes:

[0035] A driving substrate 201 including an anode reflective electrode 202', wherein the anode reflective electrode 202' is located on the top of the driving substrate 201, and the anode reflective electrode 202' is arranged at intervals on the top of the driving substrate 201; the anode reflective electrode 202' realizes an anode function;

[0036] The Micro-LED tube core is located on the driving substrate 201, and the bottom of the Micro-LED tube core is connected to the top of the anode reflective electrode 202'; the Micro-LED tube core includes a hole type conductive layer 107', an optimization layer 106', a light-emitting functional layer 105', and an electron type conductive layer 104' arranged in sequence from bottom to top, and the hole type conductive layer 107' is connected to the top of the anode reflective electrode 202'; the Micro-LED tube core includes a number of pixels, and the pixels are isolated from each other; the number of anode reflective electrodes 202' is the same as the number of pixels in the Micro-LED tube core. In this embodiment, the driving substrate 201 is a high-reflective metal film layer on a Si-based CMOS driving circuit using electron beam evaporation.

[0037] A passivation layer 401 wrapping the side walls of the anode reflective electrode 202' and the side walls of the Micro-LED tube core, a cathode electrode 402 located on the Micro-LED tube core; a microlens 403 located on the driving substrate 201, on the cathode electrode 402, and wrapping the side walls of the passivation layer 401, the microlens 403 is a continuous structure for improving the pixel light output efficiency.

[0038] The driving substrate 201 is connected to the Micro-LED tube core 10 through the anode reflective electrode 202', and the anode reflective electrode 202' is in direct contact with the hole type conductive layer 107' and forms a good ohmic contact. The Micro-LED tube core is composed of the hole type conductive layer 107', the optimization layer 106', the light-emitting functional layer 105' and the electronic type conductive layer 104' from bottom to top. The passivation layer 401 wraps the side walls of the above layers to achieve protection and passivation. The cathode electrode 402 is in direct contact with the electronic type conductive layer 104'. The microlens 403 is located at the top of the Micro-LED structure, which plays the role of filling, protecting and improving the light extraction efficiency.

[0039] A method for manufacturing a Micro-LED structure with improved pixel stability in this embodiment is used to manufacture the Micro-LED structure with improved pixel stability described above, comprising the following steps:

[0040] Step 1: Figure 2As shown, a nucleation layer 102, a transition buffer layer 103, an electronic type conductive layer material 104, a light emitting functional layer material 105, an optimization layer material 106 and a hole type conductive layer material 107 are sequentially grown from bottom to top on the surface of a substrate 101 to form an epitaxial full-structure film; wherein the epitaxial full-structure film is a nitride semiconductor, and the nucleation layer 102 and the transition buffer layer 103 are respectively a combination of one or more of AlN, low-temperature GaN, (Al, Ga, N) ternary alloy, and unintentionally doped GaN, and the total thickness of the nucleation layer and the transition buffer layer is ≤1 μm; the electronic type conductive layer material 104 is of the first conductive type, and the first conductive type is electronic type Si-doped GaN, and the doping concentration is ≥1×10 18 cm -3 , thickness ≥ 800 nm; the hole type conductive layer material 107 is of the second conductive type, the second conductive type is hole conductive Mg-doped GaN, and the doping concentration is ≥ 1×10 19 cm -3 , thickness ≥ 200 nm; the core of the light-emitting functional layer material 105 is an InGaN-based quantum well, and can also include one or more combinations of InGaN-based superlattice and low-temperature GaN buffer layer. The thickness of the light-emitting functional layer material 105 is ≤ 300 nm; the optimization layer material 106 is an AlGaN ternary alloy or an AlGaN-based superlattice, the Al component in the optimization layer material 106 accounts for 10%~30%, and the thickness range of the optimization layer is 15 nm~50 nm.

[0041] The material of the substrate 101 is silicon (Si), silicon carbide (SiC), GaN or sapphire. In this embodiment, the substrate 101 is made of <111> Direction Si substrate;

[0042] In this embodiment, the nucleation layer 102 is AlN, and the transition buffer layer 103 is a ternary alloy of (Al, Ga, N) with a gradient of 20% to 80% and unintentionally doped GaN;

[0043] In this embodiment, the electronic type conductive layer material 104 is Si-doped GaN, and the Si doping concentration is 1×10 18 cm -3 ;

[0044] In this embodiment, the light-emitting functional layer material 105 includes a combination of three structures: low-temperature GaN, InGaN / GaN superlattice, and InGaN / GaN quantum well. The In component of the light-emitting InGaN / GaN quantum well is 20%, and the total thickness of the light-emitting functional layer material 105 is 100 nm; the optimization layer material 106 is composed of a ternary alloy (Al, Ga, N), the Al component is 20%, and the thickness is 20 nm.

[0045] In this embodiment, the hole-type conductive layer material 107 is Mg-doped GaN, and the Mg doping concentration is 1e19 cm -3 .

[0046] Step 2: Figure 3 As shown, metal is evaporated on the surface of the hole type conductive layer material 107 and the surface of the driving substrate 201 to form an anode reflective electrode material 202, and bonded in a high temperature and high pressure environment, and the epitaxial full-structure film and the driving substrate 201 and the anode reflective electrode material 202 form a bonding sheet, wherein the anode reflective electrode material 202 is located between the hole type conductive layer material 107 and the driving substrate 201;

[0047] Specifically, the epitaxial wafer corresponding to the epitaxial full-structure thin film is annealed at a temperature of 650-850° C. for 5-30 minutes; then, metal evaporation is performed on the epitaxial wafer and the substrate corresponding to the driving substrate 201, and the metal is a combination of one or more of Ni, Au, Sn, Pt, Ag, Cr, Rh, indium tin oxide (ITO) or Ti to form an anode reflective electrode material 202, and the total thickness of the anode reflective electrode material 202 is in the range of 300 nm to 800 nm;

[0048] For example, in this embodiment, annealing is performed on the epitaxial wafer, the annealing temperature is 850° C., and the annealing time is 5 minutes.

[0049] Step 3: Figure 4 As shown, the epitaxial full-structure thin film substrate 101 in the bonding wafer is removed, so that the nucleation layer 102 in the epitaxial full-structure thin film is exposed;

[0050] Step 4: Perform the first ICP etching, including: removing the nucleation layer 102 and the transition buffer layer 103, performing pixel etching on the epitaxial full-structure film, etching the electronic type conductive layer material 104 and the light-emitting functional layer material 105 into several unconnected parts according to the pixel position, and forming the electronic type conductive layer 104' and the light-emitting functional layer 105'; Figure 5 As shown, the first step of the ICP etching process includes a rapid etching and an etching self-stopping stage, specifically: the nucleation layer 102 and the transition buffer layer 103 are etched away by etching gas, and the etching rate is ≥2nm / s, which is in the rapid etching stage; further as shown Figure 6As shown, the electronic type conductive layer material 104 and the light emitting functional layer material 105 in the epitaxial wafer are etched pixel-wise using a mask to form an electronic type conductive layer 104' and a light emitting functional layer 105'. The etching of the optimization layer material is a self-stopping stage. By introducing the optimization layer material 106 and finely controlling the etching parameters, the electronic type conductive layer material 104 and the light emitting functional layer material 105 are first quickly etched and then the optimization layer material 106 is etched and self-stopped by conventional etching equipment. The optimization layer plays an electron blocking role and an etching self-stopping role. The self-stopping effect is due to the reaction between the etching gas combination and the dangling bonds on the surface of the epitaxial layer. In the rapid etching stage, the etching rates of the nucleation layer, transition buffer layer, electron type conductive layer material 104 and light emitting functional layer material 105 are ≥2nm / s, the etching rate of the optimization layer material in the etching self-stop stage is ≤0.3nm / s, and the etching selectivity ratio between the optimization layer material 106 and the hole type conductive layer material 107 or the electron type conductive layer material 104 in the etching self-stop stage is ≥4.

[0051] In this embodiment, the pixelation etching process of step 4 requires that multiple working gases be introduced into the ICP chamber at the same time and the atmosphere pressure and power of the ICP etching equipment be regulated during the etching process to perform fine etching on the epitaxial layer;

[0052] Etching parameters include the following:

[0053] The ICP chamber gas includes ambient gas and etching gas, wherein the ambient gas is Ar or N 2 ; Etching gases suitable for the optimized layer include SF 6 , Cl 2 , BCl 3 Combination or Cl 2 With O 2 The present embodiment selects SF 6 , Cl 2 , BCl 3 combination.

[0054] In this embodiment, the gas atmosphere pressure of the ICP etching equipment is 15 mTorr~30 mTorr;

[0055] In this embodiment, the power of the ICP etching equipment is 200W~500W;

[0056] In this embodiment, the RF power of the ICP etching equipment is 30-80W.

[0057] Step 5: forming a protective dielectric layer 301 on and above the sidewall of the electronic type conductive layer 104' and the sidewall of the light emitting functional layer 105', and forming a second step etching mask 302 on the sidewall and top of the protective dielectric layer 301; Figure 7As shown, sidewall treatment is performed, including growing a protective dielectric layer 301 for protecting pixels on the surface of the device formed in step 4, performing photolithography to realize the second step etching mask, and the line width of the second step etching mask 302 area is greater than the pixelated etching line width in the first step ICP etching. The sidewall treatment includes wet treatment, and the treatment solution includes KOH, tetramethylammonium hydroxide (TMAH), etc.

[0058] In the second step, the etching mask 302 is a superposition of the photoresist mask and the protective dielectric layer 301. The protective dielectric layer is a combination of one or more of silicon nitride, silicon oxide, aluminum oxide, and silicon oxynitride, with a thickness ranging from 200 nm to 500 nm. In this embodiment, the protective dielectric layer is silicon oxide, which is grown by PECVD at a growth temperature of 250°C and a thickness of 300 nm.

[0059] Step 6: Perform the second ICP etching, including: etching the non-pixel area of ​​the optimization layer material 106, the hole type conductive layer material 107, and the anode reflective electrode material 202 with the assistance of the second etching mask 302 to achieve isolation between pixels, and forming the optimization layer 106', the hole type conductive layer 107', and the anode reflective electrode 202' after etching; wherein, the electron type conductive layer 104', the light emitting functional layer 105', the optimization layer 106', and the hole type conductive layer 107' after etching constitute the Micro-LED tube core; Figure 8 As shown, the second step ICP etching process realizes the isolation between pixels, including etching of the optimization layer material 106, the hole type conductive layer material 107 and etching of the non-pixel area of ​​the anode reflective electrode material 202. After the second step ICP etching is completed, the second step etching mask 302 is also removed. In step six, the etching of the anode reflective electrode material 202 can be over-etched appropriately;

[0060] Specifically, the width of the grooves etched between adjacent pixels needs to be less than half the line width of the pixel core in the Micro-LED core.

[0061] Step 7: forming a passivation layer 401 on the sidewalls of the electron type conductive layer 104', the sidewalls of the light emitting functional layer 105', the sidewalls of the optimization layer 106', the sidewalls of the hole type conductive layer 107', and the sidewalls of the anode reflective electrode 202', and forming a cathode electrode 402 on the passivation layer 401 and the electron type conductive layer 104'; Fig. 9 As shown, a passivation layer 401 and a cathode electrode 402 are prepared on the device structure formed in step 6. In this embodiment, the passivation layer 401 is SiO 2 , with a thickness of 300 nm; the cathode electrode 402 is ITO (indium tin oxide) with a thickness of 200 nm.

[0062] Specifically, the preparation of the cathode electrode requires first removing the passivation layer 401 and the upper surface of the inner protective dielectric layer 301, and then forming a transparent cathode electrode. The material of the cathode electrode can be ITO.

[0063] Step 8: forming a micro lens 403 on the driving substrate 201, the side wall of the passivation layer 401, and the cathode electrode 402, wherein the top of the micro lens 403 is hemispherical on the orthographic projection of the pixel in the Micro-LED die; Fig.10 As shown, a micro lens 403 is prepared above the pixel array, and the micro lens 403 is a dielectric micro lens structure, and finally forms a Micro-LED structure with high stability pixels. The micro lens 403 covers all non-pixel areas on the driving substrate 201.

[0064] Specifically, the material of the microlens 403 is a combination of one or more of silicon nitride, silicon oxide, aluminum oxide, and silicon oxynitride. The microlens combination under the combination of multiple materials satisfies: the refractive index of the microlens material decreases layer by layer from the inside to the outside, wherein the inside from the inside to the outside refers to the side close to the driving substrate 201; the material of the microlens 403 can be grown by PECVD (plasma enhanced chemical vapor deposition), and a hemispherical dielectric microlens is realized by ultraviolet lithography and ICP etching.

[0065] The "first" and "second" in the names such as "first" and "second" (if any) mentioned in the embodiments of the present application are only used as name identifiers and do not represent the first or second in order.

[0066] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a Micro-LED structure for improving pixel stability, characterized in that: The following steps are involved: Step 1: growing a nucleation layer, a transition buffer layer, an electron type conductive layer material, a light emitting functional layer material, an optimization layer material and a hole type conductive layer material on the surface of the substrate from bottom to top in sequence to form an epitaxial full-structure thin film; Step 2: evaporating metal on the surface of the hole-type conductive layer material and the surface of the driving substrate to form an anode reflective electrode material; Step 3, removing the substrate in the epitaxial full-structure film to expose the nucleation layer in the epitaxial full-structure film; Step 4: performing the first step of ICP etching, including: removing the nucleation layer and the transition buffer layer, performing pixel etching on the epitaxial full-structure film, etching the electronic type conductive layer material and the light-emitting functional layer material into several unconnected parts according to the pixel position, and forming the electronic type conductive layer and the light-emitting functional layer; Step 5: forming a protective dielectric layer on and above the side wall of the electronic type conductive layer and the side wall of the light emitting functional layer, and forming a second step etching mask on the side wall and top of the protective dielectric layer; Step 6: performing a second ICP etching, including: etching the non-pixel area of ​​the optimization layer, the hole type conductive layer, and the anode reflective electrode with the assistance of the second etching mask to achieve isolation between pixels; after etching, the optimization layer, the hole type conductive layer, and the anode reflective electrode are formed; Step 7: forming a passivation layer on the sidewalls of the electronic type conductive layer, the sidewalls of the light emitting functional layer, the sidewalls of the optimization layer, the sidewalls of the hole type conductive layer, and the sidewalls of the anode reflective electrode, and forming a cathode electrode on the passivation layer and the electronic type conductive layer; Step 8: forming a microlens on the driving substrate, the side wall of the passivation layer, and the cathode electrode; In the first step of ICP etching, the first step of etching self-stop is achieved through the introduction of the optimization layer and the control of etching parameters through conventional etching equipment. The ICP chamber gas includes etching gas and ambient gas. The etching gas and the optimization layer are adapted to achieve the self-stop effect. The combination of SF6, Cl2, BCl3, or the combination of Cl2 and O2, and the ambient gas is Ar or N2; The first step of ICP etching is divided into rapid etching and etching self-stopping stages. In the rapid etching stage, the etching rates of the nucleation layer, transition buffer layer, electronic type conductive layer material and light-emitting functional layer material are ≥2nm / s; in the etching self-stopping stage, the etching rate of the optimization layer material is ≤0.3nm / s, and the etching selectivity ratio between the optimization layer material and the hole type conductive layer material or the electron type conductive layer material is ≥4; the optimization layer plays the role of electron blocking and etching self-stopping.

2. The method for manufacturing a Micro-LED structure for improving pixel stability according to claim 1, characterized in that: The nucleation layer and the transition buffer layer respectively include a combination of one or more of AlN, low-temperature GaN, (Al, Ga, N) ternary alloy, and unintentionally doped GaN, and the total thickness of the nucleation layer and the transition buffer layer is ≤1 μm.

3. The method for manufacturing a Micro-LED structure for improving pixel stability according to claim 1, characterized in that: The line width of the etching mask area in the second step is larger than the pixelated etching line width in the first ICP etching, and the width of the groove formed by etching between adjacent pixels in step six is ​​less than half of the line width of the pixel core in the Micro-LED core.

4. A Micro-LED structure with improved pixel stability, manufactured by the method for manufacturing a Micro-LED structure with improved pixel stability as claimed in any one of claims 1 to 3, characterized in that: include: A driving substrate including an anode reflective electrode, a Micro-LED tube core located on the driving substrate, wherein the bottom of the Micro-LED tube core is connected to the top of the anode reflective electrode; the Micro-LED tube core includes a hole-type conductive layer, an optimization layer, a light-emitting functional layer, an electron-type conductive layer arranged in sequence from bottom to top, a passivation layer wrapping the side wall of the anode reflective electrode and the side wall of the Micro-LED tube core, and a cathode electrode located on the Micro-LED tube core; A microlens is located on the driving substrate, on the cathode electrode, and wraps around the side wall of the passivation layer.

5. The Micro-LED structure for improving pixel stability according to claim 4, characterized in that: The electronic type conductive layer is Si-doped GaN, with a doping concentration of ≥1×10 18 cm -3 , thickness ≥ 800 nm, hole type conductive layer is Mg doped GaN, doping concentration ≥ 1×10 19 cm -3 , thickness ≥200 nm.

6. The Micro-LED structure for improving pixel stability according to claim 4, characterized in that: The light-emitting functional layer includes an InGaN-based quantum well, and also includes one or more combinations of an InGaN-based superlattice and a low-temperature GaN buffer layer. The thickness of the light-emitting functional layer is ≤300nm.

7. The Micro-LED structure for improving pixel stability according to claim 4, characterized in that: The optimized layer is an AlGaN ternary alloy or an AlGaN-based superlattice, the thickness of the optimized layer ranges from 15 nm to 50 nm, and the Al component is 10% to 30%.

8. The Micro-LED structure for improving pixel stability according to claim 4, characterized in that: The microlens is hemispherical, and the material is a combination of one or more of silicon nitride, silicon oxide, aluminum oxide, and silicon oxynitride. The combination of microlenses under the combination of multiple materials satisfies: the refractive index of the material decreases layer by layer from the inside to the outside.

Images