Non-polar surface Micro-LED with independent mesa structure and preparation method of non-polar surface Micro-LED

Abstract

The invention discloses a non-polar surface micro light-emitting diode (Micro-LED) with an independent mesa structure and a preparation method of the non-polar surface micro light-emitting diode (Micro-LED), full relaxation of an epitaxial structure is realized based on selective area epitaxy and lateral epitaxy, and generation of defects in an epitaxial layer can be effectively inhibited. Meanwhile, mutually independent Micro-LED functional layers such as quantum wells are grown on mutually independent mesas, so that the Micro-LED can be prepared without etching damage of the quantum wells, the etching damage of the quantum wells caused by reducing the size of the LED through process etching in a traditional scheme and non-radiative recombination additionally caused by the etching damage of the quantum wells are eliminated, and the efficiency of the Micro-LED is effectively improved. The invention provides a new structure and a new method for preparing the Micro-LED, and is beneficial to promoting commercial application of the Micro-LED.

Description

Technical Field

[0001] The present invention relates to a non-polar surface Micro-LED with an independent table structure and a preparation method thereof, and belongs to the fields of semiconductor epitaxial growth, Micro-LED, etc. Background Art

[0002] As an emerging display technology, Micro-LED technology is gaining more and more attention due to its significant advantages such as high brightness, high contrast, wide color gamut and low power consumption. However, to successfully commercialize Micro-LED technology, it is necessary to solve problems such as defects in the epitaxial layer, quantum well etching damage and the resulting non-radiative recombination.

[0003] On the one hand, the core structure of Micro-LED is a semiconductor material formed by epitaxial layers. Epitaxial layers are usually grown on substrates by metal organic chemical vapor deposition (MOCVD) technology, a process often accompanied by the generation of various defects. Defects in the epitaxial layer include lattice dislocations, holes, and dislocations, which can have a negative impact on the performance of Micro-LEDs. For example, defects may lead to reduced luminous efficiency, uneven brightness, and shortened lifespan. These problems are particularly serious in mass production because defects may not only affect the performance of a single Micro-LED, but may also affect the quality of the entire display panel. On the other hand, quantum wells are key structures for semiconductor excitation light and have decisive luminescent properties. However, during the etching process, etching damage may be introduced, which can affect the photoelectric properties of quantum wells. Etching damage may not only lead to reduced luminous efficiency of quantum wells, but also induce non-radiative recombination processes, further affecting the photoelectric conversion efficiency. This non-radiative recombination refers to the recombination of electrons and holes without emitting light, thereby converting into heat instead of photons. This phenomenon significantly reduces the brightness and power consumption efficiency of Micro-LEDs. Summary of the invention

[0004] The present invention discloses a non-polar surface Micro-LED with an independent table structure and a preparation method thereof. Based on selective epitaxy and lateral epitaxy, the full relaxation of the epitaxial structure is achieved, which can effectively suppress the generation of defects in the epitaxial layer. At the same time, Micro-LED functional layers such as independent quantum wells are grown on independent table surfaces, so that Micro-LEDs can be prepared without quantum well etching damage, eliminating quantum well etching damage and additional non-radiative recombination caused by reducing the size of LEDs through process etching in traditional solutions, and effectively improving the efficiency of Micro-LEDs. In addition, the present invention sets a strain control layer, and by adjusting the molar composition, Al x1 Ga 1-x1 N and In x Ga 1-xThe lattice mismatch value of N in the c direction is comparable to that of GaN, thereby better releasing stress to obtain high-quality quantum wells and improving the overall Micro-LED light efficiency; an electron blocking layer or a high P-doped hole injection layer with a wider bandgap is set to limit the carriers in the active area, i.e., the multiple quantum wells, so that the overlap of the hole and electron wave functions in the multiple quantum wells increases, achieving higher radiation recombination efficiency, and further solving the problem of the decrease in internal quantum efficiency as the injection current density increases. The present invention provides a new structure and method for preparing Micro-LEDs, which is conducive to promoting the commercial application of Micro-LEDs.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] On the one hand, the present invention provides a non-polar surface Micro-LED with an independent mesa structure, characterized in that: it comprises an N-type GaN layer 101 with a non-polar surface facing upward, a mask layer 102 containing a microhole array, an N-type In with an In component x of 0≤x≤0.35 connected to the N-type GaN layer 101 through the microholes of the mask layer 102, and a x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y of 0≤y≤0.15 successively grown on the mesa structure 103 y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-y The N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is a P electrode 111 on the isolation layer 110; wherein the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-mesa structures 103 are parallel, and the strain regulation layer 104 and the carrier regulation layer 106 may be selectively provided or not provided.

[0007] Preferably, the mask layer 102 containing the micropore array is a micropore array etched from top to bottom by process technology after a 5 to 50 nm thick SiO2, SiN or hBN dielectric film is plated on the non-polar surface N-type GaN layer 101, and the underlying non-polar surface N-type GaN layer 101 is exposed in the micropores; wherein the micropore array is arranged in a form of micropore center close packing, and the center distance between any micropore and the adjacent 6 micropores is equal, and can be adjusted according to actual needs.

[0008] Preferably, the non-polar surface N-type GaN layer 101 and the N-type In x Ga 1-x The top surface of the N-type mesa structure 103 is also a (11-20) plane. In this case, the mesa structure 103 is a triangular mesa structure, which includes, in addition to the top surface, two left and right inclined planes of the {1-101} crystal plane family and a side surface of the (000-1) crystal plane perpendicular to the top surface. x Ga 1-x When the top surface of the N-table structure 103 is the (11-20) plane, the {1-101} crystal plane family is a lower potential energy surface, which can form a regular triangular island, and the layer structure above can grow regularly and controllably. At this time, the diameter of the micropores of the mask layer 102 is between 0.2 and 2 μm. When the diameter of the micropores of the mask layer 102 is not greater than 1.5 μm, the diameter of the circumscribed circle of the table structure 103 in the plane is between 5 and 20 μm and can be adjusted as needed, because when the micropores are small, regular islands are easily formed, and the size of the island can be controlled as needed; when the diameter of the micropores of the mask layer 102 is greater than 1.5 μm, the diameter of the circumscribed circle of the table structure 103 in the plane is 3 to 4 times the diameter of the micropores, but the maximum does not exceed 15 μm, because when the micropores are large, the islands are easily irregular, so the size of the islands is limited.

[0009] Preferably, the non-polar surface N-type GaN layer 101 and the N-type In x Ga 1-x The top surface of the N-type mesa structure 103 can also be a (1-100) plane at the same time. In this case, the mesa structure 103 is a trapezoidal mesa structure, which, in addition to the top surface, also includes two left and right inclined planes of the {11-20} crystal plane family and two front and rear side surfaces perpendicular to the top surface whose crystal planes are (0001) and (000-1) respectively; an N-type In x Ga 1-xWhen the upward top surface of the N mesa structure 103 is the (1 - 100) plane, the {11 - 20} crystal plane family is the lower potential energy plane, and a regular and flat crystal plane can be formed, and the upper layer structure can grow regularly and controllably. At this time, the size of the micropores in the mask layer 102 in the left - right direction is between 0.3 and 0.6 times the left - right direction size of the mesa structure 103 and the maximum is 5 μm, and the size in the up - down direction is the same as the up - down direction size of the mesa structure 103, which is adjusted according to the device size. The mesa - mounting structure fundamentally avoids the damage to the multiple quantum wells during etching, improves the radiative recombination efficiency of the Micro - LED, and the mesa structure is beneficial to releasing the stress of the bottom layer, improving the crystal quality of the entire LED structure, thereby weakening the influence of defects and polarization on carriers and improving the light - emitting efficiency of the LED.

[0010] Preferably, the N - type In x Ga 1-x When the molar fraction x of the N mesa structure 103 is x ≤ 0.05, the strain - regulating layer 104 is a 1 - 3 - period GaN / Al x1 Ga 1-x1 N / GaN composite layer, where the thickness of Al x1 Ga 1-x1 N is less than 3 nm, and x1 < 0.15. When x is set to be small, the stress of In x Ga 1-x N is small, and only a lower - component AlGaN needs to be introduced to compensate for a certain in - plane stress in the c - direction; when the molar fraction 0.05 < x < 0.15 of the N - type In x Ga 1-x N mesa structure 103, the strain - regulating layer 104 is a 1 - 3 - period GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-x N composite layer, where the molar fraction of In x Ga 1-x N is the molar fraction of the N - type In x Ga 1-x N mesa structure 103, the thickness of Al x1 Ga 1-x1 N is less than 2 nm; where the lattice mismatch value between In x Ga 1-x N and GaN in the c - direction is △1 = 0.09797×x, and the lattice mismatch value between GaN and Al x1 Ga 1-x1 N in the c - direction is △2 = - 0.03915×x1;; By adjusting the molar fractions x and x1, Al x1 Ga 1-x1 N and In x Ga1-x The lattice mismatch value of N in the c direction is equivalent to that of GaN (that is, it satisfies △1=-△2), that is, it satisfies x1=2.5×x±0.05, realizing stress compensation between layers, and then obtaining high-quality quantum wells, thereby improving the overall Micro-LED lighting efficiency.

[0011] Preferably, when the emission wavelengths of the quantum well layer 105 are red, green, and blue, respectively, the number of quantum well pairs does not exceed 2, 4, and 5 pairs, respectively; the layer structure of the quantum well is In x2 Ga 1-x2 N / GaN / Al x3 Ga 1-x3 N / GaN, where In x2 Ga 1-x2 The lattice mismatch between N and GaN in the c direction is △3 = 0.09797 × x2; Al x3 Ga 1-x3 The lattice mismatch value between N and GaN in the c direction is △4 = -0.03915 × x3; by adjusting the molar composition x2 and x3, In x2 Ga 1-x2 N and Al x3 Ga 1-x3 The lattice mismatch value of N in the c direction is equivalent to that of GaN (i.e., satisfying △1=-△2), that is, satisfying x3=2.5×x2±0.05, while controlling In x2 Ga 1-x2 The thickness of N is 2 to 4 nm, and the two layers of GaN and Al x3 Ga 1-x3 The total thickness of N does not exceed 6nm, which can better release stress, improve the radiation recombination efficiency of the quantum well, and improve the light efficiency.

[0012] Preferably, the carrier regulation layer 106 is one of an electron blocking layer and a hole injection layer; wherein the electron blocking layer is an Al2O3 layer having 2 to 8 cycles and a single cycle thickness of less than 8 nm. y1 Ga (1-y1) N / GaN superlattice, where the molar composition y1 is between 0.1 and 0.6, and Al y1 Ga (1-y1) The hole injection layer is P-doped with an overall thickness of less than 30nm Al y2 Ga (1-y2) N / In y3 Ga (1-y3) N / GaN superlattice, y2=0.5×y3, Mg doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3The hole concentration is not higher than 1×10 18 cm -3 By setting an electron blocking layer with a wider bandgap or a highly P-doped hole injection layer, the carriers in the active region, i.e., the multiple quantum wells, are restricted, thereby increasing the overlap of the hole and electron wave functions in the multiple quantum wells and achieving a higher radiation recombination efficiency.

[0013] Preferably, P-type In y Ga 1-y The thickness of the N layer 107 is between 50 and 200 nm, and the molar composition y is between 0 and 0.15. When y=0, it is GaN. The Mg element doping concentration is 2×10 19 cm -3 ~5×10 19 cm -3 The hole concentration is not less than 1×10 18 cm -3 ; Among them, P type In y Ga 1-y In the 5-30 nm thickness region on the upper surface of the N layer 107, the doping concentration of the Mg element is not less than 1×10 20 cm -3 , the hole concentration is not less than 5×10 18 cm -3 .

[0014] On the other hand, the present invention provides a method for preparing a non-polar surface Micro-LED with an independent mesa structure, wherein the structural features of the Micro-LED are arranged in sequence from bottom to top: an N-type GaN layer 101 with a non-polar surface on the upward crystal plane, a mask layer 102 containing a micropore array, an N-type In with an In component x of 0≤x≤0.35 connected to the N-type GaN layer 101 through the micropores of the mask layer 102, x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y of 0≤y≤0.15 successively grown on the mesa structure 103 y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-yThe N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is a P electrode 111 on the isolation layer 110; wherein the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-table structure 103 are parallel, and the strain control layer 104 and the carrier control layer 106 can be selectively provided or not provided. When the top surface of the non-polar surface N-type GaN layer 101 is the (11-20) plane, the table structure 103 is a triangular table structure, and the diameter of the micropores of the mask layer 102 is between 0.2 and 2 μm. The preparation method of this Micro-LED includes the following steps: a) preparing a non-polar (11-20) plane N-type GaN template as the non-polar plane N-type GaN layer 101, preparing a dielectric film (made of silicon oxide, silicon nitride or boron nitride) on it, and then using micromachining technology to machine microholes in the dielectric layer (exposing the N-type GaN layer 101 below), which is the mask layer 102; b) Using a MOCVD (metal organic chemical vapor deposition) system and utilizing the micropores of the mask layer 102 to selectively epitaxially grow an N-type In x Ga 1-x The growth conditions of the N triangle island are as follows: the growth temperature is 1080-1100°C, the V / III ratio (the molar flow ratio of the N source to the Ga source) is 1800-2500, the growth pressure is 40-120 Torr, and the total flow rate v (in sccm) of the carrier gas introduced into the reaction chamber satisfies 100PA<760v<300PA (according to the ideal gas law v act =v std ×P std / P act Get, where v act = gas flow rate × A, v std is the total flow rate of carrier gas into the reaction chamber v, P std is the standard pressure, usually 760Torr, P act is the growth pressure P), where P is the growth pressure (in Torr), A is The area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters). Only a lower flow rate and a lower growth pressure can effectively transport the source to the micropores of the mask layer 102 to complete the selective epitaxy. A higher growth temperature and a higher V / III ratio are conducive to three-dimensional growth, so that a triangular island can be obtained by selective epitaxy. c) Growth to obtain N-type In x Ga 1-x After the N triangle island, turn off the supply of group III (Ga and In) sources, increase the total flow rate of carrier gas into the reaction chamber to more than twice that of the previous step, keep other conditions unchanged, and x Ga 1-x In-situ annealing of the N triangle island promotes N-type In x Ga 1-x The N triangle island starts to thermally decompose from the top to form N-type In x Ga 1-x N mesa structure 103; then, the growth conditions of the MOCVD system are controlled as follows: the growth temperature is 1050±20℃, the V / III ratio is 1000± 200, growth pressure 40 ~ 200Torr, while the total flow rate v of the carrier gas into the reaction chamber satisfies 150PA<760v<250PA, in N-type In x Ga 1-x A 5-20 nm thick N-type In layer with the same parameters is grown on the N mesa structure 103. x Ga 1-x N, complete the repair of the thermal annealing damage on the mesa; d) maintaining the growth conditions of the MOCVD system: the V / III ratio is 1000±200, the growth pressure is 40-200 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber satisfies 150PA<760v<250PA, and sequentially epitaxially growing the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y N layer 107, completing the growth of the epitaxial layer structure; e) depositing or sputtering a layer of silicon oxide, silicon nitride or boron nitride film on the surface of the epitaxial wafer as a passivation layer 108, using a standard micromachining process, etching from top to bottom at the location where the N electrode is to be prepared to expose the N-type GaN layer 101, and then preparing the N electrode 109; f) Spin-coat a polymer layer, such as SOG (spin on glass), to fill the passivation layer 108 and the outside of the N electrode 109, and its height is higher than the P-type In y Ga 1-y N layer 107; g) Use the standard micromachining process again to etch from top to bottom at the location where the P electrode is required to be prepared, leaking the P-type Iny Ga 1-y The N layer 107 is then followed by the P electrode 111 ; the preparation of the Micro-LED main structure is completed.

[0015] The present invention also provides a method for preparing a non-polar surface Micro-LED with an independent mesa structure. The structural features of the Micro-LED are arranged in sequence from bottom to top: an N-type GaN layer 101 with a non-polar surface on the upward crystal plane, a mask layer 102 containing a micropore array, an N-type In with an In component x of 0≤x≤0.35 connected to the N-type GaN layer 101 through the micropores of the mask layer 102, and a x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y of 0≤y≤0.15 successively grown on the mesa structure 103 y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-y The N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is a P electrode 111 on the isolation layer 110; wherein the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-table structure 103 are parallel, and the strain control layer 104 and the carrier control layer 106 can be selectively set or not set. When the top surface of the non-polar N-type GaN layer 101 is the (1-100) plane, the table structure 103 is a trapezoidal table structure. At this time, the size of the micropores of the mask layer 102 in the left-right direction is between 0.3 and 0.6 times the size of the table structure 103 in the left-right direction and the maximum is 5μm. The size in the up-down direction is the same as the up-down direction size of the table structure 103, and is adjusted according to the device size. This Micro-LED preparation method includes the following steps: a) preparing a non-polar (1-100) plane N-type GaN template as the non-polar plane N-type GaN layer 101, preparing a dielectric film (made of silicon oxide, silicon nitride or boron nitride) on it, and then using micromachining technology to machine microholes in the dielectric layer (exposing the N-type GaN layer 101 below), which is the mask layer 102; b) Using a MOCVD (metal organic chemical vapor deposition) system and utilizing the micropores of the mask layer 102 to selectively epitaxially grow an N-type In x Ga 1-x The growth conditions of the N mesa structure 103 are as follows: the growth temperature is 1080-1100°C, The V / III ratio (the molar flow ratio of the N source to the Ga source) is 1800-2500, the growth pressure is 40-120 Torr, and the total flow rate v (in sccm) of the carrier gas introduced into the reaction chamber satisfies 100PA<760v<300PA, where P is the growth pressure (in Torr) and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters). Only a lower flow rate and a lower growth pressure can effectively transport the source to the micropores of the mask layer 102 to complete the selective epitaxy. A higher growth temperature and a higher V / III ratio are conducive to three-dimensional growth, so that a mesa structure can be obtained by selective epitaxy. c) Setting the growth conditions of the MOCVD system to: V / III ratio of 1000±200, growth pressure of 40-200 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber to satisfy 150PA<760v<250PA, and sequentially epitaxially growing the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y N layer 107, completing the growth of the epitaxial layer structure; d) depositing or sputtering a layer of silicon oxide, silicon nitride or boron nitride film on the surface of the epitaxial wafer as a passivation layer 108, and using a standard micromachining process, etching from top to bottom at the location where the N electrode is to be prepared to expose the N-type GaN layer 101, Then, the N electrode 109 is prepared; e) Spin-coat a layer of polymer, such as SOG, to fill the passivation layer 108 and the outside of the N electrode 109, and its height is higher than that of the P-type In y Ga 1-y N layer 107; f) Use the standard micromachining process again to etch from top to bottom at the location where the P electrode needs to be prepared to leak out the P-type In y Ga 1-y The N layer 107 is then followed by the P electrode 111 ; the preparation of the Micro-LED main structure is completed.

[0016] Beneficial effects:

[0017] The present invention achieves full relaxation of the epitaxial structure based on selective epitaxy and lateral epitaxy, which can effectively suppress the generation of defects in the epitaxial layer. At the same time, by growing independent Micro-LED functional layers such as quantum wells on independent countertops, Micro-LEDs can be prepared without quantum well etching damage, eliminating quantum well etching damage and additional non-radiative recombination caused by traditional solutions that reduce the size of LEDs through process etching, effectively improving the efficiency of Micro-LEDs. Setting up a table-mounted structure fundamentally avoids etching damage to multiple quantum wells and improves the radiative recombination efficiency of Micro-LEDs.

[0018] At the same time, the present invention sets the non-polar surface N-type GaN layer 101 and the N-type In x Ga 1-x When the top surface of the N-table structure 103 is simultaneously the (11-20) plane and the table structure 103 is a triangular table structure, because the {1-101} crystal plane family is a lower potential energy surface, a regular triangular island can be formed, and the layer structure above can grow regularly and controllably. At this time, when the diameter of the micropores of the mask layer 102 is not greater than 1.5 μm, the diameter of the circumscribed circle of the table structure 103 within the plane is adjusted between 5 and 20 μm as needed, because when the micropores are small, regular islands are easily formed, and the size of the island can be controlled as needed; when the diameter of the micropores of the mask layer 102 is greater than 1.5 μm, the diameter of the circumscribed circle of the table structure 103 within the plane is 3 to 4 times the diameter of the micropores, but the maximum does not exceed 15 μm, because when the micropores are large, the islands are prone to irregularity, so the size of the islands is limited. Set a non-polar surface N-type GaN layer 101 and an N-type In x Ga 1-x When the top surface of the N-table structure 103 is simultaneously the (1-100) plane and the table structure 103 is a trapezoidal table structure, because the {11-20} crystal plane family is a lower potential energy surface, a regular and flat crystal plane can be formed, and the layer structure above can grow regularly and controllably. At this time, the size of the micropores of the mask layer 102 in the left-right direction is between 0.3 and 0.6 times the size of the table structure 103 in the left-right direction and is 5 μm at most, and the size in the up-down direction is the same as the size of the table structure 103 in the up-down direction, and is adjusted according to the device size. In addition, the table structure is conducive to releasing the underlying stress, improving the crystal quality of the entire structure of the LED, and thus weakening the influence of defects and polarization on carriers, and improving the luminous efficiency of the LED.

[0019] In addition, to alleviate x Ga 1-xThe N quantum well has a series of adverse effects (such as defects caused by stress release) caused by the large lattice mismatch with GaN. The present invention sets a strain control layer and a specially designed quantum well structure before growing the quantum well, and introduces an AlGaN layer with a specific molar composition to produce a strain opposite to that of InGaN to offset the strain of InGaN. The principle is as follows: First, according to the formula

[0020] Calculate the lattice mismatch value, where △ is the lattice mismatch value, c GaN The c-axis lattice constant of GaN is 5.185 angstroms, c n Al x1 Ga 1-x1 N and In x Ga 1-x The c-axis lattice constant of N. n The calculation formula is: c n =b×c AlN或InN +(1-b)c GaN

[0021] Where b is x, x1, x2 or x3, c AlN或InN is the c-axis lattice constant of AlN or InN, which are 4.982 angstroms and 5.693 angstroms respectively. Substituting the corresponding values ​​into InN gives x Ga 1-x The lattice mismatch between N and GaN in the c direction is △1 = 0.09797×x, Al x1 Ga 1-x1 The lattice mismatch value between N and GaN in the c direction is △2 = -0.03915×x1; In x2 Ga 1-x2 The lattice mismatch between N and GaN in the c direction is △3 = 0.09797 × x2; Al x3 Ga 1-x3 The lattice mismatch value between N and GaN in the c direction is △4 = -0.03915×x3. By adjusting the molar composition x, x1, x2, x3, Al x1 Ga 1-x1 N and In x Ga 1-x The lattice mismatch between N and GaN in the c direction is comparable. x2 Ga 1-x2 N and Al x3 Ga 1-x3The lattice mismatch value of N in the c direction is equivalent to that of GaN (that is, it satisfies △1=-△2, △3=-△4), that is, it satisfies x1=2.5×x±0.05, x3=2.5×x2±0.05. At this time, AlGaN will produce a strain in the opposite direction and with a similar value to InGaN to offset the strain of InGaN and suppress defects in InGaN due to excessive strain, thereby obtaining high-quality quantum wells and improving the overall Micro-LED lighting efficiency.

[0022] An electron blocking layer or a highly P-doped hole injection layer with a wider bandgap width is provided to limit the carriers in the active region, i.e., the multi-quantum wells, so that the overlap of the hole and electron wave functions in the multi-quantum wells is increased, and a higher radiation recombination efficiency is achieved, further solving the problem of the decrease in internal quantum efficiency as the injection current density increases. A lower flow rate and a lower growth pressure can effectively transport the source to the micropores of the mask layer 102 to complete the selective epitaxy. A higher growth temperature and a higher V / III ratio are conducive to three-dimensional growth, so that a triangular island can be obtained by selective epitaxy. The present invention provides a new structure and method for preparing Micro-LEDs, which is conducive to promoting the commercial application of Micro-LEDs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A cross-sectional schematic diagram of a non-polar surface Micro-LED including a triangular mesa structure and a trapezoidal mesa structure provided by the present invention.

[0024] Figure 2 A schematic top view of a non-polar surface Micro-LED with a triangular table structure provided by the present invention, wherein the passivation layer 108, the isolation layer 110 filled outside the passivation layer 108 and the N electrode 109, and the P-type In y Ga 1-y The N layer 107 is the P electrode 111 on the isolation layer 110, which is convenient for reflecting the overall structure.

[0025] Figure 3 Schematic diagram of a non-polar surface Micro-LED with a trapezoidal table structure provided by the present invention. In order to reflect the positional relationship of different structures, the figure does not show the passivation layer 108, the isolation layer 110 filled outside the passivation layer 108 and the N electrode 109, and the P-type In y Ga 1-y The N layer 107 is the P electrode 111 on the isolation layer 110, which is convenient for reflecting the overall structure.

[0026] Among them, 101 is a non-polar N-type GaN layer; 102 is a mask layer containing a microhole array; 103 is an N-type In x Ga1-x N mesa structure; 104 is a strain control layer; 105 is a quantum well layer; 106 is a carrier control layer; 107 is a P-type In y Ga 1-y N layer 107; 108 is a passivation layer; 109 is an N electrode; 110 is an isolation layer; and 111 is a P electrode. DETAILED DESCRIPTION

[0027] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0028] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0029] Embodiment 1:

[0030] A cross-sectional schematic diagram of a non-polar surface Micro-LED with a triangular table structure provided in Example 1 of the present invention is shown in FIG. Figure 1 As shown, the top view diagram is as follows Figure 2 As shown, the structural features of this Micro-LED are arranged from bottom to top in sequence: an N-type GaN layer 101 with an upward crystal plane (11-20) plane, a mask layer 102 containing a microhole array, an N-type In with an In component x=0.1 connected to the N-type GaN layer 101 through the microholes of the mask layer 102, x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y=0.1 are sequentially grown on the mesa structure 103. y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-yThe N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is a P electrode 111 on the isolation layer 110; wherein the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-mesa structures 103 are parallel, and the strain regulation layer 104 and the carrier regulation layer 106 may be selectively provided or not provided.

[0031] The non-polar surface N-type GaN layer 101 and the N-type In x Ga 1-x The top surface of the N-table structure 103 is also a (11-20) plane. At this time, the table structure 103 is a triangular table structure. In addition to the top surface, it also includes two left and right inclined planes that are also {1-101} crystal plane family and a side surface whose crystal plane is (000-1) and perpendicular to the top surface. The diameter of the circumscribed circle of the table structure 103 within the plane is 10μm.

[0032] A 30nm thick SiO2 dielectric film is plated on the non-polar (11-20) plane N-type GaN layer 101 as a mask layer 102, and a microhole array is etched from top to bottom through process technology, exposing the underlying GaN layer 101 in the microholes. The diameter of the microholes in the mask layer 102 is 1μm.

[0033] N-type In x Ga 1-x The molar composition x of the N mesa structure 103 is 0.1, and the strain control layer 104 is a three-period bottom-up GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-x N composite layer, where In x Ga 1-x The molar composition of N is x = 0.1, Al x1 Ga 1-x1 The thickness of N is 1 nm and the molar composition x1=0.25±0.05.

[0034] The layer structure of the quantum well layer 105 is In x2 Ga 1-x2 N / GaN / Al x3 Ga 1-x3N / GaN, where the molar composition x2=0.2, x3=0.5, and In x2 Ga 1-x2 The thickness of N is 3nm, two layers of GaN and Al x3 Ga 1-x3 The total thickness of N is 4 nm. When the light emission wavelengths of the quantum well layer 105 are red, green, and blue, respectively, the number of quantum well pairs is 1 pair, 2 pairs, and 3 pairs, respectively.

[0035] The carrier regulation layer 106 is an electron blocking layer, wherein the electron blocking layer is an Al2O3 layer having 4 periods and a thickness of 6 nm per period. y1 Ga (1-y1) N / GaN superlattice with molar composition y1=0.2.

[0036] P-type In y Ga 1-y The thickness of the N layer 107 is 100 nm, the molar composition y=0.1, and the Mg element doping concentration is 4×10 19 cm -3 , and its hole concentration is 2×10 18 cm -3 ; Among them, P type In y Ga 1-y In the 30 nm thick region on the upper surface of the N layer 107, the doping concentration of Mg element is 2×10 20 cm -3 , and its hole concentration is 6×10 18 cm -3 .

[0037] The method for preparing a non-polar surface Micro-LED with a triangular table structure provided in Embodiment 1 of the present invention comprises the following steps: a) preparing a non-polar (11-20) face N-type GaN template as the non-polar face N-type GaN layer 101, preparing a layer of silicon oxide dielectric film on it, and then using micromachining technology to machine microholes in the dielectric layer (exposing the N-type GaN layer below) GaN layer 101), namely mask layer 102; b) Using the MOCVD system and the micro-holes in the mask layer 102 to selectively grow N-type In x Ga 1-x The growth conditions of the N triangle island are as follows: the growth temperature is 1100°C, the V / III ratio (the molar flow ratio of the N source to the Ga source) is 2000, the growth pressure is 100 Torr, and the total flow rate v (in sccm) of the carrier gas into the reaction chamber satisfies 760v=2×10 4A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters), and the carrier gas flow rate is 200 cm / min. c) Growth to obtain N-type In x Ga 1-x After the N triangle island, turn off the supply of group III (Ga and In) sources, increase the total flow rate of carrier gas into the reaction chamber to 2.5 times of the previous step, keep other conditions unchanged, and x Ga 1-x In-situ annealing of the N triangle island promotes N-type In x Ga 1-x The N triangle island starts to thermally decompose from the top to form N-type In x Ga 1-x N mesa structure 103; then, the growth conditions of the MOCVD system are controlled as follows: the growth temperature is 1050±20℃, the V / III ratio is 1000± 200, growth pressure 100Torr, and the total flow rate v of the carrier gas into the reaction chamber satisfies 760v=2×10 4 A, where A is The area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters) and the carrier gas flow rate are 200 cm / min. x Ga 1-x A 10 nm thick N-type In layer with the same parameters is grown on the N mesa structure 103. x Ga 1-x N, complete the repair of the thermal annealing damage on the mesa; d) Maintain the growth conditions of the MOCVD system: V / III ratio is 1000±200, growth pressure is 100 Torr, and the total flow rate v of the carrier gas into the reaction chamber satisfies 760v=2×10 4 A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters), and the carrier gas flow rate is 200 cm / min. The strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y N layer 107, completing the growth of the epitaxial layer structure; e) depositing a silicon oxide film as a passivation layer 108 on the surface of the epitaxial wafer, and using a standard micromachining process, etching from top to bottom at the location where the N electrode is to be prepared to expose the N-type GaN layer 101, and then preparing the N electrode 109; f) Spin-coat a layer of polymer SOG (spin on glass) to fill the passivation layer 108 and the outside of the N electrode 109. Its height is higher than that of the P-type In y Ga 1-y N layer 107; g) Use the standard micromachining process again to etch from top to bottom at the location where the P electrode is required to be prepared, leaking the P Type y Ga 1-y The N layer 107 is then followed by the P electrode 111 ; the preparation of the Micro-LED main structure is completed.

[0038] Embodiment 2:

[0039] A cross-sectional schematic diagram of a non-polar surface Micro-LED with a trapezoidal table structure provided in Example 2 of the present invention is shown in FIG. Figure 1 As shown, the top view diagram is as follows Figure 3 As shown, the structural features of this Micro-LED are arranged from bottom to top in sequence: an N-type GaN layer 101 with a (1-100) plane facing upward, a mask layer 102 containing a microhole array, an N-type In with an In component x=0.1 connected to the N-type GaN layer 101 through the microholes in the mask layer 102, x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y=0.1 are sequentially grown on the mesa structure 103. y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-y The N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is a P electrode 111 on the isolation layer 110; wherein the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-mesa structures 103 are parallel, and the strain regulation layer 104 and the carrier regulation layer 106 may be selectively provided or not provided.

[0040] The non-polar surface N-type GaN layer 101 and the N-type In x Ga 1-xThe top surface of the N-table structure 103 is also the (1-100) plane. In this case, the table structure 103 is a trapezoidal table structure, which, in addition to the top surface, also includes two left and right inclined planes of the {11-20} crystal plane family and two front and back side surfaces perpendicular to the top surface whose crystal planes are (0001) and (000-1) respectively.

[0041] A 30nm thick SiO2 dielectric film is plated on the non-polar surface N-type GaN layer 101 as a mask layer 102, and a microhole array is etched from top to bottom through process technology, exposing the underlying GaN layer 101 in the microholes. The size of the microholes in the mask layer 102 in the left-right direction is 0.5 times the size of the mesa structure 103 in the left-right direction, and the size in the up-down direction is the same as the up-down direction size of the mesa structure 103.

[0042] N-type In x Ga 1-x The molar composition x of the N mesa structure 103 is 0.1, and the strain control layer 104 is a three-period bottom-up GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-x N composite layer, where In x Ga 1-x The molar composition of N is x = 0.1, Al x1 Ga 1-x1 The thickness of N is 1 nm and the molar composition x1=0.25±0.05.

[0043] The layer structure of the quantum well layer 105 is In x2 Ga 1-x2 N / GaN / Al x3 Ga 1-x3 N / GaN, where the molar composition x2=0.1, x3=0.25, and In x2 Ga 1-x2 The thickness of N is 3nm, two layers of GaN and Al x3 Ga 1-x3 The total thickness of N is 4 nm. When the light emission wavelengths of the quantum well layer 105 are red, green, and blue, respectively, the number of quantum well pairs is 1 pair, 2 pairs, and 3 pairs, respectively.

[0044] The carrier regulation layer 106 is an electron blocking layer, wherein the electron blocking layer is an Al2O3 layer having 4 periods and a thickness of 6 nm per period. y1 Ga (1-y1) N / GaN superlattice with molar composition y1=0.2.

[0045] P-type In y Ga 1-yThe thickness of the N layer 107 is 100 nm, the molar composition y=0.1, and the Mg element doping concentration is 4×10 19 cm -3 , and its hole concentration is 2×10 18 cm -3 ; Among them, P type In y Ga 1-y In the 30 nm thick region on the upper surface of the N layer 107, the doping concentration of Mg element is 2×10 20 cm -3 , and its hole concentration is 6×10 18 cm -3 .

[0046] A method for preparing a non-polar surface Micro-LED with a trapezoidal table structure provided in Embodiment 2 of the present invention comprises the following steps: a) preparing a non-polar (1-100)-plane N-type GaN template as the non-polar plane N-type GaN layer 101, preparing a layer of silicon oxide dielectric film on it, and then using micromachining technology to machine micropores in the dielectric layer (exposing the N-type GaN layer below) GaN layer 101), namely mask layer 102; b) Using the MOCVD system and the micro-holes in the mask layer 102 to selectively grow N-type In x Ga 1-x The N mesa structure 103 is grown under the following conditions: the growth temperature is 1100°C, the V / III ratio (the molar flow ratio of the N source to the Ga source) is 2000, the growth pressure is 100 Torr, and the total flow rate v (in sccm) of the carrier gas introduced into the reaction chamber satisfies 760v=2×10 4 A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters), and the carrier gas flow rate is 200 cm / min. c) The growth conditions of the MOCVD system were set to: V / III ratio of 1000±200, growth pressure of 100 Torr, and the total flow rate v of the carrier gas into the reaction chamber satisfied 760v=2×10 4 A, where A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters), and the carrier gas flow rate is 200 cm / min. The strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y N layer 107, completing the growth of the epitaxial layer structure; d) depositing a silicon oxide film as a passivation layer 108 on the surface of the epitaxial wafer, and using a standard micromachining process, etching from top to bottom at the location where the N electrode is to be prepared to expose the N-type GaN layer 101, and then preparing the N electrode 109; e) Spin-coat a layer of polymer SOG (spin on glass) to fill the passivation layer 108 and the outside of the N electrode 109, and its height is higher than that of the P-type In y Ga 1-y N layer 107; f) Use the standard micromachining process again to etch from top to bottom at the location where the P electrode needs to be prepared to leak out the P-type In y Ga 1-y The N layer 107 is then followed by the P electrode 111 ; the preparation of the Micro-LED main structure is completed.

Claims

1. A non-polar surface Micro-LED with an independent table structure, characterized by: The invention comprises an N-type GaN layer 101 with a non-polar surface facing upward, a mask layer 102 having a microhole array, and an N-type In layer 104 having an In component x of 0≤x≤0.35 connected to the N-type GaN layer 101 through the microholes of the mask layer 102. x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y of 0≤y≤0.15 successively grown on the mesa structure 103 y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-y The N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is a P electrode 111 on the isolation layer 110; wherein the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-mesa structures 103 are parallel, and the strain regulation layer 104 and the carrier regulation layer 106 may be selectively provided or not provided.

2. The non-polar surface Micro-LED with independent mesa structure as claimed in claim 1, characterized in that: The mask layer 102 containing the micropore array is formed by etching a 5 to 50 nm thick SiO2, SiN or hBN dielectric film on the non-polar surface N-type GaN layer 101 from top to bottom through a process technology, and the underlying non-polar surface N-type GaN layer 101 is exposed in the micropores; wherein the micropore array is arranged in a close-packed form with micropore centers, and the center distance between any micropore and the six adjacent micropores is equal, and can be adjusted according to actual needs.

3. The non-polar surface Micro-LED with independent mesa structure as claimed in claim 1, characterized in that: The non-polar surface N-type GaN layer 101 and the N-type In x Ga 1-x The top surface of the N-table structure 103 is also a (11-20) plane. At this time, the table structure 103 is a triangular table structure. In addition to the top surface, it also includes two left and right inclined planes of the {1-101} crystal plane family and a side surface with a crystal plane of (000-1) and perpendicular to the top surface. At this time, the diameter of the micropores of the mask layer 102 is between 0.2 and 2 μm. When the diameter of the micropores of the mask layer 102 is not greater than 1.5 μm, the diameter of the circumscribed circle of the table structure 103 within the plane is between 5 and 20 μm and can be adjusted as needed. When the diameter of the micropores of the mask layer 102 is greater than 1.5 μm, the diameter of the circumscribed circle of the table structure 103 within the plane is 3 to 4 times the diameter of the micropores, but the maximum does not exceed 15 μm. In addition, the non-polar surface N-type GaN layer 101 and the N-type In x Ga 1-x The top surface of the N-table structure 103 facing upward can also be a (1-100) plane at the same time. In this case, the table structure 103 is a trapezoidal table structure, which, in addition to the top surface facing upward, also includes two left and right inclined planes of the {11-20} crystal plane family and two front and back side surfaces perpendicular to the top surface whose crystal planes are (0001) and (000-1) respectively; in this case, the size of the micropores of the mask layer 102 in the left-right direction is between 0.3 and 0.6 times the size of the table structure 103 in the left-right direction and is 5 μm at most, and the size in the up-down direction is the same as the up-down direction size of the table structure 103, and is adjusted according to the device size.

4. The non-polar surface Micro-LED with independent mesa structure as claimed in claim 1, characterized in that: N-type In x Ga 1-x When the molar component x of the N mesa structure 103 is ≤ 0.05, the strain control layer 104 is a 1 - 3 cycle GaN / Al x1 Ga 1- x1 N / GaN composite layer, where the thickness of Al x1 Ga 1-x1 N is less than 3 nm and x1 < 0.15; if the molar component 0.05 < x < 0.15, the strain control layer 104 is a 1 - 3 cycle bottom - up GaN / Al x1 Ga 1-x1 N / GaN / In x Ga 1-x N composite layer, where the molar component of In x Ga 1-x N is the molar component x of the N - type In x Ga 1-x N mesa structure 103, and the thickness of Al x1 Ga 1-x1 N is less than 2 nm and x1 = 2.5×x ± 0.

05.

5. The non-polar surface Micro-LED with independent mesa structure as claimed in claim 1, characterized in that: When the emission wavelengths of the quantum well layer 105 are red, green, and blue, respectively, the number of quantum well pairs does not exceed 2, 4, and 5 pairs, respectively; the layer structure of the quantum well is In x2 Ga 1-x2 N / GaN / Al x3 Ga 1-x3 N / GaN, where x3 = 2.5 x2 ± 0.05, and In x2 Ga 1-x2 The thickness of N is 2 to 4 nm, and the two layers of GaN and Al x3 Ga 1-x3 The total thickness of N does not exceed 6 nm.

6. The non-polar surface Micro-LED with independent mesa structure as claimed in claim 1, characterized in that: The carrier regulation layer 106 is one of an electron blocking layer and a hole injection layer; wherein the electron blocking layer is an Al2O3 layer having 2 to 8 cycles and a single cycle thickness of less than 8 nm. y1 Ga (1-y1) N / GaN superlattice, where the molar composition y1 is between 0.1 and 0.6, and Al y1 Ga (1-y1) The hole injection layer is P-doped with an overall thickness of less than 30nm Al y2 Ga (1-y2) N / In y3 Ga (1-y3) N / GaN superlattice, y2=0.5×y3, Mg doping concentration is 5×10 17 cm -3 ~1×10 19 cm -3 The hole concentration is not higher than 1×10 18 cm -3 .

7. The non-polar surface Micro-LED with independent mesa structure as claimed in claim 1, characterized in that: P-type In y Ga 1-y The thickness of the N layer 107 is between 50 and 200 nm, and the molar composition y is between 0 and 0.

15. When y=0, it is GaN. The Mg element doping concentration is 2×10 19 cm -3 ~5×10 19 cm -3 The hole concentration is not less than 1×10 18 cm -3 ; Among them, P type In y Ga 1- y In the 5-30 nm thickness region on the upper surface of the N layer 107, the doping concentration of the Mg element is not less than 1×10 20 cm -3 , the hole concentration is not less than 5×10 18 cm -3 .

8. A method for preparing a non-polar surface Micro-LED with an independent mesa structure, wherein the structural features of the Micro-LED are arranged in sequence from bottom to top: an N-type GaN layer 101 with a non-polar surface on the upward crystal plane, a mask layer 102 containing a micropore array, an N-type In with an In component x of 0≤x≤0.35 connected to the N-type GaN layer 101 through the micropores of the mask layer 102, and x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y of 0≤y≤0.15 successively grown on the mesa structure 103 y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-y The N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is the P electrode 111 on the isolation layer 110; The strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-table structure 103 are parallel, and the strain control layer 104 and the carrier control layer 106 can be selectively provided or not provided. When the top surface of the non-polar surface N-type GaN layer 101 is the (11-20) plane, the table structure 103 is a triangular table structure, and the diameter of the micropores of the mask layer 102 is between 0.2 and 2 μm. The preparation method of this Micro-LED includes the following steps: a) preparing a non-polar (11-20) plane N-type GaN template as the non-polar plane N-type GaN layer 101, preparing a dielectric film (made of silicon oxide, silicon nitride or boron nitride) on it, and then using micromachining technology to machine microholes in the dielectric layer (exposing the N-type GaN layer 101 below), which is the mask layer 102; b) Using a MOCVD (metal organic chemical vapor deposition) system and utilizing the micropores of the mask layer 102 to selectively epitaxially grow an N-type In x Ga 1-x N triangle island, the growth conditions are as follows: growth temperature is 1080-1100°C, V / III ratio (molar flow ratio of N source to Ga source) is 1800-2500, growth pressure is 40-120 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber (in sccm) satisfies 100PA<760v<300PA, where P is the growth pressure (in Torr), and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters). c) Growth to obtain N-type In x Ga 1-x After the N triangle island, turn off the supply of group III (Ga and In) sources, increase the total flow rate of carrier gas into the reaction chamber to more than twice that of the previous step, keep other conditions unchanged, and x Ga 1-x In-situ annealing of the N triangle island promotes N-type In x Ga 1-x The N triangle island starts to thermally decompose from the top to form N-type In x Ga 1-x N mesa structure 103; then, the MOCVD system growth conditions are controlled as follows: growth temperature is 1050±20°C, V / III ratio is 1000±200, growth pressure is 40-200Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber satisfies 150PA<760v<250PA, in the N-type In x Ga 1-x A 5-20 nm thick N-type In layer with the same parameters is grown on the N mesa structure 103. x Ga 1-x N, complete the repair of the thermal annealing damage on the table; d) maintaining the growth conditions of the MOCVD system: the V / III ratio is 1000±200, the growth pressure is 40-200 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber satisfies 150PA<760v<250PA, and sequentially epitaxially growing the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y N layer 107, completing the growth of the epitaxial layer structure; e) depositing or sputtering a layer of silicon oxide, silicon nitride or boron nitride film on the surface of the epitaxial wafer as a passivation layer 108, using a standard micromachining process, etching from top to bottom at the location where the N electrode is to be prepared to expose the N-type GaN layer 101, and then preparing the N electrode 109; f) Spin-coat a polymer layer, such as SOG (spin on glass), to fill the passivation layer 108 and the outside of the N electrode 109, and its height is higher than the P-type In y Ga 1-y N layer 107; g) Use the standard micromachining process again to etch from top to bottom at the location where the P electrode is required to be prepared, leaking the P-type In y Ga 1-y The N layer 107 is then followed by the P electrode 111 ; the preparation of the Micro-LED main structure is completed.

9. A method for preparing a non-polar surface Micro-LED with an independent mesa structure, wherein the structural features of the Micro-LED are arranged in sequence from bottom to top: an N-type GaN layer 101 with a non-polar surface on the upward crystal plane, a mask layer 102 containing a micropore array, an N-type In with an In component x of 0≤x≤0.35 connected to the N-type GaN layer 101 through the micropores of the mask layer 102, x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In with In composition y of 0≤y≤0.15 successively grown on the mesa structure 103 y Ga 1-y N layer 107, covered with N-type In x Ga 1-x N-type mesa structure 103, strain control layer 104, quantum well layer 105, carrier control layer 106 and P-type In y Ga 1-y The N-layer 107 is composed of five parts: the oblique surface and side surface of the mesa body and the passivation layer 108 of a part of the mask layer 102; the N-electrode 109 that passes through the mask layer 102 and the passivation layer 108 and has a good ohmic contact with the N-type GaN layer 101; the isolation layer 110 filled outside the passivation layer 108 and the N-electrode 109; and the P-type In y Ga 1-y The N layer 107 is the P electrode 111 on the isolation layer 110; The strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y The surface of the N layer 107 is N-type In x Ga 1-x The surfaces of the N-table structure 103 are parallel, and the strain control layer 104 and the carrier control layer 106 can be selectively set or not set. When the top surface of the non-polar N-type GaN layer 101 is the (1-100) plane, the table structure 103 is a trapezoidal table structure. At this time, the size of the micropores of the mask layer 102 in the left-right direction is between 0.3 and 0.6 times the size of the table structure 103 in the left-right direction and the maximum is 5μm. The size in the up-down direction is the same as the up-down direction size of the table structure 103, and is adjusted according to the device size. This Micro-LED preparation method includes the following steps: a) preparing a non-polar (1-100) plane N-type GaN template as the non-polar plane N-type GaN layer 101, preparing a dielectric film (made of silicon oxide, silicon nitride or boron nitride) on it, and then using micromachining technology to machine microholes in the dielectric layer (exposing the N-type GaN layer 101 below), which is the mask layer 102; b) Using a MOCVD (metal organic chemical vapor deposition) system and utilizing the micropores of the mask layer 102 to selectively epitaxially grow an N-type In x Ga 1-x N mesa structure 103, the growth conditions are as follows: growth temperature is 1080-1100°C, V / III ratio (molar flow ratio of N source to Ga source) is 1800-2500, growth pressure is 40-120 Torr, and the total flow rate v (in sccm) of the carrier gas introduced into the reaction chamber satisfies 100PA<760v<300PA, wherein P is the growth pressure (in Torr), and A is the area of ​​the graphite disk in the reaction chamber of the MOCVD system (in square centimeters). c) Setting the growth conditions of the MOCVD system to: V / III ratio of 1000±200, growth pressure of 40-200 Torr, and the total flow rate v of the carrier gas introduced into the reaction chamber to satisfy 150PA<760v<250PA, and sequentially epitaxially growing the strain control layer 104, the quantum well layer 105, the carrier control layer 106 and the P-type In y Ga 1-y N layer 107, completing the growth of the epitaxial layer structure; d) depositing or sputtering a layer of silicon oxide, silicon nitride or boron nitride film on the surface of the epitaxial wafer as a passivation layer 108, using a standard micromachining process, etching from top to bottom at the location where the N electrode needs to be prepared to expose the N-type GaN layer 101, and then preparing the N electrode 109; e) Spin-coat a polymer layer, such as SOG (spin on glass), to fill the passivation layer 108 and the outside of the N electrode 109, and its height is higher than the P-type In y Ga 1-y N layer 107; f) Use the standard micromachining process again to etch from top to bottom at the location where the P electrode needs to be prepared to leak out the P-type In y Ga 1-y The N layer 107 is then followed by the P electrode 111 ; the preparation of the Micro-LED main structure is completed.

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