Wafer structure for reducing wafer stress and chip particle arrangement photomask design method
By designing a balanced chip particle arrangement on the wafer and using the spaced chip particle arrangement, the warping problem caused by uneven stress in mini-LED chip grinding is solved, and the stability of the wafer and the chip are improved. Rate.
Patent Information
- Application Number
- CN202411401057.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-10
AI Technical Summary
During the mini-LED chip grinding process, the wafer warping caused by the compressive stress of the GaN epitaxial layer, which increases the problem of laser cracking difficulty and chip yield decline.
By designing a wafer structure and chip particle arrangement photomask method, we ensure that the width of the chip particles on the substrate tends to be consistent, and blank chip particles are spaced on the substrate to reduce stress unevenness and reduce stress Warpage risk of wafers.
It effectively balances the stress imbalance of the wafer, reduces warpage, and improves the chip yield and stability of the cutting process.
Smart Images
Figure CN119300587A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a wafer structure and a chip particle arrangement mask design method for reducing wafer stress. Background Art
[0002] As mini-LED display technology continues to improve, the market's requirements for mini-LED chips are becoming more diversified and miniaturized. Therefore, mini-LED chips are developing in the direction of smaller size and thinner thickness. However, in the process of epitaxial growth of GaN epitaxial layer on the substrate, GaN molecules are stacked from bottom to top, such as Figure 1 As shown in the figure, the lattice mismatch with the Al2O3 substrate generates compressive stress inside the GaN material. When the thickness of the mini-LED wafer is ground thinner, the stress is more likely to appear and the wafer is more likely to warp, such as Figure 2 As shown in the figure, the difficulty of laser scribing increases and the chip yield decreases.
[0003] Therefore, there is an urgent need for a wafer structure and a wafer design method that can solve the above problems. Summary of the invention
[0004] The purpose of the present invention is to provide a wafer structure and chip particle arrangement mask design method, which can make the horizontal and vertical cutting road widths in the entire wafer tend to be consistent, thereby balancing the risk of thinning fragments caused by the self-stress imbalance caused by the chip particle arrangement.
[0005] In order to achieve the above-mentioned purpose, the present invention provides a wafer structure for reducing wafer stress, comprising a substrate, a plurality of chip particles formed on the substrate, the cutting road width of adjacent chip particles is W, the length A of the chip particles arranged horizontally along the substrate is less than the width B of the chip particles arranged vertically along the substrate, so that the chip particles are arranged horizontally in X columns and vertically in Y rows on the substrate, and in the vertical columns of the substrate, reserved areas for a plurality of chip particles are spaced apart, and the vacated reserved areas are called blank chip particles, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting road widths of the chip particles on the substrate at least adjacent to the center point of the substrate and 1 is less than or equal to a preset value.
[0006] Preferably, the blank chip particles are arranged in rows to form a plurality of blank particle rows, and the plurality of blank particle rows are spaced apart. This solution not only facilitates balancing the width of the cutting path in the area where most chip particles are located on the substrate in the horizontal and vertical regions, but also prevents the core particles from being damaged during subsequent cutting and splitting.
[0007] Preferably, in a longitudinal column of the substrate passing through or near the center point of the substrate, a reserved area of a chip particle is vacated in every N chip particles to form a blank chip particle. The longitudinal column passing through or near the center point of the substrate refers to the longitudinal column closest to the center point of the substrate.
[0008] Preferably, there are at least N / 3 chip particles between two adjacent rows of blank chip particles, which effectively reduces the local uneven stress in the substrate.
[0009] Preferably, the blank particle rows are arranged at equal intervals, so that there are N-1 chip particles between two adjacent rows of blank chip particles.
[0010] Optionally, N is The nearest integer.
[0011] Optionally, A=100 μm, B=150 μm, W=20 μm, and N=15.
[0012] Preferably, the substrate is a circular substrate.
[0013] The present invention also provides a chip particle arrangement mask design method for reducing wafer stress, setting an arrangement diagram of chip particles on a substrate: designing the number of chip particles with a cutting road width of W on the substrate according to the size of the substrate, arranging the chip particles in X columns horizontally and Y rows vertically on the substrate, the length A of the chip particles arranged horizontally along the substrate is less than the width B of the chip particles arranged vertically along the substrate, and in the vertical columns of the substrate, a number of reserved areas for chip particles are spaced apart, and the vacated reserved areas are called blank chip particles, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting road widths of the chip particles on the substrate at least adjacent to the center point of the substrate and 1 is less than or equal to a preset value.
[0014] Preferably, in the longitudinal column closest to the center point of the substrate on the substrate, several chip particles are spaced out to set several blank chip particles, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting path widths of the chip particles closest to the center point of the substrate in the longitudinal column and 1 is less than or equal to a preset value; for the remaining longitudinal columns, the chip particles in the row where the blank chip particles are located are all spaced out to set blank core particles, so that all the blank chip particles are arranged in rows to form several blank particle rows, and the spacing between the several blank particle rows is set. This solution not only facilitates the balancing of the cutting path widths in the transverse and longitudinal regions in the area where most of the chip particles on the substrate are located, but also prevents the core particles from being damaged during subsequent cutting and splitting.
[0015] Specifically, in a longitudinal column of the substrate passing through or near the center point of the substrate, a reserved area of a chip particle is vacated in every N chip particles to form a blank chip particle.
[0016] Preferably, there are at least N / 3 chip particles between two adjacent rows of blank chip particles, which effectively reduces the local uneven stress in the substrate.
[0017] Preferably, the blank particle rows are arranged at equal intervals, so that there are N-1 chip particles between two adjacent rows of blank chip particles.
[0018] Preferably, N is The nearest integer.
[0019] Specifically, A=100 μm, B=150 μm, W=20 μm, and N=15.
[0020] Preferably, the substrate is a circular substrate.
[0021] Compared with the prior art, the present invention leaves a reserved area for a chip particle every few rows in the shorter longitudinal direction of the chip particles on the wafer. When the epitaxial layer of the wafer is formed and etched, the epitaxial layer in the reserved area is completely etched away as a cutting path. The above-mentioned reserved area is called a blank chip particle (equivalent to being left blank without setting chip particles). The blank chip particles are also arranged for splitting in the subsequent splitting process. The blank chip particles have the same size as the chip particles, but due to their own inconsistent length and width, the length A arranged horizontally along the substrate is smaller than the width B arranged vertically along the substrate, so that the blank chip particles do not affect the various processes of the wafer, and only the longitudinal cutting path area is increased in the subsequent splitting process. Finally, the horizontal and vertical cutting path widths of the chip particles near the center point of the substrate in the entire wafer tend to be consistent, so that the central area of the substrate will not produce a large warpage due to uneven stress, thereby balancing the risk of thinning fragments caused by the stress imbalance caused by the chip particle arrangement itself, so that the warpage of the wafer is better. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a top view of the wafer structure for reducing wafer stress in Example 1 of the present invention.
[0023] Figure 2 It is a partial side cross-sectional view of the wafer structure for reducing wafer stress in Example 1 of the present invention.
[0024] Figure 3 It is a top view of the wafer structure for reducing wafer stress in Example 2 of the present invention. DETAILED DESCRIPTION
[0025] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.
[0026] Embodiment 1:
[0027] Since the chip particles 21 are rectangles with unequal lengths and widths, the number of horizontal chip particles 21 arranged in the entire wafer is greater than that of vertical chips. The size of the chip particles 21 becomes smaller and smaller, and the thickness becomes thinner and thinner during the wafer thinning process. Due to the influence of the wafer's own stress, the thinning process may cause wafer cracking. A chip particle 21 arrangement on the wafer is required to balance the wafer's own stress during the deep etching process at the front end of the chip. In other words, the wafer needs to have a consistent cutting path (deep etching) area in at least the horizontal and vertical directions through the center area to achieve balance.
[0028] To this end, the present invention discloses a wafer structure for reducing wafer stress. Figure 1 and Figure 2 The wafer 10 includes a substrate 11, a plurality of chip particles 21 formed on the substrate 11, the width of the cutting path between adjacent chip particles 21 is W, the length A of the chip particles 21 arranged horizontally along the substrate is less than the width B of the chip particles 21 arranged vertically along the substrate, so that the chip particles 21 are arranged horizontally in X columns and vertically in Y rows on the substrate, and in the vertical columns of the substrate 11, a plurality of reserved areas of chip particles are spaced apart, and the reserved areas are called blank chip particles 22, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting path widths of the chip particles 21 located at least near the center point of the substrate on the substrate and 1 is less than or equal to a preset value. The preset value tends to zero, so that the length of the cutting path in the transverse and longitudinal directions of the chips located in the central area of the substrate 11 tends to be consistent, so that the central area of the substrate 11 will not be warped and twisted due to stress, thereby balancing the risk of thinning and fragmentation caused by the self-stress imbalance caused by the arrangement of the core particles. The blank chip particles 22 are also arranged for splitting in the subsequent splitting process. The blank chip particles 22 have the same size as the chip particles 21, so that the blank chip particles 22 do not affect the wafer process and only increase the cutting area.
[0029] The chip particle 21 on the substrate at least adjacent to the center point of the substrate may be a chip particle 21 closest to the center point of the substrate 11 , or may be a plurality of chip particles 21 closest to the center point of the substrate 11 .
[0030] In the present invention, in each longitudinal column, a reserved area of a chip particle is vacated among every N chip particles, and the vacated reserved area is called a blank chip particle 22 .
[0031] The better, reference Figure 1, the blank chips 22 are arranged alternately on the substrate 11. In this embodiment, N in different longitudinal columns can be the same or different from the center to both sides, or partly the same and partly different. When N in different longitudinal columns is at least partly different, the longitudinal column closer to the center point of the substrate 11 has a larger N.
[0032] Preferably, a blank chip particle 22 is arranged every N-1 chip particles 21, so that the blank chip particles 22 are arranged at equal intervals in the vertical column.
[0033] Of course, different from this, the blank chip particles 22 can also be arranged at unequal intervals, as long as there are at least five chip particles 21 (N / 3 chip particles 21) between adjacent rows of blank chip particles 22, and only one blank chip particle 22 is left in every N chip particles, so that the blank chip particles 22 remain balanced as a whole.
[0034] Embodiment 2:
[0035] refer to Figure 3 Different from Example 1, in Example 2, the blank chip particles 22 are arranged in rows on the substrate 10 to form a plurality of blank particle rows, and the plurality of blank particle rows are spaced apart.
[0036] Among them, in the longitudinal column of the substrate 11 passing through or adjacent to the center point of the substrate 11, a reserved area of a chip particle is vacated in every N chip particles 21 to form a blank chip particle 22. The longitudinal column of the substrate 11 passing through or adjacent to the center point of the substrate 11 refers to the longitudinal column closest to the center point of the substrate. In this embodiment, in the longitudinal column of the substrate 11 passing through or adjacent to the center point of the substrate 11, the blank chip particles 22 are arranged according to the above rules, and in other longitudinal columns, the blank chip particles 22 are arranged following the blank chip particles 22 in the longitudinal column passing through or adjacent to the center point of the substrate 11, so that the blank chip particles 22 are arranged in rows.
[0037] In this embodiment, N is Of course, the value of N is not limited to this formula, wherein it is preferable to ensure that the absolute value of the difference between the ratio of the longitudinal and transverse cutting road widths of the chip particles 21 located at least near the center point of the substrate 11 and 1 is less than 0.01.
[0038] In a 4-inch wafer 10 (R = 50mm circle), a total of 1000 0406mil (100*150um) chip particles 21 can be arranged in the horizontal and vertical lines passing through the center of the wafer 10. The chip particles 21 are rectangular, with a length A = 100um and a width B = 150um. The cutting road width W = 20um, and the cutting road area needs to be increased by (1000-666.66) * 20 = 6666.8um in the vertical direction. The entire vertical arrangement of 14 chips requires 1 row of blank core particles 21 (150um), and the entire vertical space is 6666.8 / 150 = 44.44 chips. 6666.8 / 44.44=15 particles, there is a blank particle 22 in every 15 particles. If the blank particles 22 are arranged at equal intervals in the vertical column, a blank particle 22 is arranged every 14 chip particles 21. This can make the horizontal and vertical cutting path widths of the chip particles at the center of the entire wafer tend to be consistent, thereby balancing the risk of thinning fragments caused by the self-stress imbalance caused by the core particle arrangement.
[0039] In this embodiment, a blank chip particle 22 is arranged every N-1 chip particles 21, so that the blank chip particles 22 are arranged at equal intervals in the vertical column.
[0040] Of course, different from this, the blank chip particles 22 can also be arranged at unequal intervals, as long as there are at least five chip particles 21 (N / 3 chip particles 21) between adjacent rows of blank chip particles 22, and only one blank chip particle 22 is left in every N chip particles, so that the blank chip particles 22 remain balanced as a whole.
[0041] The present invention also discloses a chip particle arrangement mask design method for reducing wafer stress, and sets an arrangement diagram of chip particles on a substrate: the number of chip particles with a cutting road width of W is designed on the substrate according to the size of the substrate 11, and the chip particles 21 are arranged in X columns horizontally and Y rows vertically on the substrate. The length A of the chip particles arranged horizontally along the substrate is less than the width B of the chip particles arranged vertically along the substrate, and in the vertical column of the substrate, a blank chip particle 22 is arranged every N chip particles 21, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting road widths of the chip particles 21 located at least near the center point of the substrate 11 and 1 is less than or equal to a preset value. In this embodiment, the preset value is 0.01.
[0042] Preferably, the blank chip particles 22 are arranged in rows on the substrate 11 (refer to Figure 3 ) or interlaced (ref. Figure 1 ) is arranged on the substrate 11.
[0043] Preferably, the blank chip particles 22 are arranged in rows on the substrate 11, and N is Of course, the value of N is not limited to this formula, as long as the substrate 11 ensures that the absolute value of the difference between the ratio of the longitudinal and transverse cutting road widths of the chip particles 21 at least close to the center point of the substrate 11 and 1 is less than 0.01.
[0044] Specifically, in the longitudinal column closest to the center point of the substrate 11 on the substrate 11, a number of chip particles 21 are spaced out to set a number of blank chip particles 22, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting road widths of the chip particles 21 closest to the center point of the substrate in the longitudinal column and 1 is less than or equal to a preset value; for the remaining longitudinal columns, the chip particles in the row where the blank chip particles 22 are located are all spaced out to set blank core particles 22, so that all the blank chip particles 22 are arranged in rows to form a number of blank particle rows, and the spacing between the several blank particle rows is set.
[0045] In this embodiment, the substrate is a circular substrate, A=100 μm, B=150 μm, W=20 μm, and N=15.
[0046] In this embodiment, a blank chip particle 22 is arranged every N-1 chip particles 21, so that the blank chip particles 22 are arranged at equal intervals in the vertical column.
[0047] Of course, different from this, the blank chip particles 22 can also be arranged at unequal intervals, as long as there are at least five chip particles 21 (N / 3 chip particles 21) between adjacent rows of blank chip particles 22, and only one blank chip particle 22 is left in every N chip particles, so that the blank chip particles 22 remain balanced as a whole.
[0048] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.
Claims
1. A wafer structure for reducing wafer stress, characterized in that: The invention comprises a substrate and a plurality of chip particles formed on the substrate, wherein the width of the cutting path between adjacent chip particles is W, and the length A of the chip particles arranged horizontally along the substrate is smaller than the width B of the chip particles arranged vertically along the substrate, so that the chip particles are arranged horizontally in X columns and vertically in Y rows on the substrate, and in the vertical columns of the substrate, reserved areas for a plurality of chip particles are spaced apart, and the reserved areas are referred to as blank chip particles, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting path widths of the chip particles on the substrate at least adjacent to the center point of the substrate and 1 is less than or equal to a preset value.
2. The wafer structure for reducing wafer stress as claimed in claim 1, characterized in that: The blank chip particles are arranged in rows to form a plurality of blank particle rows, and a plurality of blank particle rows are spaced apart.
3. The wafer structure for reducing wafer stress as claimed in claim 2, characterized in that: In a longitudinal column of the substrate passing through or near the center point of the substrate, a reserved area of a chip particle is vacated in every N chip particles to form a blank chip particle; there are at least N / 3 chip particles between two adjacent rows of blank chip particles.
4. The wafer structure for reducing wafer stress as claimed in claim 3, characterized in that: The blank particle rows are arranged at equal intervals, so that there are N-1 chip particles between two adjacent rows of blank chip particles.
5. The wafer structure for reducing wafer stress as claimed in claim 3, characterized in that: N is The nearest integer.
6. A chip particle arrangement mask design method for reducing wafer stress, characterized in that: Set the layout of chip particles on the substrate: According to the size of the substrate, the number of chip particles arranged with a cutting line width of W is designed on the substrate, and the chip particles are arranged in X columns horizontally and Y rows vertically on the substrate, and the length A of the chip particles arranged horizontally along the substrate is less than the width B of the chip particles arranged vertically along the substrate; In the longitudinal column of the substrate, a number of reserved areas for chip particles are spaced apart, and the reserved areas are called blank chip particles, so that the absolute value of the difference between the ratio of the longitudinal and transverse cutting road widths of the chip particles on the substrate at least adjacent to the center point of the substrate and 1 is less than or equal to a preset value.
7. The chip particle arrangement mask design method according to claim 6, characterized in that: In a longitudinal column closest to the center point of the substrate on the substrate, a plurality of chip particles are spaced apart to provide a plurality of blank chip particles, so that the absolute value of the difference between the longitudinal and transverse cutting road widths of the chip particles in the longitudinal column closest to the center point of the substrate and 1 is less than or equal to a preset value; For the remaining longitudinal columns, the chip particles in the row where the blank chip particles are located are all vacated to set blank core particles, so that all the blank chip particles are arranged in rows to form a number of blank particle rows, and the spacing between the blank particle rows is set.
8. The chip particle arrangement mask design method according to claim 6, characterized in that: In a longitudinal column of the substrate passing through or near the center point of the substrate, a reserved area of a chip particle is vacated in every N chip particles to form a blank chip particle; there are at least N / 3 chip particles between two adjacent rows of blank chip particles.
9. The chip particle arrangement mask design method according to claim 8, characterized in that: The blank particle rows are arranged at equal intervals, so that there are N-1 chip particles between two adjacent rows of blank chip particles.
10. The chip particle arrangement mask design method according to claim 8, characterized in that: N is The nearest integer.