Efficient system-on-chip power delivery with adaptive voltage margin control

Abstract

Systems and methods related to efficient system-on-chip (SoC) power delivery with adaptive voltage margin control are described. A method for adaptively controlling a voltage margin of a system includes independently adjusting an operating frequency of a respective core clock signal in response to detecting a margin violation by a per-core voltage regulator margin monitor or a voltage drop by a per-core drop detector. The method further includes, in response to a predetermined criterion being satisfied: (1) reducing an operating frequency of the respective core clock signal, (2) monitoring a margin violation event and a fall event at the reduced operating frequency, and (3) if the monitored margin violation event or the monitored fall event continues to satisfy the predetermined criterion, determining that the core clock signal is in a non-normal operation state, and if the monitored margin violation event or the monitored fall event continues to satisfy the predetermined criterion, determining that the core clock signal is in a non-normal operation state. If so, a voltage set point associated with the motherboard voltage regulator is changed to a second voltage set point corresponding to the higher voltage.

Description

Background Art

[0001] A power delivery device for a system-on-chip (SoC) device includes a voltage regulator (e.g., a motherboard voltage regulator) for providing power to transistors or other semiconductor devices in the SoC device. Practical physical limitations and cost optimization requirements impose low limits on the resistance between the motherboard voltage regulator and the SoC transistors. Conventional power delivery devices attempt to ensure sufficient voltage margin for the entire SoC load current and current transient range at the transistor level. The conventional method of ensuring sufficient voltage margin at the transistor level is to set the voltage regulator voltage high enough to ensure that the minimum voltage requirement is not violated under any load. Although such conventional power delivery devices can ensure sufficient voltage margin, setting the voltage regulator to provide a high enough voltage to not violate the minimum voltage requirement under any load will result in avoidable power losses.

[0002] Therefore, there is a need for improved SoC power delivery systems and methods. Summary of the invention

[0003] In one example, the present disclosure relates to a system including a system on a chip (SoC) including a plurality of cores. The system may also include a voltage regulator module (VRM) configured to provide an input voltage to each of per-core voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core voltage regulators is configured to provide an output voltage to a corresponding core among the plurality of cores. The system may also include an adaptive voltage headroom control device including: (1) a voltage controller for controlling a voltage set point associated with the VRM, (2) a per-core voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control a frequency of a core clock signal for a corresponding core among the plurality of cores.

[0004] The adaptive voltage headroom control device can be configured to independently adjust the operating frequency of the corresponding core clock signal in response to a headroom violation detected by the per-core voltage regulator headroom monitor or in response to a voltage droop detected by the per-core droop detector. The adaptive voltage headroom control device can also be configured to, in response to a headroom violation event or a droop event satisfying a predetermined criterion: (1) reduce the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitor the headroom violation event and the droop event at the lower operating frequency, and (3) if the monitored headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the lower operating frequency, change the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

[0005] In another example, the present disclosure is directed to a method for adaptively controlling voltage headroom of a system, the system comprising: (1) a system on chip (SoC) comprising a plurality of cores, and (2) a voltage regulator module (VRM), the VRM configured to provide an input voltage to each of per-core voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core voltage regulators is configured to provide an output voltage to a corresponding core in the plurality of cores. The method may include, in response to detecting a headroom violation by a per-core voltage regulator headroom monitor or in response to detecting a voltage droop by a per-core droop detector, independently adjusting an operating frequency of a corresponding core clock signal.

[0006] The method may also include, in response to a margin violation event or a droop event satisfying predetermined criteria: (1) reducing the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitoring the margin violation event and the droop event at the lower operating frequency, and (3) if the margin violation event or the monitored droop event continues to satisfy the predetermined criteria even at the lower operating frequency, changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

[0007] In another example, the present disclosure relates to a system including a system on chip (SoC) including a plurality of cores. The system may also include a voltage regulator module (VRM) configured to provide an input voltage to each of a per-core low dropout (LDO) voltage regulator in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core LDO voltage regulators is configured to provide an output voltage to a corresponding core among the plurality of cores. The system may also include an adaptive voltage headroom control device including: (1) a voltage controller for controlling a voltage set point associated with the VRM, (2) a per-core LDO voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control the frequency of a core clock signal for a corresponding core among the plurality of cores.

[0008] The adaptive voltage headroom control device can be configured to independently adjust the operating frequency of the corresponding core clock signal in response to a headroom violation detected by the per-core LDO voltage regulator headroom monitor or in response to a voltage droop detected by the per-core droop detector. The adaptive voltage headroom control device can also be configured to, in response to the headroom violation event or the droop event satisfying a predetermined criterion: (1) reduce the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitor the headroom violation event and the droop event at the lower operating frequency, and (3) if the headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the lower operating frequency, change the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

[0009] This summary is provided to introduce a series of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals designate similar elements. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0011] Figure 1 shows a voltage regulator set point (VR SET POINT ) is set in conservative VR SET POINT Schematic diagram of power loss at ;

[0012] Figure 2 shows a voltage regulator set point (VR SET POINT ) is set in VR with conservative SET POINT Compared to lower VR SET POINT A schematic diagram of the power saved when

[0013] Figure 3 shows a block diagram of a system including various components for implementing adaptive voltage headroom control according to one example;

[0014] Figure 4 According to an example, Figure 3 A block diagram of a drop detector for use with a system;

[0015] Figure 5shows the effect of adaptive clock control according to one example; and

[0016] Figure 6 A flow chart of a method for adaptively controlling voltage margin of a system according to an example is shown. DETAILED DESCRIPTION

[0017] Examples described in the present disclosure relate to efficient system-on-chip (SoC) power delivery with adaptive voltage headroom control. As explained above, conventional power delivery devices attempt to guarantee sufficient voltage headroom at the transistor level for the entire SoC load current and current transient range. In other words, the conventional method of guaranteeing sufficient voltage headroom at the transistor level is to set the voltage regulator voltage high enough so that the minimum voltage requirement is not violated at any load. Although such conventional power delivery devices can guarantee sufficient voltage headroom, setting the voltage regulator to provide a high enough voltage so that the minimum voltage requirement is not violated at any load can result in avoidable power losses.

[0018] Although the reduction of the voltage guard band allows a large amount of power to be saved, it also creates an undervoltage condition when the system-on-chip (SoC) current consumption is unpredictable and increases rapidly. In this case, the voltage on the SoC side can immediately drop below the minimum allowed level and cause a potential SoC failure. In order to address this potential SoC failure, additional mechanisms are established to ensure the safe operation of the SoC in such an event. Example mechanisms include distributed per-voltage regulator margin monitors and drop detectors, per-core adaptive clock control plans, per-core performance monitors that record drop and margin violation events, alarm systems, and voltage controllers that close control loops. The distributed adaptive clock control plan described herein allows independent fast frequency adjustments to the affected cores in response to low-dropout (LDO) regulator input voltage margin violation events or LDO regulator output voltage drop events. Fast detectors with voltage change rate sensitivity trigger frequency adjustments, which result in reduced drops and prevent violations of the core frequency voltage operating point. Detected events are recorded and reported to the motherboard voltage regulator (MBVR) voltage controller, which adjusts the MBVR set point to reduce the probability of such events occurring again.

[0019] Figure 1 shows that when the voltage regulator set point (VR SET POINT ) is set in conservative VR SET POINT100 is a diagram of power loss when the voltage is 0. The vertical axis of the graph 100 represents voltage, and the horizontal axis represents current (e.g., the current drawn by the system on chip (SoC)). In this example, curve 110 represents the input voltage to a regulator (e.g., a low dropout (LDO) regulator), and curve 120 represents the output voltage of the regulator (e.g., the LDO regulator). In this example, I TDP corresponds to the current drawn by the SoC at the thermal design power point. This current corresponds to the maximum amount of current that the SoC can draw given cooling constraints related to how hot the SoC gets as the current draw increases. In this example, I PEAK Corresponding to the peak current that the SoC can draw. As shown in Figure 100, as the current drawn by the SoC increases, the output voltage of the regulator (represented by curve 120) decreases. In order to ensure that the output voltage of the regulator never drops to the peak current (I PEAK ) required minimum voltage (V MIN ), the regulator is configured so that curve 110 (corresponding to the input voltage of the regulator) and curve 120 (corresponding to the output voltage of the regulator) intersect at point 122 shown in graph 100. This ensures that the margin (the difference between the input voltage of the regulator and the output voltage of the regulator) is equal to or greater than zero (e.g., a difference of a few millivolts) at point 122. However, ensuring the margin according to graph 100 results in a power penalty 140 relative to the actual computational power 150 used by the SoC. In this case, the power penalty 140 is a conservative VR SET POINT The voltage minus the peak current (I PEAK ) required minimum voltage (V MIN ) multiplied by the current drawn by the SoC.

[0020] Figure 2 shows that when the voltage regulator set point (VR SET POINT ) is set in VR with conservative SET POINT Compared to lower VR SET POINT 100, in this diagram 200, the vertical axis represents voltage and the horizontal axis represents current (e.g., the current drawn by the system on chip (SoC)). In this example, curve 210 represents the input voltage to a regulator (e.g., a low dropout (LDO) regulator) and curve 220 represents the output voltage of the regulator (e.g., the LDO regulator). In this example, similar to reference Figure 1 As described, I TDPcorresponds to the current drawn by the SoC at the thermal design power point. This current corresponds to the maximum amount of current that the SoC can draw given cooling constraints related to how hot the SoC gets as the current draw increases. In this example, I PEAK Corresponding to the peak current that the SoC can draw. As shown in graph 200, as the current drawn by the SoC increases, the output voltage of the regulator (represented by curve 220) decreases. In this example, the set point of the voltage regulator does not guarantee that the output voltage of the regulator will never drop to the peak current (I PEAK ) required minimum voltage (V MIN )the following.

[0021] Continue to refer Figure 2 , unlike the regulator configuration in which curve 110 (corresponding to the regulator input voltage) and curve 120 (corresponding to the regulator output voltage) intersect at point 122, in this regulator configuration, curve 230 (corresponding to the reduced regulator input voltage) and curve 220 (corresponding to the regulator output voltage) intersect at point 222. This means that at point 222, the margin (the difference between the regulator input voltage and the regulator output voltage) is guaranteed to be equal to or greater than zero (e.g., a difference of a few millivolts). However, the margin set according to diagram 200 results in a reduction in power loss 240 relative to the actual computing power 250 used by the SoC. This advantageously saves power 260. In the present disclosure, compared with the conservative VR SET POINT Compared to the lower VR SET POINT Tuned to dynamically reduce SoC voltage to a conservative VR SET POINT By monitoring the actual short-term average SoC current, a less conservative voltage regulator set point is used that is sufficient to achieve optimal performance operation of the SoC in normal operating conditions. In rare cases, when a reduced VR set point (e.g., Figure 2 The lower VR shown in SET POINT ) is insufficient, a distributed sag mitigation mechanism and an adaptive clock control mechanism are used to prevent failures due to voltage sag.

[0022] Figure 3A block diagram of a system 300 including various components for implementing adaptive voltage headroom control according to one example is shown. The system 300 may include a motherboard voltage regulator (MBVR 302) coupled to a system on chip (SoC) 304. The MBVR 302 may be a voltage regulator configured to provide voltage to a plurality of voltage regulators, such as low dropout (LDO) regulators associated with various processing units of the SoC 304. In this example, the MBVR 302 may be configured to provide LDO_VDD as an input voltage to various LDOs included as part of the SoC 304.

[0023] Continue to refer Figure 3 , SoC 304 may include multiple processing units (e.g., central processing units (CPUs) or portions thereof), including, for example, processing units 310, 340, 350, and 360. In this example, each processing unit may include a core. As an example, processing unit 310 may include core 312. Each core may have a corresponding LDO. As an example, core 312 may have a corresponding LDO 314, which is configured to provide CORE_VDD as an input voltage to core 312. Each core may also have a corresponding core phase-locked loop (PLL) and a frequency controller associated with the core PLL. As an example, core 312 may have a corresponding core PLL 316 and a corresponding frequency controller 318. Each core may also have a corresponding drop detector and a margin monitor. As an example, core 312 may have a corresponding drop detector 320 and a corresponding margin monitor 330.

[0024] Still reference Figure 3, the core PLL 316 can be implemented as a phase-locked loop that is configured to output a clock signal (e.g., a CORE_CLK signal) for the core 312. The core PLL 316 can provide functions associated with a PLL for clocking the core, including clock division or multiplication, and using a feedback loop to ensure that the output clock is closely aligned with the reference clock. The frequency controller 318 can include dynamic voltage frequency (DVFS) control logic. The DVFS control logic can be configured to receive an output indicating the detection of a drop from the drop detector 320, and dynamically compensate for the detected drop. In one example, the DVFS control logic corresponding to the frequency controller 318 can operate in accordance with a core voltage ID corresponding to the frequency at which the core needs to operate. Because the core can operate at different frequencies, there may be multiple core voltage IDs corresponding to different clock frequencies. The DVFS control logic can also track the adaptive voltage clock ID of each core. For a given core voltage ID, the adaptive voltage clock ID corresponds to a voltage within a selected increment of the voltage specified by the core voltage ID. The increment itself can be set to only a few millivolts. The droop detector 320 may be configured to detect a difference between a voltage corresponding to a given core voltage ID and a corresponding adaptive voltage clock ID. A difference that meets or exceeds a threshold may result in a droop detection event.

[0025] Reference now Figure 4 , is based on an example for Figure 3 The droop detector 400 is a block diagram of a droop detector for use with a system. The droop detector 400 can be configured to compare a core voltage (eg, CORE_VDD) with a voltage reference (V REF ) for comparison. The voltage reference may involve a voltage that can be compared to the core voltage to determine the amount of the drop. The voltage reference may be generated by converting a digital value to an analog value using a digital-to-analog converter (DAC). As previously explained, the voltage reference may be a voltage corresponding to the adaptive clock ID, and the core voltage may be a voltage corresponding to the core voltage ID. The comparator 420 may compare the two voltages and generate a signal that may be sampled using sampling logic 430. The sampling logic 430 may be clock controlled, which allows the comparator output to be sampled over several clock cycles as desired. Based on the sampled output of the comparator 420, the drop detector 400 generates a drop detection signal. As previously explained, Figure 3 The frequency controller 318 may receive the drop detection signals and respond to them. Figure 4 The drop detector 400 is shown as including a certain number of components arranged in a certain manner, but the drop detector 400 may include additional or fewer components arranged in a different manner.

[0026] Return to reference Figure 3 , each core may also include a margin monitor for each LDO. As an example, Figure 3 A margin monitor 330 of LDO 314 is shown. As described above, margin refers to the difference between the input voltage of a regulator (e.g., LDO 314) and the output voltage of the regulator. The margin monitor 330 can be configured to detect the difference between the input voltage (e.g., LDO_VDD) and the output voltage of the LDO (e.g., CORE_VDD). The margin monitor 330 can be configured so that when the difference between the input voltage to the LDO and the output voltage of the LDO is equal to or lower than a threshold (e.g., a threshold of a few millivolts), a signal indicating a margin event is generated. The margin event signal can be provided to the frequency controller 318 and the MBVR voltage controller 380. The frequency controller 318 can respond to the margin event signal independently of the descent detected by the descent detector, and vice versa. As an example, once the margin event signal is generated, the frequency controller 318 can take actions related to adaptive control. In one example, any violation of the margin can result in a change in clock frequency, a change in core voltage, or another remedial action.

[0027] Figure 5 The effect of adaptive clock control according to an example is shown. As explained above, the system 300 is configured to implement adaptive clock control per core in response to margin event signals or drop detection signals that are independent of each other. In one example, the fast response aspect of the adaptive voltage margin response mechanism can be implemented as a combination of a frequency controller 318 and a margin monitor 330. In one example, the drop response mechanism can be implemented as a combination of a frequency controller 318 and a drop detector 320. In this example, the control device can reduce the core clock frequency by a certain percentage of the operating frequency by shielding the alternating high phases of the core clock. This helps stop the drop and restore the core voltage because reducing the effective clock frequency reduces the current draw. The control device can continue to shield the core clock, which allows the core voltage to recover. When the voltage is fully restored, the control device can restore the core performance by raising the frequency to the original value. By gradually increasing the number of unshielded high phases, the frequency recovery process can be performed in a smooth (graceful) manner, thereby avoiding any subsequent decline. In addition, other mechanisms can be used to perform frequency reduction and recovery.

[0028] Continue to refer Figure 5, waveform 510 shows the core clock signal without adaptive clock control (e.g., without the effect of the adaptive voltage headroom response mechanism or the droop response mechanism). Waveform 540 shows the core clock signal with adaptive clock control. Waveform 540 shows the effect of masking the core clock signal in response to detecting a droop. Curve 512 shows the core current without adaptive clock control, and curve 514 shows the core voltage without adaptive clock control. Figure 5 As shown, without adaptive clock control, after N core clock cycles, the core current is maximized and does not rise any further. In the case of a falling event (e.g., when the voltage drops from V SET Change to V SET –ΔV), in the absence of adaptive clock control, the core voltage drops and does not recover until later. Curve 542 shows the core current with adaptive clock control, and curve 544 shows the core voltage with adaptive clock control. Figure 5 As shown, with additional synchronization delay ( Figure 5 After the EXTRA SYNC DELAY in Figure 5 At the DROOP DETECTED time in the DROOP DETECTED time, clock masking is initiated ( Figure 5 In one example, clock masking is performed by Figure 3 The frequency controller 318 implements this by applying a mask to selected high phases of the core clock signal. Applying the mask (e.g., mask 11111010101010 . . . ) generates a waveform 540 that corresponds to the core clock signal with adaptive clock control. Figure 5 As shown, masking is used in such a way that the clock recovery is smooth rather than abrupt. As an example, to ensure a smooth response, masking is selected in such a way that the core current increases gradually (e.g., as Figure 5 542 in FIG. 54). Masking ensures that initially only some of the high phases of the clock signal are demasked, and the number of high phases of the clock signal that are demasked increases slowly. As an example, after N' core clock cycles, the high phases of the clock signal are demasked in a controlled and gradual manner. This prevents further drops that may occur when the current increases rapidly (e.g., as shown by curve 514 in response to the sharp increase in current shown by curve 512).

[0029] Return to reference Figure 3, the SoC 304 may also include an MBVR voltage controller 380. The MBVR voltage controller 380 may be configured to keep a count of each droop event and margin violation event within a certain time window. If the number of droop events and / or margin violation events exceeds a set threshold (each type of event may have a different threshold), it provides an indication to the MBVR voltage controller 380 that the current performance level cannot be maintained by the power delivery configuration. Continuous droops can have a negative impact on performance because each droop event causes the frequency to be reduced by a selected percentage. The MBVR voltage controller 380 continues to monitor and keep track of droop events or margin violation events and can respond in two ways: (1) reduce the core clock frequency by a small amount (2-5 percent of the operating frequency) for a certain duration, and / or (2) increase the on-die and / or off-die voltage regulator output voltage to increase the voltage margin, thereby reducing the likelihood of another droop event or margin violation event occurring.

[0030] By reducing the frequency and monitoring the droop behavior after reducing the frequency, the adaptive voltage headroom control finds the maximum sustained performance level without causing additional droop events that result in performance loss. The adaptive voltage headroom control can also use this knowledge to adapt the setting. By increasing the input voltage, the adaptive voltage headroom control can provide additional voltage margin to maintain a higher rate of current change. This reduces the impact on performance of reducing the clock frequency due to voltage droop. Once the system operates in this state for a set duration, the adaptive voltage headroom control attempts to restore the energy efficiency of the system by increasing the frequency or reducing the headroom of the voltage regulator. Although Figure 3 System 300 is shown as including a certain number of components arranged and coupled in a certain manner, but system 300 may include fewer or additional components arranged and coupled in a different manner.

[0031] Figure 6 A flowchart 600 of a method for adaptively controlling voltage margin according to an example is shown. In this example, the method corresponding to flowchart 600 can be performed as part of a system including: (1) a system on a chip (SoC) including a plurality of cores, and (2) a voltage regulator module (VRM) configured to provide an input voltage to each of per-core voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core voltage regulators is configured to provide an output voltage to a corresponding core in the plurality of cores. In one example, the method can be performed using Figure 3 The various components of the system 300 are used to perform the method. Figure 3MBVR 302 may perform the function of a voltage regulator module (VRM) and provide input voltage to the SoC. Step 610 may include independently adjusting the operating frequency of the corresponding core clock signal in response to a margin violation detected by a per-core voltage regulator margin monitor or a voltage drop detected by a per-core drop detector. As part of this step, as described above with respect to Figure 3-5 As explained, the margin monitor (e.g. Figure 3 A margin monitor 330) can detect margin violations. In addition, as part of this step, as described above with respect to Figure 3-5 As explained, a drop detector (e.g. Figure 3 The voltage drop detector 320 can detect the voltage drop. Figure 3 As depicted, system 300 includes a per-core headroom monitor and a per-core degradation detector.

[0032] Continue to refer Figure 6 , step 620 may include, in response to the margin violation event or the droop event satisfying a predetermined criterion: (1) reducing the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitoring the margin violation event and the droop event at the lower operating frequency, and (3) if the monitored margin violation event or the monitored droop event continues to satisfy the predetermined criterion even at the lower operating frequency, changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage. As explained above, including Figure 3 The adaptive headroom voltage control device of the MBVR voltage controller 380 may be configured to set the voltage regulator module (e.g., Figure 3 MBVR 302) and perform these steps. As an example, Figure 3 The MBVR voltage controller 380 may keep a count of each droop event and margin violation event within a certain time window. If the number of droop events and / or margin violation events exceeds a set threshold (each type of event may have a different threshold), it provides an indication to the MBVR voltage controller 380 that the current performance level cannot be maintained by the power delivery configuration. Figure 3-5 As explained, the adaptive headroom voltage control device including the MBVR voltage controller 380 can change the voltage regulator module (e.g., Figure 3 The voltage set point associated with the MBVR302). Figure 6 A certain number of steps are shown performed in a certain order, but additional or fewer steps may be performed in a different order as part of flowchart 600 .

[0033] In summary, the present disclosure relates to a system including a system on a chip (SoC) including a plurality of cores. The system may also include a voltage regulator module (VRM) configured to provide an input voltage to each of per-core voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core voltage regulators is configured to provide an output voltage to a corresponding core among the plurality of cores. The system may also include an adaptive voltage headroom control device including: (1) a voltage controller for controlling a voltage set point associated with the VRM, (2) a per-core voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control the frequency of a core clock signal for a corresponding core among the plurality of cores.

[0034] The adaptive voltage margin control device can be configured to independently adjust the operating frequency of the corresponding core clock signal in response to a margin violation detected by the per-core voltage regulator margin monitor or a voltage droop detected by the per-core droop detector. The adaptive voltage margin control device can also be configured to, in response to the margin violation event or the droop event satisfying a predetermined criterion: (1) reduce the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitor the margin violation event and the droop event at the lower operating frequency, and (3) if the margin violation event or the monitored droop event continues to satisfy the predetermined criterion even at the lower operating frequency, change the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

[0035] Each of the per-core voltage regulators may include a low dropout (LDO) regulator, and the margin violation event may correspond to a margin violation associated with the corresponding LDO regulator. Each of the per-core voltage regulators may include a low dropout (LDO) regulator, and the voltage droop event may correspond to a droop associated with an output voltage of the corresponding LDO regulator.

[0036] The adaptive voltage headroom control means may be configured to independently adjust the frequency of the respective core clock signals by masking the respective core clock signals. The adaptive voltage headroom control means may also be configured to, after changing the voltage set point associated with the VRM to a second voltage set point associated with the VRM, increase the operating frequency of one or more respective core clock signals if the system has been operated during a predetermined duration.

[0037] The adaptive voltage headroom control device may also be configured to, after changing the voltage set point associated with the VRM to a second voltage set point associated with the VRM, reduce the headroom associated with one or more per-core voltage regulators if the system has been operated during a predetermined duration. The per-core frequency controller may also be configured to monitor the corresponding core voltage and increase the adjusted operating frequency of the corresponding core clock signal to the original frequency once the corresponding core voltage recovers from the voltage drop.

[0038] In another example, the present disclosure is directed to a method for adaptively controlling voltage headroom of a system, the system comprising: (1) a system on chip (SoC) comprising a plurality of cores, and (2) a voltage regulator module (VRM), the VRM configured to provide an input voltage to each of per-core voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core voltage regulators is configured to provide an output voltage to a corresponding core in the plurality of cores. The method may include, in response to detecting a headroom violation by a per-core voltage regulator headroom monitor or detecting a voltage droop by a per-core droop detector, independently adjusting an operating frequency of a corresponding core clock signal.

[0039] The method may also include, in response to a margin violation event or a droop event satisfying predetermined criteria: (1) reducing the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitoring the margin violation event and the droop event at the lower operating frequency, and (3) if the margin violation event or the monitored droop event continues to satisfy the predetermined criteria even at the lower operating frequency, changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

[0040] Each of the per-core voltage regulators may include a low dropout (LDO) regulator, and the margin violation event may correspond to a margin violation associated with the corresponding LDO regulator. Each of the per-core voltage regulators may include a low dropout (LDO) regulator, and the voltage droop event may correspond to a droop associated with an output voltage of the corresponding LDO regulator.

[0041] Independently adjusting the frequency of the corresponding core clock signal may include masking the corresponding core clock signal. The method may also include, after changing the voltage set point associated with the VRM to a second voltage set point associated with the VRM, while the system has been operated during a predetermined duration, increasing the operating frequency of one or more corresponding core clock signals. The method may also include, after changing the voltage set point associated with the VRM to a second voltage set point associated with the VRM, while the system has been operated during a predetermined duration, reducing the margin associated with one or more per-core voltage regulators. The method may also include monitoring the corresponding core voltage and, once the corresponding core voltage recovers from a voltage drop, increasing the adjusted operating frequency of the corresponding core clock signal to the original frequency.

[0042] In another example, the present disclosure relates to a system including a system on chip (SoC) including a plurality of cores. The system may also include a voltage regulator module (VRM) configured to provide an input voltage to each of a per-core low dropout (LDO) voltage regulator in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core low dropout (LDO) voltage regulators is configured to provide an output voltage to a corresponding core among the plurality of cores. The system may also include an adaptive voltage headroom control device including: (1) a voltage controller for controlling a voltage set point associated with the VRM, (2) a per-core LDO voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control the frequency of a core clock signal for a corresponding core among the plurality of cores.

[0043] The adaptive voltage headroom control device can be configured to independently adjust the operating frequency of the corresponding core clock signal in response to a headroom violation detected by the per-core LDO voltage regulator headroom monitor or a voltage droop detected by the per-core droop detector. The adaptive voltage headroom control device can also be configured to, in response to the headroom violation event or the droop event satisfying a predetermined criterion: (1) reduce the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitor the headroom violation event and the droop event at the lower operating frequency, and (3) if the headroom violation event or the monitored droop event continues to satisfy the predetermined criterion even at the lower operating frequency, change the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

[0044] The headroom violation event may correspond to a headroom violation associated with the corresponding LDO regulator. The voltage drop event may correspond to a drop associated with an output voltage of the corresponding LDO regulator. The adaptive voltage headroom control device may also be configured to independently adjust the frequency of the corresponding core clock signal by masking the corresponding core clock signal.

[0045] The adaptive voltage headroom control device may also be configured to, after changing the voltage set point associated with the VRM to a second voltage set point associated with the VRM, increase the operating frequency of one or more corresponding core clock signals if the system has been operated during a predetermined duration. The adaptive voltage headroom control device may also be configured to, after changing the voltage set point associated with the VRM to a second voltage set point associated with the VRM, decrease the headroom associated with one or more per-core LDO voltage regulators if the system has been operated during a predetermined duration.

[0046] It should be understood that the systems, services, devices, methods, terminals, and components described herein are only examples. Alternatively or additionally, the functions described herein may be performed at least in part by one or more hardware logic components. For example, the types of exemplary hardware logic components that can be used include FPGA, ASIC, application specific standard product (ASSP), system on chip (SoC), complex programmable logic device (CPLD). In an abstract but still clear sense, the arrangement of any components that implement the same function is effectively "associated", thereby achieving the desired function. Therefore, any two components combined to achieve a specific function herein can be regarded as "associated" with each other, thereby achieving the desired function, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be regarded as "operably connected" or "coupled" to each other to achieve the desired function. Just because a component that can be any other implementation of a device, structure, equipment, system, or function is described as being coupled to another component in this article, it does not mean that these components must be separate components. As an example, a component A described as being coupled to another component B can be a subcomponent of component B, component B can be a subcomponent of component A, or component A and component B can be subcomponents of a combination of another component C.

[0047] Functions associated with some of the examples described in this disclosure may also include instructions stored in non-transient media. The term "non-transient media" used herein refers to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Exemplary non-transient media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, disks or tapes, optical disks or optical tapes, flash memory, EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory, such as DRAM, SRAM, cache, or other such media. Non-transient media are different from transmission media, but can be used in conjunction with transmission media. Transmission media are used to transmit data and / or instructions from / to a machine. Exemplary transmission media include coaxial cables, fiber optic cables, copper wires, and wireless media (such as radio waves).

[0048] In addition, those skilled in the art will recognize that the boundaries between the functions of the operations described above are merely illustrative. The functions of multiple operations can be combined into a single operation, and / or the functions of a single operation can be distributed in additional operations. In addition, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments.

[0049] Although the present disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the following claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems described herein with respect to specific examples are not intended to be construed as key, essential, or essential features or elements of any or all claims.

[0050] In addition, the terms "a" or "an" as used herein are defined as one or more. Likewise, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an". The same is true for the use of definite articles.

[0051] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between elements such as these terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other prioritization of these elements.

Claims

1. A system comprising: System-on-chip (SoC) including multiple cores; a voltage regulator module (VRM) configured to provide an input voltage to each of per-core voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core voltage regulators is configured to provide an output voltage to a corresponding core among the plurality of cores; as well as An adaptive voltage headroom control apparatus comprising: (1) a voltage controller for controlling the voltage set point associated with the VRM, (2) a per-core voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control the frequency of a core clock signal for a corresponding core among the plurality of cores, wherein the adaptive voltage headroom control apparatus is configured to: In response to detecting a margin violation by the per-core voltage regulator margin monitor or in response to detecting a voltage droop by the per-core droop detector, independently adjusting an operating frequency of a corresponding core clock signal, and In response to a margin violation event or a falling event satisfying predetermined criteria: (1) reducing the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitoring margin violation events and falling events at the lower operating frequency, and (3) if the monitored margin violation events or the monitored falling events continue to satisfy the predetermined criteria even at the lower operating frequency, changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

2. The system of claim 1, wherein each of the per-core voltage regulators comprises a low dropout (LDO) regulator, and wherein the margin violation event corresponds to a margin violation associated with the corresponding LDO regulator.

3. The system of claim 1, wherein each of the per-core voltage regulators comprises a low dropout (LDO) regulator, and wherein the voltage drop event corresponds to a drop associated with an output voltage of a corresponding LDO regulator. 4 . The system of claim 1 , wherein the adaptive voltage headroom control device is configured to independently adjust the frequency of the corresponding core clock signal by masking the corresponding core clock signal.

5. The system of claim 1 , wherein the adaptive voltage margin control device is further configured to, after changing the voltage set point associated with the VRM to the second voltage set point associated with the VRM, increase the operating frequency of one or more corresponding core clock signals if the system has been operated during a predetermined duration.

6. The system of claim 1 , wherein the adaptive voltage headroom control device is further configured to reduce a headroom associated with one or more per-core voltage regulators after changing the voltage set point associated with the VRM to the second voltage set point associated with the VRM, if the system has been operated for a predetermined duration.

7. The system of claim 1, wherein the per-core frequency controller is further configured to monitor a corresponding core voltage and increase the adjusted operating frequency of the corresponding core clock signal to an original frequency once the corresponding core voltage has recovered from the voltage drop.

8. A method for adaptively controlling voltage margin for a system, comprising: (1) a system on chip (SoC) including a plurality of cores, and (2) a voltage regulator module (VRM), the VRM being configured to provide an input voltage to each of per-core voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core voltage regulators is configured to provide an output voltage to a corresponding core among the plurality of cores, the method comprising: In response to detecting a margin violation by a per-core voltage regulator margin monitor, or in response to detecting a voltage droop by a per-core droop detector, independently adjusting an operating frequency of a corresponding core clock signal; and In response to a margin violation event or a falling event satisfying predetermined criteria: (1) reducing the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitoring margin violation events and falling events at the lower operating frequency, and (3) if the monitored margin violation events or the monitored falling events continue to satisfy the predetermined criteria even at the lower operating frequency, changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

9. The method of claim 8, wherein each of the per-core voltage regulators comprises a low dropout (LDO) regulator, and wherein the margin violation event corresponds to a margin violation associated with the corresponding LDO regulator.

10. The method of claim 8, wherein each of the per-core voltage regulators comprises a low dropout (LDO) regulator, and wherein the voltage drop event corresponds to a drop associated with an output voltage of a corresponding LDO regulator. The method of claim 8 , wherein independently adjusting the frequencies of the respective core clock signals comprises masking the respective core clock signals.

12. The method according to claim 8, further comprising: After changing the voltage set point associated with the VRM to the second voltage set point associated with the VRM, an operating frequency of one or more corresponding core clock signals is increased while the system has been operated during a predetermined duration.

13. The method according to claim 8, further comprising: After changing the voltage set point associated with the VRM to the second voltage set point associated with the VRM, a headroom associated with one or more per-core voltage regulators is reduced if the system has been operated during a predetermined duration.

14. The method of claim 8, further comprising monitoring a corresponding core voltage and increasing the adjusted operating frequency of the corresponding core clock signal to the original frequency once the corresponding core voltage has recovered from the voltage drop.

15. A system comprising: System-on-chip (SoC) including multiple cores; a voltage regulator module (VRM) configured to provide an input voltage to each of per-core low dropout (LDO) voltage regulators in the SoC based on a voltage set point associated with the VRM, wherein each of the per-core LDO voltage regulators is configured to provide an output voltage to a corresponding core among the plurality of cores; as well as An adaptive voltage headroom control device, comprising: (1) a voltage controller for controlling the voltage set point associated with the VRM, (2) a per-core LDO voltage regulator headroom monitor, (3) a per-core droop detector, and (4) a per-core frequency controller configured to control the frequency of a core clock signal for a corresponding core among the plurality of cores, wherein the adaptive voltage headroom control device is configured to: In response to detecting a margin violation by the per-core LDO voltage regulator margin monitor or in response to detecting a voltage droop by the per-core droop detector, independently adjusting an operating frequency of a corresponding core clock signal, and In response to a margin violation event or a falling event satisfying predetermined criteria: (1) reducing the operating frequency of the corresponding core clock signal to a lower operating frequency, (2) monitoring margin violation events and falling events at the lower operating frequency, and (3) if the monitored margin violation events or the monitored falling events continue to satisfy the predetermined criteria even at the lower operating frequency, changing the voltage set point associated with the VRM to a second voltage set point corresponding to a higher voltage.

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