Cross array to implement truth tables

Abstract

A method for preparing a trained crossover array of a neural network is provided. The method includes feeding an input portion of a predetermined truth table into a computer simulation of the cross-over array, and generating analog output values for the input portion of the truth table based on the simulation weights. The method further includes calculating a loss value from each of the analog output value and the desired value of the output portion of the truth table, and adjusting the simulation weight based on the calculated loss values. The method further includes re-sending the input portion of the predetermined truth table into the computer for simulation and re-calculating the output value using the adjusted simulation weight until the simulated output value produces a desired value of the truth table output portion within a predetermined error amplitude.

Description

Technical Field

[0001] The present invention generally relates to the use of crossbar arrays and neural networks to implement complex truth tables, and more particularly to implementing crossbar arrays and neural networks to replace field programmable gate arrays (FPGAs) to provide complex truth tables and additional neural network functionality. Background Art

[0002] One way to design combinational logic circuits is to interconnect logic gates, but digital logic circuits constructed using discrete logic gates have fixed functions that are defined at the time of manufacturing. A Field Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the customer after manufacturing. An FPGA contains an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together. Before an FPGA can be used, it will be programmed to implement the desired functionality. A Programmable Logic Array (PLA) is a programmable logic device used to implement combinational logic circuits. FPGAs can be used to develop deep neural networks.

[0003] Combinational logic circuits are constructed from basic logic NAND, NOR, or NOT gates that are "combined" or connected together to create more complex switching circuits. These logic gates are the building blocks of combinatorial logic circuits that comprise FPGAs.

[0004] A truth table is a mathematical table used in logic in which each input variable has its own column and each output variable has its own column, with the output column showing the result of the logical operation represented by the table. Each row of the truth table contains one possible configuration of input variables and output values. Summary of the invention

[0005] According to an embodiment of the present invention, a method for preparing a trained crossbar array of a neural network is provided. The method includes feeding an input portion of a predetermined truth table into a computer simulation of a crossbar array, and generating simulated output values ​​for the input portion of the truth table based on simulation weights. The method also includes calculating a loss value from each of the simulated output value and the expected value of the output portion of the truth table, and adjusting the simulation weights based on the calculated loss values. The method also includes re-feeding the input portion of the predetermined truth table to the computer simulation and recalculating the output value using the adjusted simulation weights until the simulated output value produces the expected value of the output portion of the truth table within a predetermined error margin.

[0006] According to an embodiment of the present invention, a computer program product for training a cross array of neural networks, the computer program product comprising: providing one or more computer-readable storage media, and program instructions stored together on the one or more computer-readable storage media. The program instructions include program instructions for feeding the input portion of a predetermined truth table into a computer simulation of a cross array, and generating a simulated output value for the input portion of the truth table based on simulation weights. The program instructions also include program instructions for calculating a loss value based on each of the simulated output value and the expected value of the output portion of the truth table, and adjusting the simulation weights based on the calculated loss value. The program instructions also include program instructions for re-feeding the input portion of the predetermined truth table into the computer simulation and recalculating the output value using the adjusted simulation weights until the simulated output value generates an expected value of the output portion of the truth table within a predetermined error margin.

[0007] According to an embodiment of the present invention, a computer system for preparing a trained crossbar array of a neural network is provided. The computer system includes one or more processors and a computer memory electrically coupled to the processor. The computer system includes a computer simulation stored in the computer memory, including a model of a crossbar array, wherein the computer simulation is configured to receive an input portion of a predetermined truth table; generate a simulated output value of the input portion of the truth table based on a simulation weight; calculate a loss value based on one of the simulated output value and an expected value of the output portion of the truth table; adjust the simulation weight based on the calculated loss value; and re-feed the input portion of the predetermined truth table into the computer simulation and recalculate the output value using the adjusted simulation weight until the simulated output value produces the expected value of the output portion of the truth table within a predetermined error margin.

[0008] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following description will provide details of the preferred embodiments with reference to the following drawings, in which:

[0010] Figure 1 is a cross-sectional diagram showing a cross-sectional array of a neural network trained using a truth table according to an embodiment of the present invention;

[0011] Figure 2 is a cross-sectional diagram illustrating a cross-sectional array of a neural network output that generates a truth table according to an embodiment of the present invention;

[0012] Figure 3 is a top view showing a crossbar array of a neural network implementing inverters at the output to generate digital ones and zeros from digital inputs in accordance with an embodiment of the present invention;

[0013] Figure 4 is a block diagram / flow chart illustrating the generation of adjusted simulation weights by computer simulation according to an embodiment of the present invention;

[0014] Figure 5 is a block diagram / flow chart illustrating training of a crossbar array according to an embodiment of the present invention; and

[0015] Figure 6 A computer system for generating adjusted simulation weights through computer simulation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Various embodiments are directed to implementing crossbar arrays and neural networks to replace field programmable gate arrays (FPGAs) to provide complex truth tables and additional neural network functionality. Crossbar arrays can be used for machine learning and learning digital logic truth tables, where the crossbar arrays can be trained or programmed based on truth table data sets. The truth table may include an input portion that provides input values ​​for training the neural network, and an output portion that represents the expected value generated at the output of the neural network. For a particular environment, not all combinations of input values ​​or output values ​​are expected. However, learning a digital logic truth table may require 100% accuracy. In various embodiments, the combinational logic block can be replaced with a crossbar array.

[0017] In various embodiments, there may be noise margin at the output of a crossbar array based neural network. Inverters and / or sense amplifiers may be used to output digital logic of zeros and ones, regardless of variations and noise in the neural network output signal. This may provide digital inputs and digital outputs. Due to noise, a logic high signal at the output of a driving device may arrive at the input of a receiving device at a lower voltage than the trigger high digital value. Noise margin is the amount of noise that can be added to the worst case output so that the signal can still be interpreted as a valid input. I / O noise margin (low and high), NM L and NM H Refers to the ability of a logic gate (e.g., an inverter) to accommodate input noise without producing a faulty logic output. In various embodiments, the inverter may have a noise margin of less than 50% of Vdd (drain voltage), e.g., 2% to 49%. In various embodiments, there may be two or more inverters in series.

[0018] In various embodiments, a neural network trained according to a truth table can be reset in the field and reprogrammed by retraining or by direct programming of new weights. This can provide flexibility because the crossbar array can be used for artificial neural network (ANN) applications and the same neural network device package can be utilized to implement reprogrammable digital logic like an FPGA.

[0019] In various embodiments, training of a predetermined truth table can be performed in a simulation environment using a model that simulates the signal noise of a crossbar array. The training can be done offline using a graphics processing unit (GPU). The weight values ​​generated by the computer simulation and model can be directly loaded into the non-volatile storage unit of the crossbar array.

[0020] In various embodiments, the neural network may have variable layer size and depth to provide training with 100% accuracy, where the exact expected output of the truth table for each input is generated each time by the crossbar array.

[0021] Exemplary applications / uses to which the present invention can be applied include, but are not limited to: for FPGA, data centers, medical devices, automotive applications, edge computing, etc.

[0022] It should be understood that aspects of the invention will be described in terms of a given illustrative architecture; however, other architectural, component and process features and steps may be varied within the scope of aspects of the invention.

[0023] Referring now to the drawings, in which like numerals represent the same or similar elements, reference is first made to Figure 1 , Figure 1 is a cross-sectional view showing a cross-sectional array of an artificial neural network (ANN) trained using a truth table according to an embodiment of the present invention.

[0024] In one or more embodiments, the cross-type array 110 can be implemented using a non-volatile memory device 120 electrically coupled between the cross-wires, wherein the non-volatile memory device 120 can be an analog non-volatile memory device 120 configured to store a range of weights, wherein each cell / NVM device can store multiple bits of weight data. Memory elements with low cycle-to-cycle variability or noise in the weight values ​​stored therein can be used to store multiple bits of weight information. The upper conductor 130 can be perpendicular to the lower conductor 140 or cross at an angle less than 90 degrees. By using these non-volatile memory (NVM) arrays to store weights and directly utilizing the memory elements storing the weights to perform neural network calculations, calculations can be performed in parallel and the energy and latency costs associated with data movement can be reduced.

[0025] In one or more embodiments, a (one or more) predetermined truth table 150 may be used to establish weights stored by the non-volatile memory devices 120 of the crossbar array 110 through training. The crossbar array may be trained directly using the truth table as input, or a computer simulation modeling the crossbar array may be used to implement the trained weights, and the weights may be programmed into the crossbar array. The number of elements in each input set may determine the number of input nodes of the neural network and the number of weights used to calculate the set of output values, which may include one or more values representing one or more states (e.g., 1 or 0), where the number of output values is determined by the truth table.

[0026] In various embodiments, the size and complexity of the input and output portions of the truth table may determine the size and complexity of the neural network and the (one or more) crossbar arrays utilized by the neural network.

[0027] In various embodiments, the non-volatile memory devices 120 retain the weights for the crossbar array 110 learned through training or programming. One or more non-volatile memories may be used to construct the weights. For example, the phase change material (PCM) conductance will be positive, so a differential pair of conductances may be used to construct negative weights such that the total weight W = G+ - G-. If G+ > G-, the weight is positive, or if G+ < G-, the weight is negative. Even more conductances may also be used to build the weights, such as W = F*(G+ - G-) + g+ - g-, where F* is some fixed scale factor to increase the overall dynamic range of the (one or more) weights that can be represented.

[0028] Figure 2 is a cross-sectional view of a crossbar array of a neural network generating the output of a truth table according to an embodiment of the present invention.

[0029] In one or more embodiments, the known values of the input portion of the truth table 150 may be input into a neural network having one or more crossbar arrays 110, and the (one or more) output tables 160 generated by the neural network may be compared with the expected outputs defined by the output portion of the truth table. The truth table input 150 and the truth table output 160 may be used to train the neural network to learn the truth table with 100% accuracy. For example, the training samples may cover 100% or less of the input / output value combinations, where not all combinations are possible in the environment where the neural network is ultimately implemented. The actual circuit may only encounter a subset of the exhaustive list of possible combinations. For a truth table, for all input combinations, all output values may be known (ground truth), so the neural network may be trained to 100% accuracy without overfitting.

[0030] In various embodiments, training can be performed through software simulation of the neural network and crossbar array, including noise simulation in the model. The weights generated by the training simulation can then be programmed / stored into the actual crossbar array.

[0031] In various embodiments, the truth table output(s) 160 generated by the neural network may have one or more values ​​representing outputs of different logic states. The truth table input 150 and the truth table output 160 may be Boolean truth tables or more complex truth tables. This may also be used for logic with more than two states (e.g., 3-values, multi-levels, etc.). The truth table outputs generated by the crossbar array may be sent to other digital circuits or may be input to another crossbar array.

[0032] In various embodiments, the test set is not used to determine the accuracy of the neural network because the known values ​​of the truth table for the input have a one-to-one mapping to the known values ​​of the truth table output, with an expected 100% accuracy, so overtraining will not be a problem.

[0033] Figure 3 is a top view of a crossbar array showing a neural network implementing inverters at the output to generate digital ones and zeros from digital inputs in accordance with an embodiment of the present invention.

[0034] In one or more embodiments, the output can be digitized and processed by digital circuits. Because the crossbar array performs calculations on analog signals, the output can be converted into a digital form that can be interpreted as a result or transmitted to the next crossbar array / layer of the neural network. Inverter 180 can be electrically coupled to each crossbar output to generate a voltage corresponding to a digital one or zero to avoid intermediate voltage values ​​that can be misunderstood. Even if there is noise at the crossbar output signal, inverter 180 can generate a digital output from the crossbar output. In various embodiments, crossbar array 110 can generate an output signal / value within a noise tolerance. Inverter 180 can convert the output value within the noise tolerance into a digital one or zero.

[0035] In various embodiments, the AND interface 170 can be electrically coupled and electrically communicated with the cross array 110 to sum the values ​​generated by the analog non-volatile memory device 120 and apply a suitable activation function f to the summed output, where f can be a nonlinear activation function. The interface 170 can perform a transformation on the analog values ​​output by the cross array 110, where the transformation can map one representation of the input to another representation. For the simulated weights and signals, errors caused by noise, nonlinearity, and variability in the cross array can be accumulated from array to array for the neural network layer. The output representation can be propagated as input to another cross array. In various embodiments, the nonlinear activation function can be, for example, a rectified linear unit (ReLU), a sigmoid function, or a hyperbolic tangent (tanh(x)).

[0036] The Multiply and Accumulate (MAC) unit may be used for vector-matrix multiplication. The Multiply and Accumulate hardware / unit / circuitry / operation may calculate the product of two numbers and add the product to an accumulator.

[0037] The MAC can be used in traditional ANN applications and in truth table applications, where the ANN (and therefore the MAC) can be used to learn a digital logic truth table.

[0038] In one or more embodiments, a crossbar array may replace combinatorial logic blocks that would be used in an FPGA.

[0039] Figure 4 is a block diagram / flow chart illustrating the generation of adjusted simulation weights through computer simulation according to an embodiment of the present invention.

[0040] In one or more embodiments, a computer simulation may generate weights for a crossbar array of a neural network, wherein the computer simulation models the crossbar array and the training of the neural network by back-propagation.

[0041] At block 410, the input portion of the predetermined truth table may be fed into a computer simulation of the crossbar array. The input values ​​may be digital ones and zeros. In various embodiments, the weights of the computer simulation may be initialized with random weight values ​​prior to training to avoid problems that may occur if the initial weights are all set to one, zero, or the same value. The output portion of the predetermined truth table may be fed into the computer simulation for loss calculations.

[0042] At block 420, the computer simulation may generate simulated output values ​​for the input portion of the truth table based on the simulated hardware and simulated weights of the crossbar array. The values ​​output by the computer simulation may be simulated signals generated by a matrix-vector multiplication (MVM).

[0043] At block 430, a loss value may be calculated from each of the analog output value and the expected value from the output portion of the truth table using a loss function. The output value may be an analog or digital value. In various embodiments, the loss function may be a mean square error (MSE).

[0044] At block 440, simulation weights may be adjusted based on the calculated loss values.The weights stored by the computer simulation of the crossbar array may be adjusted using the loss values ​​calculated from the output portion of the truth table using back-propagation and the output values.

[0045] At block 450, training is repeated by re-feeding the input portion of the predetermined truth table into the computer simulation and recalculating the output value using the adjusted simulation weights until the simulated output value produces the expected value of the output portion of the truth table within a predetermined error margin. In supervised learning, the network can be trained to make accurate predictions by iteratively updating the weight matrix until the output provides the correct value. The original truth table can be fed to the neural network (NN), for example, in a range of about 10 times to about 1,000,000 times. In various embodiments, training can be repeated until 100% of the outputs converge to within a predetermined error tolerance, such as a 0% error tolerance, where the output value matches 100% of the output portion of the truth table.

[0046] In one or more embodiments, the simulated crossbar array and trained weights of the neural network may be implemented in the field for intended operation using truth tables for training.

[0047] In one or more embodiments, the crossbar array can be retrained with new simulation weights and results by feeding a new truth table with known output values ​​into a computer simulation. Prior to inputting the new truth table, the crossbar array's weights can be reset in a manner appropriate for the type of non-volatile memory used in the crossbar array (e.g., phase change, ferroelectric, magnetic, etc.).

[0048] Figure 5 is a block diagram / flow chart illustrating training of a crossbar array according to an embodiment of the present invention.

[0049] In one or more embodiments, the neural network and crossbar array may be trained 500 using a predetermined truth table representing inputs and desired outputs (eg, ground truth values).

[0050] At block 510, a predetermined truth table may be fed into an input node of a neural network to train one or more crossbar arrays that will store the learned weights. The input values ​​may be the numbers one and zero. In various embodiments, the crossbar array(s) may be initialized with random weight values ​​prior to training to avoid problems that may occur if the initial weights are all set to one, zero, or the same value. In various embodiments, multiple crossbar arrays may store the learned weights.

[0051] At block 520, the neural network may output the resulting values ​​of the input truth table generated from the weights stored by the crossbar array. The values ​​output by the crossbar array may be analog signals, while the outputs produced by the inverters or sense amplifiers may be digital signals.

[0052] At block 530, the output value may be compared to the known / expected value of the input truth table. The output value may be an analog or digital value, depending on whether the output value is output by a crossbar array or an inverter.

[0053] At block 540, the loss may be calculated from the output values ​​compared to the input truth table. In various embodiments, analog values ​​of the weights may be used to calculate the loss and train the weights, where the analog signal values ​​may be compared to analog values ​​that will produce the expected digital output. In various embodiments, the digital values ​​may be used directly in the calculation of the loss function.

[0054] In various embodiments, the loss function may be mean squared error (MSE), where one or more cross-wise arrays may be trained to be 100% accurate by minimizing the loss function over a training data set.

[0055] The weights stored in the crossbar array may be adjusted using the loss value calculated from the output value and the input truth table at block 550. The amount of the learned weights may be adjusted based on the loss value.

[0056] At block 560, training may be repeated by re-feeding the truth table into the neural network and recalculating the output values ​​using the adjusted weights in the crossbar array. In various embodiments, the original truth table may be fed into the neural network (NN), for example, in a range of about 10 times to about 1,000,000 times. In various embodiments, training may be repeated until 100% of the outputs have converged to within a certain error tolerance, for example, determined by the inverters.

[0057] At block 570, the truth table used for training may be used to implement the crossbar array and the trained weights of the neural network in the field for intended operation.

[0058] At block 580, the crossbar array may be retrained by feeding a new truth table with known output values ​​into the neural network and the crossbar array. Prior to inputting the new truth table, the weights of the crossbar array may be reset in a manner appropriate to the type of non-volatile memory used in the crossbar array (e.g., phase change, ferroelectric, magnetic, etc.).

[0059] In various embodiments, a complete set of new weights trained on another crossbar array can be stored in a neural network implemented in the field by rewriting the implemented crossbar array. The memory can be programmed or reprogrammed by applying voltage pulses of varying duration and current. These can be used to reset the memory. Additional pulses can then be used to incrementally adjust the conductance of the non-volatile memory devices of the crossbar array.

[0060] In one or more embodiments, the neural network and the crossbar array(s) may have a reset feature and accompanying circuitry to erase or reset the weights stored in the non-volatile memory device 120 of the crossbar array 110 so that the non-volatile memory device 120 of the crossbar array 110 may be reprogrammed or retrained with new weights in the field. Reprogramming of the non-volatile memory device 120 of the crossbar array 110 may result in pre-trained weights determined offline being stored in the non-volatile memory device 120 of the crossbar array 110, while retraining may involve re-entering / inputting a new truth table to generate a new set of weights in the field, where the new truth table may be different from the original truth table used for previous training.

[0061] Figure 6 A computer system for generating adjusted simulation weights through computer simulation according to an embodiment of the present invention.

[0062] In one or more embodiments, one or more processors 610 (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.) may be electronically coupled and in electrical communication with computer memory 620 via bus 630. In various embodiments, display screen 640 may be electronically coupled and in electrical communication with one or more processors 610 and computer memory 620 via bus 630.

[0063] In various embodiments, a computer simulation 650 modeling the crossbar array(s) may be stored in computer memory 620. In various embodiments, a truth table 660 that may be used to train a neural network through simulation may be stored in computer memory 620.

[0064] As used herein, the term "hardware processor subsystem" or "hardware processor" may refer to a processor, memory, software, or a combination thereof that collaborate to perform one or more specific tasks. In useful embodiments, the hardware processor subsystem may include one or more data processing elements (e.g., logic circuits, processing circuits, instruction execution devices, etc.). One or more data processing elements may be included in a central processing unit, a graphics processing unit, and / or a separate processor- or computing element-based controller (e.g., logic gates, etc.). The hardware processor subsystem may include one or more on-board memories (e.g., caches, dedicated memory arrays, read-only memories, etc.). In some embodiments, the hardware processor subsystem may include one or more memories, which may be on-board or off-board, or may be dedicated for use by the hardware processor subsystem (e.g., ROM, RAM, basic input / output system (BIOS), etc.).

[0065] In some embodiments, the hardware processor subsystem may include and execute one or more software elements. The one or more software elements may include an operating system and / or one or more applications and / or specific code to achieve a specified result.

[0066] In other embodiments, the hardware processor subsystem may include dedicated, specialized circuits that perform one or more electronic processing functions to achieve specified results. Such circuits may include one or more application specific integrated circuits (ASICs), FPGAs, and / or PLAs.

[0067] These and other variations of hardware processor subsystems are also contemplated according to embodiments of the present invention.

[0068] The present invention may be a system, method and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon, and the computer-readable program instructions are used to cause a processor to perform various aspects of the present invention.

[0069] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be interpreted as a temporary signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0070] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium in the corresponding computing / processing device.

[0071] The computer-readable program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages, such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider via the Internet). In some embodiments, in order to perform various aspects of the present invention, an electronic circuit including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute a computer-readable program instruction by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit.

[0072] Various aspects of the present invention are described herein with reference to the flow chart and / or block diagram of the method, device (system) and computer program product according to embodiments of the present invention. It will be understood that each frame of the flow chart and / or block diagram and the combination of frames in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0073] These computer-readable program instructions can be provided to a processor of a computer or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can guide the computer, programmable data processing device and / or other equipment to work in a specific manner, so that the computer-readable storage medium having the instructions stored therein includes an article of manufacture, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0074] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0075] References in the specification to "one embodiment" or "an embodiment" and other variations of the present invention mean that the particular features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing in various places throughout the specification do not necessarily refer to the same embodiment.

[0076] It should be understood that the use of any of the following " / ", "and / or", and "at least one", such as in the case of "A / B", "A and / or B", and "at least one of A and B", is intended to cover selecting only the first listed option (A), or selecting only the second listed option (B), or selecting both options (A and B). As a further example, in the case of "A, B, and / or C" and "at least one of A, B, and C", such wording is intended to include selecting only the first listed option (A), or selecting only the second listed option (B), or selecting only the third listed option (C), or selecting only the first and second listed options (A and B), or selecting only the first and third listed options (A and C), or selecting only the second and third listed options (B and C), or selecting all three options (A and B and C). This can be extended to many of the listed items, as will be apparent to one of ordinary skill in the art and related arts.

[0077] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, the module, segment or part of the instruction that each frame in the flow chart or block diagram can represent include one or more executable instructions for realizing the specified logical function.In some alternative embodiments, the function noted in the frame may not occur in the order noted in the figure.For example, the two frames shown continuously can actually be realized as a step, and are performed simultaneously, substantially simultaneously, in a mode of partial or full time overlap, or these frames can sometimes be performed in reverse order, depending on the function involved.It will also be noted that the combination of the frames in each frame of the block diagram and / or flow chart illustration and the block diagram and / or flow chart illustration can be realized by a dedicated hardware-based system that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0078] Having described preferred embodiments of the systems and methods (which are intended to be illustrative and not limiting), it is noted that modifications and variations may be made by those skilled in the art in light of the above teachings. Therefore, it should be understood that changes may be made in the particular embodiments disclosed that are within the scope of the invention as outlined by the appended claims. Having thus described the various aspects of the invention with the details and particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. A computer method for preparing a trained crossbar array of a neural network, comprising: feeding an input portion of the predetermined truth table into a computer simulation of the crossbar array; generating a simulated output value for the input portion of the truth table based on a simulation weight; calculating a loss value based on each of the simulated output value and an expected value of an output portion of the truth table; adjusting the simulation weights based on the calculated loss values; as well as The input portion of the predetermined truth table is fed back into the computer simulation and the output value is recalculated using the adjusted simulation weights until the simulated output value produces the expected value of the output portion of the truth table within a predetermined error margin.

2. The computer method of claim 1, wherein each simulated analog output value includes an error of less than 49% of Vdd. The computer method of claim 2 , wherein the predefined margin of error is 0%.

4. The computer method of claim 3, wherein: The loss value is calculated using a mean square error (MSE) loss function.

5. The computer method of claim 4, further comprising programming one or more crossbar arrays using the adjusted simulation weights, wherein the programmed one or more crossbar arrays emulate a field programmable gate array (FPGA).

6. The computer method of claim 5, further comprising resetting weights of the one or more crossbar arrays.

7. The computer method of claim 6, further comprising reprogramming the one or more crossbar arrays with different weights to emulate different field programmable gate arrays (FPGAs).

8. A computer program product for training a crossbar array of neural networks, the computer program product comprising: One or more computer-readable storage media, and program instructions stored together on the one or more computer-readable storage media, the program instructions comprising: program instructions for: feeding an input portion of the predetermined truth table into a computer simulation of the crossbar array; generating a simulated output value for the input portion of the truth table based on a simulation weight; calculating a loss value based on each of the simulated output value and an expected value of an output portion of the truth table; adjusting the simulation weights based on the calculated loss values; and The input portion of the predetermined truth table is fed back into a computer simulation and the output value is recalculated using the adjusted simulation weights until the simulated output value produces the expected value of the output portion of the truth table within a predetermined error margin.

9. The computer program product of claim 8, wherein each analog output value comprises an error of less than 49% of Vdd.

10. The computer program product of claim 9, wherein the predefined margin of error is 0%.

11. The computer program product according to claim 10, wherein: The loss value is calculated using a mean square error (MSE) loss function.

12. The computer program product of claim 11, further comprising programming one or more crossbar arrays with the adjusted simulation weights, wherein: The programmed crossbar array or arrays emulate a field programmable gate array (FPGA).

13. The computer program product of claim 12, further comprising resetting the weights of the one or more crossbar arrays and reprogramming the one or more crossbar arrays with different weights to emulate a different field programmable gate array (FPGA).

14. A computer system for preparing a trained crossbar array of a neural network, comprising: one or more processors; a computer memory electronically coupled to the processor; A computer simulation comprising a model of a crossbar array, wherein the computer simulation is configured to: receiving an input portion of a predetermined truth table; generating a simulated output value for the input portion of the truth table based on a simulation weight; calculating a loss value based on each of the simulated output value and the expected value of the output portion of the truth table; adjusting the simulation weights based on the calculated loss values; and The input portion of the predetermined truth table is fed back into the computer simulation and the output value is recalculated using the adjusted simulation weights until the simulated output value produces the expected value of the output portion of the truth table within a predetermined error margin.

15. The computer system of claim 14, further comprising a digital logic truth table stored in the computer memory as a training data set.

16. The computer system of claim 15, wherein each analog output value includes an error of less than 49% of Vdd.

17. The computer system of claim 16, wherein: The loss value is calculated using a mean square error (MSE) loss function.

18. The computer system of claim 16, wherein the predefined margin of error is 0%.

19. The computer system of claim 18, further comprising one or more crossbar arrays and an inverter at each output of the one or more crossbar arrays, the inverter generating a digital one or zero output from a noisy input signal.

20. The computer system of claim 19, wherein the one or more crossbar arrays are configured to be reset and reprogrammed by applying a voltage pulse.

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