Sensitive path judgment method and device based on truth table, equipment and medium

Abstract

The invention relates to the technical field of integrated circuits, and discloses a sensitive path judgment method and device based on a truth table, equipment and a medium, and the method comprises the steps: obtaining a target lookup table in a circuit netlist, and truth table data corresponding to the target lookup table; performing binary bit operation on the input combination of the target lookup table to obtain at least one group of verification data; the verification data comprises a verification input combination and a verification output; based on the at least one group of verification data and truth table data, obtaining a sensitivity analysis result; and judging a time sequence arc type of the time sequence path based on a sensitive analysis result. According to the scheme, the binary bit operation is used for processing the input combination of the lookup table, and verification data can be quickly generated; and obtaining a sensitivity analysis result of the lookup table based on the verification data and the truth table data, so that the time sequence arc type of the time sequence path can be efficiently and accurately judged.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a truth table-based sensitive path judgment method, device, equipment and medium. Background Art

[0002] In digital circuit design, static timing analysis is usually required to verify whether the logic unit delays between timing units (such as flip-flops, DSPs, RAMs, etc.) meet the setup and hold time requirements.

[0003] Logic cells primarily refer to lookup tables (LUTs). Not all paths within a logic cell actually affect circuit performance. Some paths are insensitive, meaning the input signal never propagates to the output. In other words, these paths do not exist. STA analysis should avoid this because it can lead to overly pessimistic results that deviate from reality and wastes time and space. Summary of the Invention

[0004] In view of this, the present invention provides a sensitive path determination method, apparatus, device and medium based on a truth table to solve the problem that current static timing analysis fails to efficiently identify sensitive paths.

[0005] In a first aspect, the present invention provides a sensitive path judgment method based on a truth table.

[0006] The method comprises:

[0007] Obtaining a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table; the target timing path is composed of the lookup tables; the truth table data is used to represent the mapping relationship between all input combinations and output values of the corresponding target lookup table;

[0008] Performing binary bit operations on the input combination of the target lookup table to obtain at least one set of verification data; the verification data includes a verification input combination and a verification output;

[0009] Based on the at least one set of verification data and the truth table data, obtaining the sensitivity analysis result; the sensitivity analysis result includes positive monotonically increasing, negative monotonically increasing, and non-monotonic;

[0010] Based on the sensitivity analysis result, a timing arc type of a timing path corresponding to the target lookup table is determined.

[0011] In an optional embodiment, performing a binary bit operation on the input combination of the target lookup table to obtain at least one set of verification data includes:

[0012] Obtain the target input combination and the corresponding target output value from the target lookup table;

[0013] Flipping the target input value of the target input port in the target input combination and keeping the input values of the remaining input ports unchanged to obtain a verification input combination;

[0014] According to the truth table data, a verification output corresponding to the verification input combination is obtained.

[0015] The obtaining the sensitivity analysis result based on the at least one set of verification data and the truth table data includes:

[0016] Traversing all input combinations of the target lookup table, and obtaining comparison results based on each input combination, the flipped input combination, the output value, and the verification output;

[0017] The sensitivity analysis result is obtained based on the comparison results.

[0018] In an optional embodiment, all input combinations of the target lookup table are traversed according to the above steps, and comparison results are obtained based on each input combination, the flipped input combination, the output value, and the verification output, including:

[0019] Comparing the input combination with the flipped input combination to determine the input flip type; the input flip type includes rising edge and falling edge;

[0020] Comparing the output value and verifying the output to determine the output flip type; the output flip type includes rising edge and falling edge;

[0021] The comparison result is determined based on the input flip type and the output flip type.

[0022] In an optional implementation, determining the comparison result based on the input flip type and the output flip type includes:

[0023] If the input flip type is the same as the output flip type, the comparison result is positive monotonically increasing;

[0024] If the input flip type is different from the output flip type, the comparison result is negative monotonically increasing.

[0025] In an optional embodiment, obtaining the sensitivity analysis result based on the comparison results includes:

[0026] If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing;

[0027] If all the comparison results are negative monotonically increasing, then the sensitivity analysis result is negative monotonically increasing;

[0028] If the comparison results show both positive monotonically increasing and negative monotonically increasing trends, the sensitivity analysis result is non-monotonic.

[0029] In an optional implementation, determining the timing arc type of the timing path corresponding to the target lookup table based on the sensitivity analysis result includes:

[0030] When the monotonicity of the input and output ports corresponding to the target timing path in each lookup table is consistent, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc;

[0031] When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-function timing arc.

[0032] In an optional embodiment, the method further includes:

[0033] If there is a non-function timing arc in the timing path corresponding to the target lookup table, the non-function timing arc is removed during the timing analysis process.

[0034] In a second aspect, the present invention provides a sensitive path determination device based on a truth table, the device comprising:

[0035] An acquisition path module acquires a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table; the target timing path is composed of various lookup tables; the truth table data is used to represent the mapping relationship between all input combinations and output values of the corresponding target lookup table;

[0036] an operation module, configured to perform a binary bit operation on the input combination of the target lookup table to obtain at least one set of verification data; the verification data includes a verification input combination and a verification output;

[0037] An analysis module, configured to obtain the sensitivity analysis result based on the at least one set of verification data and the truth table data; the sensitivity analysis result includes positive monotonically increasing, negative monotonically increasing, and non-monotonic;

[0038] A judgment module is used to judge the timing arc type of the timing path corresponding to the target lookup table based on the sensitivity analysis result.

[0039] In an optional implementation, the operation module is configured to:

[0040] Obtain the target input combination and the corresponding target output value from the target lookup table;

[0041] Flipping the target input value of the target input port in the target input combination and keeping the input values of the remaining input ports unchanged to obtain a verification input combination;

[0042] According to the truth table data, obtaining the verification output corresponding to the verification input combination;

[0043] The analysis module is used to:

[0044] Traversing all input combinations of the target lookup table, and obtaining comparison results based on each input combination, the flipped input combination, the output value, and the verification output;

[0045] The sensitivity analysis result is obtained based on the comparison results.

[0046] In an optional embodiment, the analysis module is further configured to:

[0047] Comparing the input combination with the flipped input combination to determine the input flip type; the input flip type includes rising edge and falling edge;

[0048] Comparing the output value and verifying the output to determine the output flip type; the output flip type includes rising edge and falling edge;

[0049] The comparison result is determined based on the input flip type and the output flip type.

[0050] In an optional embodiment, the analysis module is further configured to:

[0051] If the input flip type is the same as the output flip type, the comparison result is positive monotonically increasing;

[0052] If the input flip type is different from the output flip type, the comparison result is negative monotonically increasing.

[0053] In an optional embodiment, the analysis module is further configured to:

[0054] If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing;

[0055] If all the comparison results are negative monotonically increasing, then the sensitivity analysis result is negative monotonically increasing;

[0056] If the comparison results show both positive monotonically increasing and negative monotonically increasing trends, the sensitivity analysis result is non-monotonic.

[0057] In an optional embodiment, the analysis module is further configured to:

[0058] When the monotonicity of the input and output ports corresponding to the target timing path in each lookup table is consistent, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc;

[0059] When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-function timing arc.

[0060] In an optional embodiment, the analysis module is further configured to:

[0061] If there is a non-function timing arc in the timing path corresponding to the target lookup table, the non-function timing arc is removed during the timing analysis process.

[0062] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the sensitive path judgment method based on the truth table of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0063] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the truth table-based sensitive path judgment method of the above-mentioned first aspect or any corresponding embodiment thereof.

[0064] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, which are used to enable a computer to execute the sensitive path judgment method based on a truth table of the above-mentioned first aspect or any corresponding embodiment thereof.

[0065] The technical solution provided by this application may have the following beneficial effects:

[0066] Obtain the target lookup table in the circuit netlist, and the truth table data corresponding to the target lookup table, and the target timing path is composed of various lookup tables; wherein, the truth table data is used to characterize the mapping relationship between all input combinations and output values of the corresponding target lookup table; at this time, perform binary bit operations on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs; based on at least one set of verification data and truth table data, determine whether the sensitivity analysis result of the target timing path is positive monotonically increasing, negative monotonically increasing, or non-monotonic; at this time, based on the sensitivity analysis result, the timing arc type of the target timing path can be determined. The above scheme uses binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data; based on the verification data and truth table data, the sensitivity analysis results of the lookup table are obtained, so that the timing arc type of the timing path can be efficiently and accurately determined. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0068] Figure 1 1 is a flow chart of a sensitive path determination method based on a truth table according to an embodiment of the present invention;

[0069] Figure 2 is a flow chart of another sensitive path determination method based on a truth table according to an embodiment of the present invention;

[0070] Figure 3 is a structural block diagram of a sensitive path determination device based on a truth table according to an embodiment of the present invention;

[0071] Figure 4 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0072] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0073] In digital circuit design, static timing analysis is usually required to verify whether the logic unit delays between timing units (such as flip-flops, DSPs, RAMs, etc.) meet the setup and hold time requirements.

[0074] Logic cells primarily refer to lookup tables (LUTs). Not all paths within a logic cell actually affect circuit performance. Some paths are insensitive, meaning the input signal never propagates to the output. In other words, these paths do not exist. STA analysis should avoid this because it can lead to overly pessimistic results that deviate from reality and wastes time and space.

[0075] LUTs can be configured (programmed) to implement different logical operations, such as AND, OR, NOT, XOR, and more complex combinational logic functions. Their operating principle is similar to a pre-populated mapping table, or truth table, which directly searches for output results based on the combination of input signals. In other words, the functionality of the LUT and the characteristics of timing analysis are uniquely determined by its internal truth table. This embodiment of the present invention provides a sensitive path determination method based on a truth table to address the current problem of static timing analysis failing to efficiently identify sensitive paths.

[0076] According to an embodiment of the present invention, an embodiment of a sensitive path judgment method based on a truth table is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0077] In this embodiment, a sensitive path judgment method based on a truth table is provided, which can be used in computer equipment. Figure 1 FIG. 1 is a flow chart of a sensitive path determination method based on a truth table according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0078] Step 101: Obtain a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table.

[0079] In the embodiments of the present application, the timing paths are composed of various lookup tables. Therefore, to determine whether each timing path needs to be pruned, the lookup tables that constitute the timing paths must first be analyzed. For each target lookup table in each lookup table, the truth table data in the target lookup table is used to represent the mapping relationship between all input combinations and output values of the corresponding target lookup table.

[0080] In an embodiment of the present application, a circuit netlist file can be read to identify and locate the target timing path. The netlist describes the circuit elements and their connections in detail. Furthermore, all LUT elements on the target path are identified, and their identifiers and connections are obtained. For each LUT, a truth table is extracted or generated to clearly identify all input combinations and corresponding output values.

[0081] Step 102: perform binary bit operations on the input combination of the target lookup table to obtain at least one set of verification data; the verification data includes a verification input combination and a verification output.

[0082] In an embodiment of the present application, all possible input combinations are determined based on the number of input bits of the LUT, and then a specific binary bit operation (such as flipping a bit) is performed on each input combination to generate a new input combination; finally, the original input combination, the input combination after the bit operation and its corresponding output value (obtained by consulting the truth table) are combined into a verification data set.

[0083] Step 103: Obtain the sensitivity analysis result based on the at least one set of verification data and the truth table data; the sensitivity analysis result includes positive monotonically increasing, negative monotonically increasing, and non-monotonic.

[0084] In an embodiment of the present application, by using verification data to observe the impact of input changes (such as a bit changing from 0 to 1 or from 1 to 0) on the output, it can be determined whether the target lookup table is positively monotonically increasing, negatively monotonically increasing, or non-monotonic.

[0085] Step 104 : Determine the timing arc type of the timing path based on the sensitivity analysis result.

[0086] The sensitivity analysis results of all LUTs on the target path are summarized. If all LUTs on the path are positively monotonically increasing or negatively monotonically increasing, the path is considered a sensitive path. At this time, the timing arc type of the timing path can be a positive function timing arc or a negative function timing arc. If there is a non-monotonic LUT in a timing path, for example, one path is positively monotonically increasing and one path is positively monotonically decreasing, or the sensitivity combination between the LUTs causes the path to be insensitive to input changes, then the timing arc type corresponding to the target timing path is a non-function timing arc. Subsequent timing analysis does not need to analyze the path of the non-function timing arc, thereby improving the analysis efficiency of the path timing analysis.

[0087] In summary, the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table are obtained, and the target timing path is composed of various lookup tables; wherein, the truth table data is used to characterize the mapping relationship between all input combinations and output values of the corresponding target lookup table; at this time, binary bit operations are performed on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs; based on at least one set of verification data and truth table data, it is determined whether the sensitivity analysis result of the target timing path is positive monotonically increasing, negative monotonically increasing or non-monotonic; at this time, based on the sensitivity analysis result, the timing arc type of the target timing path can be determined. The above scheme uses binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data; based on the verification data and truth table data, the sensitivity analysis results of the lookup table are obtained, so that the timing arc type of the timing path can be efficiently and accurately determined.

[0088] In this embodiment, a sensitive path determination method based on a truth table is provided, which can be used in the above-mentioned computer device. Figure 2 FIG. 1 is a flow chart of a sensitive path determination method based on a truth table according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0089] Step 201: Obtain a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table.

[0090] Read the circuit netlist file and parse the type, connection relationship, and timing path information of each component in the circuit. Determine the target timing path, which is a path composed of several lookup tables connected in series, with the lookup tables interconnected in timing. Identify all LUT elements on the target timing path in sequence, and obtain the identification information of each LUT and its position in the entire path. For each target lookup table, extract or calculate its truth table data, where the truth table data shows all input combinations and corresponding output values of the LUT, providing a basis for subsequent sensitivity analysis.

[0091] Step 202: Obtain a target input combination and a corresponding target output value from a target lookup table.

[0092] For each lookup table extracted in step 201 , one or more target input combinations are determined from its truth table, and output values corresponding to these combinations are simultaneously obtained.

[0093] Step 203: flip the target input value of the target input port in the target input combination, and keep the input values of the remaining input ports unchanged, to obtain a verification input combination.

[0094] Specifically, one or more input ports to be flipped are selected from the target input combination; then the input values of the selected ports are inverted, while the other inputs remain unchanged, thereby obtaining a new verification input combination to observe the output response through single-point or multi-point input changes.

[0095] Step 204: Obtain the verification output corresponding to the verification input combination according to the truth table data.

[0096] According to the verification input combinations generated in step 203, the verification outputs corresponding to these verification input combinations are determined by consulting the truth table data.

[0097] Step 205 , traverse all input combinations of the target lookup table, and obtain comparison results based on each input combination, the flipped input combination, the output value, and the verification output.

[0098] Specifically, all target input combinations of the LUT are processed one by one, and the original input combination is compared with the flipped verification input combination to determine which input port has changed.

[0099] In one possible implementation, an input combination and a flipped input combination are compared to determine an input flip type; the input flip type includes a rising edge and a falling edge; an output value is compared with a verification output to determine an output flip type; the output flip type includes a rising edge and a falling edge; and a comparison result is determined based on the input flip type and the output flip type.

[0100] Compare the original input combination with the input combination after the flip operation to observe which input port value has changed. If the port value changes from 0 to 1, the input change is considered a "rising edge"; if it changes from 1 to 0, it is a "falling edge." Similarly, compare the original output value with the verification output (i.e., the output value after the input flip) to observe the change in the output value. If the output value changes from low to high, it is considered a "rising edge"; if it changes from high to low, it is a "falling edge."

[0101] In a possible implementation, if the input flip type is the same as the output flip type, the comparison result is positive monotonically increasing; if the input flip type is different from the output flip type, the comparison result is negative monotonically increasing.

[0102] In the embodiment of the present application, the logical relationship can be determined based on the matching of the input flip type and the output flip type: if the input flip and the output flip are of the same type (both rising edges or both falling edges), then the input change and the output change are consistent in direction, corresponding to a positive monotonically increasing situation. If the input flip and the output flip are inconsistent in type (for example, the input is a rising edge, while the output is a falling edge), then there is a change in the opposite direction, corresponding to a negative monotonically increasing situation.

[0103] Step 206: Obtain the sensitivity analysis result based on the comparison results.

[0104] Using each sensitivity analysis result, the sensitivity of the entire timing path is comprehensively judged, and then whether the path is sensitive to the input data is determined. For insensitive paths, path pruning optimization is performed.

[0105] Specifically, if all comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing; if all comparison results are negatively monotonically increasing, then the sensitivity analysis result is negatively monotonically increasing; if all comparison results are both positively monotonically increasing and negatively monotonically increasing, then the sensitivity analysis result is non-monotonic.

[0106] Step 207: Determine the timing arc type of the timing path based on the sensitivity analysis result.

[0107] In a possible implementation, when the monotonicity of the input and output ports corresponding to the target timing path in each look-up table is consistent, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc;

[0108] When the monotonicity of the input and output ports corresponding to the target timing path in the target look-up table is inconsistent, the timing arc type of the target timing path is a non-function timing arc.

[0109] In a possible implementation, if there is a non-function timing arc in the timing path corresponding to the target look-up table, the non-function timing arc is removed during the timing analysis process, so as to achieve pruning of the non-function timing arc during the timing analysis process.

[0110] Specifically, according to the connection order of the logic units (LUTs), the subsequent logic units starting from the first non-monotonic look-up table in the target timing path can be removed, so as to obtain a "pruned sensitive path", the purpose of which is to only retain those critical paths that can stably respond to input changes for subsequent optimization and verification.

[0111] The following specifically describes the processing process of a single LUT in combination with a specific scenario.

[0112] There are only two sensitive paths, rise-rise and fall-fall, for a timing arc with sensitivity of positve-unate. There are only two sensitive paths, rise-fall and fall-rise, for a timing arc with sensitivity of negative-unate, and there are 4 such paths for a timing arc with sensitivity of non-unate.

[0113] By processing multiple LUTs in parallel and using a multi-threaded or distributed computing framework, the sensitivities of multiple LUTs are judged simultaneously. The following will specifically describe the processing process of a single LUT.

[0114] Function (input parameter: id):

[0115] Initialize variables:

[0116] state = unknown / / The initial state is unknown

[0117] bitOffset = 1 << id / / The offset of the current input

[0118] Traverse all possible input combinations:

[0119] Execute for i from 0 to the number of LUT input ports:

[0120] / / Extract the current bit value and the next bit value

[0121] currBitVal=(currInit>>i)&1

[0122] nextBitVal=(currInit>>(i+bitOffset))&1

[0123] / / Judge the status

[0124] If currBitVal is 1 and nextBitVal is 0: / / 1.fall

[0125] If state is unknown:

[0126] state=negative-unate

[0127] Otherwise if state is positive-unate:

[0128] return non-unate / / Exit judgment

[0129] If currBitVal is 0 and nextBitVal is 1: / / 2.rise

[0130] If state is unknown:

[0131] state=positive-unate

[0132] Otherwise if state is negative-unate:

[0133] return non-unate / / Exit judgment

[0134] return state

[0135] The judgment logic is as follows: traverse all the change combinations corresponding to the current input port and find the change of the output port from the truth table:

[0136] 1. If the input port changes are consistent with the output port, it is temporarily considered to be positive-unate and continue to check

[0137] 2. If the input port changes in the opposite direction to the output port, temporarily consider it a negative-unate and continue checking

[0138] 3. If both positive-unate and negative-unate appear, it is considered non-unate and the check is exited.

[0139] Furthermore, in an embodiment of the present application, different LUTs can be processed in parallel, that is, multiple LUTs are assigned to different threads, and each thread independently processes the sensitivity judgment task of one or more LUTs.

[0140] Therefore, the technical solution shown in the embodiments of this application supports parallel path classification for multiple input combinations. By combining path judgment logic with parallel computing, it can simultaneously process input signal flips of multiple LUTs, thereby quickly determining the type of each path. This method effectively reduces the overhead of repeated calculations through batch operations, significantly improving the efficiency of path analysis in large-scale designs. It quickly parses the truth table of the input signal through binary bit operations (such as bit shifts and bitwise AND) to extract the current state (currBitVal) and flip state (nextBitVal) from the input signal.

[0141] During the path classification process, a state machine mechanism and consistency check logic are used to ensure the accuracy and reliability of the path classification results. Initial state protection: The initial state is unknown to avoid misjudgment of path types.

[0142] The solution presented in the embodiments of this application can also be optimized for path analysis in large-scale designs. It is widely applicable to static timing analysis of complex logic designs such as FPGAs and ASICs. By parallelizing and automating the process, analysis time is reduced, significantly improving efficiency. It is highly adaptable to large-scale designs, particularly in complex logic netlists, by reducing invalid path checks.

[0143] In summary, the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table are obtained, and the target timing path is composed of various lookup tables; wherein, the truth table data is used to characterize the mapping relationship between all input combinations and output values of the corresponding target lookup table; at this time, binary bit operations are performed on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs; based on at least one set of verification data and truth table data, it is determined whether the sensitivity analysis result of the target timing path is positive monotonically increasing, negative monotonically increasing or non-monotonic; at this time, based on the sensitive analysis results, the sensitive path and non-sensitive path of the target timing path can be determined. The above scheme uses binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data; based on the verification data and truth table data, the sensitivity analysis results of the lookup table are obtained, so that the timing arc type of the timing path can be efficiently and accurately determined.

[0144] In this embodiment, a sensitive path judgment device based on a truth table is also provided. The device is used to implement the above-mentioned embodiments and preferred implementation methods. The details that have been described will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0145] This embodiment provides a sensitive path judgment device based on a truth table, such as Figure 3 Shown, including:

[0146] The path acquisition module 301 acquires a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table; the target timing path is composed of various lookup tables; the truth table data is used to represent the mapping relationship between all input combinations and output values of the corresponding target lookup table;

[0147] An operation module 302 is configured to perform a binary bit operation on the input combination of the target lookup table to obtain at least one set of verification data; the verification data includes a verification input combination and a verification output;

[0148] An analysis module 303 is configured to obtain the sensitivity analysis result based on the at least one set of verification data and the truth table data; the sensitivity analysis result includes positive monotonically increasing, negative monotonically increasing, and non-monotonic;

[0149] The judgment module 304 is configured to judge the timing arc type of the timing path based on the sensitivity analysis result.

[0150] In an optional implementation, the operation module is configured to:

[0151] Obtain the target input combination and the corresponding target output value from the target lookup table;

[0152] Flipping the target input value of the target input port in the target input combination and keeping the input values of the remaining input ports unchanged to obtain a verification input combination;

[0153] According to the truth table data, obtaining the verification output corresponding to the verification input combination;

[0154] The analysis module is used to:

[0155] Traversing all input combinations of the target lookup table, and obtaining comparison results based on each input combination, the flipped input combination, the output value, and the verification output;

[0156] The sensitivity analysis result is obtained based on the comparison results.

[0157] In an optional embodiment, the analysis module is further configured to:

[0158] Comparing the input combination with the flipped input combination to determine the input flip type; the input flip type includes rising edge and falling edge;

[0159] Comparing the output value and verifying the output to determine the output flip type; the output flip type includes rising edge and falling edge;

[0160] The comparison result is determined based on the input flip type and the output flip type.

[0161] In an optional embodiment, the analysis module is further configured to:

[0162] If the input flip type is the same as the output flip type, the comparison result is positive monotonically increasing;

[0163] If the input flip type is different from the output flip type, the comparison result is negative monotonically increasing.

[0164] In an optional embodiment, the analysis module is further configured to:

[0165] If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing;

[0166] If all the comparison results are negative monotonically increasing, then the sensitivity analysis result is negative monotonically increasing;

[0167] If the comparison results show both positive monotonically increasing and negative monotonically increasing trends, the sensitivity analysis result is non-monotonic.

[0168] In an optional embodiment, the analysis module is further configured to:

[0169] When the monotonicity of the input and output ports corresponding to the target timing path in each lookup table is consistent, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc;

[0170] When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-function timing arc.

[0171] In an optional embodiment, the analysis module is further configured to:

[0172] If there is a non-function timing arc in the timing path corresponding to the target lookup table, the non-function timing arc is removed during the timing analysis process.

[0173] In summary, the target lookup table in the circuit netlist and the truth table data corresponding to the target lookup table are obtained, and the target timing path is composed of various lookup tables; wherein, the truth table data is used to characterize the mapping relationship between all input combinations and output values of the corresponding target lookup table; at this time, binary bit operations are performed on the input combinations of the target lookup table to obtain at least one set of verification data; the verification data includes verification input combinations and verification outputs; based on at least one set of verification data and truth table data, it is determined whether the sensitivity analysis result of the target timing path is positive monotonically increasing, negative monotonically increasing or non-monotonic; at this time, based on the sensitivity analysis result, the timing arc type of the target timing path can be determined. The above scheme uses binary bit operations to process the input combinations of the lookup table, which can quickly generate verification data; based on the verification data and truth table data, the sensitivity analysis results of the lookup table are obtained, so that the timing arc type of the timing path can be efficiently and accurately determined.

[0174] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0175] The truth table-based sensitive path judgment device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0176] The embodiment of the present invention also provides a computer device having the above Figure 3 The sensitive path judgment device based on the truth table is shown.

[0177] See also Figure 4 , Figure 4 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 4 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 4A processor 10 is taken as an example.

[0178] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0179] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0180] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0181] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0182] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0183] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0184] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0185] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A sensitive path judgment method based on a truth table, characterized in that: The method comprises: Obtaining a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table; the truth table data is used to represent the mapping relationship between all input combinations and output values of the corresponding target lookup table; Performing binary bit operations on the input combination of the target lookup table to obtain at least one set of verification data; the verification data includes a verification input combination and a verification output; Based on the at least one set of verification data and the truth table data, obtaining a sensitivity analysis result; the sensitivity analysis result includes positive monotonically increasing, negative monotonically increasing, and non-monotonic; Based on the sensitivity analysis result, a timing arc type of a timing path corresponding to the target lookup table is determined.

2. The method according to claim 1, characterized in that The performing binary bit operations on the input combination of the target lookup table to obtain at least one set of verification data includes: Obtain the target input combination and the corresponding target output value from the target lookup table; Flipping the target input value of the target input port in the target input combination and keeping the input values of the remaining input ports unchanged to obtain a verification input combination; According to the truth table data, obtaining the verification output corresponding to the verification input combination; The obtaining the sensitivity analysis result based on the at least one set of verification data and the truth table data includes: Traversing all input combinations of the target lookup table, and obtaining comparison results based on each input combination, the flipped input combination, the output value, and the verification output; The sensitivity analysis result is obtained based on the comparison results.

3. The method according to claim 2, characterized in that Obtaining the sensitivity analysis result based on the comparison results includes: If all the comparison results are positively monotonically increasing, then the sensitivity analysis result is positively monotonically increasing; If all the comparison results are negative monotonically increasing, then the sensitivity analysis result is negative monotonically increasing; If the comparison results show both positive monotonically increasing and negative monotonically increasing trends, the sensitivity analysis result is non-monotonic.

4. The method according to claim 3, characterized in that The steps of traversing all input combinations of the target lookup table and obtaining comparison results based on each input combination, the flipped input combination, the output value, and the verification output include: Comparing the input combination with the flipped input combination to determine the input flip type; the input flip type includes rising edge and falling edge; Comparing the output value and verifying the output to determine the output flip type; the output flip type includes rising edge and falling edge; The comparison result is determined based on the input flip type and the output flip type.

5. The method according to claim 4, characterized in that The determining the comparison result based on the input flip type and the output flip type includes: If the input flip type is the same as the output flip type, the comparison result is positive monotonically increasing; If the input flip type is different from the output flip type, the comparison result is negative monotonically increasing.

6. The method according to any one of claims 2 to 5, characterized in that: The determining, based on the sensitivity analysis result, the timing arc type of the timing path corresponding to the target lookup table includes: When the monotonicity of the input and output ports corresponding to the target timing path in each lookup table is consistent, the timing arc type of the target timing path is a positive function timing arc or a negative function timing arc; When the monotonicity of the input and output ports corresponding to the target timing path in the target lookup table is inconsistent, the timing arc type of the target timing path is a non-function timing arc.

7. The method according to claim 6, characterized in that The method further comprises: If there is a non-function timing arc in the timing path corresponding to the target lookup table, the non-function timing arc is removed during the timing analysis process.

8. A sensitive path judgment device based on a truth table, characterized in that: The device comprises: An acquisition path module acquires a target lookup table in a circuit netlist and truth table data corresponding to the target lookup table; the target timing path is composed of various lookup tables; the truth table data is used to represent the mapping relationship between all input combinations and output values of the corresponding target lookup table; an operation module, performing a binary bit operation on the input combination of the target lookup table to obtain at least one set of verification data; the verification data includes a verification input combination and a verification output; An analysis module, configured to obtain the sensitivity analysis result based on the at least one set of verification data and the truth table data; the sensitivity analysis result includes positive monotonically increasing, negative monotonically increasing, and non-monotonic; A judgment module is used to judge the timing arc type of the timing path corresponding to the target lookup table based on the sensitivity analysis result.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes a sensitive path judgment method based on a truth table according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute a sensitive path judgment method based on a truth table according to any one of claims 1 to 7.

Images