Digital-to-analog converter (DAC) with adaptive calibration scheme

Abstract

Methods and apparatus are provided for controlling a supply voltage for a switch driver in a digital-to-analog converter (DAC). An example DAC generally includes a plurality of DAC cells, each DAC cell including: a current source; a first switch coupled in series with the current source at a first node; and a switch driver having an output coupled to a control input of the first switch; and a calibration circuit having a first input coupled to a first DAC unit of the plurality of DAC units and having an output coupled to at least one DAC unit of the plurality of DAC units, the calibration circuit is configured to sense a voltage of the first node in the first DAC cell and control the supply voltage for the switch driver in the at least one DAC cell of the plurality of DAC cells based on the sensed voltage of the first node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 806,679 filed on June 13, 2022, which is hereby incorporated by reference into this document. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to techniques and apparatus for controlling a supply voltage for a switch driver in a digital-to-analog converter (DAC). Background Art

[0004] Wireless communication devices are widely deployed to provide various communication services, such as telephony, video, data, messaging, broadcast, etc. Such wireless communication devices may send and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, Wireless Local Area Network (WLAN) RATs (e.g., WiFi), etc.

[0005] A wireless communication network may include multiple base stations that can support communications for multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. A downlink (or forward link) refers to a communication link from a base station to a mobile station, while an uplink (or reverse link) refers to a communication link from a mobile station to a base station. A base station may send data and control information to a mobile station on a downlink, and / or may receive data and control information from a mobile station on an uplink. A base station and / or a mobile station may include a transmit digital-to-analog converter (TX DAC), which may be used, for example, to convert a digital signal into an analog signal for signal processing (e.g., filtering, up-conversion, and amplification) before being transmitted by one or more antennas. Summary of the invention

[0006] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desired characteristics. Without limiting the scope of the present application as expressed by the claims that follow, some features will now be briefly discussed. After considering this discussion, and especially after reading the section entitled "Detailed Description," one will understand how the features of the present disclosure provide advantages including lower distortion at operation corners without significantly increasing the area or power consumption of a digital-to-analog converter (DAC).

[0007] Certain aspects of the present disclosure provide a DAC. The DAC generally includes a plurality of DAC cells, each DAC cell including: a current source; a first switch coupled in series with the current source at a first node; and a switch driver having an output coupled to a control input of the first switch. The DAC also generally includes a calibration circuit having a first input coupled to a first DAC cell among the plurality of DAC cells and having an output coupled to at least one DAC cell among the plurality of DAC cells. The calibration circuit can be configured to sense a voltage of a first node in the first DAC cell, and to control a power supply voltage for a switch driver in the at least one DAC cell among the plurality of DAC cells based on the voltage of the first node in the first DAC cell.

[0008] Certain aspects of the present disclosure provide a wireless device that includes a DAC as described herein, one or more antennas, and one or more transmission paths coupled between one or more outputs of the DAC and the one or more antennas.

[0009] Certain aspects of the present disclosure provide a method of operating a DAC. The DAC generally includes a plurality of DAC cells, each DAC cell including: a current source; a switch coupled in series with the current source at a first node; and a switch driver having an output coupled to a control input of the first switch. The method generally includes controlling a power supply voltage for a switch driver in at least one of the plurality of DAC cells based on a voltage of a first node in the first DAC cell.

[0010] Certain aspects of the present disclosure provide a device for digital-to-analog conversion. The device generally includes a plurality of DAC units, each DAC unit including a component for emitting a current, a component for switching coupled in series with the component for emitting the current at a node, and a component for driving the component for switching. The device also includes a component for the following operation: based on the voltage of a node in the first DAC unit, a power supply voltage of a component for driving a component for switching in at least one DAC unit of the plurality of DAC units is controlled.

[0011] To achieve the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail some illustrative features of one or more aspects. However, these features are merely indicative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, a more specific description briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered as limiting the scope thereof, as the specification may admit to other equally effective aspects.

[0013] Figure 1 is an illustration of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0014] Figure 2 is a block diagram conceptually illustrating designs of example base stations (BSs) and user equipment (UEs) in which aspects of the present disclosure may be practiced.

[0015] Figure 3 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced.

[0016] Figure 4 is a schematic diagram of an example current-steering digital-to-analog converter (DAC) in which aspects of the present disclosure may be practiced.

[0017] Figure 5A An example current-steering DAC with calibration circuitry according to certain aspects of the present disclosure is illustrated.

[0018] Figure 5B Illustrate some aspects of the present disclosure for implementing Figure 5A An example circuit of a calibration circuit.

[0019] Figure 6is a flow chart of example operations for operating a DAC in accordance with certain aspects of the present disclosure.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0021] Certain aspects of the present disclosure relate to techniques and apparatus for adaptively adjusting (eg, calibrating) a supply voltage (eg, a reference potential) for a switch driver in a digital-to-analog converter (DAC), such as a current-steering DAC.

[0022] The various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms, and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. Instead, these aspects are provided so that the present disclosure will be thorough and complete, and the protection scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods implemented using other structures, functions, or structures and functions in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present invention.

[0023] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0025] Example Wireless System

[0026] Figure 1An example wireless communication network 100 in which aspects of the present disclosure may be practiced is illustrated. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to IEEE standards such as one or more of the 802.11 standards.

[0027] like Figure 1 As shown in , the wireless communication network 100 may include several base stations (BSs) 110a to 110z (each also individually referred to as BS 110 or collectively referred to as BS 110 herein) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB) or some other terminology.

[0028] BS 110 may provide communication coverage for a particular geographic area (sometimes referred to as a "cell"), which may be stationary or may move depending on the location of mobile BS 110. In some examples, BS 110 may be interconnected with each other and / or connected to one or more other BSs or network nodes (not shown) in wireless communication network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network. Figure 1 In the example shown, BSs 110a, 110b, and 110c may be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x may be a pico BS for pico cell 102x. BSs 110y and 110z may be femto BSs for femto cells 102y and 102z, respectively. A BS may support one or more cells.

[0029] The BS 110 communicates with one or more user equipment (UE) 120a to 120y (each also individually or collectively referred to herein as UE 120) in the wireless communication network 100. A UE may be fixed or mobile, and may also be referred to as a user terminal (UT), a mobile station (MS), an access terminal, a station (STA), a client, a wireless device, a mobile device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smart phone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet computer, a personal computer, etc.

[0030] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a "transmitting entity" is an independently operated device or apparatus capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates a downlink, and the subscript "up" indicates an uplink. N may be selected. up UEs are used for simultaneous transmission on the uplink, N dn UEs are used for simultaneous transmission on the downlink. up May or may not be equal to N dn , and N up and N dn It may be a static value or may change for each scheduling interval.Beam steering or some other spatial processing technique may be used at the BS 110 and the UE 120.

[0031] UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include a relay station (e.g., relay station 110r) (also referred to as a repeater, etc.) that receives transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and transmits transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110), or relays transmissions between UEs 120 to facilitate communication between devices.

[0032] BS 110 may communicate on the downlink and uplink with one or more UEs 120 at any given moment. The downlink (i.e., forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., reverse link) is the communication link from UE 120 to BS 110. A UE 120 may also communicate peer-to-peer with another UE 120.

[0033] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. The BS 110 may be equipped with several (N ap A group of (N) antennas can be used to implement transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u Each UE 120 may receive downlink transmissions and send uplink transmissions. Each UE 120 may send user-specific data to and / or receive user-specific data from BS 110. Typically, each UE 120 may be equipped with one or more antennas. uThe UEs 120 may have the same or different numbers of antennas.

[0034] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to reduce costs) or multiple antennas (e.g., where additional costs can be supported).

[0035] The network controller 130 (sometimes also referred to as a "system controller") may communicate with a set of BSs 110 and provide coordination and control (e.g., via backhaul) for these BSs 110. In some cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In some aspects, the network controller 130 may communicate with a core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network open functions, network repository functions, network slice selection functions, etc.

[0036] In certain aspects of the present disclosure, BS 110 and / or UE 120 may include a digital-to-analog converter (DAC) with an adaptive calibration scheme, as described in greater detail herein.

[0037] Figure 2 1 and 120a (eg, from a BS 110a) in which various aspects of the present disclosure may be practiced. Figure 1 Example components of a wireless communication network 100).

[0038] On the downlink, at BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be transmitted on different transport channels. For example, control information may be designated for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. Data may be designated for a physical downlink shared channel (PDSCH), etc. A medium access control (MAC)-control element (MAC-CE) is a MAC layer communication structure that may be used for the exchange of control commands between wireless nodes. The MAC-CE may be carried in a shared channel such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0039] The processor 220 may process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS).

[0040] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 may perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and may provide an output symbol stream to a modulator (MOD) in a transceiver 232a-232t. Each modulator 232a-232t in the transceiver may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM) or the like) to obtain an output sample stream. Each transceiver 232a-232t may further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signals from the transceivers 232a-232t may be transmitted via antennas 234a-234t, respectively.

[0041] At UE 120a, antennas 252a-252r may receive downlink signals from BS110a and may provide received signals to transceivers 254a-254r, respectively. Transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 may obtain received symbols from all demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols (where applicable), and provide detected symbols. Receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to data sink 260, and provide decoded control information to controller / processor 280.

[0042] On the uplink, at the UE 120a, a transmit processor 264 may receive and process data from a data source 262 (e.g., for a physical uplink shared channel (PUSCH)) and control information from a controller / processor 280 (e.g., for a physical uplink control channel (PUCCH)). The transmit processor 264 may also generate reference symbols for reference signals (e.g., for a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be pre-decoded by a TX MIMO processor 266 (if applicable), further processed by a modulator (MOD) in the transceivers 254a to 254r (e.g., for single carrier frequency division multiplexing (SC-FDM), etc.), and transmitted to the BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators in transceivers 232a-232t, detected by MIMO detector 236 (if applicable), and further processed by receive processor 238 to obtain decoded data and control information transmitted by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to controller / processor 240.

[0043] Memories 242 and 282 may store data and program codes for BS 110a and UE 120a, respectively. Memories 242 and 282 may also interface with controllers / processors 240 and 280, respectively. Scheduler 244 may schedule UEs for data transmission on the downlink and / or uplink.

[0044] The antennas 252, processors 258, 264, 266 and / or controller / processor 280 of the UE 120a and / or the antennas 234, processors 220, 230, 238 and / or controller / processor 240 of the BS 110a may be used to perform the various techniques and methods described herein.

[0045] In certain aspects of the present disclosure, transceiver 232 and / or transceiver 254 may include a digital-to-analog converter (DAC) with adaptive calibration circuitry, as described in greater detail herein.

[0046] NR can use orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) on the uplink and downlink. NR can use time division duplex (TDD) to support half-duplex operation. OFDM and single carrier frequency division multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are also commonly referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into subbands. For example, one subband can cover multiple resource blocks (RBs).

[0047] Example RF Transceiver

[0048] Figure 3 is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of the present disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a “transmit chain”) for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a “receive chain”) for receiving signals via antenna 306. When TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via interface 308, which can include any of a variety of suitable RF devices, such as switches, duplexers, diplexers, multiplexers, etc.

[0049] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included in a radio frequency integrated circuit (RFIC). For certain aspects, the PA 318 may be external to the RFIC.

[0050] For certain aspects, DAC 310 can be implemented by any of a variety of suitable high-speed DAC topologies, such as a current-steering DAC. For certain aspects, DAC 310 can be implemented with a calibration circuit for calibrating a supply voltage (e.g., a reference potential) for a switch driver of DAC 310, as described in more detail below.

[0051] The BBF 312 filters the baseband signal received from the DAC 310, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process produces sum and difference frequencies between the LO frequency and the frequency of the baseband signal of interest. The sum and difference frequencies are referred to as "beat frequencies." The beat frequencies are typically in the RF range, so that the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or by the PA 318 before being transmitted by the antenna 306. Although one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and thereafter upconvert the intermediate frequency (IF) signal to a frequency for transmission.

[0052] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC that includes the TX path components, or may be a different RFIC. The RF signal received via the antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-convert). The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to a digital I and / or Q signal by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0053] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by the amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by the amplifier 334 before being mixed with the RF signal in the mixer 326. For some aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In some aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0054] Controller 336 (eg, Figure 2 Controller / processor 280 in the RF transceiver circuit 300A may direct the operation of the RF transceiver circuit 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. Controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. Memory 338 (e.g., Figure 2 The memory 282 in the controller 336 may store data and / or program codes for operating the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (eg, complementary metal oxide semiconductor (CMOS) logic).

[0055] Although Figures 1 to 3 Wireless communication in which certain aspects of the present disclosure may be implemented is provided as an example application to facilitate understanding, but certain aspects described herein may be used for digital-to-analog conversion in any of a variety of other suitable systems (e.g., audio systems or other electronic systems).

[0056] Example DAC with calibration circuit

[0057] A current-steering digital-to-analog converter (DAC) is an example architecture used in many wireless transmitters for high-performance digital-to-analog conversion. A current-steering DAC provides design versatility, high-speed operation, and high performance. Although a current-steering DAC is described as an example type of DAC in which aspects of the present disclosure may be implemented, it should be understood that aspects of the present disclosure may also be applied to other suitable types of DACs.

[0058] Figure 4 An example current steering DAC 400 (eg, which may implement Figure 3 The core of the DAC 400 includes a number n of current steering DAC units 4041 to 404 n (collectively referred to as "current steering DAC cells 404"), where n is an integer greater than 1. Each DAC cell 404 can represent a different bit for DAC 400, and thus at least some of the DAC cells can also be referred to as "most significant bit (MSB) cells". Each DAC cell 404 can include a current source 406, a switch driver 410, and at least one current steering switch 408a. In some aspects, the current steering switch 408a can be part of a pair of differential current steering switches. That is, each DAC cell can also optionally include a complementary current steering switch 408b that operates differentially with the current steering switch 408a, such as Figure 4 For ease of description, the current steering switches 408a and 408b may be collectively referred to as “current steering switches 408”.

[0059] The switch driver 410 may receive power from a first power rail (labeled "VDDD" to indicate the digital domain power rail), while the current source 406 and the switch 408 may receive power from a second power rail (labeled "VDDA" to indicate the analog domain power rail). In some aspects, the VDDA power rail may have a higher voltage than the VDDD power rail. As shown, a controlled current source (labeled "CalDAC") may also be coupled between the second power rail and the current source 406 and may be used as a calibration DAC to adjust the current effectively supplied by the current source 406 via the current steering switch 408.

[0060] The switch driver 410 may include multiple stages, including a final stage 412, which may have a first supply voltage (e.g., a reference potential labeled “VSS_LDO”) that is different from a second supply voltage (e.g., another reference potential labeled “VSS”) used for other stages of the switch driver 410. In some aspects, as Figure 4 As shown in FIG. 4 , the final stage 412 may be implemented as a complementary metal oxide semiconductor (CMOS) inverter. The switch driver 410 may generally be used to improve the dynamic performance of the current steering DAC 400. For example, the switch driver 410 may be used to reduce signal feedthrough, reduce current source node settings, reduce local and global timing errors, etc. The switch driver 410 may receive a digital input signal and a clock signal and generate one or more output signals (e.g., such as gates of transistors implementing switches) that drive the control inputs of one or more current steering switches in the current steering switch 408. Figure 4 The complementary output signals are shown in FIG. 1 and are labeled “q” and “qb” respectively.

[0061] Based on the digital input signal, each bit of the DAC 400 associated with the current steering DAC cell 404 can control one or more of the current steering switches 408 of the corresponding cell to source or block current from the cell's current source 406 to the output of the DAC cell 404. The currents sourced from the individual DAC cells 404 can be combined (e.g., using current summing) to provide an analog output signal at the DAC output. The DAC output can be coupled to a baseband filter (e.g., Figure 3 Any suitable circuit in the BBF312) or various other suitable circuits.

[0062] The current source 406 may be coupled in series with one or more of the current steering switches 408 at a first node 414 (also referred to as a “common source node”) having a common source voltage (labeled “vs”). The current source 406 may be a cascaded current source implemented by a first transistor Mcs and a second transistor Mcsc having a source coupled to a drain of the first transistor Mcs at a second node 416. The first transistor Mcs and the second transistor Mcsc may be any type of suitable transistor, such as Figure 4 Each transistor in the cascade transistors may have a control input (e.g., the gates of transistors Mcs and Mcsc) that may receive a control input signal (the bias voltage signals labeled “vb1” and “vb2”) that controls the amount of current sourced by current source 406.

[0063] One or more of the current steering switches 408 may also be made of transistors such as Figure 4 408 is implemented as a PMOS transistor as shown in . In this case, the source of the current steering switch 408 can be coupled in series to the current source 406 (and more specifically to the drain of the transistor Mcsc). As shown, the current steering switch 408 can also be coupled to a load having a common mode voltage source (labeled as "Vcm"). A differential output signal (labeled as "voutp" and "voutm") can be generated at a differential output node (e.g., at the drain of the current steering switch 408).

[0064] Non-ideal factors in a DAC can reduce the signal-to-noise-distortion ratio (SNDR) and distortion performance (e.g., spurious-free dynamic range (SFDR)) of the DAC, and thus can reduce the effective number of bits (ENOB) of the DAC. Therefore, such non-ideal factors can also degrade the performance of a transmitter system in which the DAC is implemented. An example non-ideal factor is distortion at the common source node (first node 414) of each DAC cell. During output switching of the current steering switch 408 between the positive output and the negative output, charge redistribution can generate interference at the common source node. The interference (e.g., Δvs) at the common source node is signal-dependent and can significantly contribute to the dynamic nonlinearity of the DAC. The interference at the common source node from the output swing can be expressed as:

[0065]

[0066] where g m and g ds is the transconductance of the current steering switch 408, and Δvoutp is the output swing. Therefore, to reduce the interference at the common source node, the DAC 400 can be designed so that g m With g ds The ratio is greater than 1 (and preferably as large as possible without affecting the headroom of the DAC unit).

[0067] For some implementations, to reduce this interference, the voltage (e.g., VSS_LDO) supplied to the last stage 412 of the switch driver 410 is fixed to a specific value (e.g., 200 mV) to push the current steering switch 408 into operating in the saturation region. However, increasing the voltage at VSS_LDO will reduce the headroom of the current source 406 (e.g., by reducing the drain-to-source voltage of the transistor Mcsc). In addition, the operating region of the transistor (e.g., implementing the current steering switch 408) is highly dependent on process, voltage, and temperature (PVT) variations.

[0068] Certain aspects of the present disclosure provide techniques and circuits for ensuring that the voltage of a common source node (or the drain-to-source voltage of transistor Mcsc) is equal to (or at least approximately equal to) or less than a preset direct current (DC) voltage (e.g., a "reference voltage" or "calibration voltage"). The preset DC voltage may be selected to optimize (or at least improve) the tradeoff between the interference at the common source node and the headroom of the current source 406 across operating corners and PVT variations. Therefore, certain aspects of the present disclosure provide techniques and circuits for calibrating the supply voltage of a switch driver in one or more DAC cells for a current steering DAC (e.g., calibrating the VSS_LDO of the last stage 412 in one or more switch drivers in the switch driver 410). The calibration may improve dynamic DAC performance across PVT variations in the DAC core (such as the PVT of the current steering switch 408 of the DAC cell). In addition, the calibration may be performed once during factory calibration (e.g., no additional or repeated calibration is required), and the calibration circuit may contribute relatively small area and power consumption.

[0069] Figure 5A An example DAC 500A according to aspects of the present disclosure is illustrated. DAC 500A may be similar to DAC 400, but with the addition of calibration circuit 510. As shown, calibration circuit 510 may have at least one input coupled to at least one DAC cell 404 of the plurality of DAC cells 404, and may have an output coupled to at least one DAC cell of the plurality of DAC cells 404.

[0070] Specifically, the calibration circuit 510 may have a first input terminal coupled to a first node 414 between the current source 406 (e.g., at the drain of the transistor Mcsc) and the current steering switch 408 (e.g., at the source of the transistor implementing the current steering switch 408) in the first DAC cell 4041. The calibration circuit 510 may also have an output terminal coupled to a power supply input terminal of at least one stage (e.g., the last stage 412) of the switch driver 410 in one or more DAC cells (e.g., the first DAC cell 4041 or all DAC cells 404) in the DAC cells. The calibration circuit 510 may be configured to sense a voltage of the first node 414 in the first DAC cell 4041, and control a power supply voltage (e.g., VSS_LDO) for the switch driver 410 in at least one DAC cell of the plurality of DAC cells 404 based on the voltage of the first node 414 in the first DAC cell 4041.

[0071] For example, the calibration circuit 510 may be configured to compare the voltage at the first node 414 with a reference voltage and increase the supply voltage for the switch driver 410 until the voltage at the first node 414 is greater than or equal to the reference voltage. The reference voltage may be selected to cover PVT variations and random mismatches of various components (such as transistor Mcs, transistor Mcsc) and non-ideal factors from the calibration circuit 510.

[0072] As shown, the calibration circuit 510 may optionally have a second input coupled to a second node 416 located between the cascade transistors of the current source 406 (e.g., between the drain of transistor Mcs and the source of transistor Mcsc). In this case, the calibration circuit 510 may be configured to sense a differential voltage between the first node 414 and the second node 416 in the first DAC unit 4041. The calibration circuit 510 may be further configured to control a supply voltage for a switch driver 410 in one or more of the DAC units 404 based on a voltage difference between the voltage of the first node 414 and the voltage of the second node 416 in the first DAC unit 4041. The voltage difference between the voltage of the first node 414 and the voltage of the second node 416 may also be referred to as a drain-to-source voltage (Vds) of the transistor Mcsc.

[0073] In some aspects, the calibration circuit 510 can be configured to adjust the supply voltage (e.g., VSS_LDO) of the switch driver 410 in response to determining that the voltage difference between the voltage of the first node 414 and the voltage of the second node 416 is greater than a reference voltage. The reference voltage can be set, for example, to a value that ensures that the transistor Mcsc operates in the saturation region across PVT variations. In some aspects, the calibration circuit 510 can be configured to iteratively compare the reference voltage and the voltage difference between the voltage of the first node 414 and the voltage of the second node 416, and increase the supply voltage until the voltage difference between the voltage of the first node 414 and the voltage of the second node 416 is less than or equal to the reference voltage.

[0074] In some aspects, the calibration circuit 510 may be coupled to all of the DAC cells 404. In this case, the calibration circuit 510 may be configured to adjust the supply voltage of the switch driver 410 in one or more of the DAC cells 404 based on the sense voltages from all of the DAC cells 404. For example, the supply voltage for the switch driver 410 in each DAC cell 404 may be calibrated based on the one or more sense voltages from the corresponding DAC cells 404. While this implementation balances parasitic capacitance and prevents one or more outliers from compromising the performance of the DAC 500A (e.g., by accounting for Vds and accounting for Vds mismatches between all of the DAC cells 404), the layout of the calibration circuit 510 may be complex and / or may significantly increase calibration time (e.g., if several DAC cells 404 in the DAC 500A are calibrated one at a time).

[0075] In other aspects, the calibration circuit 510 may be coupled to a single DAC cell 404 (e.g., the first DAC cell 4041). In this case, the calibration circuit 510 may be configured to adjust the supply voltage of the switch driver 410 in one or more of the DAC cells 404 based on one or more sense voltages (e.g., a single voltage or a differential voltage) from the single DAC cell. While this implementation provides a compact layout and short calibration time, mismatched parasitics and / or mismatched Vds between the DAC cells 404 may result in degraded performance of the DAC 500A (e.g., if the sensed Vds of a single DAC cell is an outlier).

[0076] In yet another example aspect, the calibration circuit 510 may be coupled to a selected set of DAC cells 404 (e.g., three DAC cells 404). In this case, the calibration circuit 510 may be configured to adjust the supply voltage of the switch driver 410 in one or more of the DAC cells 404 based on the sense voltage from the selected DAC cell 404. For example, the supply voltage for the switch driver 410 in each DAC cell 404 may be calibrated based on one or more sense voltages from a selected set of DAC cells 404. In some examples, each DAC cell 404 may be calibrated based on one or more voltages from the selected set of DAC cells 404 that are sized most similar to the DAC cell 404 being calibrated. This implementation may provide the balance between mismatch, accuracy, layout complexity, and calibration time discussed above with respect to other example implementations.

[0077] In some aspects, the first input and / or the second input of the calibration circuit 510 may be optionally coupled to one or more DAC units 404 via switches 502 and 504. Switches 502 and 504 may be implemented by any of a transmission gate or other various suitable components (such as a PMOS switch). Implementing switches 502, 504 with a smaller transistor size may introduce a smaller parasitic capacitance to the transistor Mcsc and the common source node. According to certain aspects, switches 502 and 504 may be configured to be in a closed state in response to receiving an indication that DAC 500A is in calibration mode (labeled "EN_cal"). In some aspects, switches 502 and 504 may be considered as part of the calibration circuit 510. In other aspects, switches 502 and 504 may be part of the DAC unit 404, so that one or more DAC units may be selected to calibrate the supply voltage, as described above. In this case, switches 502 and 504 may be replicated and appear in more than one DAC unit.

[0078] Figure 5B A DAC 500B is illustrated with example circuitry for implementing a calibration circuit 510 in accordance with certain aspects of the present disclosure. As shown, the calibration circuit 510 may generally include a differential amplifier 515, a comparator 520, a digital logic component 525, and a voltage control module 530.

[0079] The differential amplifier 515 may have a first input terminal coupled to the first node 414 (e.g., at the drain of the transistor Mcsc) in the first DAC cell 4041, and may have a second input terminal coupled to the second node 416 (e.g., at the source of the transistor Mcsc) in the first DAC cell 4041. The differential amplifier 515 may be configured to output a voltage difference between a voltage of the first node 414 and a voltage of the second node 416.

[0080] The comparator 520 may have a first input coupled to the output of the differential amplifier 515, and may have a second input coupled to a reference voltage source configured to output a reference voltage (labeled "Vcal"). The comparator 520 may be configured to compare the voltage difference between the voltage of the first node 414 and the voltage of the second node 416 (as output by the differential amplifier 515) with the reference voltage, and output an indication of the comparison result. For example, the comparator 520 may be configured to output a logic "0" when the voltage difference between the voltage of the first node 414 and the voltage of the second node 416 is less than or equal to the reference voltage. The comparator may also be configured to output a logic "1" when the voltage difference between the voltage of the first node 414 and the voltage of the second node 416 is greater than the reference voltage.

[0081] The digital logic component 525 may have an input coupled to the output of the comparator 520, and may have an output coupled to the input of the voltage control module 530. The digital logic component 525 may be configured to output a digital signal representing a voltage to be output by the voltage control module 530 based on the output of the comparator 520. If more than one DAC unit is sensed, the digital logic component 525 may have a corresponding number of memories to store calibration results for each sensing DAC unit. In this case, the digital logic component 525 may be configured to process (e.g., average) the stored results to output a single voltage output to the voltage control module 530. The voltage control module 530 may be configured to convert the digital signal at the output of the digital logic component 525 into a supply voltage for the switch driver 410. In some aspects, the voltage control module 530 may be implemented by a DAC such as a ground low dropout (ground LDO or GND LDO) DAC or a voltage regulator (LDO regulator). In other aspects, the voltage control module 530 may be implemented by a lookup table such that the output of the digital logic component 525 corresponds to a voltage in the lookup table, which the voltage control module 530 may then output.

[0082] Continuing with the above example, if the comparator 520 outputs a logic "1", the digital logic component 525 can be configured to output a digital signal representing a voltage greater than the voltage being generated by the voltage control module 530. In other words, in response to determining (by the comparator 520) that the voltage difference between the voltage of the first node 414 and the voltage of the second node 416 is greater than the reference voltage, the digital logic component 525 can instruct the voltage control module 530 to increase the power supply voltage (e.g., VSS_LDO) for the switch driver 410. The increase can be according to a predefined step size (e.g., 50mV) each iteration through the calibration cycle. For certain aspects, the starting point of the power supply voltage for the first iteration can be a minimum value (e.g., VSS_LDO=0V).

[0083] Once the voltage control module 530 has increased the supply voltage, the above process may be repeated in an iterative manner until the comparator 520 outputs a logic "0" indicating that the voltage difference between the voltage at the first node 414 and the voltage at the second node 416 is less than or equal to the reference voltage. If calibration of a single DAC unit is selected, the digital logic component 525 may be configured to instruct the voltage control module 530 to continue generating (e.g., maintaining) the current supply voltage.

[0084] If multiple DAC units are selected to be calibrated, the digital logic component 525 can be configured to store the results of each DAC unit calibration (e.g., a code indicating the value of VSS_LDO) in a memory, and repeat the process in each of the selected DAC units until all selected DAC units are calibrated. The digital logic component 525 can be further configured to process (e.g., average) the stored code to generate an output code to output to the voltage control module 530. Then, when the DAC 500B operates in the mission mode, the voltage control module 530 can use the output code to generate the power supply voltage indicated by the output code.

[0085] As shown, each DAC unit 404 may optionally include a first switch 552 and a second switch 554. That is, the first input terminal and / or the second input terminal of the calibration circuit 510 may optionally be coupled to one or more DAC units 404 via switches 552 and 554. Switches 552 and 554 may be implemented as transmission gates, as described above. According to certain aspects, switches 552 and 554 may be configured to be in a closed state in response to receiving an indication that the DAC 500B is in calibration mode (labeled "EN_cal").

[0086] According to certain aspects, the calibration circuit 510 may be coupled to more than one DAC cell 404. That is, a first input of the calibration circuit 510 may be selectively coupled to the first DAC cell 4041 and selectively coupled to a second DAC cell (e.g., the second DAC cell 4042) of the plurality of DAC cells 404 (e.g., via switches 552 and / or 554). In this case, the calibration circuit 510 may be configured to sense a voltage of the first node 414 in the second DAC cell 4042 (in addition to or in lieu of sensing a voltage of the first node 414 in the first DAC cell 4041) and control a supply voltage for the switch driver 410 in one or more of the DAC cells 404 based on the voltage of the first node 414 in the first DAC cell 4041 and / or the voltage of the first node 414 in the second DAC cell 4042.

[0087] For ease of description, the above example refers to DAC unit 4041 as a “first DAC unit 4041” and DAC unit 4042 as a “second DAC unit 4042”. However, a person skilled in the relevant art will understand that any one of the DAC units 404 may be considered a “first DAC unit” and any one of the DAC units 404 may be considered a “second DAC unit”. That is, in other examples, the input of the calibration circuit 510 may be coupled to the first node 414 and / or the second node 416 in any one or more of the DAC units 404 (not only the DAC unit 4041 and / or the DAC unit 4042).

[0088] Compared to some other DAC switch biasing solutions, aspects of the present disclosure with calibration circuits for the supply voltage of the switch driver provide increased signal-to-noise-distortion ratio (SNDR) and lower distortion at operating corners. Compared to some other DAC switch biasing schemes, aspects of the present disclosure may also provide reduced switching noise, smaller area, lower supply voltage, lower quiescent current, and / or lower peak load current.

[0089] Example Transformation Operation

[0090] Figure 6 6 is a flow chart of example operations 600 for operating a DAC (e.g., DAC 500A or 500B) according to certain aspects of the present disclosure. The DAC generally includes a plurality of DAC cells (e.g., DAC cell 404), and each DAC cell may include a current source (e.g., current source 406), a first switch (e.g., current steering switch 408a or 408b) coupled in series with the current source at a first node (e.g., first node 414), and a switch driver (e.g., switch driver 410) having an output coupled to a control input (e.g., gate) of the first switch. Operation 600 may be performed, for example, by a DAC with a calibration circuit as described above (e.g., DAC 500A or DAC 500B with calibration circuit 510).

[0091] Operations 600 may generally involve controlling a supply voltage (e.g., a reference potential such as VSS_LDO) for a switch driver in at least one DAC cell of the plurality of DAC cells based on a voltage (e.g., a common source voltage vs) of a first node in a first DAC cell (e.g., first DAC cell 4041) at block 602. The first DAC cell need not be a most significant bit (MSB) cell (i.e., the first DAC cell may be any of the DAC cells).

[0092] According to certain aspects, operation 600 may involve sensing a voltage of a first node in a first DAC cell. In this case, controlling may involve controlling a supply voltage for the switch driver in the at least one DAC cell of the plurality of DAC cells based on the sensed voltage of the first node in the first DAC cell at block 604. In certain aspects, controlling may involve providing a supply voltage to a last stage (e.g., last stage 412) of a switch driver in the at least one DAC cell of the plurality of DAC cells.

[0093] According to certain aspects, the current source may be a cascade current source including a first transistor (e.g., transistor Mcs) and a second transistor (e.g., transistor Mcsc). The second transistor may have a source coupled to the drain of the first transistor at a second node (e.g., second node 416). In some aspects, operation 600 may further involve sensing the voltage of the second node in the first DAC unit. In this case, control may involve controlling the power supply voltage for the switch driver based on the voltage difference (e.g., Vds) between the voltage of the first node and the voltage of the second node at box 606. For certain aspects, control may further involve determining at box 608 that the voltage difference between the voltage of the first node and the voltage of the second node is greater than a reference voltage (e.g., Vcal), and increasing the power supply voltage in response to the determination at box 610.

[0094] According to certain aspects, operation 600 may involve iteratively comparing a reference voltage and a voltage difference between a voltage at a first node and a voltage at a second node. In this case, operation 600 may further involve increasing the power supply voltage until the voltage difference between the voltage at the first node and the voltage at the second node is less than or equal to the reference voltage.

[0095] According to certain aspects, operation 600 may involve amplifying a voltage difference between a first node and a second node with a differential amplifier (e.g., differential amplifier 515). In this case, operation 600 may further involve comparing the amplified voltage difference with a reference voltage (e.g., Vcal) (e.g., via comparator 520) and outputting a digital logic signal based on the comparison (e.g., via digital logic component 525). In this case, controlling may include controlling a supply voltage for a switch driver based on the digital logic signal.

[0096] In certain aspects, sensing the voltage at the first node may involve closing a second switch (e.g., switch 504 or switch 554) coupled between the first node in the first DAC cell and the first input of the differential amplifier, and sensing the voltage at the second node may involve closing a third switch (e.g., switch 502 or switch 552) coupled between the second node in the first DAC cell and the second input of the differential amplifier.

[0097] According to certain aspects, operation 600 may involve sensing a voltage of a first node in a second DAC cell (e.g., DAC cell 4042). In this case, the control at block 602 may involve controlling a power supply voltage for a switch driver in at least one of the plurality of DAC cells based on the sensed voltage of the first node in the first DAC cell and the sensed voltage of the first node in the second DAC cell. The current source in the second DAC cell may be a cascaded current source including a first transistor and a second transistor, and the second transistor may have a source coupled to the drain of the first transistor at a second node. In this case, operation 600 may further involve sensing a voltage of a second node in the first DAC cell and sensing a voltage of a second node in the second DAC cell. In this case, the control may involve controlling a power supply voltage for the switch driver based on a first voltage difference between a voltage of the first node in the first DAC cell and a voltage of the second node in the first DAC cell and a second voltage difference between a voltage of the first node in the second DAC cell and a voltage of the second node in the second DAC cell.

[0098] Example aspects

[0099] In addition to the above-mentioned aspects, specific combinations of the aspects are also within the scope of the present disclosure, and the details of some of the specific combinations are as follows:

[0100] Aspect 1: A digital-to-analog converter (DAC), comprising: a plurality of DAC cells, each DAC cell comprising: a current source; a first switch, the first switch being coupled in series with the current source at a first node; and a switch driver, the switch driver having an output terminal coupled to a control input terminal of the first switch; and a calibration circuit, the calibration circuit having a first input terminal coupled to a first DAC cell among the plurality of DAC cells and having an output terminal coupled to at least one DAC cell among the plurality of DAC cells, the calibration circuit being configured to sense a voltage of the first node in the first DAC cell and to control a power supply voltage of the switch driver in the at least one DAC cell among the plurality of DAC cells based on the voltage of the first node in the first DAC cell.

[0101] Aspect 2: A DAC according to Aspect 1, wherein: the current source is a cascade current source including a first transistor and a second transistor, the second transistor having a source coupled to the drain of the first transistor at a second node; the calibration circuit has a second input terminal coupled to the first DAC unit among the multiple DAC units; the calibration circuit is further configured to sense the voltage of the second node in the first DAC unit; and the calibration circuit is configured to control the power supply voltage for the switch driver based on the voltage difference between the voltage of the first node and the voltage of the second node.

[0102] Aspect 3: The DAC according to Aspect 2, wherein the calibration circuit comprises a differential amplifier having a first input coupled to the first node in the first DAC cell and having a second input coupled to the second node in the first DAC cell.

[0103] Aspect 4: A DAC according to Aspect 3, wherein the calibration circuit further includes: a second switch and a third switch, the second switch being coupled between the first node in the first DAC unit and the first input terminal of the differential amplifier; the third switch being coupled between the second node in the first DAC unit and the second input terminal of the differential amplifier.

[0104] Aspect 5: The DAC according to aspect 4, wherein the second switch and the third switch comprise transmission gates.

[0105] Aspect 6: The DAC according to aspect 4 or aspect 5, wherein the second switch and the third switch are configured to be in a closed state in response to receiving an indication that the DAC is in a calibration mode.

[0106] Aspect 7: A DAC according to any one of Aspects 3 to 6, wherein the calibration circuit further includes: a comparator having a first input terminal coupled to the output terminal of the differential amplifier and having a second input terminal coupled to a reference voltage source; and a logic component having an input terminal coupled to the output terminal of the comparator.

[0107] Aspect 8: According to the DAC of Aspect 7, the DAC also includes a voltage control module, the voltage control module has an input terminal coupled to the output terminal of the logic component, and the voltage control module is configured to convert the signal at the output terminal of the logic component into the power supply voltage for the switch driver.

[0108] Aspect 9: The DAC according to aspect 8, wherein the voltage control module includes another digital-to-analog converter (DAC).

[0109] Aspect 10: A DAC according to any one of Aspects 2 to 9, wherein the calibration circuit is configured to increase the power supply voltage in response to determining that the voltage difference between the voltage of the first node and the voltage of the second node is greater than a reference voltage.

[0110] Aspect 11: A DAC according to Aspect 10, wherein the calibration circuit is configured to: iteratively compare the reference voltage and the voltage difference between the voltage of the first node and the voltage of the second node; and increase the power supply voltage until the voltage difference between the voltage of the first node and the voltage of the second node is less than or equal to the reference voltage.

[0111] Aspect 12: The DAC according to aspect 10 or aspect 11, wherein the reference voltage is selected based on a characteristic including voltage and temperature variation of at least one of the following: the first transistor; the second transistor; or the calibration circuit.

[0112] Aspect 13: The DAC according to any one of the preceding aspects, wherein the power supply voltage is provided to a final stage of the switch driver in the at least one DAC unit among the plurality of DAC units.

[0113] Aspect 14: A DAC according to Aspect 1, wherein: the first input terminal of the calibration circuit is selectively coupled to the first DAC unit and is selectively coupled to a second DAC unit among the multiple DAC units; the calibration circuit is further configured to sense the voltage of the first node in the second DAC unit; and the calibration circuit is configured to control the power supply voltage for the switch driver based on the voltage of the first node in the first DAC unit and the voltage of the first node in the second DAC unit.

[0114] Aspect 15: A DAC according to Aspect 14, wherein: the current source is a cascade current source including a first transistor and a second transistor, the second transistor having a source coupled to the drain of the first transistor at a second node; the calibration circuit has a second input terminal selectively coupled to the first DAC unit and selectively coupled to the second DAC unit; the calibration circuit is further configured to sense the voltage of the second node in the first DAC unit and the voltage of the second node in the second DAC unit; and the calibration circuit is configured to control the power supply voltage for the switch driver based on a first voltage difference between the voltage of the first node in the first DAC unit and the voltage of the second node in the first DAC unit and a second voltage difference between the voltage of the first node in the second DAC unit and the voltage of the second node in the second DAC unit.

[0115] Aspect 16: A DAC according to Aspect 15, wherein: the calibration circuit includes a differential amplifier, the differential amplifier having a first input terminal selectively coupled to the first node in the first DAC unit and selectively coupled to the first node in the second DAC unit, and having a second input terminal selectively coupled to the second node in the first DAC unit and selectively coupled to the second node in the second DAC unit; the first DAC unit also includes: a second switch and a third switch, the second switch is coupled between the first node in the first DAC unit and the first input terminal of the differential amplifier; the third switch is coupled between the second node in the first DAC unit and the second input terminal of the differential amplifier; and the second DAC unit also includes: a fourth switch and a fifth switch, the fourth switch is coupled between the first node in the second DAC unit and the first input terminal of the differential amplifier; the fifth switch is coupled between the second node in the second DAC unit and the second input terminal of the differential amplifier.

[0116] Aspect 17: A wireless device comprising a DAC according to any of the preceding aspects, the wireless device further comprising: one or more antennas; and one or more transmission paths, the one or more transmission paths being coupled between one or more output ends of the DAC and the one or more antennas.

[0117] Aspect 18: A method for operating a digital-to-analog converter (DAC), the digital-to-analog converter (DAC) comprising a plurality of DAC units, each DAC unit comprising: a current source; a first switch coupled in series with the current source at a first node; and a switch driver having an output coupled to a control input of the first switch, the method comprising controlling a power supply voltage for the switch driver in at least one DAC unit among the plurality of DAC units based on a voltage of the first node in the first DAC unit.

[0118] Aspect 19: According to the method described in Aspect 18, the method also includes sensing the voltage of the first node in the first DAC unit, wherein the control includes controlling the power supply voltage of the switch driver in at least one DAC unit among the multiple DAC units based on the sensed voltage of the first node in the first DAC unit.

[0119] Aspect 20: A method according to Aspect 18 or Aspect 19, wherein: the current source is a cascade current source including a first transistor and a second transistor, the second transistor having a source coupled to the drain of the first transistor at a second node; the method also includes sensing the voltage of the second node in the first DAC unit; and the control includes controlling the power supply voltage for the switch driver based on a voltage difference between the voltage of the first node and the voltage of the second node.

[0120] Aspect 21: The method according to aspect 20, the method further comprising: determining that the voltage difference between the voltage of the first node and the voltage of the second node is greater than a reference voltage; and increasing the power supply voltage in response to the determination.

[0121] Aspect 22: According to the method described in Aspect 20, the method also includes: iteratively comparing a reference voltage and the voltage difference between the voltage of the first node and the voltage of the second node; and increasing the power supply voltage until the voltage difference between the voltage of the first node and the voltage of the second node is less than or equal to the reference voltage.

[0122] Aspect 23: The method according to any one of Aspects 20 to 22, further comprising amplifying the voltage difference between the first node and the second node using a differential amplifier.

[0123] Aspect 24: A method according to Aspect 23, wherein the sensing includes: closing a second switch coupled between the first node in the first DAC unit and the first input terminal of the differential amplifier; and closing a third switch coupled between the second node in the first DAC unit and the second input terminal of the differential amplifier.

[0124] Aspect 25: The method according to Aspect 23 or Aspect 24, the method further comprising: comparing the amplified voltage difference with a reference voltage; and outputting a digital logic signal based on the comparison, wherein the control comprises controlling the power supply voltage for the switch driver based on the digital logic signal.

[0125] Aspect 26: According to the method described in Aspect 19, the method also includes sensing the voltage of the first node in the second DAC unit, wherein the control includes controlling the power supply voltage of the switch driver in at least one DAC unit among the multiple DAC units based on the sensed voltage of the first node in the first DAC unit and the sensed voltage of the first node in the second DAC unit.

[0126] Aspect 27: A method according to Aspect 26, wherein: the current source is a cascade current source including a first transistor and a second transistor, the second transistor having a source coupled to the drain of the first transistor at a second node; the method also includes sensing the voltage of the second node in the first DAC unit and the voltage of the second node in the second DAC unit; and the control includes controlling the power supply voltage for the switch driver based on a first voltage difference between the voltage of the first node in the first DAC unit and the voltage of the second node in the first DAC unit and a second voltage difference between the voltage of the first node in the second DAC unit and the voltage of the second node in the second DAC unit.

[0127] Aspect 28: The method according to any one of Aspects 18 to 27, wherein the controlling comprises providing the power supply voltage to a final stage of the switch driver in the at least one DAC unit among the plurality of DAC units.

[0128] Aspect 29: A device for digital-to-analog conversion, the device comprising: a plurality of digital-to-analog converter (DAC) units, each DAC unit comprising a component for emitting a current, a component for switching coupled in series with the component for emitting a current at a node, and a component for driving the component for switching; and a component for the following operations: controlling a power supply voltage of the component for driving the component for switching in at least one of the plurality of DAC units based on a voltage of the node in a first DAC unit.

[0129] Aspect 30: An apparatus according to Aspect 29, the apparatus further comprising a component for sensing the voltage of the node in the first DAC unit, wherein the component for controlling is configured to control the power supply voltage of the component for driving the component for switching in the at least one DAC unit among the plurality of DAC units based on the sensed voltage of the node in the first DAC unit.

[0130] in conclusion

[0131] A digital-to-analog converter (DAC) circuit design is described herein to reduce distortion in a DAC at operating corners without significantly increasing the area or power consumption of the DAC. Certain aspects of the present disclosure provide a calibration circuit for a current-steering DAC that calibrates a supply voltage (e.g., a reference potential) provided to the last (inverter) stage of a switch driver in the DAC. To calibrate the supply voltage, the calibration circuit compares a sensed voltage at one or more nodes of at least one DAC cell with a reference voltage, and increases the supply voltage until the sensed voltage (or the voltage difference between the sensed voltages) is greater than the reference voltage.

[0132] The above description provides examples, but does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of the present disclosure, the functions and arrangements of the elements discussed may be changed. Each example may ignore, replace or add each process or component as appropriate. For example, the method described may be performed in a different order than described, and various steps may be added, omitted or combined. In addition, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods practiced using other structures, functional functions or structures and functionality in addition to or different from the various aspects of the present disclosure given herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the present invention. The word "exemplary" is used herein to mean "used as an example, instance or illustration". Any aspect described as "exemplary" herein is not necessarily interpreted as being preferred or having advantages over other aspects.

[0133] The various operations of the above methods may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. In general, where there are operations illustrated in the accompanying drawings, these operations may have corresponding corresponding means plus functional components. For example, a means for emitting current may include a current source, such as a Figure 4 , Figure 5A or Figure 5B The current source 406. The means for switching may include one or more switches, such as Figure 4 , Figure 5A or Figure 5B The switch 408. The means for driving the means for switching may include a switch driver, such as Figure 4 , Figure 5A or Figure 5B The switch driver 410. The means for controlling the power supply voltage (eg, reference potential) of the means for driving and the means for sensing the voltage of the node may include a calibration circuit, such as Figure 5A or Figure 5B The calibration circuit 510 is provided.

[0134] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc or any other ordering of a, b, and c).

[0135] The methods disclosed herein include one or more steps or actions for implementing the described methods. The method steps and / or actions may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0136] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A digital-to-analog converter (DAC), the digital-to-analog converter (DAC) comprising: a plurality of DAC units, each DAC unit comprising: a current source; a first switch coupled in series with the current source at a first node; and a switch driver having an output terminal coupled to a control input terminal of the first switch; and a calibration circuit having a first input coupled to a first DAC cell among the plurality of DAC cells and having an output coupled to at least one DAC cell among the plurality of DAC cells, the calibration circuit being configured to sense a voltage of the first node in the first DAC cell and to control a supply voltage for the switch driver in the at least one DAC cell among the plurality of DAC cells based on the voltage of the first node in the first DAC cell.

2. The DAC of claim 1 , wherein: the current source being a cascaded current source including a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node; The calibration circuit has a second input terminal coupled to the first DAC unit of the plurality of DAC units; The calibration circuit is further configured to sense a voltage of the second node in the first DAC unit; and The calibration circuit is configured to control the supply voltage for the switch driver based on a voltage difference between the voltage of the first node and the voltage of the second node.

3. The DAC of claim 2, wherein the calibration circuit comprises a differential amplifier having a first input coupled to the first node in the first DAC cell and having a second input coupled to the second node in the first DAC cell.

4. The DAC of claim 3 , wherein the calibration circuit further comprises: a second switch and a third switch, the second switch being coupled between the first node in the first DAC unit and the first input terminal of the differential amplifier; The third switch is coupled between the second node in the first DAC unit and the second input terminal of the differential amplifier.

5. The DAC of claim 4, wherein the second switch and the third switch comprise transmission gates. 6 . The DAC of claim 4 , wherein the second switch and the third switch are configured to be in a closed state in response to receiving an indication that the DAC is in a calibration mode.

7. The DAC of claim 3, wherein the calibration circuit further comprises: a comparator having a first input coupled to the output of the differential amplifier and having a second input coupled to a reference voltage source; and A logic component has an input coupled to the output of the comparator.

8. The DAC of claim 7 , further comprising a voltage control module having an input coupled to the output of the logic component, the voltage control module being configured to convert a signal at the output of the logic component into the supply voltage for the switch driver.

9. The DAC of claim 8, wherein the voltage control module comprises another digital-to-analog converter (DAC). 10 . The DAC of claim 2 , wherein the calibration circuit is configured to increase the supply voltage in response to determining that the voltage difference between the voltage of the first node and the voltage of the second node is greater than a reference voltage.

11. The DAC of claim 10 , wherein the calibration circuit is configured to: iteratively comparing the reference voltage with the voltage difference between the voltage of the first node and the voltage of the second node; and The power supply voltage is increased until the voltage difference between the voltage of the first node and the voltage of the second node is less than or equal to the reference voltage.

12. The DAC of claim 10 , wherein the reference voltage is selected based on a characteristic including voltage and temperature variation of at least one of: the first transistor; the second transistor; or The calibration circuit. 13 . The DAC according to claim 1 , wherein the power supply voltage is provided to a final stage of the switch driver in the at least one DAC unit among the plurality of DAC units.

14. The DAC of claim 1 , wherein: The first input of the calibration circuit is selectively coupled to the first DAC cell and selectively coupled to a second DAC cell of the plurality of DAC cells; The calibration circuit is further configured to sense a voltage of the first node in the second DAC unit; and The calibration circuit is configured to control the supply voltage for the switch driver based on the voltage of the first node in the first DAC cell and the voltage of the first node in the second DAC cell.

15. The DAC of claim 14, wherein: the current source being a cascaded current source including a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node; The calibration circuit has a second input terminal selectively coupled to the first DAC unit and selectively coupled to the second DAC unit; The calibration circuit is further configured to sense a voltage of the second node in the first DAC cell and a voltage of the second node in the second DAC cell; and The calibration circuit is configured to control the power supply voltage for the switch driver based on a first voltage difference between the voltage of the first node in the first DAC cell and the voltage of the second node in the first DAC cell and a second voltage difference between the voltage of the first node in the second DAC cell and the voltage of the second node in the second DAC cell.

16. The DAC of claim 15, wherein: the calibration circuit comprising a differential amplifier having a first input selectively coupled to the first node in the first DAC cell and selectively coupled to the first node in the second DAC cell, and having a second input selectively coupled to the second node in the first DAC cell and selectively coupled to the second node in the second DAC cell; The first DAC unit further includes: a second switch and a third switch, the second switch coupled between the first node in the first DAC unit and the first input terminal of the differential amplifier; the third switch coupled between the second node in the first DAC unit and the second input terminal of the differential amplifier; and The second DAC unit also includes: a fourth switch and a fifth switch, the fourth switch is coupled between the first node in the second DAC unit and the first input terminal of the differential amplifier; the fifth switch is coupled between the second node in the second DAC unit and the second input terminal of the differential amplifier.

17. A wireless device comprising the DAC according to claim 1, the wireless device further comprising: one or more antennas; and One or more transmit paths are coupled between one or more outputs of the DAC and the one or more antennas.

18. A method for operating a digital-to-analog converter (DAC), the digital-to-analog converter (DAC) comprising a plurality of DAC units, each DAC unit comprising: Current source; a first switch coupled in series with the current source at a first node; and a switch driver having an output terminal coupled to a control input terminal of the first switch, the method comprising controlling a supply voltage for the switch driver in at least one DAC cell of the plurality of DAC cells based on a voltage of the first node in a first DAC cell.

19. The method of claim 18, further comprising sensing the voltage of the first node in the first DAC cell, wherein the controlling comprises controlling the power supply voltage of the switch driver in the at least one DAC cell among the plurality of DAC cells based on the sensed voltage of the first node in the first DAC cell.

20. The method of claim 19, wherein: the current source being a cascaded current source including a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node; The method further includes sensing a voltage of the second node in the first DAC unit; and The controlling includes controlling the supply voltage for the switch driver based on a voltage difference between the voltage of the first node and the voltage of the second node.

21. The method according to claim 20, further comprising: determining that the voltage difference between the voltage of the first node and the voltage of the second node is greater than a reference voltage; as well as The supply voltage is increased in response to the determination.

22. The method according to claim 20, further comprising: iteratively comparing a reference voltage and the voltage difference between the voltage of the first node and the voltage of the second node; as well as The power supply voltage is increased until the voltage difference between the voltage of the first node and the voltage of the second node is less than or equal to the reference voltage.

23. The method of claim 20, further comprising amplifying the voltage difference between the first node and the second node with a differential amplifier.

24. The method of claim 23, wherein the sensing comprises: closing a second switch coupled between the first node in the first DAC unit and a first input terminal of the differential amplifier; as well as A third switch coupled between the second node in the first DAC unit and a second input terminal of the differential amplifier is closed.

25. The method according to claim 23, further comprising: comparing the amplified voltage difference with a reference voltage; as well as A digital logic signal is output based on the comparison, wherein the controlling includes controlling the supply voltage for the switch driver based on the digital logic signal.

26. The method of claim 19, further comprising sensing a voltage of the first node in a second DAC cell, wherein the controlling comprises controlling the power supply voltage of the switch driver in at least one of the plurality of DAC cells based on the sensed voltage of the first node in the first DAC cell and the sensed voltage of the first node in the second DAC cell.

27. The method of claim 26, wherein: the current source being a cascaded current source including a first transistor and a second transistor, the second transistor having a source coupled to a drain of the first transistor at a second node; The method further includes sensing a voltage of the second node in the first DAC cell and a voltage of the second node in the second DAC cell; and The control includes controlling the power supply voltage for the switch driver based on a first voltage difference between the voltage of the first node in the first DAC cell and the voltage of the second node in the first DAC cell and a second voltage difference between the voltage of the first node in the second DAC cell and the voltage of the second node in the second DAC cell.

28. The method of claim 18, wherein the controlling comprises providing the power supply voltage to a final stage of the switch driver in the at least one DAC cell among the plurality of DAC cells.

29. A device for digital-to-analog conversion, the device comprising: a plurality of digital-to-analog converter (DAC) cells, each DAC cell comprising means for sourcing current, means for switching coupled in series with the means for sourcing current at a node, and means for driving the means for switching; and means for controlling a power supply voltage of the means for driving the means for switching in at least one DAC cell among the plurality of DAC cells based on a voltage of the node in the first DAC cell.

30. The apparatus according to claim 29, further comprising means for sensing the voltage of the node in the first DAC cell, wherein the means for controlling is configured to control the supply voltage of the means for driving the means for switching in the at least one DAC cell among the plurality of DAC cells based on the sensed voltage of the node in the first DAC cell.

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