Non-volatile memory with different word line-to-word line pitches

Abstract

In a multi-level non-volatile memory structure that may perform operations on sub-blocks, the performance of different levels / sub-blocks is consistent by using different word line-to-word line pitches in the different levels / sub-blocks.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 17 / 955,878, filed on September 29, 2022, entitled “NON-VOLATILE MEMORY WITH DIFFERENT WORD LINE TO WORD LINE PITCHES,” the contents of which are hereby incorporated by reference for all purposes. Background Art

[0003] The present disclosure relates to non-volatile storage devices.

[0004] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories may include non-volatile memories or volatile memories. Non-volatile memories allow information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memory (e.g., NAND-type and NOR-type flash memory).

[0005] Users of nonvolatile memory can program (i.e., write) data to nonvolatile memory and subsequently read the data back. For example, a digital camera can take a picture and store the picture in nonvolatile memory. Later, the user of the digital camera can view the picture by having the digital camera read the picture from the nonvolatile memory. Because users often rely on the data they store, it is important for users of nonvolatile memory to be able to reliably store data so that the data can be successfully read back. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like numbered elements refer to common parts in different figures.

[0007] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0008] Figure 2A is a block diagram of one embodiment of a memory die.

[0009] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0010] Figure 3A and Figure 3B Various embodiments of integrated memory components are depicted.

[0011] Figure 4 is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

[0012] Figure 4A is a block diagram of one embodiment of a memory structure having two planes.

[0013] Figure 4B Depicted is a top view of a portion of one embodiment of a block of memory cells.

[0014] Fig.4C1 A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0015] Figure 4C2 A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0016] Fig.4D1 A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0017] Figure 4D2 A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0018] Figure 4D3 A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0019] Figure 4D4 A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0020] Figure 4E A cross-sectional view of a portion of one embodiment of a block of memory cells is depicted.

[0021] Figure 4F is a cross-sectional view of one embodiment of a vertical column of memory cells.

[0022] Figure 4G A cross section of a memory hole implementing a vertical NAND string is depicted.

[0023] Figure 4H A cross section of a memory hole implementing a vertical NAND string is depicted.

[0024] Fig. 4I A cross section of a memory hole implementing a vertical NAND string is depicted.

[0025] Figure 4J is a schematic diagram of multiple NAND strings.

[0026] Figure 5A The threshold voltage distribution is depicted.

[0027] Figure 5B The threshold voltage distribution is depicted.

[0028] Figure 5C The threshold voltage distribution is depicted.

[0029] Figure 5D The threshold voltage distribution is depicted.

[0030] Figure 5E The threshold voltage distribution is depicted.

[0031] Fig. 5F The threshold voltage distribution is depicted.

[0032] Figure 6 is a flow chart describing one embodiment of a process for programming nonvolatile memory cells connected to a common word line.

[0033] Figure 7 is a flow chart describing one embodiment of a process for programming nonvolatile memory cells connected to multiple word lines.

[0034] Fig. 8A The threshold voltage distribution is depicted.

[0035] Figure 8B The threshold voltage distribution is depicted.

[0036] Fig. 9 is a flow chart describing one embodiment of a process for fabricating non-volatile memory. DETAILED DESCRIPTION

[0037] Because there are limitations on the maximum height / depth that can be reliably etched, some non-volatile memories are manufactured in multiple levels. In addition, because a block of memory with multiple levels can be quite large, it is more efficient to operate the block in a sub-block mode. However, as device sizes shrink, the differences in how the levels / sub-blocks perform memory operations become more pronounced and these differences make it difficult to operate the memory reliably. To address this issue, it is proposed to use different wordline to wordline spacing in different levels and / or different sub-blocks.

[0038] Figure 11 is a block diagram of an embodiment of a non-volatile storage system 100 implementing the technology of the present invention described herein. In one embodiment, the non-volatile storage system 100 is a solid state drive ("SSD"). The non-volatile storage system 100 can also be a memory card, a USB drive, or other types of storage systems. The technology of the present invention is not limited to any one type of storage system. The storage system 100 is connected to a host 102, which can be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses a memory and has data processing capabilities. In some embodiments, the host 102 is separated from the storage system 100, but connected to the storage system. In other embodiments, the storage system 100 is embedded in the host 102.

[0039] Figure 1 The components of the memory system 100 depicted in FIG. 1 are electronic circuits. The memory system 100 includes a memory controller 120 connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores logic in a physical address translation table ("L2P table").

[0040] The memory controller 120 includes a host interface 152 connected to and communicating with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) through PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and DRAM controller 164 are connected to and communicate with NOC 154. DRAM controller 164 is used to operate and communicate with local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, local high-speed volatile memory 140 may be SRAM or another type of volatile memory.

[0041] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is an electronic circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0042] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a customized dedicated hardware circuit without any software. Processor 156 also implements a conversion module as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between the locations of one or more memory dies as desired. In order to implement such a system, memory controller 120 (e.g., conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory die. An example specific implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in the memory die 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0043] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory dies.

[0044] In one embodiment, non-volatile memory 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 including non-volatile memory 130. Each of the one or more memory dies of non-volatile memory 130 may be implemented as Figure 2A A memory die 200 is provided. Figure 2AThe components depicted in are circuits. The memory die 200 includes a memory array 202, which may include non-volatile memory cells, as described in more detail below. The array terminal lines of the memory array 202 include individual word line layers organized into rows, and individual bit line layers organized into columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit system 220, the output end 208 of which is connected to the corresponding word lines of the memory array 202. The row control circuit system 220 receives a set of M row address signals and one or more various control signals from the system control logic circuit 206, and may generally include circuits such as a row decoder 222, an array terminal driver 224, and a block selection circuit system 226 for both reading and writing (programming). The row control circuit system 220 may also include a read / write circuit system. The memory die 200 also includes a column control circuit system 210, which includes a sense amplifier 230, the input end / output end 206 of which is connected to the corresponding bit line of the memory array 202. Although only a single block is shown for array 202, a memory die may include multiple arrays that may be accessed individually. Column control circuitry 210 receives a set of N column address signals and one or more various control signals from system control logic 260, and may generally include circuits such as column decoders 212, array terminal receivers or driver circuits 214, and read / write circuitry and I / O multiplexers.

[0045] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is implemented entirely in hardware (e.g., electronic circuits). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. The system control logic 262 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operation, and may include a charge pump and regulator circuit for generating a regulated voltage. The system control logic 262 includes a storage device 366 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory array 202.

[0046] Commands and data are transmitted between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used.

[0047] In some embodiments, all elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on different dies.

[0048] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed over a single substrate such as a wafer. The memory structure may include any type of non-volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0049] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (eg, NOR-type flash memory) may also be used.

[0050] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0051] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0052] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cells, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0053] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be disabled by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves. These memory elements within each selectable memory cell or bit can include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0054] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0055] Figure 2A The components of the memory structure 202 can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuit system, which includes Figure 2A 202; however, this reduces the area of ​​the memory die available for peripheral circuitry. This can place quite severe constraints on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to system control logic 260, the reduction in available area can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a fundamental trade-off needs to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry.

[0056] Another area where the memory structure 202 and the peripheral circuitry often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs of having different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, this is an NMOS structure, while the peripheral circuitry is often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuitry in the system control logic 260 often employ CMOS devices. The processing operations used to manufacture a CMOS die will differ in many ways from processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0057] To improve these limitations, the embodiments described below can Figure 2AThe components of the memory structure 202 can be separated into separately formed dies, and then these dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit system elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Some or all of the peripheral circuit systems (even including elements such as decoders and sense amplifiers) can then be moved to a separate control die. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are confined to the edge of the same die that houses the memory cell array, additional capabilities that may not be easily combined can now be combined. The two dies can then be bonded together in a bonded multi-die memory circuit where the array on one die is connected to the peripheral components on the other die. For example, although the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0058] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 may be used to implement the non-volatile memory 130 of the memory system 100. The integrated memory component 207 includes two types of semiconductor dies (or more succinctly, "dies"). The memory die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

[0059] Figure 2B An example of peripheral circuitry is shown, which includes control circuits formed in a peripheral circuit or control die 211 that are coupled to a memory structure 202 formed in a memory die 201. Common components are similar to Figure 2ASystem control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory die 201. In some embodiments, some of the circuitry in system control logic 260 is located on memory die 201.

[0060] System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by conventional processes (e.g., CMOS processes), such that adding elements and functionality more commonly found on memory controller 120 (such as ECC) may require little or no additional process steps (i.e., the same process steps used to manufacture controller 120 may also be used to manufacture system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, while removing such circuitry from a die (such as memory 2 die 201) may reduce the number of steps required to manufacture such a die, adding such circuitry to a die (such as control die 211) may not require many additional process steps. Because some or all of control circuitry 260, 210, 220 are implemented using CMOS technology, control die 211 may also be referred to as a CMOS die.

[0061] Figure 2B Column control circuitry 210 including sense amplifier 230 on control die 211 is shown coupled to memory structure 202 on memory die 201 via electrical path 206. For example, electrical path 206 can provide electrical connections between column decoder 212 and driver circuitry 214, and bit lines of memory structure 202. Electrical paths can extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of memory die 201 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 can have a corresponding electrical path in electrical path 306 connected to column control circuitry 210, including a pair of bond pads. Similarly, row control circuitry 220 (including row decoder 222, array driver 224, and block selector 226) is coupled to memory structure 202 via electrical path 208. Each of the electrical paths 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory die 201 .

[0062] For purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and / or other similar functional circuits. The control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, FGA, ASIC, integrated circuit, or other type of circuitry.

[0063] In some embodiments, there is more than one control die 211 and more than one memory die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 3A Depicted is a side view of one embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory dies 201) stacked on a substrate 271. The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0064] Each control die 211 is attached (e.g., bonded) to at least one of the memory dies 201. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280, but in an embodiment, the material can be Hysol epoxy resin from Henkel Corporation (which has offices in California, USA).

[0065] The integrated memory components 207 may be stacked, for example, in a stepped offset manner so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds may be formed across the width of each control die 211 (i.e., formed to Figure 3A ).

[0066] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. TSVs 276, 278 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier to prevent metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor, such as copper, although other suitable materials may be used, such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof.

[0067] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory component 207 is to be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory component 207 and memory controller 120.

[0068] Figure 3B A side view of another embodiment of an integrated memory component 207 stacked on a substrate 271 is depicted. Figure 3B The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are far more than three memory dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 can be bonded to two or more memory dies 201.

[0069] Some of the bonding pads 282, 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3B The integrated memory component 207 in FIG. 2 has no step offset. Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201 . Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211 .

[0070] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package.

[0071] As briefly discussed above, the control die 211 and the memory die 201 can be bonded together. The bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles, otherwise the environmental particles may be deposited on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In the embodiment using Cu-Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu-Cu bonding in this article, the term can also be applied to the case where the bonding pads are formed by materials other than copper.

[0072] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size and spacing of the bonding pad can be further reduced. The film layer is arranged around the bonding pad. When the die are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technology can be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding technology can be used to provide bonding pads with smaller size and spacing.

[0073] Some embodiments may include a film on the surface of the tube core 201, 211. If such a film is not initially provided, the space between the tube cores can be filled with epoxy or other resins or polymers at the bottom. The bottom fill material can be applied as a liquid and then hardened into a solid layer. This bottom filling step protects the electrical connection between the tube core 201, 211 and further fixes the tube core together. Various materials can be used as the bottom fill material, but in an embodiment, the bottom fill material can be a Hysol epoxy resin from Henkel Corporation (the company has offices in California, USA).

[0074] Figure 4 is a perspective view of a portion of an example embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4A portion 400 of a memory block is shown. The depicted structure includes a set of bit lines BL positioned above a stack 401 of alternating dielectric and conductive layers. For example, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into six (or a different number of) regions by isolation regions IR. These regions are sometimes referred to as fingers or strings. Figure 4 An isolation region IR is shown separating the two regions. A source line layer SL is located below the alternating dielectric layer and word line layer. A memory hole is formed in the stack of alternating dielectric layers and conductive layers. For example, the memory hole is marked as MH. Note that Figure 4 2, the dielectric layers are depicted as a perspective view so that the reader can see the memory holes located in the stack of alternating dielectric layers and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form a vertical column of memory cells. Each memory cell can store one or more data bits. More details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0075] Figure 4A 4 and 5. 4. The memory cells of FIG. 200 are grouped into blocks. FIG. 201 is a block diagram illustrating an example organization of a memory structure 202 that is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, a different number of blocks and planes may also be used. In one embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. Memory cells may also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the block. Although Figure 4A Two planes 402 / 404 are shown, but more or less than two planes may be implemented.In some embodiments, the memory structure 202 includes four planes, eight planes, or more than eight planes.

[0076] FIG. 4B to FIG. 4J An example three-dimensional ("3D") NAND structure is depicted, corresponding to Figure 4 structure and can be used to implement Figure 2A and Figure 2B Memory structure 202. Figure 4B is a block diagram depicting a top view of a portion 406 of block 2 of plane 402. Figure 4B As can be seen, Figure 4B The blocks depicted in FIG. extend in the direction of 432. In one embodiment, the memory array has many layers; however, Figure 4B Only the top layer is shown.

[0077] Figure 4B A plurality of circles representing vertical columns corresponding to memory holes are depicted. Each of the vertical columns includes a plurality of select transistors (also referred to as select gates / selection gates) and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B A subset of vertical columns / NAND strings 426, 432, 436, 446, 456, 462, 466, 472, 474, and 476 are labeled.

[0078] Figure 4B Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 411 is connected to vertical columns 426, 436, 446, 456, 466, and 476.

[0079] Figure 4B The block depicted in FIG. 4 includes a set of isolation regions 480, 482, 484, 486, and 488 formed of SiO2; however, other dielectric materials may also be used. Isolation regions 480, 482, 484, 486, and 488 are used to divide the top layer of the block into six regions; for example, Figure 4B 4 is divided into regions 420, 430, 440, 450, 460, and 470. In one embodiment, the isolation regions divide only the layers used to implement the select gates (e.g., SGD) so that NAND strings in different regions can be independently selected. In one example implementation, the bit lines are connected to only one vertical column / NAND string in each of regions 420, 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to six rows in each block. In one embodiment, all six vertical columns / NAND strings connected to a common bit line are connected to the same word line (or word line group); therefore, the system uses the drain-side select line (SGD) to select one (or another subset) of the six for which a memory operation (program, verify, read, and / or erase) is to be performed.

[0080] although Figure 4BEach region 420, 430, 440, 450, 460, and 470 is shown with four vertical columns in one block, and six regions have twenty-four vertical columns, but these exact numbers are example implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block. Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0081] Fig.4C1 Describes also Figure 4B A side view of portion 406 of block 2 is depicted in plane 402 . Fig.4C1 4 shows an embodiment of a memory array implemented as a two-level architecture, where the levels are separated by tie regions. Each of regions 420 to 470 extends across the levels (and sub-blocks). The first level (Level 0) includes word lines WL0 to WL134. The second level (Level 1) positioned above Level 0 includes word lines WL135 to WL269. More or less than 270 word lines may be used, and different divisions of word lines into levels may be implemented.

[0082] In one set of embodiments, the memory can be implemented in sub-block mode. That is, the block is divided into two or more sub-blocks, and each sub-block can be independently programmed, read and / or erased. Fig.4C1 An example of a block divided into two sub-blocks: SB0 and SB1 is shown. Sub-block SB1 is positioned above sub-block SB0. In the depicted embodiment, first sub-block SB0 includes word lines WL0 to WL134, and second sub-block SB1 includes word lines WL135 to WL269; therefore, level 0 operates as sub-block SB0 and level 1 operates as sub-block SB1. However, in other examples, these levels may correspond to different sub-blocks, or sub-blocks may correspond to partial levels or more than one level.

[0083] Figure 4C2 A side view of a portion 406 of block 2 of plane 402 is depicted, showing an embodiment of a memory array implemented as a three-level architecture, where the levels are separated by tie regions. Each of regions 420 to 470 extends across the levels (and sub-blocks). The first level (Level 0) includes word lines WL0 to WL89. The second level (Level 1) positioned above Level 0 includes word lines WL90 to WL179. The third level (Level 2) positioned above Level 1 includes word lines WL180 to WL269. More or less than 270 word lines may be used, and different divisions of word lines into levels may be implemented. Figure 4C2An example of a block divided into two sub-blocks: SB0 and SB1 is shown. Sub-block SB1 is positioned above sub-block SB0. In the depicted embodiment, first sub-block SB0 includes word lines WL0 to WL133 and second sub-block SB1 includes word lines WL136 to WL269; therefore, level 0 and the bottom portion of level 1 operate as sub-block SB0, and level 2 and the top portion of level 1 operate as sub-block SB1. Figure 4C2 In the depicted arrangement of , word lines WL134 and WL135 operate as dummy word lines to provide a buffer between sub-blocks. In other embodiments, more or less than two word lines may operate as buffers between sub-blocks. In other examples, the levels may correspond to different sub-blocks, or the sub-blocks may correspond to partial levels or more than one level. Other embodiments may include more than two sub-blocks.

[0084] Fig.4D1 A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B Sectional view along line AA. Fig.4D1 The implementation scheme corresponds to Fig.4C1 This cross-sectional view cuts through vertical columns (NAND strings) 472 and 474 of region 470 (see Figure 4B ). Fig.4D1 The structure includes: three drain side selection layers SGD0, SGD1 and SGD2 (which form selection lines); three source side selection layers SGS0, SGS1 and SGS2 (which form selection lines); dummy word line layers D0L, D0U, D1L and D1U for connecting to dummy memory cells (which do not store data from the host); two hundred and seventy data word line layers WL0 to WL269 for connecting to data memory cells (which store data), and a dielectric layer DL. Other embodiments may implement more or less than the above embodiments for Figure 4 The number described in D. In one embodiment, SGD0, SGD1 and SGD2 are linked together; and SGDS0, SGS1 and SGS2 are linked together.

[0085] Vertical columns 472 and 474 are depicted as protruding through the drain side select layer, source side select layer, dummy word line layer, and word line layer. In one embodiment, each vertical column includes a vertical NAND string. Below the vertical columns and the layers listed below is a substrate 453, an insulating film 454 on the substrate, and a source line SL. The NAND string of vertical column 472 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4B Consistent, Figure 4 D shows vertical columns 442 connected to bit lines 414 via connectors 417 .

[0086] For ease of reference, the drain side selection layer, the source side selection layer, the dummy word line layer, and the data word line layer are collectively referred to as conductive layers. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten or metal silicide). In some embodiments, different conductive layers can be formed of different materials. Between the conductive layers is a dielectric layer DL. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layer.

[0087] The nonvolatile memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings to form a block having two levels (Level 0 and Level 1) and two sub-blocks (SB0 and SB1), as described above with respect to Fig.4C1 The word line layers WL0 to W269 are connected to memory cells (also referred to as data memory cells). Each NAND string of the block includes memory cells in each of the two levels; for example, the memory cells connected to word lines WL0 to WL134 are in level 0, and the memory cells connected to word lines WL135 to WL260 are in level 1. The dummy word line layer is connected to the dummy memory cells. The dummy memory cells do not store host data and are not eligible to store host data (data provided from a host or an entity external to the memory system 100), while the data memory cells are eligible to store host data. The host data can be contrasted with system data generated by the memory system 100 (e.g., L2P table). In some embodiments, the data memory cells and the dummy memory cells can have the same structure. The drain side selection layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect the NAND strings to the bit lines. The source side selection layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect the NAND strings with the source lines SL.

[0088] Fig.4D1 Also shown is a tie region. In one embodiment, etching so many word line layers intermixed with dielectric layers is expensive and / or challenging. To alleviate this burden, one embodiment includes laying a first stack of word line layers alternating with dielectric layers (e.g., for level 0), laying a tie region, and laying a second stack of word line layers alternating with dielectric layers (e.g., for level 1). The tie region is positioned between the first stack and the second stack. In one embodiment, the tie region is made of polysilicon. The tie region serves as a buffer layer to allow some misalignment between the upper level and the lower level.

[0089] Figure 4D2 A portion of another embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B Sectional view along line AA. Figure 4D2 The implementation scheme corresponds to Figure 4C2 This cross-sectional view cuts through vertical columns (NAND strings) 472 and 474 of region 470. Figure 4D2 The structure includes Figure 4C2 The same three levels (Level 0, Level 1 and Level 2), two concatenated regions and two sub-blocks (SB0 and SB1).

[0090] Figure 4D2 The structure includes Fig.4D1 The same drain side select layers SGD0, SGD1 and SGD2 (which form the select lines); source side select layers SGS0, SGS1 and SGS2 (which form the select lines); and data word lines (WL0 to WL269). However, Figure 4D2 The structure includes Fig.4D1 A different set of dummy word lines. For example, WL134 and WL135 operate as dummy word lines, as discussed above. In addition, Figure 4D2 Dummy word line layers on either side of the two bonding regions are shown, including dummy word line layers D0L, D0U, D1L, D1U, D2L, and D2U for connecting to dummy memory cells.

[0091] Figure 4D3 A portion of another embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B Sectional view along line AA. Figure 4D3 The implementation scheme corresponds to Fig.4C1 This cross-sectional view cuts through vertical columns (NAND strings) 472 and 474 of region 470. Figure 4D3 The structure includes Fig.4C1 The same two levels (Level 0 and Level 1), the concatenated region, and the two sub-blocks (SB0 and SB1). Figure 4D3 The structure includes Fig.4D1The same drain side selection layers SGD0, SGD1 and SGD2 (which form the selection lines); source side selection layers SGS0, SGS1 and SGS2 (which form the selection lines); data word lines (WL0 to WL269); and dummy word lines (D0L, D0U, D1L, D1U). Therefore, the first level (level 0) includes word lines WL0 to WL134, and the second level (level 1) positioned above level 0 includes word lines WL135 to WL269. Similarly, the first sub-block SB0 includes word lines WL0 to WL134, and the second sub-block SB1 includes word lines WL135 to WL269; therefore, level 0 operates as sub-block SB0 and level 1 operates as sub-block SB1. However, in other examples, these levels may correspond to different sub-blocks, or the sub-blocks may correspond to part of the levels or more than one level.

[0092] Figure 4D3 The structure and Fig.4D1 The difference between the structures is that Figure 4D3 , the word lines in level 1 and sub-block SB1 have a looser (larger) word line to word line spacing than the word lines in level 0 and sub-block SB0. For the purposes of this document, the term "word line to word line spacing" refers to the distance from the edge of a word line to the same edge of an adjacent (or neighboring) word line. For example, Figure 4D3 A first word line to word line spacing WP1 for SB0 and level 0 is shown, where (for example purposes) WP1 is depicted as measured from the top edge of WL133 to the top edge of WL134. Figure 4D3 In the structure of , the word line to word line pitch WP1 is the same for all word lines of SB0 and level 0.

[0093] Figure 4D3 A second word line to word line spacing WP2 for SB1 and Tier 1 is also shown, where (for purposes of illustration) WP2 is depicted as measured from the top edge of WL136 to the top edge of WL137. Figure 4D3 The word line to word line spacing WP2 is the same for all word lines of SB1 and level 1. Figure 4D3 In an embodiment of , WP2>WP1, that is, the second word line to word line spacing WP2 is greater than the first word line to word line spacing WP1. In one example, WP1=42nm and WP2=43nm; however, other dimensions may also be implemented.

[0094] Figure 4D3An arrow 502 is included to depict the programming direction of level 0 and SB0 and an arrow 504 is included to depict the programming direction of level 1 and SB1. For example, level 0 has a first end opposite the tie region; level 1 has a second end opposite the tie region; the memory cells of level 0 are configured to be programmed on a word-line basis in a direction from the tie toward the first end (per arrow 502); and the memory cells of level 1 are configured to be programmed on a word-line basis in a direction from the tie toward the second end (per arrow 504). In other words, the control circuit is configured to program the memory cells of level 1 on a word-line basis in a direction toward the bit lines, and to program the memory cells of level 0 on a word-line basis in a direction toward one or more source lines. In one embodiment, instead of having a single source line, the memory may include multiple source lines connected to the NAND string at the opposite side of the NAND string from the bit lines.

[0095] Figure 4D4 A portion of another embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B Sectional view along line AA. Figure 4D4 The implementation scheme corresponds to Figure 4C2 This cross-sectional view cuts through vertical columns (NAND strings) 472 and 474 of region 470. Figure 4D3 The structure includes Figure 4C2 z and Figure 4D2 The same three levels (Level 0, Level 1 and Level 2), two concatenated regions and two sub-blocks (SB0 and SB1). Figure 4D4 The structure includes Figure 4D2 The same drain side selection layers SGD0, SGD1 and SGD2 (which form the selection lines); source side selection layers SGS0, SGS1 and SGS2 (which form the selection lines); data word lines (WL0 to WL269); and dummy word lines (D0L, D0U, D1L, D1U). Therefore, the first level (level 0) includes word lines WL0 to WL89, the second level (level 1) includes word lines WL90 to WL179, and the third level (level 2) includes word lines WL180 to WL269. Similarly, the first sub-block SB0 includes word lines WL0 to WL89, the second sub-block SB1 includes word lines WL90 to WL179, and the third sub-block SB2 includes word lines WL1800 to WL269. In Figure 4D4 In the embodiment of , level 0 and the bottom portion of level 1 are operated as sub-block SB0, and level 2 and the top portion of level 1 are operated as sub-block SB1. However, in other examples, the levels may correspond to different sub-blocks.

[0096] Figure 4D4 The structure and Figure 4D3 The difference between the structures is that Figure 4D4 , the word lines in sub-block SB1 (level 2 and top of level 1) have a looser (larger) word line to word line spacing than the word lines in sub-block SB0 (level 0 and bottom of level 1). Figure 4D4 A first word line to word line spacing WP1 for SB0 is shown, where an example of WP1 is depicted as measured from the top edge of WL90 to the top edge of WL91. Figure 4D4 , the word line to word line pitch WP1 is the same for all word lines of SB0 (including all word lines of level 0 and word lines WL90 to WL133 in the bottom of level 1).

[0097] Figure 4D4 A second word line to word line spacing WP2 for SB1 is also shown. An example of WP2 is depicted as measured from the top edge of WL268 to the top edge of WL269. Figure 4D4 In the structure of , the word line to word line spacing WP2 is the same for all word lines of SB1 (including all word lines of level 2 and word lines WL136 to WL179 at the top of level 1). Figure 4D4 In an embodiment of , WP2>WP1; that is, the second word line to word line spacing WP2 is greater than the first word line to word line spacing WP1. In one example, WP1=42nm and WP2=43nm; however, other dimensions may also be implemented.

[0098] Thus, for example, the middle level (level 1) is divided into a top portion and a bottom portion; the word lines in the top portion of the middle level are separated by a second word line to word line spacing WP2; the word lines in the bottom portion of the middle level are separated by a first word line to word line spacing WP1; level 0 and the bottom portion of the middle level (level 1) are configured to operate together as a first sub-block SB0; and level 2 and the top portion of the middle level (level 1) are configured to operate together as a second sub-block SB1.

[0099] Figure 4D4 An arrow 520 is included to depict a programming direction for SB0 and an arrow 522 is included to depict a programming direction for SB1. For example, the control circuit is configured to program the memory cells of SB1 on a word line basis in a direction toward the bit lines and to program the memory cells of SB0 on ​​a word line basis in a direction toward one or more source lines.

[0100] Figure 4E A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the vertical columns (NAND strings) 432 and 434 of region 430 (see Figure 4B ). Figure 4E Shown with Figures 4D1 to 4D4 Same alternating conductive and dielectric layers. Figure 4E Isolation region 482 is also shown. Isolation regions 480, 482, 484, 486, and 488 occupy space that was already used for a portion of memory holes / vertical columns / NAND strings. For example, isolation region 482 occupies space that was already used for a portion of vertical column 434. More specifically, a portion of vertical column 434 (e.g., half of the diameter) has been removed in layers SDG0, SGD1, SGD2, and DD0 to accommodate isolation region 482. Therefore, while most of vertical column 434 is cylindrical (having a circular cross-section), portions of vertical column 434 in layers SDG0, SGD1, and SGD2 have a semicircular cross-section. In one embodiment, after forming a stack of alternating conductive layers and dielectric layers, the stack is etched to create space for the isolation region, and the space is subsequently filled with SiO2.

[0101] Figure 4F A portion of a vertical column 472 is depicted. Fig.4D1 429 . In one embodiment, the vertical columns are circular; however, in other embodiments, other shapes may be used. In one embodiment, the vertical columns 472 include an inner core layer 490 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core 490 is a polysilicon channel 491. Materials other than polysilicon may also be used. Note that the channel 491 is connected to the bit line and the source line. Surrounding the channel 491 is a tunneling dielectric 492. In one embodiment, the tunneling dielectric 492 has an ONO structure. Surrounding the tunneling dielectric 492 is a charge trapping layer 493, such as (for example) silicon nitride. Other memory materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0102] Figure 4FA dielectric layer DL is depicted, as well as word line layers WL264, WL265, WL266, WL267, and WL268. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer can be a vertical layer parallel to and adjacent to the charge trapping layer 493. The physical interaction of the word line layers with the vertical columns forms a memory cell. Thus, in one embodiment, a memory cell includes a channel 491, a tunneling dielectric 492, a charge trapping layer 493, a blocking oxide layer 498, an aluminum oxide layer 497, and a word line region 496. For example, word line layer WL268 and a portion of vertical column 472 constitute memory cell MC1. Word line layer WL267 and a portion of vertical column 472 constitute memory cell MC2. Word line layer WL266 and a portion of vertical column 472 constitute memory cell MC3. Word line layer WL265 and a portion of vertical column 472 constitute memory cell MC4. Word line layer WL264 and a portion of vertical column 472 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still still be storage cells.

[0103] When programming a memory cell, electrons are stored in a portion of the charge trapping layer 493 that is associated with (e.g., in) the memory cell. In response to an appropriate voltage on the word line region 496, these electrons are attracted from the channel 491 into the charge trapping layer 493 through the tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0104] Figure 4G Shows Figure 4F A cross section of a vertical column 472, wherein MC5 is cut through. Thus, Figure 4G Word line layer WL264, inner core 490, channel 491, tunneling dielectric 492, charge trapping layer 493, aluminum oxide layer 497, and blocking oxide layer 498 are depicted.

[0105] Figure 4H A cross section is shown cutting through a vertical column 472 of SGD1 (the select gate layer implementing the select gates). Figure 4HA drain side select line layer SGD1 , an inner core 490 , a channel 491 , a tunneling dielectric 492 , a charge trapping layer 493 , an aluminum oxide layer 497 , and a blocking oxide layer 498 are depicted.

[0106] Fig. 4I A cross section through a vertical column 434 of SGD1 is shown. Thus, Fig. 4I A drain side select line layer SGD1 , an inner core 490 , a channel 491 , a tunneling dielectric 492 , a charge trapping layer 493 , an aluminum oxide layer 497 , and a blocking oxide layer 498 are depicted. Fig. 4I A portion of the isolation region 482 is also shown. Fig. 4I As can be seen in FIG. 4 , since the vertical column (NAND string) 434 intersects with the isolation region 482, the selection gate (selection gate layer) of the vertical column 434 is in a semicircular shape (or a partially circular shape). Note that FIG. 4E to FIG. 4I The structure described in is applicable to Fig.4C1 , Figure 4C2 , Fig.4D1 , Figure 4D2 , Figure 4D3 and Figure 4D4 implementation plan.

[0107] Figure 4J yes Figures 4 to 4I A schematic diagram of a portion of memory array 202 is depicted in FIG. Figure 4J Physical data word lines WL0 to WL269 are shown extending across the block. Figure 4J The structure corresponds to Figure 4A The portion 406 in block 2 includes bit lines 411. Within this block, in one embodiment, each bit line is connected to six NAND strings. Thus, Figure 4J Bit line 411 is shown connected to NAND string NS0 (which corresponds to vertical column 426), NAND string NS1 (which corresponds to vertical column 436), NAND string NS2 (which corresponds to vertical column 446), NAND string NS3 (which corresponds to vertical column 456), NAND string NS4 (which corresponds to vertical column 466), and NAND string NS5 (which corresponds to vertical column 476). As described above, in one embodiment, SGD0, SGD1, and SGD2 are connected together to operate as a single logic select gate for each region separated by isolation regions (480, 482, 484, 486, and 487) to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5. SGS0, SG1, and SGS2 are also connected together to operate as a single logic select gate for each region separated by isolation regions (480, 482, 484, 486, and 487) to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5. Figure 4JAlthough the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5 are isolated from each other due to the isolation region, the data word lines WL0 to WL269 are connected to the data memory cells in each region (e.g., 420, 430, 44, 450, 460, and 470) of the block. Figure 4J Only the NAND string connected to bit line 411 is shown. However, a complete schematic diagram of the block would show each bit line and the six vertical NAND strings connected to each bit line.

[0108] Although Figures 4 to 4J An example memory of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0109] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 5A is a graph of threshold voltage versus number of memory cells and illustrates an example threshold voltage distribution for a memory array when each memory cell stores one bit of data per memory cell. A memory cell storing one bit of data per memory cell is referred to as a single-level cell ("SLC"). Data stored in an SLC memory cell is referred to as SLC data; therefore, SLC data includes one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Thus, memory cells having threshold voltages in threshold voltage distribution E are in an erased data state (e.g., they are erased). Thus, memory cells having threshold voltages in threshold voltage distribution P are in a programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data "1" and programmed memory cells store data "0". Figure 5A Depicted is a read compare voltage Vr. By testing (eg, performing one or more sensing operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A Also depicted is a verify reference voltage Vv. In some implementations, when programming memory cells to data state P, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv.

[0110] FIG. 5B to FIG. 5F Example threshold voltage distributions for a memory array when each memory cell stores multiple bits of data per memory cell are illustrated. Memory cells that store multiple bits of data per memory cell are referred to as multi-level cells ("MLC"). Data stored in an MLC memory cell is referred to as MLC data; therefore, MLC data includes multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. Figure 5B In an example embodiment, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three bits of data, four bits of data, five bits of data, or six bits of data per memory cell).

[0111] Figure 5B A first threshold voltage distribution E for erasing memory cells is shown. Also depicted are three threshold voltage distributions A, B, and C for programming memory cells. In one embodiment, the threshold voltages in distribution E are negative, and the threshold voltages in distributions A, B, and C are positive. Figure 5B Each different threshold voltage distribution corresponds to a predetermined value for a set of data bits. In one embodiment, each of the two bits of data stored in the memory cell is in a different logical page, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all data bits stored in the memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. Table 1 provides an example encoding scheme.

[0112] Table 1

[0113] E A B C LP 1 0 0 1 UP 1 1 0 0

[0114] In one implementation, referred to as full sequence programming, the Figure 6 The process of programming memory cells directly from erased data state E to any of programmed data states A, B, or C (discussed below) is used. For example, a population of memory cells to be programmed may first be erased so that all memory cells in the population are in erased data state E. Then, a programming process is used to program the memory cells directly to data states A, B, and / or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 5B The arrows represent full sequence programming. In some embodiments, data states A through C may overlap, where the memory controller 120 (or control die 211) relies on error correction to identify the correct data being stored.

[0115] Figure 5C Example threshold voltage distributions for memory cells are depicted, where each memory cell stores three bits of data per memory cell (which is another example of MLC data). Figure 5C Eight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) A ​​to G represent programmed memory cells, and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. In one embodiment, the data value is assigned to the threshold voltage range using Gray code distribution, so that if the threshold voltage of the memory is incorrectly shifted to its adjacent physical state, only one bit will be affected. Table 2 provides an example of a coding scheme for an embodiment in which each bit of the three bits of data stored in the memory cell is in different logical pages, and the logical page is called a lower page (LP), a middle page (MP), and an upper page (UP).

[0116] Table 2

[0117] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0118] Figure 5C Seven read compare voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG are shown for reading data from a memory cell. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read compare voltages, the system can determine the data state (i.e., A, B, C, D, ...) that the memory cell is in.

[0119] Figure 5CAlso shown are seven verification comparison voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when the memory cells are programmed to data state A, the system will test whether the memory cells have a threshold voltage greater than or equal to VvA. When the memory cells are programmed to data state B, the system will test whether the memory cells have a threshold voltage greater than or equal to VvB. When the memory cells are programmed to data state C, the system will determine whether the memory cells have a threshold voltage greater than or equal to VvC. When the memory cells are programmed to data state D, the system will test whether the memory cells have a threshold voltage greater than or equal to VvD. When the memory cells are programmed to data state E, the system will test whether the memory cells have a threshold voltage greater than or equal to VvE. When the memory cells are programmed to data state F, the system will test whether the memory cells have a threshold voltage greater than or equal to VvF. When the memory cells are programmed to data state G, the system will test whether the memory cells have a threshold voltage greater than or equal to VvG. Figure 5C Also shown is Vev, which is the voltage level used to test whether the memory cell has been properly erased.

[0120] In an implementation utilizing full sequence programming, the Figure 6 The process of programming memory cells from erased data state Er directly to any of programmed data states A to G (discussed below) can be used. For example, a group of memory cells to be programmed can be first erased so that all memory cells in the group are in erased data state Er. Then, the programming process is used to program the memory cells directly to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state ER to data state A, other memory cells are being programmed from data state ER to data state B and / or from data state ER to data state C, and so on. Figure 5C The arrows represent full sequence programming. In some embodiments, data states A to G may overlap, where the control die 211 and / or memory controller 120 rely on error correction to identify the correct data being stored. Note that in some embodiments, the system may use a multi-pass programming process known in the art instead of using full sequence programming.

[0121] Generally speaking, during a verify operation and a read operation, a selected word line is connected to a voltage (an example of a reference signal) whose level is determined for each read operation (eg, see Figure 5C of read comparison voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or a verification operation (see, for example, Figure 5CThe verification target voltages (VvA, VvB, VvC, VvD, VvE, VvF, and VvG) of the memory cell are specified in order to determine whether the threshold voltage of the associated memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also called bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0122] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has been discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other reading and verification techniques known in the art can also be used.

[0123] Figure 5D Depicted is a threshold voltage distribution when each memory cell stores four bits of data, which is another example of MLC data. Figure 5D It is shown that there can be some overlap between the threshold voltage distributions (data states) S0 to S15. This overlap can occur due to factors such as memory cells losing charge (and therefore the threshold voltage dropping). Program disturbances can unintentionally increase the threshold voltage of a memory cell. Similarly, read disturbances can unintentionally increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distributions can change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read compare voltage can help mitigate such effects. Using ECC during the read process can repair errors and ambiguities. Note that in some embodiments, the threshold voltage distributions of a population of memory cells storing four bits of data per memory cell do not overlap and are separated from each other; for example, as Figure 5E Depicted. Figure 5D The threshold voltage distribution will include a read compare voltage and a verify compare voltage, as discussed above.

[0124] When four bits are used per memory cell, the memory can be programmed using the full sequence programming discussed above or a multi-pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted for the cell. Table 3 provides an example of an encoding scheme for an embodiment in which each bit of the four bits of data stored in the memory cell is in a different logical page, which is referred to as the lower page (LP), the middle page (MP), the upper page (UP), and the top page (TP).

[0125] Table 3

[0126] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

[0127] Fig. 5F Depicted is a threshold voltage distribution when each memory cell stores five bits of data (which is another example of MLC data). In one example implementation, when the memory cell stores five bits of data, the data is stored in any one of thirty-two data states (eg, S0 to S31).

[0128] Figure 6 2 is a flow chart describing one embodiment of a process for programming memory cells. For the purposes of this document, the term programming is synonymous with writing. In one example embodiment, memory array 202 is programmed using one or more of the control circuits discussed above (e.g., system control logic 260, column control circuitry 210, row control circuitry 220). Figure 6 In one example embodiment, Figure 6 The process is performed by integrated memory component 207 using one or more control circuits (e.g., system control logic 260, column control circuitry 210, row control circuitry 220) of control die 211 to program memory cells on memory die 201. The process includes multiple cycles (referred to as programming cycles), each of which includes a programming phase and a verification phase. Figure 6 to implement full sequence programming, as well as other programming schemes including multi-pass programming, which includes a programming process that uses multiple passes to complete programming. When implementing multi-pass programming, Figure 6 The process is used to implement any / each pass of the multi-pass programming process.

[0129] Typically, the programming voltage applied to the control gate (via the selected data word line) during a programming operation is applied as a series of programming pulses (e.g., voltage pulses). Between the programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 6 In step 602, the programming voltage signal (Vpgm) is initialized to a starting value (e.g., about 12V to 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and all connected to the same word line (the selected word line). There may be other memory cells (unselected memory cells) that are not selected for programming that are also connected to the selected word line. That is, the selected word line will also be connected to the memory cells that should be prohibited from programming. In addition, when the memory cells reach their expected target data state, they will be prohibited from further programming. These NAND strings (e.g., unselected NAND strings) have their channels boosted to prohibit programming, and these strings include memory cells that are connected to the selected word line to be prohibited from programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is not enough to cause programming. To help boost, in step 604, the control die will precharge the channel of the NAND string including the memory cells connected to the selected word line that will be prohibited from programming. In some embodiments, the channel of the unselected NAND string is precharged to clear the electrons of the channel and raise the channel to a low positive voltage (e.g., about 1v to 1.3v). In step 606, the NAND string including the memory cell connected to the selected word line to be prohibited from programming has its channel boosted to prohibit programming. Such NAND strings are referred to as "unselected NAND strings" herein. In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7 volts to 11 volts) (also referred to as pass voltage) to perform the boost scheme. The program inhibit voltage is applied to the bit line of the coupled unselected NAND string. For example, in one embodiment, the channel is precharged to about 2 volts and then floated in step 604. In step 606, the channel is boosted from 2 volts to a boost voltage of about 8 volts to 10 volts.

[0130] In step 608, a programming voltage pulse of a programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). In some embodiments, the magnitude and / or pulse width of the programming voltage pulse may be modified by one or more offsets from the standard magnitude and / or pulse width, as described below. If the memory cell on the NAND string should be programmed, the corresponding bit line is biased at a programming enable voltage. In step 608, a programming pulse is applied simultaneously to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed simultaneously (unless they are prohibited from programming). That is, they are programmed at the same time or during overlapping time (both are considered to be simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changes at the same time unless they are prohibited from programming.

[0131] In step 610, program verification is performed and memory cells that have reached their target state are locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verify compare levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verify compare voltage. Figure 5C In one embodiment, executing Figure 6 6. The process for memory cells being programmed to data states A, B, C, D, E, F, and G. In one embodiment, step 610 may include testing each of the data states A, B, C, D, E, F, and G (e.g., testing to see if the threshold voltage of the memory cell is greater than VvA, VvB, VvC, VvD, VvE, VvF, and VvG). In another embodiment, the system tests only a subset of data states A, B, C, D, E, F, and G based on the current threshold voltage of the memory cell during each cycle of steps 604 to 626 in a process referred to as smart verification. In step 610, after the memory cell has been verified (by testing of Vt) that the memory cell has reached its target state, the memory cell may be locked out.

[0132] If, in step 612, it is determined that all memory cells have reached their target threshold voltage (PASS), then the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. In step 614, a "PASS" status is reported. Otherwise, if, in step 612, it is determined that not all memory cells have reached their target threshold voltage (FAIL), then the programming process will continue to step 616.

[0133] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution is counted. That is, the number of memory cells that have so far been unable to reach their target state is counted. This counting may be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0134] In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and report a "pass" status in step 614. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming less than all memory cells of a page, or comparing counts of only one data state (or less than all states), the predetermined limit can be a portion (proportional or non-proportional) of the number of bits that can be corrected by ECC during the read process of a page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0135] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 620 and checks the programming counter PC against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​may be used. If the programming counter PC is not less than the programming limit value PL, the programming process is deemed to have failed and a "failed" status is reported in step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is a step size ΔVpgm (e.g., a step size of 0.1 volts to 1.0 volts) greater than the previous pulse. After step 626, the process loops back to step 604 and another programming pulse is applied (to the control die) to the selected word line so that execution Figure 6 Another cycle of the programming process (steps 604 to 626). Figure 6 The cycle of the programming process (steps 604 to 626) is called a program cycle.

[0136] In one embodiment, the memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from Figure 5A The state P changes to the state E, from Figure 5B The state A / B / C changes to state E, from Figure 5C A changes to state G or changes from state E to state G Figure 5D States S1 to S15 are changed to state S0.

[0137] One technique for erasing memory cells in some memory devices is to bias the p-well (or other type) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell to erase the memory cell. This is referred to herein as p-well erase.

[0138] Another method of erasing a memory cell is to generate a gate induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential to erase the memory cell. This is referred to herein as GIDL erase. Both p-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of a memory cell.

[0139] In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a GIDL generating transistor (e.g., a transistor connected to SGDT0, SGDT1, SGDT2, SGSB0, SGSB1, and SGSB2). In some embodiments, a select gate (e.g., SGD or SGS) may be used as a GIDL generating transistor. The drain-to-gate voltage of the transistor that generates the GIDL current is referred to herein as the GIDL voltage. When the drain voltage of the GIDL generating transistor is significantly higher than the control gate voltage of the GIDL generating transistor, a GIDL current may be generated. The GIDL current is the result of carrier generation, i.e., electron-hole pair generation and / or trap-assisted generation due to band-band tunneling. In one embodiment, the GIDL current may cause one type of carrier (also referred to as charge carrier) (e.g., hole) to move primarily into the NAND channel, thereby increasing or changing the potential of the channel. Another type of carrier (e.g., electron) is extracted from the channel by an electric field in the direction of the bit line or in the direction of the source line. During erase, holes can tunnel from the channel to the charge storage region of the memory cell (eg, to the charge trapping layer 493) and recombine with electrons therein to lower the threshold voltage of the memory cell.

[0140] A GIDL current may be generated at either end (or both ends) of a NAND string. A first GIDL voltage may be generated between two terminals of a GIDL generating transistor (e.g., connected to SGDT0, SGDT1, SGDT2) connected to or near a bit line to generate a transistor to generate a first GIDL current. A second GIDL voltage may be generated between two terminals of a GIDL generating transistor (e.g., SGSB0, SGSB1, and SGSB2) connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current only at one end of a NAND string is referred to as single-sided GIDL erasing. Erasing based on GIDL current at both ends of a NAND string is referred to as double-sided GIDL erasing. The techniques described herein may be used with single-sided GIDL erasing and double-sided GIDL erasing.

[0141] The above article about Figure 6 The discussion of describes a process for programming nonvolatile memory cells connected to a common word line. However, in some cases, the amount of data received for programming is too large to be stored on one word line. Therefore, it is necessary to store the data in nonvolatile memory cells connected to multiple word lines.

[0142] Figure 7 is a flow chart describing one embodiment of a process for programming nonvolatile memory cells connected to multiple word lines. Figure 7 The process may be performed by any of the control circuits discussed above. For example, Figure 7The process can be completely handled by the memory die 200 (see Figure 2A ) or by the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of system control logic 260, column control circuitry 210, and row control circuitry 220. Figure 7 In another embodiment, Figure 7 The process is performed by the memory controller 120 or under the direction of the memory controller.

[0143] exist Figure 7 In step 702, the control circuit receives data (e.g., from the host 102 or another entity). The amount of data received is too large to be stored on one word line. Therefore, it is necessary to store the data in non-volatile memory cells connected to multiple word lines. In step 704, the control circuit selects a sub-block to store the received data, the selection including selecting a block and a sub-block of the selected block. In step 706, an initial word line is selected. For example, if the sub-block is completely erased and does not store any data, an ending word line may be selected (e.g., for Figure 4D3 In step 708, the control circuit uses Figure 6 The process of programming a portion of the received data into the current word line. In step 710, it is determined whether more data needs to be programmed. If not, the control circuit reports to the host (or other entity) in step 712 that the programming has been completed. If there is more data to be programmed, the next word line for programming needs to be selected. If the control circuit is programming SB0 (see step 714), the next word line selected (step 716) is the adjacent word line in the source line direction. That is, WLx=WLx-1. Therefore, if the current word line being programmed is WL40, the next word line selected is WL39. If the control circuit is programming SB1 (see step 714), the next word line selected (step 718) is the adjacent word line in the bit line direction. That is, WLx=WLx+1. Therefore, if the current word line being programmed is WL230, the next word line selected is WL231. After selecting the next word line (step 716 or step 718), the process loops back to step 708 to program the memory cells connected to the newly selected word line. Figure 7 The process includes controlling the circuit for a two-level architecture (see, for example, Figure 4D3 ) in the direction according to arrows 502 / 504 or for a three-tier architecture (see, for example, Figure 4D4) Programming is performed on a word-by-word line basis in the direction according to arrows 520 / 522.

[0144] When using Figure 7 When programming memory cells by a process of (or other programming process), the memory cells are programmed to a set of threshold voltage distributions (e.g., see FIG. 5A to FIG. 5F ). The memory system is engineered so that the set of threshold voltage distributions takes into account interference from other memory cells, capacitive coupling from other memory cells, drift over time, other data retention issues, programming errors, read errors, etc. Due to the different programming orders of SB0 and SB1 (see, e.g., Figure 4D3 and Figure 4D4 ), different sub-blocks can be programmed to different groups of threshold voltage distributions. For example, Fig. 8A Threshold voltage distributions 802, 804, 806, 808, 810, 812, 814, and 816 of an ideal memory are shown, where SB0 and SB1 are programmed to exactly the same threshold voltage distribution. However, in many cases, the memory cells of SB1 (using the above description of Figure 4D3 and Figure 4D4 The programming order discussed) may experience more interference from memory cells on adjacent word lines. For example, Figure 8B Depicted are threshold voltage distributions 820, 822, 824, 826, and 828 that deviate from (and are wider than) corresponding threshold voltage distributions 802, 804, 806, 808, and 810, respectively, due to memory cells of SB1 experiencing more interference from memory cells on neighboring word lines than memory cells of SB0. This deviation is one example of differences in how levels / sub-blocks perform memory operations. As device sizes shrink, differences in how levels / sub-blocks perform memory operations become more pronounced and these differences make it difficult to operate memory reliably. To address this issue, it is proposed to use different word line to word line spacings in different levels and / or different sub-blocks. For example, it is proposed to use Figure 4D3 and Figure 4D4 Thus, one embodiment includes word lines in a first level separated by a first word line to word line spacing and word lines in a second level separated by a second word line to word line spacing, such that the first word line to word line spacing is different from the second word line to word line spacing. In another embodiment, word lines in a first sub-block are separated by a first word line to word line spacing, and word lines in a second sub-block are separated by a second word line to word line spacing. As described above, using different word line to word line spacings for different sub-blocks / levels results in different sub-blocks / levels programming data into the same set of threshold voltage distributions (e.g., 802 to 816).

[0145] Fig. 9is a method for manufacturing nonvolatile memory (e.g., Figure 4D3 or Figure 4D4 902, a source line (e.g., SL) is added to the memory structure. This source line will be below the lower sub-block (e.g., SB0). In step 904, the lower sub-block (e.g., SB0) is manufactured and added to the memory structure. The word lines in the lower sub-block are separated by a first word line to word line spacing. In step 906, one or more connection regions are added to the memory structure. In step 908, an upper sub-block (e.g., SB1) is manufactured and added to the memory structure. The word lines in the upper sub-block are separated by a second word line to word line spacing. The second word line to word line spacing is greater than the first word line to word line spacing (e.g., WL2>WP1). In step 910, multiple bit lines are added above the upper sub-block of the memory structure.

[0146] In step 912, the control circuit programs the memory cells of the upper sub-block on a word-line basis in a direction toward the bit lines (see, e.g., arrows 504 / 522). The arrow between steps 910 and 912 is dot-dashed to indicate that step 912 may be performed immediately after step 910 (e.g., during a manufacturing and / or testing phase) or later in time (e.g., during user operation). In step 914, the control circuit programs the memory cells of the lower sub-block on a word-line basis in a direction toward the source lines (see, e.g., arrows 502 / 520).

[0147]

[0013] Nonvolatile memories have been described that use different wordline to wordline spacings in different sub-blocks and / or different levels in order to achieve uniform performance between different sub-blocks and / or different levels.

[0148] One embodiment includes a nonvolatile memory structure including a plurality of nonvolatile memory cells and a plurality of word lines connected to the memory cells. The word lines and the memory cells are organized into at least a first level and a second level. The second level is positioned above the first level. The word lines in the first level are separated by a first word line to word line spacing. The word lines in the second level are separated by a second word line to word line spacing. The first word line to word line spacing is different from the second word line to word line spacing.

[0149] In one example implementation, the first level is a first sub-block and the second level is a second sub-block.

[0150] In one example implementation, the nonvolatile memory cells are arranged as NAND strings divided into at least a first level, a second level, and a middle level, with a first connection region between the first level and the middle level, and a second connection region between the second level and the middle level. In this example embodiment, the middle level is divided into a top portion and a bottom portion, the word lines in the top portion of the middle level are separated by the second word line to word line spacing; and the word lines in the bottom portion of the middle level are separated by a first word line to word line spacing. The first level and the bottom portion of the middle level are configured to operate together as a first sub-block; and the second level and the top portion of the middle level are configured to operate together as a second sub-block.

[0151] In one example implementation, the non-volatile memory cells are arranged as NAND strings divided into at least the first level and the second level with a linking region between the first level and the second level.

[0152] In one example implementation, the nonvolatile memory structure further includes a plurality of bit lines, each NAND string is connected to one of the bit lines, each of the word lines is connected to all of the NAND strings; one or more source lines, each NAND string is connected to the one or more source lines; and a control circuit connected to the bit lines, word lines, and one or more source lines. The control circuit is configured to program the second level of memory cells on a word line by word line basis in a direction toward the bit lines, and the control circuit is configured to program the first level of memory cells on a word line by word line basis in a direction toward the one or more source lines. Additionally, in this example implementation, the second word line to word line spacing is greater than the first word line to word line spacing.

[0153] One embodiment includes a method of fabricating a nonvolatile memory structure, the method comprising: fabricating a lower sub-block having a first wordline to wordline spacing; and fabricating an upper sub-block above the lower sub-block having a second wordline to wordline spacing, the second wordline to wordline spacing being greater than the first wordline to wordline spacing.

[0154] One embodiment includes a nonvolatile memory structure, the nonvolatile memory structure comprising: a block of nonvolatile memory cells arranged as NAND strings, the block divided into two or more sub-blocks, the two or more sub-blocks including at least a first sub-block and a second sub-block; a plurality of bit lines, each NAND string connected to one of the bit lines; a plurality of word lines, each of the word lines connected to all of the NAND strings, the word lines connected to the memory cells in the first sub-block separated by a first word line to word line spacing, and the word lines connected to the memory cells in the second sub-block separated by a second word line to word line spacing, the second word line to word line spacing being different from the first word line to word line spacing; one or more source lines, each NAND string connected to the one or more source lines; and a control circuit connected to the bit lines, word lines, and one or more source lines. The control circuit is configured to program the memory cells of the second sub-block on a word line by word line basis in a direction toward the bit lines. The control circuit is configured to program the memory cells of the first sub-block on a word line by word line basis in a direction toward the one or more source lines.

[0155] In one example implementation, the word lines and memory cells are arranged into at least a top level, a lower level, and an intermediate level positioned between the top level and the lower level; the intermediate level is divided into a top portion and a bottom portion; the first sub-block includes the bottom level and the bottom portion of the middle level; the second sub-block includes the top level and the top portion of the middle level; the word lines in the top level and the top portion are separated by the second word line to word line spacing; and the word lines in the bottom level and the bottom portion are separated by the first word line to word line spacing.

[0156] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0157] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0158] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0159] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0160] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0161] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A non-volatile memory structure, the non-volatile memory structure comprising: a plurality of non-volatile memory cells; and A plurality of word lines connected to the memory cells, the word lines and the memory cells being organized into at least a first level and a second level positioned above the first level, the word lines in the first level being separated by a first word line to word line spacing, the word lines in the second level being separated by a second word line to word line spacing, the first word line to word line spacing being different from the second word line to word line spacing.

2. The non-volatile memory structure according to claim 1, wherein: The first level is a first sub-block; and The second level is a second sub-block.

3. The non-volatile memory structure according to claim 1, wherein: The second word line to word line spacing is greater than the first word line to word line spacing.

4. The non-volatile memory structure according to claim 1, further comprising: A connection region, the first level is separated from the second level by the connection region.

5. The non-volatile memory structure according to claim 4, wherein: The first level has a first end opposite the attachment region; The second level has a second end opposite the attachment region; The memory cells of the first level are configured to be programmed on a word-line basis in a direction from the junction toward the first end; and The memory cells of the second level are configured to be programmed on a word-line basis in a direction from the junction toward the second end.

6. The non-volatile memory structure according to claim 1, further comprising: Additional nonvolatile memory cells and additional word lines connected to the additional nonvolatile memory cells are arranged in an intermediate level below the second level and above the first level.

7. The non-volatile memory structure according to claim 6, wherein: The middle level is divided into a top portion and a bottom portion; word lines in the top portion of the intermediate level are separated by the second word line to word line spacing; and Word lines in the bottom portion of the intermediate level are separated by the first word line to word line spacing.

8. The non-volatile memory structure according to claim 7, wherein: The first level and the bottom portion of the intermediate level are configured to operate together as a first sub-block; and The second level and the top portion of the intermediate level are configured to operate together as a second sub-block.

9. The non-volatile memory structure according to claim 1, further comprising: a plurality of bit lines connected to the nonvolatile memory cells; one or more source lines connected to the nonvolatile memory cells; and a control circuit connected to the word lines, the bit lines, and the one or more source lines; The control circuitry is configured to program the second level of memory cells on a word line by word line basis in a direction toward the bit lines, and the control circuitry is configured to program the first level of memory cells on a word line by word line basis in a direction toward the one or more source lines.

10. The non-volatile memory structure according to claim 1, wherein: The non-volatile memory cells are arranged as NAND strings divided into at least the first level and the second level with a linking region therebetween.

11. The non-volatile memory structure according to claim 10, further comprising: a plurality of bit lines, each NAND string connected to one of the bit lines, each of the word lines connected to all of the NAND strings; one or more source lines to which each NAND string is connected; and a control circuit connected to the bit lines, the word lines, and the one or more source lines; The control circuit is configured to program the second level of memory cells on a word line basis in a direction toward the bit line, and the control circuit is configured to program the first level of memory cells on a word line basis in a direction toward the one or more source lines, and the second word line to word line spacing is greater than the first word line to word line spacing.

12. A method for manufacturing a non-volatile memory structure, the method comprising: fabricating a lower sub-block having a first wordline to wordline spacing; as well as An upper sub-block is fabricated over the lower sub-block having a second word line to word line spacing that is greater than the first word line to word line spacing.

13. The method according to claim 12, further comprising: A linking region is added between the upper sub-block and the lower sub-block, the manufacturing the lower sub-block includes adding a plurality of word lines at the first word line to word line spacing, and the manufacturing the upper sub-block includes adding a plurality of word lines at the second word line to word line spacing.

14. The method according to claim 12, further comprising: adding a source line below the lower sub-block; adding a plurality of bit lines above the upper sub-block; programming memory cells of the upper sub-block on a word-line-by-word-line basis in a direction toward the bit lines; as well as Memory cells of the lower sub-block are programmed on a word-line basis in a direction toward the source line.

15. The method according to claim 12, further comprising: The fabricating the lower sub-block and the fabricating the upper sub-block include fabricating three-level word lines separated by a linking region.

16. A non-volatile memory structure, the non-volatile memory structure comprising: a block of non-volatile memory cells arranged as NAND strings, the block divided into two or more sub-blocks, the two or more sub-blocks comprising at least a first sub-block and a second sub-block; a plurality of bit lines, each NAND string being connected to one of the bit lines; a plurality of word lines, each of the word lines connected to all of the NAND strings, the word lines connected to the memory cells in the first sub-block being separated by a first word line to word line spacing, and the word lines connected to the memory cells in the second sub-block being separated by a second word line to word line spacing, the second word line to word line spacing being different from the first word line to word line spacing; one or more source lines to which each NAND string is connected; and a control circuit connected to the bit lines, the word lines, and the one or more source lines; The control circuit is configured to program the memory cells of the second sub-block on a word line basis in a direction toward the bit lines, and the control circuit is configured to program the memory cells of the first sub-block on a word line basis in a direction toward the one or more source lines.

17. The non-volatile memory structure of claim 16, wherein: The second word line to word line spacing is greater than the first word line to word line spacing.

18. The non-volatile memory structure of claim 16, wherein: The first sub-block includes a first level word line; and The second sub-block includes a second-level word line separated from the first-level word line by a linking region.

19. The non-volatile memory structure of claim 18, wherein: The bit line is positioned above the second level; and The one or more source lines are positioned below the first level.

20. The non-volatile memory structure of claim 16, wherein: The word lines and the memory cells are arranged into at least a top level, a lower level, and an intermediate level between the top level and the lower level; The middle level is divided into a top portion and a bottom portion; The first sub-block includes the bottom level and the bottom portion of the middle level; the second sub-block includes the top level and the top portion of the middle level; the word lines in the top level and the top portion are separated by the second word line to word line spacing; and Word lines in the bottom level and the bottom portion are separated by the first word line to word line spacing.

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