SiC-MOSFET Miller platform voltage online monitoring circuit and method based on gate oscillation

Abstract

The SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation provided by the present invention includes a signal trigger circuit, a trigger signal isolation circuit, a sampling and holding circuit and a data processing circuit; the input end of the signal trigger circuit is connected to the gate of M2, the output end of the signal trigger circuit is connected to the input end of the trigger signal isolation circuit, and the trigger signal isolation circuit, the sampling and holding circuit, and the data processing circuit are electrically connected in sequence; the signal trigger circuit determines whether the driving voltage of M1 reaches the Miller platform moment by detecting whether the driving voltage of M2 generates damped attenuation oscillation, and then determines whether to trigger the Miller platform voltage acquisition signal; the sampling and holding circuit keeps the extracted driving voltage stable after the Miller platform voltage acquisition signal is triggered, and this driving voltage is the M1 Miller platform voltage. The present invention has a simple structure and can quickly and accurately obtain the Miller platform voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of online monitoring of characteristic parameters of SiC-MOSFET, and in particular to an online monitoring circuit and method for Miller platform voltage of SiC-MOSFET based on gate oscillation. Background Art

[0002] In the application process of gate devices such as SiC-MOSFET, a unique phenomenon, the Miller platform, can be used to reflect the switching speed, junction temperature and even efficiency of the device. Accurate measurement and analysis of the Miller platform is of great significance for in-depth understanding of the switching characteristics of SiC-MOSFET and monitoring the operating status of SiC-MOSFET, and then improving the reliability and efficiency of power equipment through active control and equipment maintenance.

[0003] At present, the measurement technologies of Miller platform voltage mainly include waveform recognition after direct online measurement and measurement scheme based on industrial control chip control signal. Unfortunately, in actual application, the former requires all the driving voltage data during the conduction action to be collected and then analyzed by digital waveform, which consumes a lot of time and cannot monitor the Miller platform voltage in each switching cycle, and the additional circuits are numerous and complex. In addition, it is more difficult to identify the waveform when the Miller platform is not obvious due to excessive addition of gate-source capacitance. The latter may encounter interference factors such as signal delay, which will affect the accuracy and timeliness of measuring the Miller platform voltage. Summary of the invention

[0004] In order to solve the problems that the traditional additional circuit for identifying the Miller platform voltage of SiC-MOSFET is complex and inefficient, and it is difficult to identify the subtle Miller platform voltage, the present invention provides a SiC-MOSFET Miller platform voltage online monitoring circuit and method based on gate oscillation.

[0005] In order to solve the above technical problems, the present invention adopts the following technical methods: a SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation, including a data processing circuit that performs analog-to-digital conversion and calculation on data, and also includes a signal trigger circuit, a trigger signal isolation circuit and a sample-and-hold circuit;

[0006] The SiC-MOSFET in the same bridge arm of the inverter in the conduction process is , the SiC-MOSFET in the off state is ;

[0007] The input terminal of the signal trigger circuit is connected to The gate of the signal trigger circuit is connected, the output end of the signal trigger circuit is connected to the input end of the trigger signal isolation circuit, and the trigger signal isolation circuit, the sampling and holding circuit, and the data processing circuit are electrically connected in sequence;

[0008] The signal triggers the circuit by detecting The driving voltage of Whether the driving voltage reaches the Miller platform moment, and then determine whether to trigger the Miller platform voltage acquisition signal;

[0009] The trigger signal isolation circuit is used to isolate the signal trigger circuit from the sample and hold circuit;

[0010] The sample-and-hold circuit is used to extract The driving voltage is kept constant after the Miller platform voltage acquisition signal is triggered. The constant driving voltage is The sampling and holding circuit is also used to transmit the extracted driving voltage to the data processing circuit.

[0011] Furthermore, the signal trigger circuit includes a high-speed optical coupler 、PMOS tube and NMOS tube , The positive and negative electrodes of the photodiode are respectively The front-stage power supply terminal and the driving signal terminal of the driving chip are connected, and the The emitter and collector of the phototransistor are respectively connected to The drain, The drain connection of the The source and gate of The 0V power supply terminal of the driver chip, The gate connection of The source and gate of The low-level power supply terminal of the driver chip, The gate connection of the The drain is connected to the trigger signal isolation circuit.

[0012] Furthermore, the trigger signal isolation circuit includes a high-speed optical coupler 、PMOS tube and NMOS tube , and The gates of The drain connection of the , The source of , The source connection of the and The drain of The positive terminal of the photodiode is connected to the The cathode of the photodiode is connected to The source connection of the The collector of the phototransistor is The rear low-level power supply terminal of the driver chip is connected, The emitter of the phototransistor is connected to the sample-and-hold circuit.

[0013] Furthermore, the sample-and-hold circuit includes an NMOS tube ,capacitance , parasitic inductance ,capacitance and voltage follower AMP, the The gate and The emitter of the phototransistor is connected, and the pull-up line between the two has a The resistor connected to the high-level power supply terminal of the driver chip , The drain and The gate connection, and the The drain After The output terminal of the driver chip is connected to the The Source Sutra After The source connection of the In parallel with and The two ends of the line are composed of the non-inverting input of the AMP and The source terminal of the AMP is connected to the data processing circuit.

[0014] Preferably, the data processing circuit includes an ADC converter and an FPGA chip, the input end of the ADC converter is connected to the output end of the AMP, and the output end of the ADC converter is connected to the FPGA chip.

[0015] As another aspect of the present invention, a method for online monitoring of the Miller platform voltage of SiC-MOSFET based on gate oscillation is provided, which uses the aforementioned online monitoring circuit for the Miller platform voltage of SiC-MOSFET based on gate oscillation to perform online monitoring of the Miller platform voltage of SiC-MOSFET.

[0016] The SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation provided by the present invention is connected to the SiC-MOSFET driver chip, does not require additional new power supply, does not require control signals from the industrial control chip, and has a very simple structure. The present invention determines whether the driving voltage of the SiC-MOSFET in the conduction process reaches the Miller platform moment by detecting whether the driving voltage of the SiC-MOSFET in the off state generates damped attenuation oscillation, thereby determining whether to intercept the Miller platform voltage, and using a capacitor to keep the intercepted Miller platform voltage stable during the device conduction period, so that the Miller platform voltage can be obtained quickly and accurately, and subsequent digital sampling can be facilitated, and the original device switching speed is not affected. In general, the monitoring circuit provided by the present invention has a simple structure and high efficiency in identifying the Miller platform voltage, which effectively solves the problems of slow identification speed of the Miller platform voltage, complex identification circuit, difficulty in identifying the inconspicuous Miller platform, and interference from the delay of the control signal of the industrial control chip that affects the accuracy and timeliness of identification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the SiC-MOSFET equivalent model considering the inter-electrode junction capacitance in the present invention;

[0018] Figure 2 Schematic diagram of the equivalent circuit of the SiC-MOSFET half-bridge structure in the present invention;

[0019] Figure 3 It is a schematic diagram of a SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation according to the present invention;

[0020] Figure 4 This is the schematic diagram of the inverter SiC-MOSFET half-bridge dual-pulse main circuit in the present invention;

[0021] Figure 5 The schematic diagram of the driving circuit of the inverter SiC-MOSFET half-bridge dual-pulse main circuit in the present invention (where (a) is Schematic diagram of the driving circuit; (b) is Schematic diagram of the driving circuit);

[0022] Figure 6 It is a connection topology diagram of the Miller platform voltage online monitoring circuit and the inverter in the present invention;

[0023] Figure 7 It is obtained through simulation experiments in this embodiment. and Waveform comparison chart;

[0024] Figure 8The original embodiment without the monitoring circuit and the embodiment after adding the monitoring circuit of the present invention are shown in FIG. Comparison chart of simulation waveforms. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of those skilled in the art, the present invention is further described below in conjunction with embodiments and drawings. The contents mentioned in the implementation modes are not intended to limit the present invention.

[0026] Before describing the present invention, the Miller platform voltage is first described as follows.

[0027] With the continuous evolution of semiconductor integration technology, many driver chips designed for power devices have emerged. These chips have shown excellent ability in solving power device driving problems. Especially in the process of driving bridge inverter circuits, a noteworthy phenomenon is that the gate drive signal will oscillate at the moment of turning on the upper (or lower) tube of the same bridge arm. When the amplitude of this oscillation reaches a high level, the switching device may be damaged due to the shoot-through phenomenon.

[0028] When considering the inter-electrode junction capacitance of SiC-MOSFET, you can refer to Figure 1 The equivalent model shown in Figure 1 shows that the three junction capacitors together form a complex capacitive network at the gate input. At the same time, the drive circuit also includes distributed inductance. And the driving resistor ,like Figure 2 shown.

[0029] When the lower tube in the bridge arm When fully turned off, the gate and source potentials tend to be consistent. In the process of switching from off state to quick on state, when When the driving voltage rises to the Miller platform, The voltage between the drain and the source will quickly drop from the DC side voltage originally carried to zero. At this time, the voltage will be transferred to the lower transistor that has been turned off. Therefore, The voltage between the drain and source will rise rapidly, resulting in a very high voltage change rate. . And this high Will cause downpipe of The two ends begin to charge, inducing displacement current , the displacement current enters After the driving circuit, due to parasitic inductance The suppression effect on the current will give the junction capacitance Charging forces the drive voltage , producing a damped oscillatory voltage fluctuation, such as Figure 2 Similarly, when the lower tube in the bridge arm is turned on and the upper tube is turned off, a similar oscillation phenomenon will occur between the gate and source of the upper tube, but its phase is opposite to the oscillation phase generated when the lower tube is turned on.

[0030] In summary, we can draw a conclusion that when When the driving voltage reaches the Miller platform, it is in the off state. The driving voltage This will produce a damped oscillation. This oscillation can be used to accurately capture The platform voltage is generated at the moment.

[0031] Based on this, the present invention provides a SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation, such as Figure 3 As shown, the circuit is composed of a signal trigger circuit, a trigger signal isolation circuit, a sampling and holding circuit, and a data processing circuit connected in sequence. Specifically:

[0032] The SiC-MOSFET in the same bridge arm of the inverter in the conduction process is , the SiC-MOSFET in the off state is .

[0033] The signal trigger circuit includes a high-speed optocoupler 、PMOS tube and NMOS tube , The positive and negative electrodes of the photodiode are respectively The front-stage power supply terminal and the driving signal terminal of the driver chip are connected. The emitter and collector of the phototransistor are respectively connected to The drain, The drain connection, The source and gate of The 0V power supply terminal of the driver chip, The gate connection; The source and gate of The rear stage of the driver chip - 4V power supply terminal, The gate connection, The drain is connected to the trigger signal isolation circuit.

[0034] The trigger signal isolation circuit includes a high-speed optocoupler 、PMOS tube and NMOS tube , and The gates of The drain connection, , The source of , The source connection, and The drain of The positive terminal of the photodiode is connected to The cathode of the photodiode is connected to The source connection, The collector of the phototransistor is The rear stage -4V power supply terminal of the driver chip is connected. The emitter of the phototransistor is connected to the sampling and holding circuit. It is worth mentioning that the present invention uses a trigger signal isolation circuit to isolate the signal trigger circuit from the sampling and holding circuit. The reason for this is that the present invention uses a trigger signal isolation circuit to isolate the signal trigger circuit from the sampling and holding circuit. The drive signal control measurement The Miller plateau voltage, however and Belong to different power supply systems. If they are not isolated, If the control signal is added to the sample-and-hold circuit, the potential difference between different power supplies will make it impossible to monitor the Miller platform voltage, thus affecting the measurement result.

[0035] The sample-and-hold circuit includes an NMOS tube ,capacitance , parasitic inductance ,capacitance and voltage follower AMP, The gate and The emitter of the phototransistor is connected, and the pull-up line between the two has a The resistor connected to the 15V power supply terminal of the driver chip , The drain and The gate connection of The drain After The output terminal of the driver chip is connected to The Source Sutra After The source connection, In parallel with and The two ends of the line are composed of the AMP and the non-inverting input terminal. The source terminal of the AMP is connected to the data processing circuit.

[0036] The data processing circuit includes an ADC converter and an FPGA chip. The input end of the ADC converter is connected to the output end of the AMP, and the output end of the ADC converter is connected to the FPGA chip.

[0037] The Miller platform voltage online monitoring circuit of the present invention detects The gate voltage is judged by whether it has damped oscillation. Whether the driving voltage reaches the Miller platform moment. Before oscillation, In the off state, this means The driving voltage has not yet reached the Miller platform moment, so The subsequent stage is not conducting (which indicates that the Miller platform voltage acquisition signal is not triggered). In the on state, Equivalent to directly connecting The gate source, The voltage across follow When oscillation occurs, The gate-source voltage changes so that This means that The driving voltage reaches the Miller platform moment. The next stage is turned on (this indicates that the Miller platform voltage acquisition signal is triggered). Shutdown, At The gate-source is separated. The voltage across Stay stable and don't follow Change together, voltage It is first acquired by the AMP, then sent to the ADC converter for analog-to-digital conversion, and finally processed and calculated by the FPGA chip to obtain The Miller platform voltage value.

[0038] like Figure 4 The figure shows the inverter SiC-MOSFET half-bridge dual-pulse main circuit, which consists of the upper tube and down tube Composition. Figure 5 As shown, it is the driving circuit of the inverter SiC-MOSFET half-bridge dual-pulse main circuit. Figure 5 In the middle, on the left is The driver chip on the right is Driver chips, both of which contain 7 pins. For the driver chip, +5V and GND They are the 5V power supply terminal and ground terminal of the front stage of the driver chip ( The same is true for the driver chip). VIA It means The drive signal of the driver chip, +15V-A, -4V-A, 0V-A respectively represent The high level, low level, and 0V power supply terminals of the driver chip are represented by +15V-B, -4V-B, and 0V-B, respectively. The high level, low level, and 0V power supply terminals of the driver chip are VGA and VGB respectively. , The output signal of the driver chip, The VGB terminal passes through the parasitic inductance After The gate drive signal here and The difference between the driver chip and the VGA terminal is that the VGA terminal is not directly connected to the parasitic inductor, but is connected to the Figure 3 In the sample-and-hold circuit shown, As parasitic inductance, for The gate drive signal is The VGA terminal of the driver chip is connected to the sample-and-hold circuit, and the parasitic inductance The signal obtained later Connected to the double pulse main circuit together with 0v-A as The gate-source voltage is The signal obtained by the driver chip and Connected to the double pulse main circuit as The gate-source voltage.

[0039] Reference Figure 6 , the Miller platform voltage online monitoring circuit provided by the present invention is connected to the inverter to perform online monitoring of the Miller platform voltage. The specific working principle is as follows:

[0040] (1) The driving voltage Before reaching Miller's Terrace:

[0041] In the double pulse test circuit, when When entering the conduction process, the voltage between the gate and the source Continues to rise, and now The drive voltage remains off. Maintain at a low level of -4V. At this time, in the measurement circuit of the Miller platform voltage, As a PMOS device, the gate (point b) potential is -4V, the source (point a) potential is 0V_B (0V), and the voltage applied between its gate and source is sufficient to turn it on. Entering the conduction process, the driving signal of the driver chip VIA Before this, it has changed from low level to high level. The front photodiode does not emit light, that is The phototransistor in the next stage is not conducting. As an NMOS device, the gate (point e) potential is -4V, and the source (point f) potential is -4V_B (-4V). In the off state.

[0042] In summary, Conductivity, The next stage is not conducting. In the off state, the potential at point d is in a high impedance floating state, and the potential is 0V_B (0V). VIA Before it becomes high level, it is still in the low level period. Keep off state, Conductivity, The next stage is turned on. Being in the off state causes the potential at point d to become 0V_B (0V). Therefore, when the potential at point d becomes a high-resistance floating state, the potential does not change. The next stage is not conducting. The high-resistance floating state caused by the shutdown state is to avoid grabbing the Miller platform moment conduction , , All are conducting and short circuited.

[0043] When the potential at point d is floating 0V_B (0V), As a PMOS device, it remains in the off state. As an NMOS device, it remains in the on state, and the potential at point h remains at -4V_B (-4V). The front stage is broken, so The next stage is not conducting. Point e remains at +15V_A. As an NMOS device, it remains in the on state. The Miller platform voltage extraction capacitor has a very small value Connected in parallel to the upper tube The gate-source voltage follow Change together.

[0044] (2) The driving voltage Arrival time at Miller Platform:

[0045] exist The gate-source voltage When the Miller platform voltage is reached, according to the oscillation mechanism mentioned above, The driving signal undergoes a certain amplitude of upward damped oscillation. rises until the potential difference between point e and point f reaches The conduction condition is After the conduction, the potential at point d quickly changes to -4V_B (-4V). In this case, even if the oscillation disappears, the high-resistance floating state at point d will continue to maintain -4V_B (-4V). This method can intercept the Miller voltage and continue to maintain it for a period of time. After the potential at point d quickly changes to -4V_B (-4V), Converted to the on state, When the device is switched to the off state, the potential at point h becomes 0V_B (0V). In the front stage path, the photodiode emits light, so The next stage is turned on. Point e becomes -4V_A. It should be noted that The voltage at both ends has followed the Miller platform voltage (usually above 4V). The Miller plateau voltage extraction capacitor has a very small value. Yu Shangguan The gate source is detached and no longer follows Change together, now The voltage across It is the Miller platform voltage. From the above principle, it can be known that the present invention can quickly and accurately intercept the Miller platform voltage and maintain the Miller platform voltage during the device conduction period to facilitate subsequent digital sampling.

[0046] In order to verify the working effect of the Miller platform voltage online monitoring circuit proposed in the present invention to intercept the Miller platform voltage, a double pulse simulation is set up in LTspice, and the connection topology of the main components is referenced Figure 6 The main device parameters and models used in the simulation experiment are as follows Table 1:

[0047] ,

[0048] The simulation experiment process is as follows:

[0049] according to Figure 6 As shown, The device is turned on twice in succession. The monitoring circuit of the present invention is not added during the first turn-on. The monitoring circuit of the present invention is added during the second turn-on. The turn-on time of each turn-on is set to 7µs and the cycle is set to 20µs. Keep the off state during the whole process. Operating conditions: DC voltage (V = 500V), inductor current after the first pulse (I = 10A).

[0050] (1) Under the above conditions, if Figure 7 As shown, the Miller platform voltage online monitoring circuit proposed by the present invention obtains Exactly in When the Miller platform is reached, it no longer follows and the Miller platform voltage value is maintained for a long time, which verifies that the Miller platform voltage online monitoring circuit proposed in the present invention can realize fast and accurate monitoring of the Miller platform voltage.

[0051] (2) Record the original data without monitoring circuit and after adding the monitoring circuit proposed by the present invention Simulation waveform. Figure 8 As shown, after adding the proposed monitoring circuit, during the conduction process, The waveform is almost the same as the original waveform without the monitoring circuit, which shows that the turn-on speed of the device is almost not affected. At the same time, during the turn-off process, The waveform is also almost the same as the original waveform without the monitoring circuit, which shows that the turn-off speed of the device is almost not affected.

[0052] The above embodiments are preferred implementation schemes of the present invention. In addition, the present invention may also be implemented in other ways. Any obvious replacement without departing from the concept of the present technical solution is within the protection scope of the present invention.

[0053] In order to make it easier for ordinary technicians in the field to understand the improvements of the present invention over the prior art, some drawings and descriptions of the present invention have been simplified, and for the sake of clarity, some other elements are omitted in this application document. Ordinary technicians in the field should realize that these omitted elements may also constitute the content of the present invention.

Claims

1. A SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation, including a data processing circuit for performing analog-to-digital conversion and calculation of data, characterized in that: Also includes: Signal trigger circuit, trigger signal isolation circuit and sample-and-hold circuit; The SiC-MOSFET in the same bridge arm of the inverter in the conduction process is , the SiC-MOSFET in the off state is ; The input terminal of the signal trigger circuit is connected to The gate of the signal trigger circuit is connected, the output end of the signal trigger circuit is connected to the input end of the trigger signal isolation circuit, and the trigger signal isolation circuit, the sampling and holding circuit, and the data processing circuit are electrically connected in sequence; The signal triggers the circuit by detecting The driving voltage of Whether the driving voltage reaches the Miller platform moment, and then determine whether to trigger the Miller platform voltage acquisition signal; The trigger signal isolation circuit is used to isolate the signal trigger circuit from the sample and hold circuit; The sample-and-hold circuit is used to extract The driving voltage is kept constant after the Miller platform voltage acquisition signal is triggered. The constant driving voltage is The sampling and holding circuit is also used to transmit the extracted driving voltage to the data processing circuit.

2. The SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation according to claim 1, characterized in that: The signal trigger circuit includes a high-speed optical coupler 、PMOS tube and NMOS tube , The positive and negative electrodes of the photodiode are respectively The front-stage power supply terminal and the driving signal terminal of the driving chip are connected, and the The emitter and collector of the phototransistor are respectively connected to The drain, The drain connection of the The source and gate of The 0V power supply terminal of the driver chip, The gate connection of The source and gate of The low-level power supply terminal of the driver chip, The gate connection of the The drain is connected to the trigger signal isolation circuit.

3. The SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation according to claim 2, characterized in that: The trigger signal isolation circuit includes a high-speed optical coupler 、PMOS tube and NMOS tube , and The gates of The drain connection of the , The source of , The source connection of the and The drain of The positive terminal of the photodiode is connected to the The cathode of the photodiode is connected to The source connection of the The collector of the phototransistor is The rear low-level power supply terminal of the driver chip is connected, The emitter of the phototransistor is connected to the sample-and-hold circuit.

4. The SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation according to claim 3, characterized in that: The sample-and-hold circuit includes an NMOS tube ,capacitance , parasitic inductance ,capacitance and voltage follower AMP, the The gate and The emitter of the phototransistor is connected, and the pull-up line between the two has a The resistor connected to the high-level power supply terminal of the driver chip , The drain and The gate connection, and the The drain After The output terminal of the driver chip is connected to the The Source Sutra After The source connection of the In parallel with and The two ends of the line are composed of the non-inverting input of the AMP and The source terminal of the AMP is connected to the data processing circuit.

5. The SiC-MOSFET Miller platform voltage online monitoring circuit based on gate oscillation according to claim 4, characterized in that: The data processing circuit comprises an ADC converter and an FPGA chip. The input end of the ADC converter is connected to the output end of the AMP, and the output end of the ADC converter is connected to the FPGA chip.

6. A method for online monitoring of the Miller platform voltage of SiC-MOSFET based on gate oscillation, characterized in that: The online monitoring circuit of the Miller platform voltage of SiC-MOSFET based on gate oscillation as described in any one of claims 1 to 5 is used to perform online monitoring of the Miller platform voltage of SiC-MOSFET.

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