Main controller circuit based on domestic CPU

Abstract

The invention relates to the technical field of control circuits, and provides a domestic CPU-based main controller circuit, which comprises a domestic CPU, a bidirectional three-state buffer and a bus communication interface, the domestic CPU is internally provided with an EMI (Electro-Magnetic Interference) interface, is connected to the bidirectional three-state buffer through the EMI interface and is used for communicating with the bus communication interface; the two-way three-state buffer is connected between the EMI interface of the domestic CPU and the bus communication interface and is used for two-way data transmission; and the bus communication interface is connected to the EMI interface through a bidirectional three-state buffer and realizes data interaction with the domestic CPU. Through the scheme, the main controller circuit is simple and practical in overall architecture, high in overall reliability, low in power consumption and high in self-diagnosis capability, and does not need to be matched with excessive external equipment.

Description

[Technical field]

[0001] The present invention relates to the technical field of control circuits, and in particular to a main controller circuit based on a domestically produced CPU. [Background technology]

[0002] In industrial control equipment, the main controller module is needed to realize the control of the local circuit system, data processing, and partial field bus communication and process quantity input / output functions. The main controller module should have strong data processing capabilities, local circuit system bus communication capabilities, various field bus communication and input / output expansion support capabilities, high fault self-diagnosis capabilities, low power consumption and high reliability.

[0003] The design of traditional main controller modules is mostly based on imported CPUs, and has problems such as complex internal structure, high power consumption, and weak self-diagnosis capability. [Summary of the invention]

[0004] The embodiment of the present invention provides a main controller circuit based on a domestically produced CPU, aiming to solve the technical problems existing in the related art such as the complex internal structure of the main controller module, high power consumption, and weak self-diagnosis capability.

[0005] In a first aspect, an embodiment of the present invention provides a main controller circuit based on a domestically produced CPU, comprising:

[0006] Domestic CPU, bidirectional tri-state buffer and bus communication interface;

[0007] The domestically produced CPU has a built-in EMI interface, which is connected to the bidirectional tri-state buffer through the EMI interface and is used to communicate with the bus communication interface;

[0008] The bidirectional tri-state buffer is connected between the EMI interface of the domestic CPU and the bus communication interface, and is used for bidirectional data transmission;

[0009] The bus communication interface is connected to the EMI interface through a bidirectional three-state buffer to achieve data interaction with the domestic CPU.

[0010] In one embodiment, optionally, the domestically produced CPU further has a built-in universal input and output interface, and the circuit further comprises: a level conversion circuit and a non-isolated input and output interface;

[0011] A level conversion circuit, connected between the universal input / output interface of the domestic CPU and the non-isolated input / output interface, for performing level conversion;

[0012] The non-isolated input and output interface is connected to the level conversion circuit and is used to realize the non-isolated input and output of the switch signal of the domestic CPU.

[0013] In one embodiment, optionally, the domestically produced CPU further has a built-in universal input and output interface, and the circuit further comprises: an isolated solid-state relay and an isolated output interface;

[0014] The isolation solid-state relay is connected between the universal input and output interface of the domestic CPU and the isolation output interface, and is used to achieve isolation between the domestic CPU and the isolation output interface, and drive a large current load with a tiny signal;

[0015] The isolated output interface is connected to the isolated solid-state relay and is used to realize the isolated output of the switch signal of the domestic CPU.

[0016] In one embodiment, optionally, the domestically produced CPU also has a built-in universal input and output interface, and the circuit further includes: a photoelectric coupler and an isolation input interface;

[0017] The photoelectric coupler is connected between the universal input and output interface of the domestic CPU and the isolated input interface, and is used to achieve isolation between the domestic CPU and the isolated input interface;

[0018] The isolated input interface is connected to the photoelectric coupler and is used to realize the isolated input of the switch signal of the domestic CPU.

[0019] In one embodiment, optionally, the domestically produced CPU further has a built-in CAN controller, and the circuit further comprises: an isolated CAN (Controller Area Network) transceiver and an isolated DC power supply;

[0020] The isolated CAN transceiver is connected to the CAN controller and is used to achieve isolated communication;

[0021] The isolated DC power supply is connected to the isolated CAN transceiver and is used to supply power to the isolated CAN transceiver.

[0022] In one embodiment, optionally, the domestically produced CPU further has a built-in UART (Universal Asynchronous Receiver / Transmitte) controller, and the circuit further includes: a UART transceiver;

[0023] The UART transceiver is connected between the UART controller and the debugging interface, and is used to implement serial port debugging and program downloading.

[0024] In one embodiment, optionally, the domestically produced CPU further has a built-in GMAC (Gigabit Media Access Controller) controller, and the circuit further includes: an Ethernet transceiver and a network transformer;

[0025] The Ethernet transceiver is connected between the GMAC controller and the network transformer and is used for receiving and sending data;

[0026] The network transformer is connected between the Ethernet transceiver and the Ethernet communication interface, and is used to implement isolated Ethernet communication.

[0027] In one embodiment, optionally, the domestically produced CPU further has a built-in SD (Secure Digital) controller, and the circuit further includes: an SD card slot;

[0028] The SD card slot is connected to the SD controller and is used to implement serial port debugging and program downloading.

[0029] In one embodiment, optionally, the domestically produced CPU further has an I2C host interface built in, and the circuit further includes: an RTC (Real-Time Communications) and a battery;

[0030] The RTC is connected between the I2C host interface and the battery, and is used to implement a real-time clock;

[0031] The power supply is connected to the RTC and is used to supply power to the RTC.

[0032] In one embodiment, optionally, the domestic CPU also has a built-in ADC (Analog-to-Digital Converter) for monitoring the power status.

[0033] In one embodiment, optionally, the domestic CPU also has a built-in DDR2 controller for accessing an external DDR2 memory.

[0034] In one embodiment, optionally, the domestically produced CPU also has a built-in SPI (Serial Perripheral Interface) host interface for accessing an external NOR FLASH.

[0035] The main controller circuit based on the domestic CPU in the present invention comprises: a domestic CPU, a bidirectional tri-state buffer and a bus communication interface;

[0036] The domestically produced CPU has a built-in EMI interface, which is connected to the bidirectional tri-state buffer through the EMI interface and is used to communicate with the bus communication interface;

[0037] The bidirectional tri-state buffer is connected between the EMI interface of the domestic CPU and the bus communication interface, and is used for bidirectional data transmission;

[0038] The bus communication interface is connected to the EMI interface through a bidirectional three-state buffer to achieve data interaction with the domestic CPU.

[0039] In the present invention, a main controller circuit based on a domestic CPU includes a domestic CPU, a bidirectional three-state buffer and a bus communication interface; the domestic CPU has a built-in EMI interface, which is connected to the bidirectional three-state buffer through the EMI interface for communicating with the bus communication interface; the bidirectional three-state buffer is connected between the EMI interface of the domestic CPU and the bus communication interface for bidirectional data transmission; the bus communication interface is connected to the EMI interface through a bidirectional three-state buffer to achieve data interaction with the domestic CPU. In this way, the overall architecture of the main controller circuit is concise and practical, with high overall reliability, does not require the cooperation of too many external devices, has low power consumption and strong self-diagnosis capability. At the same time, through the application of the flexible static memory access control unit inside the domestic CPU, a variety of external functional module bus access functions can be realized with low complexity.

Brief Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A structural schematic diagram of a main controller circuit based on a domestic CPU according to an embodiment of the present invention is shown.

[0042] FIG. 2A to FIG. 2C A schematic diagram of the structure of a circuit for implementing a partial EMI interface address signal according to an embodiment of the present invention is shown.

[0043] Figure 3 A schematic diagram of the structure of a circuit for implementing a data signal portion of an EMI interface according to an embodiment of the present invention is shown.

[0044] Figure 4 A specific structural schematic diagram of a power indicator light control logic circuit according to an embodiment of the present invention is shown.

[0045] Figure 5 A power-on self-test flow chart of a main controller circuit based on a domestic CPU according to an embodiment of the present invention is shown.

[0046] Figure 6 A flow chart of monitoring during system operation based on a main controller circuit of a domestic CPU according to an embodiment of the present invention is shown.

[0047] Figure 7 A kernel startup flow chart of a main controller circuit based on a domestic CPU according to an embodiment of the present invention is shown. [Specific implementation method]

[0048] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0051] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0052] See also Figure 1 , Figure 1 The schematic block diagram of a main controller circuit based on a domestic CPU according to an embodiment of the present invention is shown. The main controller circuit based on a domestic CPU is used to solve the technical problems existing in the related art such as the complex internal structure of the main controller module, high power consumption, and weak self-diagnosis capability.

[0053] like Figure 1 As shown, a main controller circuit based on a domestic CPU according to an embodiment of the present invention includes:

[0054] Domestic CPU 11, bidirectional tri-state buffer 12 and bus communication interface 13;

[0055] The domestically produced CPU 11 has a built-in EMI interface, which is connected to the bidirectional tri-state buffer through the EMI interface and is used to communicate with the bus communication interface;

[0056] The bidirectional tri-state buffer 12 is connected between the EMI interface of the domestic CPU 11 and the bus communication interface 13, and is used for bidirectional data transmission;

[0057] The bus communication interface 13 is connected to the EMI interface through a bidirectional tri-state buffer 12 to achieve data interaction with the domestic CPU.

[0058] Among them, the external static storage access implementation and module self-diagnosis function implementation of the EMI interface are described, and the implementation of other functions has been described in the basic principles and is implemented using simplified, mature and reliable circuits.

[0059] Among them, the domestic CPU can use the GSC3290 chip of Shenzhou Loongson, and the EMI-related interfaces it supports are shown in Table 1.

[0060] Table 1

[0061]

[0062]

[0063] In the present invention, in view of the requirement of byte-based reading / writing of the backplane bus in traditional industrial control applications, the 0th to 7th bits of the EMI data in the EMI interface are used to realize the requirement of byte-based reading and writing; the address line is set to 20 bits, and a 1MB address space is used to meet the data interaction capacity requirement in industrial control applications. At the same time, the address signal can be used for address decoding by other functional boards on the backplane bus; the emi_oen and emi_wen signals are used to realize the control of the data transmission direction of the backplane bus by the main controller.

[0064] In this embodiment, the bus communication between the CPU and the local circuit system is realized by using a domestic CPU and a bidirectional tri-state buffer, and the communication is master-slave. The bidirectional tri-state buffer is a tri-state bus transceiver with bidirectional level conversion, which can realize bidirectional level conversion, bus buffering, and protection of internal circuits. Among them, the EMI interface address signal part of the present invention is implemented as shown in the attached circuit. Figure 2A-2C As shown, in the address signal partial implementation circuit, the address signal transmission direction is limited to being sent from the inside to the outside, the SMEMR / signal corresponds to the emi_oen signal, and the SMEMW / signal corresponds to the emi_wen signal. Through the unidirectional output of these two signals, the read / write enable on the backplane bus is controlled to realize the master-slave bus communication direction control of the local circuit system.

[0065] The transmission of data signals (SD0-SD7) is also achieved by cooperating with a bidirectional three-state buffer. The circuit is shown in the attached figure. Figure 3As shown. The direction of the bus transceiver is controlled by the SMEMR / signal. The I / O pin of the CPU chip corresponding to the SMEMR / signal is set to a push-pull output form. When the SMEMR / signal output is high, the data transmission direction of the bus transceiver is controlled to be external->internal. When the SMEMR / signal output is low, the data transmission direction of the bus transceiver is controlled to be internal->external. Since the SMEMR / signal and the SMEMRW / signal can be set to enable in a non-overlapping timing within the program logic, it is reasonable to use only the SMEMR / signal for direction control. As shown above, the SMEMR / signal and the SMEMRW / signal are output to the bus at the same time to control the external device to receive / send data.

[0066] In summary, the address signal, data signal, data receiving / transmitting direction control signal and the CPU program control logic can meet the application requirements of various asynchronous master-slave bus communications.

[0067] In one embodiment, optionally, the domestically produced CPU further has a built-in universal input and output interface, and the circuit further comprises: a level conversion circuit and a non-isolated input and output interface;

[0068] A level conversion circuit 14, connected between the universal input and output interface of the domestic CPU and the non-isolated input and output interface, for performing level conversion;

[0069] The non-isolated input and output interface 15 is connected to the level conversion circuit and is used to realize the non-isolated input and output of the switch signal of the domestic CPU.

[0070] In this embodiment, the non-isolated input / output of the switch signal is realized through the level conversion circuit and the non-isolated input / output interface GPIO in the CPU. In this way, the overall architecture of the main controller circuit is concise and practical, the overall reliability is high, too much external equipment is not required, the power consumption is low, and the self-diagnosis capability is strong.

[0071] In one embodiment, optionally, the domestically produced CPU also has a built-in universal input and output interface, and the circuit further includes: an isolated solid-state relay 16 and an isolated output interface 17;

[0072] The isolation solid-state relay 16 is connected between the universal input and output interface of the domestic CPU and the isolation output interface, and is used to achieve isolation between the domestic CPU and the isolation output interface, and drive a large current load with a tiny signal;

[0073] The isolated output interface 17 is connected to the isolated solid-state relay and is used to realize the isolated output of the switch signal of the domestic CPU.

[0074] In this embodiment, the isolated output of the switch signal is realized through the solid-state relay and the GPIO port in the CPU. In this way, the overall architecture of the main controller circuit is simple and practical, the overall reliability is high, too much external equipment is not required, the power consumption is low, and the self-diagnosis capability is strong.

[0075] In one embodiment, optionally, the domestically produced CPU also has a built-in universal input and output interface, and the circuit further includes: a photoelectric coupler 18 and an isolation input interface 19;

[0076] The photoelectric coupler 18 is connected between the universal input and output interface of the domestic CPU and the isolated input interface, and is used to achieve isolation between the domestic CPU and the isolated input interface;

[0077] The isolated input interface 19 is connected to the photoelectric coupler and is used to realize the isolated input of the switch signal of the domestic CPU.

[0078] In this embodiment, the isolated input of the switch signal is realized through the photoelectric coupler and the GPIO port in the CPU. In this way, the overall architecture of the main controller circuit is simple and practical, the overall reliability is high, too much external equipment is not required, the power consumption is low and the self-diagnosis capability is strong.

[0079] In one embodiment, optionally, the domestically produced CPU further has a built-in CAN controller, and the circuit further comprises: an isolated CAN transceiver 20 and an isolated DC power supply 21;

[0080] The isolated CAN transceiver 20 is connected to the CAN controller and is used to achieve isolated communication;

[0081] The isolated DC power supply 21 is connected to the isolated CAN transceiver and is used to supply power to the isolated CAN transceiver.

[0082] In this embodiment, isolated CAN communication is achieved by cooperating with the CAN controller in the CPU through the isolated CAN transceiver. In this way, the overall architecture of the main controller circuit is simple and practical, the overall reliability is high, too much external equipment is not required, the power consumption is low, and the self-diagnosis capability is strong.

[0083] In one embodiment, optionally, the domestically produced CPU further has a built-in UART controller, and the circuit further comprises: a UART transceiver 22;

[0084] The UART transceiver 22 is connected between the UART controller and the debugging interface, and is used to implement serial port debugging and program downloading.

[0085] In this embodiment, serial port debugging and program downloading are realized through the UART transceiver and the UART controller in the CPU. In this way, the overall architecture of the main controller circuit is concise and practical, the overall reliability is high, too much external equipment is not required, the power consumption is low and the self-diagnosis capability is strong.

[0086] In one embodiment, optionally, the domestically produced CPU further has a built-in GMAC controller, and the circuit further includes: an Ethernet transceiver 23 and a network transformer 24;

[0087] The Ethernet transceiver 23 is connected between the GMAC controller and the network transformer and is used for receiving and sending data;

[0088] The network transformer 24 is connected between the Ethernet transceiver and the Ethernet communication interface to implement isolated Ethernet communication.

[0089] In this embodiment, isolated Ethernet communication is achieved through an Ethernet transceiver, a network transformer and a GMAC controller in the CPU. In this way, the overall architecture of the main controller circuit is concise and practical, the overall reliability is high, it does not require the cooperation of too many external devices, the power consumption is low and the self-diagnosis capability is strong.

[0090] In one embodiment, optionally, the domestically produced CPU further has a built-in SD controller, and the circuit further comprises: an SD card slot 25;

[0091] The SD card slot 25 is connected to the SD controller and is used to implement serial port debugging and program downloading.

[0092] In this embodiment, serial port debugging and program downloading are implemented through a standard SD card slot and an SD / SDIO controller in the CPU.

[0093] In one embodiment, optionally, the domestically produced CPU also has a built-in I2C host interface, and the circuit further includes: RTC 26 and a battery 27;

[0094] The RTC26 is connected between the I2C host interface and the battery, and is used to implement a real-time clock;

[0095] The power supply 27 is connected to the RTC and is used to supply power to the RTC.

[0096] In this embodiment, the real time clock is implemented by a battery, an RTC chip, and an I2C host interface in the CPU.

[0097] In one embodiment, optionally, the domestic CPU also has a built-in ADC for monitoring power status.

[0098] In this embodiment, the power supply status monitoring is implemented by monitoring the power supply voltage through the ADC in the CPU.

[0099] In one embodiment, optionally, the domestic CPU also has a built-in DDR2 controller for accessing an external DDR2 memory.

[0100] In this embodiment, the CPU accesses the external DDR2 memory through the DDR2 controller in the CPU.

[0101] In one embodiment, optionally, the domestic CPU also has a built-in SPI host interface for accessing an external NOR FLASH.

[0102] In this embodiment, the CPU accesses the external NOR FLASH through the SPI host interface in the CPU.

[0103] In one embodiment, the domestically produced CPU may optionally be connected to a fault LED for self-diagnosis of faults. The indication function after fault diagnosis is implemented in the form of an indicator light, which provides three indication signals for a power indicator light, a normal operation indicator light, and a fault indicator light. The following is the fault diagnosis implementation logic corresponding to each indicator light.

[0104] Power indicator

[0105] The power indicator light is controlled by the POWER GOOD signal of the 3.3V, 1.8V and 1.2V power converters and the 5V power status signal through a diode to achieve line and logic. The 5V status signal is sampled by the ADC module in the CPU in real time. When the 5V power supply deviates from the nominal value by ±10%, the control LED is turned off. The driving current is a 3.3V power supply connected in series with a 300 ohm current limiting resistor to achieve a driving capacity of no less than 10mA. The control logic circuit is as follows: Figure 4 When all status signals output high level, the control LED is on, and when a status signal outputs low level, the control LED is off; among them, P1V2_PGOOD is the status signal output by the power chip, POWER_MONITOR is the GPIO signal of the CPU, P2V5_PGOOD is the status signal output by the power chip, P1V5_PGOOD is the status signal output by the power chip, P3V3_PGOOD is the status signal output by the power chip, and P1V8_PGOOD is the status signal output by the power chip.

[0106] Normal operation indicator

[0107] The normal operation indicator light is driven by the CPU's GPIO to realize LED control. After the CPU runs into the kernel, the CPU's GPIO port outputs a high level and the LED will be lit. When the CPU does not enter the kernel, the CPU's GPIO port outputs a low level and the LED is off.

[0108] Fault indicator light

[0109] The fault indicator light is driven by the CPU's GPIO to realize LED control through the subsequent field effect transistor. After the CPU runs to the kernel, it will monitor the system's operating status in real time. If it detects that the memory, NOR-FLASH, CAN bus, AT96 bus and other external devices are working abnormally, the CPU's GPIO outputs a low level and the LED will be lit. When the system is running normally, the CPU's GPIO outputs a high level and the LED will be off.

[0110] The system abnormality detection process includes the system power-on self-test process and the system operation monitoring process.

[0111] System power-on self-test process

[0112] During the power-on self-test, uboot detects the CPU, memory, Ethernet controller and kernel decompression status. If abnormal, the fault indicator light is turned on. The process is as follows: Figure 5 shown.

[0113] Perform CPU fault detection. When the system starts up and executes BOOTLOADER, BOOTLOADER will initialize the CPU. If the CPU is abnormal, BOOTLOADER will drive LED_GPIO to light up the fault indicator.

[0114] Perform memory fault detection: When the system starts and executes BOOTLOADER, BOOTLOADER will initialize the memory. During the memory initialization and memory test process (write a physical memory address and then read it to see if it is consistent, if it is inconsistent, it is abnormal), if an abnormality occurs, BOOTLOADER will drive LED_GPIO to light up the fault indicator;

[0115] Perform LASH fault detection: When the system boots up and executes BOOTLOADER, BOOTLOADER will read the FLASH ID. If the FLASH ID is not supported by uboot, BOOTLOADER will drive LED_GPIO to light up the fault indicator.

[0116] Perform Ethernet controller fault detection: When BOOTLOADER initializes GMAC, it will perform an inner loop test. If the inner loop test fails, BOOTLOADER will drive LED_GPIO to light up the fault indicator.

[0117] Debug serial port controller fault detection: When BOOTLOADER initializes the serial port, it sets the register and then reads the register value to see if they are consistent. If they are inconsistent, it is abnormal and BOOTLOADER will drive LED_GPIO to light up the fault indicator.

[0118] Perform kernel fault detection: When BOOTLOADER decompresses the kernel, if the decompression fails, it is an exception, and BOOTLOADER will drive LED_GPIO to light up the fault indicator.

[0119] After the system passes various fault detections, the system starts normally. After the system starts normally, the system operation detection process is carried out. The specific process is as follows Figure 6 As shown, including:

[0120] The system monitoring software starts automatically and the normal operation indicator light turns on.

[0121] The system monitoring software obtains the system key registers, CAN bus status, AT96 bus status, and 5V voltage status through the driver and records them in the log; sets the relevant information to the shared memory, and lights the fault indicator light if there is an abnormality.

[0122] In particular, set the abnormal fault indicator to light up when the watchdog times out or panics. The process is as follows: Figure 7 shown.

[0123] Perform CAN bus fault detection: After the monitoring software is running, it will periodically detect the status register of the CAN controller. If the ERROR state occurs, the software will drive LED_GPIO to light up the fault indicator;

[0124] Perform AT96 fault detection: After the user software is running, it will periodically read the data of the external storage device through the EMI bus. If there is no data reply when starting the read operation, it will be judged as an error. The user software will notify the monitoring software of the status to drive LED_GPIO to light up the fault indicator;

[0125] Perform 5V input voltage fault detection: The monitoring software will periodically monitor the voltage of the 5V input power supply through the ADC controller. When the voltage is in the range of 4.5V to 5.5V, it will display no fault and light up the power indicator light. If it deviates from this range, it will be judged as an error and the software will drive LED_GPIO to light up the fault indicator light and turn off the power indicator light.

[0126] Key information recording: The periodic detection program reads the system key registers and records them.

[0127] It should be noted that the circuit functions of the main controller circuit based on the domestic CPU provided in this embodiment are mainly realized through the circuit connection relationship between the various circuit modules, and do not rely on the program module in a certain circuit module. In addition, the various circuit modules in the main controller circuit based on the domestic CPU can be realized by analog circuits or digital circuits, and for the circuit modules that can be implanted with program modules, the realization of their module functions can be realized by the program modules provided by the prior art.

[0128] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0129] It should be understood that, although the terms first, second, etc. may be used to describe the setting units in the embodiments of the present invention, these setting units should not be limited to these terms. These terms are only used to distinguish the setting units from each other. For example, without departing from the scope of the embodiments of the present invention, the first setting unit may also be referred to as the second setting unit, and similarly, the second setting unit may also be referred to as the first setting unit.

[0130] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0131] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0132] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0133] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A main controller circuit based on a domestically produced CPU, characterized in that: include: Domestic CPU, bidirectional tri-state buffer and bus communication interface; The domestically produced CPU has a built-in EMI interface, which is connected to the bidirectional tri-state buffer through the EMI interface and is used to communicate with the bus communication interface; The bidirectional tri-state buffer is connected between the EMI interface of the domestic CPU and the bus communication interface, and is used for bidirectional data transmission; The bus communication interface is connected to the EMI interface through a bidirectional three-state buffer to achieve data interaction with the domestic CPU.

2. The main controller circuit based on a domestically produced CPU according to claim 1, characterized in that: The domestically produced CPU also has a built-in universal input and output interface, and the circuit also includes: a level conversion circuit and a non-isolated input and output interface; A level conversion circuit, connected between the universal input / output interface of the domestic CPU and the non-isolated input / output interface, for performing level conversion; The non-isolated input and output interface is connected to the level conversion circuit and is used to realize the non-isolated input and output of the switch signal of the domestic CPU.

3. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in universal input and output interface, and the circuit also includes: an isolated solid-state relay and an isolated output interface; The isolation solid-state relay is connected between the universal input and output interface of the domestic CPU and the isolation output interface, and is used to achieve isolation between the domestic CPU and the isolation output interface, and drive a large current load with a tiny signal; The isolated output interface is connected to the isolated solid-state relay and is used to realize the isolated output of the switch signal of the domestic CPU.

4. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in universal input and output interface, and the circuit also includes: a photoelectric coupler and an isolation input interface; The photoelectric coupler is connected between the universal input and output interface of the domestic CPU and the isolated input interface, and is used to achieve isolation between the domestic CPU and the isolated input interface; The isolated input interface is connected to the photoelectric coupler and is used to realize the isolated input of the switch signal of the domestic CPU.

5. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in CAN controller, and the circuit also includes: an isolated CAN transceiver and an isolated DC power supply; The isolated CAN transceiver is connected to the CAN controller and is used to achieve isolated communication; The isolated DC power supply is connected to the isolated CAN transceiver and is used to supply power to the isolated CAN transceiver.

6. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in UART controller, and the circuit also includes: a UART transceiver; The UART transceiver is connected between the UART controller and the debugging interface, and is used to implement serial port debugging and program downloading.

7. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in GMAC controller, and the circuit also includes: an Ethernet transceiver and a network transformer; The Ethernet transceiver is connected between the GMAC controller and the network transformer and is used for receiving and sending data; The network transformer is connected between the Ethernet transceiver and the Ethernet communication interface, and is used to implement isolated Ethernet communication.

8. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in SD controller, and the circuit also includes: an SD card slot; The SD card slot is connected to the SD controller and is used to implement serial port debugging and program downloading.

9. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in I2C host interface, and the circuit also includes: an RTC and a battery; The RTC is connected between the I2C host interface and the battery, and is used to implement a real-time clock; The power supply is connected to the RTC and is used to supply power to the RTC.

10. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in ADC for monitoring power status.

11. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in DDR2 controller for accessing an external DDR2 memory.

12. The main controller circuit based on domestic CPU according to claim 1 is characterized in that: The domestically produced CPU also has a built-in SPI host interface for accessing an external NOR FLASH.

Images