A temperature compensation circuit and electronic device

Abstract

This application provides a temperature compensation circuit and an electronic device. The temperature compensation circuit includes: a first current module configured to output a first current signal having a positive temperature coefficient characteristic; a second current module configured to output a second current signal having a negative temperature coefficient characteristic; a reference voltage module configured to output a reference voltage signal; and a compensation module connected to the first current module, the second current module, and the reference voltage module. The compensation module is configured to perform temperature detection, injecting the first current signal into the reference voltage signal when the temperature is within a first temperature range, and injecting the second current signal into the reference voltage signal when the temperature is within a second temperature range. By performing segmented temperature compensation on the reference signal, a lower temperature drift clock output can be achieved, providing a higher precision output clock and meeting the high-precision clock requirements of the MCU chip.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, specifically to a temperature compensation circuit and an electronic device. Background Technology

[0002] An on-chip clock is a clock signal generated inside an integrated circuit chip. It is used to drive the operation and synchronization of various parts on the chip. The frequency and stability of the on-chip clock are crucial to the chip's performance.

[0003] Microcontroller units (MCUs) require a stable on-chip clock signal to ensure the normal operation of internal digital circuits and other circuits. For certain processing tasks, high-precision on-chip clock support is necessary. For example, in motor control applications, automotive-grade MCUs require accurate sampling by the ADC (Analog-to-Digital Converter) module, increasing the demands on the ADC sampling clock. Similarly, automotive-grade MCUs in low-cost solutions also require a high-precision on-chip clock to support LIN communication. Existing high-precision on-chip RC clocks often use zero-temperature-drift capacitors and two types of resistors with different temperature characteristics (positive and negative temperature drift) for temperature compensation. This reduces temperature drift and improves the accuracy of the on-chip clock signal. However, existing temperature compensation methods cannot meet the requirements of high-precision on-chip clocks for MCUs. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a temperature compensation circuit and electronic device that can achieve a lower temperature drift clock output, provide a higher precision output clock, and meet the high-precision clock requirements of MCU chips.

[0005] One technical solution adopted in this application is to provide a temperature compensation circuit, which includes: a first current module configured to output a first current signal having a positive temperature coefficient characteristic; a second current module configured to output a second current signal having a negative temperature coefficient characteristic; a reference voltage module configured to output a reference voltage signal; and a compensation module connected to the first current module, the second current module, and the reference voltage module. The compensation module is configured to perform temperature detection, injecting the first current signal into the reference voltage signal when the temperature is within a first temperature range, and injecting the second current signal into the reference voltage signal when the temperature is within a second temperature range.

[0006] In one embodiment, the compensation module includes: a first mirror module connected to a first current module, configured to output a third current signal mirrored with the first current signal; a first switch, a first terminal of which is connected to the output terminal of the first mirror module, and a second terminal of which is connected to a reference voltage module; a second mirror module connected to a second current module, configured to output a fourth current signal mirrored with the second current signal; a second switch, a first terminal of which is connected to the output terminal of the second mirror module, and a second terminal of which is connected to the reference voltage module; and a first temperature detection module connected to the control terminals of the first and second switches, configured to perform temperature detection, and when the temperature is within a first temperature range, control the first switch to turn on and control the second switch to turn off to inject the first current signal into the reference voltage signal, and when the temperature is within a second temperature range, control the first switch to turn off and control the second switch to turn on to inject the second current signal into the reference voltage signal.

[0007] In one embodiment, the first temperature detection module includes: a third mirror module connected to the first current module, the third mirror module being configured to output a fifth current signal mirrored with the first current signal; a first resistor, the first end of the first resistor being connected to the output terminal of the third mirror module, and the second end of the first resistor being grounded; a first operational amplifier, the first input terminal of the first operational amplifier being connected to the first end of the first resistor, the second input terminal of the first operational amplifier being configured to input a first reference voltage signal, and the output terminal of the first operational amplifier being connected to the control terminal of a first switch; and an inverter, the input terminal of the inverter being connected to the output terminal of the first operational amplifier, and the output terminal of the inverter being connected to the control terminal of a second switch.

[0008] In one embodiment, the temperature compensation circuit further includes a third current module configured to output a sixth current signal having a zero temperature coefficient characteristic; wherein the compensation module is further configured to inject the second current signal into a reference voltage signal when the temperature is within a second temperature range, and to inject the sixth current signal into the reference voltage signal when the temperature is within a third temperature range, wherein the third temperature range is located between the first temperature range and the second temperature range.

[0009] In one embodiment, the compensation module includes: a first mirror module connected to a first current module, configured to output a third current signal mirrored with the first current signal; a first switch, a first terminal of which is connected to the output terminal of the first mirror module, and a second terminal of which is connected to a reference voltage module; a second mirror module connected to a second current module, configured to output a fourth current signal mirrored with the second current signal; a second switch, a first terminal of which is connected to the output terminal of the second mirror module, and a second terminal of which is connected to the reference voltage module; a fourth mirror module connected to the third current module, configured to output a seventh current signal mirrored with the sixth current signal; and a third switch, a first terminal of which is connected to the fourth mirror module. The output terminal of the first switch is connected to the second terminal of the third switch, which is connected to the reference voltage module. The second temperature detection module is connected to the control terminals of the first switch, the second switch, and the third switch. The second temperature detection module is configured to perform temperature detection. When the temperature is within the first temperature range, it controls the first switch to be turned on, the second switch to be turned off, and the third switch to be turned off, so as to inject the first current signal into the reference voltage signal. When the temperature is within the second temperature range, it controls the first switch to be turned off, the second switch to be turned on, and the third switch to be turned off, so as to inject the second current signal into the reference voltage signal. When the temperature is within the third temperature range, it controls the first switch to be turned off, the second switch to be turned off, and the third switch to be turned on, so as to inject the seventh current signal into the reference voltage signal.

[0010] In one embodiment, the second temperature detection module includes: a third mirror module connected to a first current module, the third mirror module being configured to output a fifth current signal equal to the first current signal; a first resistor, the first end of which is connected to the output terminal of the third mirror module, and the second end of which is grounded; a second operational amplifier, the first input terminal of which is connected to the first end of the first resistor, and the second input terminal of which is configured to input a first reference voltage signal; a third operational amplifier, the first input terminal of which is connected to the first end of the first resistor, and the second input terminal of which is configured to input a second reference voltage signal; wherein the voltage value of the second reference voltage signal is different from the voltage value of the first reference voltage signal; and a logic processing module, the input terminals of which are respectively connected to the output terminals of the second and third operational amplifiers, and the output terminals of which are respectively connected to the control terminals of the first, second, and third switches.

[0011] In one embodiment, the logic processing module includes: an XNOR gate, the first input of which is connected to the output of a second operational amplifier, the second input of which is connected to the output of a third operational amplifier, and the output of which is connected to the control terminal of a third switch; an OR gate, the first input of which is connected to the output of a second operational amplifier, the second input of which is connected to the output of a third operational amplifier, and the output of which is connected to the control terminal of a first switch; and a NAND gate, the first input of which is connected to the output of a second operational amplifier, the second input of which is connected to the output of a third operational amplifier, and the output of which is connected to the control terminal of a second switch.

[0012] In one embodiment, the first current module includes: a first MOSFET, the first terminal of which is configured to input a power supply voltage signal, and the control terminal of the first MOSFET is connected to the control terminal of a first mirror module and the control terminal of a third mirror module; a second resistor, the first terminal of which is connected to the second terminal of the first MOSFET; a third resistor, the first terminal of which is connected to the second terminal of the second resistor; a fourth resistor, the first terminal of which is connected to the second terminal of the second resistor; a fourth operational amplifier, the first input terminal of which is connected to the second terminal of the fourth resistor, the second input terminal of which is connected to the second terminal of the third resistor, and the output terminal of which is connected to the control terminal of the first MOSFET; a fifth resistor, the first terminal of which is connected to the first input terminal of the fourth operational amplifier; a first transistor, the first terminal of which is connected to the second input terminal of the fourth operational amplifier, and the second terminal of which and the control terminal are grounded; and a second transistor, the first terminal of which is connected to the second terminal of the fifth resistor, and the second terminal of which and the control terminal are grounded.

[0013] In one embodiment, the second current module includes: a second MOSFET, the first terminal of which is configured to input a power supply voltage signal, and the control terminal of which is connected to the control terminal of the second mirror module; a third MOSFET, the first terminal of which is connected to the second terminal of the second MOSFET; a sixth resistor, the first terminal of which is connected to the second terminal of the third MOSFET, and the second terminal of which is grounded; a current source, the first terminal of which is connected to the first terminal of the second MOSFET; a fifth operational amplifier, the first input terminal of which is connected to the second terminal of the current source, the second input terminal of which is connected to the first terminal of the sixth resistor, and the output terminal of which is connected to the control terminal of the third MOSFET; and a third transistor, the first terminal of which is connected to the first input terminal of the fifth operational amplifier, and the second terminal and the control terminal of which are grounded.

[0014] In one embodiment, the reference voltage module includes: a seventh resistor, the first end of which is configured to input a power supply voltage signal; and an eighth resistor, the first end of which is connected to the second end of the seventh resistor, and the second end of which is grounded; wherein the voltage divider node of the seventh and eighth resistors is configured to output a reference voltage signal.

[0015] In one embodiment, the third current module includes: a fourth MOSFET, the first terminal of which is configured to input a power supply voltage signal, and the control terminal of which is connected to the control terminal of the fourth mirror module; a fifth MOSFET, the first terminal of which is connected to the second terminal of the fourth MOSFET; a ninth resistor, the first terminal of which is connected to the second terminal of the fifth MOSFET, and the second terminal of which is grounded; a sixth operational amplifier, the first input terminal of which is grounded, the second input terminal of which is connected to the first terminal of the ninth resistor, and the output terminal of which is connected to the control terminal of the fifth MOSFET; and a voltage source, the first terminal of which is connected to the first input terminal of the sixth operational amplifier, and the second terminal of which is grounded.

[0016] This application also provides an electronic device that includes the temperature compensation circuit described above.

[0017] This application provides a temperature compensation circuit, comprising: a first current module configured to output a first current signal having a positive temperature coefficient characteristic; a second current module configured to output a second current signal having a negative temperature coefficient characteristic; a reference voltage module configured to output a reference voltage signal; and a compensation module connected to the first current module, the second current module, and the reference voltage module. The compensation module is configured to perform temperature detection, injecting the first current signal into the reference voltage signal when the temperature is within a first temperature range, and injecting the second current signal into the reference voltage signal when the temperature is within a second temperature range. By performing segmented temperature compensation on the reference signal, a lower temperature drift clock output can be achieved, providing a higher precision output clock and meeting the high-precision clock requirements of the MCU chip. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] in:

[0020] Figure 1 This is a schematic diagram of the structure of the first embodiment of the temperature compensation circuit provided in this application;

[0021] Figure 2 This is a schematic diagram of the structure of the second embodiment of the temperature compensation circuit provided in this application;

[0022] Figure 3 This is a schematic diagram of the structure of the third embodiment of the temperature compensation circuit provided in this application;

[0023] Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the temperature compensation circuit provided in this application;

[0024] Figure 5 This is a schematic diagram of the fifth embodiment of the temperature compensation circuit provided in this application;

[0025] Figure 6 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0027] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0029] See Figure 1 , Figure 1This is a schematic diagram of the structure of the first embodiment of the temperature compensation circuit provided in this application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30, and a compensation module 40.

[0030] The first current module 10 is configured to output a first current signal S1, which has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, which has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20, and the reference voltage module 30, and is configured to perform temperature detection. When the temperature is within a first temperature range, the first current signal S1 is injected into the reference voltage signal VREF; when the temperature is within a second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0031] Specifically, existing on-chip high-precision RC clocks mostly use zero-temperature-drift capacitors and two types of resistors with different temperature characteristics (positive and negative temperature drift) for temperature compensation. A zero-temperature-drift capacitor is one whose capacitance remains relatively stable with temperature changes. A positive temperature-drift resistor is one whose resistance increases with temperature, while a negative temperature-drift resistor is one whose resistance decreases with temperature increases. When the temperature rises, the resistance of the positive temperature-drift resistor increases, while the resistance of the negative temperature-drift resistor decreases. These changes in resistance values ​​can offset the performance changes of other components caused by temperature increases, ensuring that the RC time constant remains consistent across different temperatures. This temperature compensation method can easily achieve an output clock with an accuracy of around 1%, but it cannot meet the requirements for higher precision clock outputs.

[0032] In complex clock circuits or applications requiring high-precision clocks, a reference signal is often needed to calibrate or synchronize the clock signal. For example, in a high-precision on-chip RC clock with an FLL (Frequency Locked Loop) structure, the temperature drift of the output clock is determined by R, which is composed of two resistors, and C, and the temperature drift of capacitor C is usually negligible. It can be approximated that the output frequency is determined only by R, and its clock output frequency fout can be expressed by the following formula:

[0033]

[0034] Here, x is a fixed ratio obtained by voltage division of resistor R, which can be understood as the ratio of the resistance values ​​of the two resistors. R is formed by combining two resistors with different temperature drifts, thereby achieving a certain degree of temperature compensation. The voltage divider node of the two resistors outputs a reference signal, which is crucial for ensuring a stable and accurate clock signal output. As a frequency reference, the FLL system's adjustment mechanism keeps the local oscillator frequency synchronized with the reference signal or forms a certain harmonic relationship. Therefore, the temperature drift of the reference signal will affect the temperature drift of the clock output frequency. By performing temperature compensation on the reference signal, the impact of temperature on the clock signal can be further reduced, improving the accuracy of the output clock.

[0035] In one application scenario, if the resistor R exhibits a negative temperature characteristic at low temperatures and a positive temperature characteristic at high temperatures, then according to the formula for the clock output frequency, if the temperature characteristic of x is not changed, the clock output frequency will have a positive temperature characteristic at low temperatures and a negative temperature characteristic at high temperatures. That is, after first-order RC compensation, the clock frequency temperature characteristic parabola will open downwards. If R has a positive temperature characteristic, then 1 / RC has a negative temperature characteristic. In this case, it is necessary to set... For a signal to have a positive temperature characteristic (i.e., x has a negative temperature characteristic), it needs to cancel out the negative temperature characteristic of 1 / RC. Only a compensation current with a negative temperature characteristic needs to be injected into the reference signal VREF. Similarly, if R has a negative temperature characteristic, a compensation current with a positive temperature characteristic needs to be injected into the reference signal VREF. The compensation module 40 performs temperature detection. When the temperature is within the first temperature range (corresponding to the low-temperature stage), a first current signal S1 is injected into the reference voltage signal VREF. When the temperature is within the second temperature range (corresponding to the high-temperature stage), a second current signal S2 is injected into the reference voltage signal VREF. The first temperature range is smaller than the second temperature range.

[0036] In another application scenario, if the resistor R exhibits a positive temperature characteristic at low temperatures and a negative temperature characteristic at high temperatures, then the clock frequency temperature characteristic parabola opens upwards. This means that a compensation current with a positive temperature characteristic needs to be injected into the reference signal VREF at low temperatures, and a compensation current with a negative temperature characteristic needs to be injected into the reference signal VREF at high temperatures. The compensation module 40 performs temperature detection. When the temperature is within a first temperature range (corresponding to the high-temperature stage), a first current signal S1 is injected into the reference voltage signal VREF. When the temperature is within a second temperature range (corresponding to the low-temperature stage), a second current signal S2 is injected into the reference voltage signal VREF. The first temperature range is greater than the second temperature range.

[0037] This application provides a temperature compensation circuit 100, which is based on a compensation module 40. In different temperature ranges, the circuit injects a first current signal S1 with a positive temperature coefficient characteristic from the first current module 10 and a second current signal S2 with a negative temperature coefficient characteristic from the second current module 20 into the reference voltage signal VREF. This utilizes the two different temperature coefficient characteristics to cancel each other out, thereby performing segmented temperature compensation on the reference signal VREF, achieving a lower temperature drift clock output, providing a higher precision output clock, and meeting the high precision clock requirements of the MCU chip.

[0038] See Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the temperature compensation circuit provided in this application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30, and a compensation module 40.

[0039] The first current module 10 is configured to output a first current signal S1, which has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, which has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20, and the reference voltage module 30, and is configured to perform temperature detection. When the temperature is within a first temperature range, the first current signal S1 is injected into the reference voltage signal VREF; when the temperature is within a second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0040] Optionally, the compensation module 40 includes a first mirror module 41, a first switch SW1, a second mirror module 42, a second switch SW2, and a first temperature detection module 43. The first mirror module 41 is connected to the first current module 10. The first mirror module 41 is configured to output a third current signal S3 that mirrors the first current signal S1. The first terminal of the first switch SW1 is connected to the output terminal of the first mirror module 41, and the second terminal of the first switch SW1 is connected to the reference voltage module 30. The second mirror module 42 is connected to the second current module 20. The second mirror module 42 is configured to output a fourth current signal S4 that mirrors the second current signal S2. The first terminal of the second switch SW2 is connected to the output terminal of the second mirror module 42, and the second terminal of the second switch SW2 is connected to the reference voltage module 30. The first temperature detection module 43 is connected to the control terminal of the first switch SW1 and the control terminal of the second switch SW2. The first temperature detection module 43 is configured to perform temperature detection. When the temperature is within a first temperature range, it controls the first switch SW1 to be turned on and the second switch SW2 to be turned off, so as to inject the first current signal S1 into the reference voltage signal VREF. When the temperature is within a second temperature range, it controls the first switch SW1 to be turned off and the second switch SW2 to be turned on, so as to inject the second current signal S2 into the reference voltage signal VREF.

[0041] Specifically, the first mirror module 41 can be a MOS transistor, specifically a PMOS transistor. The input terminal of the first mirror module 41 is connected to the output terminal of the first current module 10. It can mirror the first current signal S1, which has a positive temperature coefficient characteristic, output by the first current module 10, and output a third current signal S3. The current value of the third current signal S3 can be proportional to the current value of the first current signal S1, and the third current signal S3 has the same temperature coefficient characteristic as the first current signal S1. That is to say, the third current signal S3 is also a current with a positive temperature coefficient characteristic. Similarly, the second mirror module 42 can also be a PMOS transistor, and obtains a fourth current signal S4 with a negative temperature coefficient characteristic by mirroring the second current signal S2.

[0042] Specifically, the first switch SW1 and the second switch SW2 can also be PMOS transistors. The control signal is the gate voltage signal of the PMOS transistor. When the control signal is high, the PMOS transistor is in the off state; when the control signal is low, the PMOS transistor is in the on state. The first temperature detection module 43 is connected to the control terminal of the first switch SW1 and the control terminal of the second switch SW2 (i.e., the gate of the PMOS transistor). In other words, the output signal of the first temperature detection module 43 is the control signal that controls the first switch SW1 and the second switch SW2 to be on and off.

[0043] Next, when the first temperature detection module 43 detects that the temperature is within the first temperature range, it outputs a low-level signal to the control terminal of the first switch SW1 and a high-level signal to the control terminal of the second switch SW2, controlling the first switch SW1 to turn on and the second switch SW2 to turn off. The first terminal of the first switch SW1 is connected to the output terminal of the first mirror module 41, therefore, the first current signal S1 of the first switch SW1 in the on state is injected into the reference voltage signal VREF. When the temperature is detected to be within the second temperature range, the first temperature detection module 43 outputs a high-level signal to the control terminal of the first switch SW1 and a low-level signal to the control terminal of the second switch SW2, controlling the first switch SW1 to turn off and the second switch SW2 to turn on. The first terminal of the second switch SW2 is connected to the output terminal of the second mirror module 42, therefore, the second switch SW2 in the on state injects the second current signal S2 into the reference voltage signal VREF.

[0044] Optionally, the first temperature detection module 43 includes a third mirror module 431, a first resistor R1, a first operational amplifier A1, and an inverter P. The third mirror module 431 is connected to the first current module 10 and is configured to output a fifth current signal S5 that mirrors the first current signal S1. The first end of the first resistor R1 is connected to the output of the third mirror module 431, and the second end of the first resistor R1 is grounded. The first input of the first operational amplifier A1 is connected to the first end of the first resistor R1, and the second input of the first operational amplifier A1 is configured to input a first reference voltage signal V1. The output of the first operational amplifier A1 is connected to the control terminal of the first switch SW1. The input of the inverter P is connected to the output of the first operational amplifier A1, and the output of the inverter P is connected to the control terminal of the second switch SW2.

[0045] Specifically, the third mirror module 431 can be a MOS transistor, specifically a PMOS transistor, which mirrors the first current signal S1 to obtain a fifth current signal S5 with a positive temperature coefficient. The output terminal of the first operational amplifier A1 is directly connected to the control terminal of the first switch SW1 and connected to the control terminal of the second switch SW2 through an inverter P. Therefore, the output signal of the first operational amplifier A1 is the control signal for controlling the first switch SW1 and the second switch SW2 to turn on and off. The output signal of the first operational amplifier A1 is determined by the voltage at its non-inverting input terminal (i.e., the first input terminal) and the voltage at its inverting input terminal (i.e., the second input terminal). The fifth current signal S5 forms a voltage at the first input terminal of the first operational amplifier A1 after flowing through the first resistor R1. By setting the first resistor R1 as a variable resistor, the voltage at the first input terminal of the first operational amplifier A1 can be changed by changing the resistance value of the first resistor R1. Since the first reference voltage signal V1 input to the second input terminal of the first operational amplifier A1 remains unchanged, the output signal of the first operational amplifier A1 can be changed by changing the resistance value of the first resistor R1.

[0046] Next, when the temperature is within the first temperature range, the resistance value of the first resistor R1 is controlled so that the voltage value at the first input terminal of the first operational amplifier A1 is less than the voltage value of the first reference voltage signal V1. The first operational amplifier A1 outputs a low-level signal, controlling the first switch SW1 to turn on. This low-level signal is inverted by the inverter P and becomes a high-level signal, controlling the second switch SW2 to turn off, so as to inject the first current signal S1 into the reference voltage signal VREF. When the temperature is within the second temperature range, the resistance value of the first resistor R1 is controlled so that the voltage value at the first input terminal of the first operational amplifier A1 is greater than the voltage value of the first reference voltage signal V1. The first operational amplifier A1 outputs a high-level signal, controlling the first switch SW1 to turn off. This high-level signal is inverted by the inverter P and becomes a low-level signal, controlling the second switch SW2 to turn on, so as to inject the second current signal S2 into the reference voltage signal VREF.

[0047] Understandably, the first resistor R1 can adjust the temperature point at which the first switch SW1 and the second switch SW2 switch on and off, i.e., adjust the temperature threshold. For example, if the initial temperature point for switching on is set to 50 degrees Celsius, when the temperature is below 50 degrees Celsius, the first switch SW1 is on and the second switch SW2 is off; when the temperature is above 50 degrees Celsius, the first switch SW1 is off and the second switch SW2 is on. Increasing the resistance of the first resistor R1 so that the temperature point for switching on is 40 degrees Celsius means that when the temperature is below 40 degrees Celsius, the first switch SW1 is on and the second switch SW2 is off; when the temperature is above 40 degrees Celsius, the first switch SW1 is off and the second switch SW2 is on. Decreasing the resistance of the first resistor R1 so that the temperature point for switching on is 60 degrees Celsius means that when the temperature is below 60 degrees Celsius, the first switch SW1 is on and the second switch SW2 is off; when the temperature is above 60 degrees Celsius, the first switch SW1 is off and the second switch SW2 is on. The above methods can improve circuit robustness, which plays an important role in enhancing the stability, reliability, anti-interference ability, adaptability, and support for the design and optimization of complex systems.

[0048] See Figure 3 , Figure 3 This is a schematic diagram of the structure of the third embodiment of the temperature compensation circuit provided in this application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30, and a compensation module 40.

[0049] The first current module 10 is configured to output a first current signal S1, which has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, which has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20, and the reference voltage module 30, and is configured to perform temperature detection. When the temperature is within a first temperature range, the first current signal S1 is injected into the reference voltage signal VREF; when the temperature is within a second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0050] Figure 3 The temperature compensation circuit 100 shown is... Figure 2 The main difference in the temperature compensation circuit 100 shown is the addition of descriptions of the components added to the third current module 50 and the compensation module 40. Therefore, the following mainly describes the added components to the third current module 50 and the compensation module 40. For other components in the temperature compensation circuit 100, please refer to [link to relevant documentation]. Figure 2 The related descriptions of the illustrated embodiments, for example Figure 3 The first mirror module 41 in the middle can be seen in Figure 2 The description of the first mirror module 41 in the image is omitted here.

[0051] Optionally, the temperature compensation circuit 100 further includes a third current module 50, configured to output a sixth current signal S6, the sixth current signal S6 having a zero temperature coefficient characteristic; wherein, the compensation module 40 is further configured to inject the second current signal S2 into the reference voltage signal VREF when the temperature is within the second temperature range, and to inject the sixth current signal S6 into the reference voltage signal VREF when the temperature is within the third temperature range, the third temperature range being between the first temperature range and the second temperature range.

[0052] Optionally, the compensation module 40 includes: a first mirror module 41, a first switch SW1, a second mirror module 42, a second switch SW2, a fourth mirror module 44, a third switch SW3, and a second temperature detection module 45. The first mirror module 41 is connected to the first current module 10 and is configured to output a third current signal S3 mirrored with the first current signal S1; the first terminal of the first switch SW1 is connected to the output terminal of the first mirror module 41, and the second terminal of the first switch SW1 is connected to the reference voltage module 30; the second mirror module 42 is connected to the second current module 20 and is configured to output a fourth current signal S4 mirrored with the second current signal S2; the first terminal of the second switch SW2 is connected to the output terminal of the second mirror module 42, and the second terminal of the second switch SW2 is connected to the reference voltage module 30; the fourth mirror module 44 is connected to the third current module 50 and is configured to output a seventh current signal S7 mirrored with the sixth current signal S6; the first terminal of the third switch SW3 is connected to the output terminal of the fourth mirror module 44, and the second terminal of the third switch SW3 is connected to the reference voltage module 30. The reference voltage module 30 and the second temperature detection module 45 are connected to the control terminals of the first switch SW1, the second switch SW2, and the third switch SW3. The second temperature detection module 45 is configured to perform temperature detection. When the temperature is within the first temperature range, it controls the first switch SW1 to be turned on, and controls the second switch SW2 to be turned off, and controls the third switch SW3 to be turned off, so as to inject the first current signal S1 into the reference voltage signal VREF. When the temperature is within the second temperature range, it controls the first switch SW1 to be turned off, and controls the second switch SW2 to be turned on, and controls the third switch SW3 to be turned off, so as to inject the second current signal S2 into the reference voltage signal VREF. When the temperature is within the third temperature range, it controls the first switch SW1 to be turned off, and controls the second switch SW2 to be turned off, and controls the third switch SW3 to be turned on, so as to inject the sixth current signal S6 into the reference voltage signal VREF.

[0053] Specifically, the first mirror module 41, the first switch SW1, the second mirror module 42, and the second switch SW2 can be found in [reference needed]. Figure 2The descriptions of the first mirror module 41, the first switch SW1, the second mirror module 42, and the second switch SW2 are not repeated here. The fourth mirror module 44 can be a PMOS transistor, and obtains a seventh current signal S7 with zero temperature coefficient characteristics by mirroring the sixth current signal S6. The third switch SW3 can also be a PMOS transistor. The second temperature detection module 45 is connected to the control terminals of the first switch SW1, the second switch SW2, and the third switch SW3. That is, the output signal of the second temperature detection module 45 is the control signal for controlling the first switch SW1, the second switch SW2, and the third switch SW3 to turn on and off.

[0054] Next, when the second temperature detection module 45 detects that the temperature is within the first temperature range, it outputs a low-level signal to the control terminal of the first switch SW1 and a high-level signal to the control terminals of the second switch SW2 and the third switch SW3, controlling the first switch SW1 to be turned on, the second switch SW2 to be turned off, and the third switch SW3 to be turned off, so as to inject the first current signal S1 into the reference voltage signal VREF; when the temperature is detected to be within the second temperature range, the second temperature detection module 45 outputs a high-level signal to the control terminals of the first switch SW1 and the third switch SW3 and outputs a low-level signal to the control terminals of the second switch SW2 and the third switch SW3. The control terminal of SW2 controls the first switch SW1 to be off, the second switch SW2 to be on, and the third switch SW3 to be off, so as to inject the second current signal S2 into the reference voltage signal VREF; when the temperature is detected to be within the third temperature range, the second temperature detection module 45 outputs a high-level signal to the control terminals of the first switch SW1 and the second switch SW2, and outputs a low-level signal to the control terminal of the third switch SW3, controlling the first switch SW1 to be off, the second switch SW2 to be off, and the third switch SW3 to be on, so as to inject the sixth current signal S6 into the reference voltage signal VREF.

[0055] Optionally, the second temperature detection module 45 includes: a third mirror module 431, a first resistor R1, a second operational amplifier A2, a third operational amplifier A3, and a logic processing module 451. The third mirror module 431 is connected to the first current module 10. The third mirror module 431 is configured to output a fifth current signal S5 equal to the first current signal S1. The first end of the first resistor R1 is connected to the output end of the third mirror module 431, and the second end of the first resistor R1 is grounded. The first input end of the second operational amplifier A2 is connected to the first end of the first resistor R1, and the second input end of the second operational amplifier A2 is configured to input the first reference voltage signal V1. The first input end of the third operational amplifier A3 is connected to the first end of the first resistor R1, and the second input end of the third operational amplifier A3 is configured to input the second reference voltage signal V2. The voltage value of the second reference voltage signal V2 is different from the voltage value of the first reference voltage signal V1. The input end of the logic processing module 451 is connected to the output end of the second operational amplifier A2 and the output end of the third operational amplifier A3, respectively. The output end of the logic processing module is connected to the control end of the first switch SW1, the control end of the second switch SW2, and the control end of the third switch SW3, respectively.

[0056] Specifically, the third mirror module 431 and the first resistor R1 can be found in [reference needed]. Figure 2 The descriptions of the third mirror module 431 and the first resistor R1 are not repeated here. The output terminals of the second operational amplifier A2 and the third operational amplifier A3 are connected to the control terminals of the first switch SW1, the second switch SW2, and the third switch SW3 through the logic processing module 451. Therefore, the output signals of the second operational amplifier A2 and the third operational amplifier A3 are the control signals that control the first switch SW1, the second switch SW2, and the third switch SW3 to be turned on and off. The output signals of the second operational amplifier A2 and the third operational amplifier A3 are determined by the voltage of their respective non-inverting input terminal (i.e., the first input terminal) and the voltage of their inverting input terminal (i.e., the second input terminal). The fifth current signal S5 flows through the first resistor R1 and forms a voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3. By setting the first resistor R1 as a variable resistor, the voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3 can be changed by changing the resistance value of the first resistor R1, thereby changing the output signals of the second operational amplifier A2 and the third operational amplifier A3.

[0057] Specifically, for the first reference voltage signal V1 and the second reference voltage signal V2, it is only necessary to ensure that their magnitudes are different. That is, the control signals for controlling the first switch SW1, the second switch SW2, and the third switch SW3 can be obtained by changing the resistance value of the first resistor R1. For example, when the first reference voltage signal V1 is greater than the second reference voltage signal V2, the resistance value of the first resistor R1 is changed so that the voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3 is less than the second reference voltage signal V2. At this time, both the second operational amplifier A2 and the third operational amplifier A3 output low-level signals. When the voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3 is greater than the second reference voltage signal V2 and less than the first reference voltage signal V1, the second operational amplifier A2 outputs a low-level signal, and the third operational amplifier A3 outputs a high-level signal. When the voltage at the first input terminal of the second operational amplifier A2 and the third operational amplifier A3 is greater than the first reference voltage signal V1, both the second operational amplifier A2 and the third operational amplifier A3 output high-level signals.

[0058] Optionally, the logic processing module 451 includes: an XOR gate G1, an OR gate G2, and a NAND gate G3. The first input of the XOR gate G1 is connected to the output of the second operational amplifier A2, the second input of the XOR gate G1 is connected to the output of the third operational amplifier A3, and the output of the XOR gate G1 is connected to the control terminal of the third switch SW3; the first input of the OR gate G2 is connected to the output of the second operational amplifier A2, the second input of the OR gate G2 is connected to the output of the third operational amplifier A3, and the output of the OR gate G2 is connected to the control terminal of the first switch SW1; the first input of the NAND gate G3 is connected to the output of the second operational amplifier A2, the second input of the NAND gate G3 is connected to the output of the third operational amplifier A3, and the output of the NAND gate G3 is connected to the control terminal of the second switch SW2.

[0059] Specifically, the output of the XNOR gate G1 depends on whether the input signals are the same. When both input signals are the same (both high or both low), the output is high; when the two input signals are different, the output is low. The output of the OR gate G2 depends on whether at least one of the input signals is high. When one or more input signals are high, the output is high; when all input signals are low, the output is low. The output of the NAND gate G3 depends on the logic relationship between its inputs. When all inputs are high, the output is low; when at least one input is low, the output is high.

[0060] Next, when the detected temperature is within the first temperature range, the resistance value of the first resistor R1 is changed so that the output signals of the second operational amplifier A2 and the third operational amplifier A3 are both low. Then, the XOR gate G1 and the NAND gate G3 output high-level signals, and the OR gate G2 outputs a low-level signal. The output terminal of the OR gate G2 is connected to the control terminal of the first switch SW1, so the first switch SW1 is turned on, and the second switch SW2 and the third switch SW3 are turned off, injecting the first current signal S1 into the reference voltage signal VREF. When the detected temperature is within the second temperature range, the resistance value of the first resistor R1 is changed so that the output signals of the second operational amplifier A2 and the third operational amplifier A3 are both low. Then, the XOR gate G1 and the OR gate G2 output high-level signals. The NAND gate G3 outputs a low-level signal. The output terminal of the NAND gate G3 is connected to the control terminal of the second switch SW2, so the second switch SW2 is turned on, and the first switch SW1 and the third switch SW3 are turned off, injecting the second current signal S2 into the reference voltage signal VREF. When the detected temperature is within the third temperature range, the resistance value of the first resistor R1 is changed so that the output signal levels of the second operational amplifier A2 and the third operational amplifier A3 are different. Then the OR logic gate G2 and the NAND gate G3 output high-level signals, and the XOR logic gate G1 outputs a low-level signal. The output terminal of the XOR logic gate G1 is connected to the control terminal of the third switch SW3, so the third switch SW3 is turned on, and the first switch SW1 and the second switch SW2 are turned off, injecting the sixth current signal S6 into the reference voltage signal VREF.

[0061] See Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the temperature compensation circuit provided in this application. The temperature compensation circuit 100 includes: a first current module 10, a second current module 20, a reference voltage module 30, and a compensation module 40.

[0062] The first current module 10 is configured to output a first current signal S1, which has a positive temperature coefficient characteristic; the second current module 20 is configured to output a second current signal S2, which has a negative temperature coefficient characteristic; the reference voltage module 30 is configured to output a reference voltage signal VREF; the compensation module 40 is connected to the first current module 10, the second current module 20, and the reference voltage module 30, and is configured to perform temperature detection. When the temperature is within a first temperature range, the first current signal S1 is injected into the reference voltage signal VREF; when the temperature is within a second temperature range, the second current signal S2 is injected into the reference voltage signal VREF.

[0063] Figure 4 The temperature compensation circuit 100 shown is... Figure 3The main difference in the temperature compensation circuit 100 shown is the addition of descriptions of the components added to the first current module 10, the second current module 20, the third current module 50, and the reference voltage module 30. Therefore, the following mainly describes the components added to the first current module 10, the second current module 20, the third current module 50, and the reference voltage module 30. For other components in the temperature compensation circuit 100, please refer to [link to relevant documentation]. Figure 3 The related descriptions of the illustrated embodiments, for example Figure 4 The logic processing module 451 in the middle can be found in [reference]. Figure 3 The description of the logic processing module 451 in the middle will not be repeated here.

[0064] Optionally, the first current module 10 includes: a first MOSFET M1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fourth operational amplifier A4, a fifth resistor R5, a first transistor Q1, and a second transistor Q2. The first terminal of the first MOSFET M1 is configured to receive the input power supply voltage signal VDD. The control terminal of the first MOSFET M1 is connected to the control terminals of the first mirror module 41 and the third mirror module 431. The first terminal of the second resistor R2 is connected to the second terminal of the first MOSFET M1. The first terminal of the third resistor R3 is connected to the second terminal of the second resistor R2. The first terminal of the fourth resistor R4 is connected to the second terminal of the second resistor R2. The first input terminal of the fourth operational amplifier A4 is connected to the second terminal of the fourth resistor R4. The second input terminal of the fourth operational amplifier A4 is connected to the second terminal of the third resistor R3. The output terminal of the fourth operational amplifier A4 is connected to the control terminal of the first MOSFET M1. The first terminal of the fifth resistor R5 is connected to the first input terminal of the fourth operational amplifier A4. The first terminal of the first transistor Q1 is connected to the second input terminal of the fourth operational amplifier A4. The second terminal of the first transistor Q1 and its control terminal are grounded. The first terminal of the second transistor Q2 is connected to the second terminal of the fifth resistor R5. The second terminal of the second transistor Q2 and its control terminal are grounded.

[0065] Specifically, the first MOS transistor M1 can be a PMOS transistor. In one embodiment, the ratio of the number of the first transistor Q1 to the number of the second transistor Q2 can be 1:8. The base-emitter voltage of the first transistor Q1 is VBE1, and the base-emitter voltage of the second transistor Q2 is VBE2. The difference between VBE1 and VBE2 is proportional to the absolute temperature, i.e., it has a positive temperature coefficient characteristic. Due to the virtual short principle of the fourth operational amplifier A4, the voltage values ​​at the first and second input terminals of the fourth operational amplifier A4 are equal. Therefore, the magnitude of the current I1 flowing through the second transistor is:

[0066]

[0067] When the resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal, the current values ​​flowing through the first transistor Q1 and the second transistor Q2 are also equal, that is, the current flowing through the first MOSFET M1 is 2I. This current is the first current signal S1 with positive temperature coefficient characteristics. By setting the fifth resistor R5 as a variable resistor, the value of the first current signal S1 can be changed by changing the resistance value of the fifth resistor R5.

[0068] Optionally, the second current module 20 includes: a second MOSFET M2, a third MOSFET M3, a sixth resistor R6, a current source IS, a fifth operational amplifier A5, and a third transistor Q3. The first terminal of the second MOSFET M2 is configured to input the power supply voltage signal VDD, and the control terminal of the second MOSFET M2 is connected to the control terminal of the second mirror module 42; the first terminal of the third MOSFET M3 is connected to the second terminal of the second MOSFET M2; the first terminal of the sixth resistor R6 is connected to the second terminal of the third MOSFET M3, and the second terminal of the sixth resistor R6 is grounded; the first terminal of the current source IS is connected to the first terminal of the second MOSFET M2; the first input terminal of the fifth operational amplifier A5 is connected to the second terminal of the current source IS, the second input terminal of the fifth operational amplifier A5 is connected to the first terminal of the sixth resistor R6, and the output terminal of the fifth operational amplifier A5 is connected to the control terminal of the third MOSFET M3; the first terminal of the third transistor Q3 is connected to the first input terminal of the fifth operational amplifier A5, and the second terminal and control terminal of the third transistor Q3 are grounded.

[0069] Specifically, the second MOSFET M2 can be a PMOS transistor, and the third MOSFET M3 can be an NMOS transistor. The base-emitter voltage of the third transistor Q3 is inversely proportional to its absolute temperature, i.e., it has a negative temperature coefficient. The current from the current source IS flows through the third transistor Q3, causing it to generate a base-emitter voltage VBE3 with a negative temperature coefficient. Due to the virtual short principle of the fifth operational amplifier A5, the potential at the second input terminal of the fifth operational amplifier A5 is equal to that at the first input terminal. Therefore, the current I2 flowing through the sixth resistor R6 can be expressed by the following formula:

[0070]

[0071] The current flowing through the second MOSFET M2 is I2, which is the second current signal S2 with a negative temperature coefficient. By setting the sixth resistor R6 as a variable resistor, the value of the second current signal S2 can be changed by changing the resistance value of the sixth resistor R6.

[0072] Optionally, the reference voltage module 30 includes a seventh resistor R7 and an eighth resistor R8. The first terminal of the seventh resistor R7 is configured as an input power supply voltage signal VDD. The first terminal of the eighth resistor R8 is connected to the second terminal of the seventh resistor R7, and the second terminal of the eighth resistor R8 is grounded. The voltage divider node of the seventh resistor R7 and the eighth resistor R8 is configured as an output reference voltage signal VREF.

[0073] Specifically, the seventh resistor R7 and the eighth resistor R8 have positive and negative temperature coefficient characteristics, respectively. The two positive and negative temperature characteristics cancel each other out, which is equivalent to performing a temperature compensation on the reference voltage signal VREF output by the voltage divider node of the two resistors.

[0074] Optionally, the third current module 50 includes: a fourth MOSFET M4, a fifth MOSFET M5, a ninth resistor R9, a sixth operational amplifier A6, and a voltage source VS. The first terminal of the fourth MOSFET M4 is configured to receive the input power supply voltage signal VDD, and the control terminal of the fourth MOSFET M4 is connected to the control terminal of the fourth mirror module 44; the first terminal of the fifth MOSFET M5 is connected to the second terminal of the fourth MOSFET M4; the first terminal of the ninth resistor R9 is connected to the second terminal of the fifth MOSFET M5, and the second terminal of the ninth resistor R9 is grounded; the first input terminal of the sixth operational amplifier A6 is grounded, the second input terminal of the sixth operational amplifier A6 is connected to the first terminal of the ninth resistor R9, and the output terminal of the sixth operational amplifier A6 is connected to the control terminal of the fifth MOSFET M5; the first terminal of the voltage source VS is connected to the first input terminal of the sixth operational amplifier A6, and the second terminal of the voltage source VS is grounded.

[0075] Specifically, the fourth MOSFET M4 can be a PMOS transistor, the fifth MOSFET M5 can be an NMOS transistor, the voltage of the voltage source VS is input to the first input terminal of the sixth operational amplifier A6, and the potential of the second input terminal of the sixth operational amplifier A6 is equal to that of the first input terminal. That is, the current I3 flowing through the ninth resistor R9 can be expressed by the following formula:

[0076]

[0077] The current flowing through the fourth MOSFET M4 is I3. This current has a near-zero temperature coefficient and is the sixth current signal S6. By setting the ninth resistor R9 as a variable resistor, the value of the sixth current signal S6 can be changed by changing the resistance of the ninth resistor R9.

[0078] Understandably, the temperature compensation circuit 100 of this application performs two-stage temperature compensation on the reference voltage signal VREF through a first current module 10, a second current module 20, a first mirror module 41, a first switch SW1, a second mirror module 42, a second switch SW2, and a first temperature detection module 43. Then, it performs three-stage temperature compensation on the reference voltage signal VREF through a first current module 10, a second current module 20, a third current module 50, a first mirror module 41, a first switch SW1, a second mirror module 42, a second switch SW2, a fourth mirror module 44, a third switch SW3, and a second temperature detection module 45. By performing segmented temperature compensation on the reference signal VREF in this way, a lower temperature drift clock output can be achieved, providing a higher precision output clock and meeting the high-precision clock requirements of the MCU chip.

[0079] In an application scenario, such as Figure 5 As shown, 20 temperature points were sampled in the temperature range of -40℃ to 150℃. Before adding two-stage temperature compensation, the temperature drift of the output clock frequency was about 0.83%. After adding two-stage temperature compensation, the temperature drift of the output clock frequency was reduced to 0.25%. After using three-stage temperature compensation, the temperature drift of the output clock frequency was reduced to 0.09%.

[0080] See Figure 6 , Figure 6 This is a schematic diagram of an embodiment of the electronic device 1000 provided in this application. The electronic device includes a temperature compensation circuit 100, which is the temperature compensation circuit 100 described above, and will not be repeated here.

[0081] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0082] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0083] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0084] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A temperature compensation circuit, characterized in that, The temperature compensation circuit includes: The first current module is configured to output a first current signal, which has a positive temperature coefficient characteristic. The second current module is configured to output a second current signal, which has a negative temperature coefficient characteristic. The reference voltage module is configured to output a reference voltage signal; The compensation module is connected to the first current module, the second current module, and the reference voltage module. The compensation module is configured to perform temperature detection. When the temperature is within a first temperature range, the first current signal is injected into the reference voltage signal. When the temperature is within a second temperature range, the second current signal is injected into the reference voltage signal. The compensation module includes: A first mirror module is connected to the first current module, and the first mirror module is configured to output a third current signal that mirrors the first current signal. A first switch, the first end of which is connected to the output terminal of the first mirror module, and the second end of which is connected to the reference voltage module; The second mirror module is connected to the second current module, and the second mirror module is configured to output a fourth current signal that mirrors the second current signal; The second switch has its first end connected to the output terminal of the second mirror module and its second end connected to the reference voltage module. A first temperature detection module is connected to the control terminal of the first switch and the control terminal of the second switch. The first temperature detection module is configured to perform temperature detection. When the temperature is within the first temperature range, it controls the first switch to be turned on and controls the second switch to be turned off, so as to inject the first current signal into the reference voltage signal. When the temperature is within the second temperature range, it controls the first switch to be turned off and controls the second switch to be turned on, so as to inject the second current signal into the reference voltage signal.

2. The temperature compensation circuit according to claim 1, characterized in that, The first temperature detection module includes: A third mirror module is connected to the first current module, and the third mirror module is configured to output a fifth current signal that mirrors the first current signal. A first resistor, the first end of which is connected to the output terminal of the third mirror module, and the second end of which is grounded; A first operational amplifier, wherein the first input terminal of the first operational amplifier is connected to the first terminal of the first resistor, the second input terminal of the first operational amplifier is configured to input a first reference voltage signal, and the output terminal of the first operational amplifier is connected to the control terminal of the first switch; An inverter, the input of which is connected to the output of the first operational amplifier, and the output of which is connected to the control terminal of the second switch.

3. The temperature compensation circuit according to claim 1, characterized in that, The temperature compensation circuit also includes a third current module, configured to output a sixth current signal, which has a zero temperature coefficient characteristic. The compensation module is further configured to inject the second current signal into the reference voltage signal when the temperature is within the second temperature range, and to inject the sixth current signal into the reference voltage signal when the temperature is within the third temperature range, wherein the third temperature range is located between the first temperature range and the second temperature range.

4. The temperature compensation circuit according to claim 3, characterized in that, The compensation module includes: A first mirror module is connected to the first current module, and the first mirror module is configured to output a third current signal that mirrors the first current signal. A first switch, the first end of which is connected to the output terminal of the first mirror module, and the second end of which is connected to the reference voltage module; The second mirror module is connected to the second current module, and the second mirror module is configured to output a fourth current signal that mirrors the second current signal; The second switch has its first end connected to the output terminal of the second mirror module and its second end connected to the reference voltage module. The fourth mirror module is connected to the third current module and is configured to output a seventh current signal that mirrors the sixth current signal. The third switch has its first end connected to the output terminal of the fourth mirror module and its second end connected to the reference voltage module. The second temperature detection module is connected to the control terminals of the first switch, the second switch, and the third switch. The second temperature detection module is configured to detect temperature. When the temperature is within the first temperature range, it controls the first switch to be on, the second switch to be off, and the third switch to be off, so as to inject the first current signal into the reference voltage signal. When the temperature is within the second temperature range, it controls the first switch to be off, the second switch to be on, and the third switch to be off, so as to inject the second current signal into the reference voltage signal. When the temperature is within the third temperature range, it controls the first switch to be off, the second switch to be off, and the third switch to be on, so as to inject the sixth current signal into the reference voltage signal.

5. The temperature compensation circuit according to claim 4, characterized in that, The second temperature detection module includes: A third mirror module is connected to the first current module, and the third mirror module is configured to output a fifth current signal equal to the first current signal; A first resistor, the first end of which is connected to the output terminal of the third mirror module, and the second end of which is grounded; A second operational amplifier, wherein the first input terminal of the second operational amplifier is connected to the first terminal of the first resistor, and the second input terminal of the second operational amplifier is configured to input a first reference voltage signal; A third operational amplifier, wherein the first input terminal of the third operational amplifier is connected to the first terminal of the first resistor, and the second input terminal of the third operational amplifier is configured to input a second reference voltage signal; wherein the voltage value of the second reference voltage signal is different from the voltage value of the first reference voltage signal; The logic processing module has its input terminals connected to the output terminals of the second operational amplifier and the third operational amplifier, respectively, and its output terminals connected to the control terminals of the first switch, the second switch, and the third switch, respectively.

6. The temperature compensation circuit according to claim 5, characterized in that, The logic processing module includes: A multi-OR logic gate, wherein the first input terminal of the multi-OR logic gate is connected to the output terminal of the second operational amplifier, the second input terminal of the multi-OR logic gate is connected to the output terminal of the third operational amplifier, and the output terminal of the multi-OR logic gate is connected to the control terminal of the third switch; An OR logic gate is provided, wherein the first input terminal of the OR logic gate is connected to the output terminal of the second operational amplifier, the second input terminal of the OR logic gate is connected to the output terminal of the third operational amplifier, and the output terminal of the OR logic gate is connected to the control terminal of the first switch. The NAND gate has its first input connected to the output of the second operational amplifier, its second input connected to the output of the third operational amplifier, and its output connected to the control terminal of the second switch.

7. The temperature compensation circuit according to claim 1, characterized in that, The first current module includes: The first MOSFET is configured to input a power supply voltage signal at its first terminal, and the control terminal of the first MOSFET is connected to the control terminal of the first mirror module and the control terminal of the third mirror module. The second resistor has its first end connected to the second end of the first MOSFET. A third resistor, wherein the first end of the third resistor is connected to the second end of the second resistor; A fourth resistor, wherein the first end of the fourth resistor is connected to the second end of the second resistor; A fourth operational amplifier, wherein the first input terminal of the fourth operational amplifier is connected to the second terminal of the fourth resistor, the second input terminal of the fourth operational amplifier is connected to the second terminal of the third resistor, and the output terminal of the fourth operational amplifier is connected to the control terminal of the first MOS transistor; The fifth resistor, the first end of which is connected to the first input terminal of the fourth operational amplifier; The first transistor has its first terminal connected to the second input terminal of the fourth operational amplifier, and its second terminal and control terminal are grounded. The second transistor, with its first terminal connected to the second terminal of the fifth resistor, and its second terminal and the control terminal grounded; or The second current module includes: The second MOSFET has its first terminal configured as an input power supply voltage signal, and its control terminal is connected to the control terminal of the second mirror module. The third MOSFET, wherein the first end of the third MOSFET is connected to the second end of the second MOSFET; The sixth resistor has its first end connected to the second end of the third MOSFET, and its second end grounded. A current source, wherein the first end of the current source is connected to the first end of the second MOS transistor; The fifth operational amplifier has its first input terminal connected to the second terminal of the current source, its second input terminal connected to the first terminal of the sixth resistor, and its output terminal connected to the control terminal of the third MOS transistor. The third transistor, wherein its first terminal is connected to the first input terminal of the fifth operational amplifier, and its second terminal and control terminal are grounded; or The reference voltage module includes: The seventh resistor, the first terminal of which is configured as an input power supply voltage signal; The eighth resistor has its first end connected to the second end of the seventh resistor, and its second end is grounded. The voltage divider node of the seventh resistor and the eighth resistor is configured to output the reference voltage signal.

8. The temperature compensation circuit according to claim 3, characterized in that, The third current module includes: The fourth MOSFET, the first terminal of which is configured to input a power supply voltage signal, and the control terminal of which is connected to the control terminal of the fourth mirror module; The fifth MOSFET, wherein the first terminal of the fifth MOSFET is connected to the second terminal of the fourth MOSFET; The ninth resistor has its first end connected to the second end of the fifth MOS transistor, and its second end grounded. The sixth operational amplifier has its first input terminal grounded, its second input terminal connected to the first terminal of the ninth resistor, and its output terminal connected to the control terminal of the fifth MOS transistor. A voltage source, the first end of which is connected to the first input terminal of the sixth operational amplifier, and the second end of which is grounded.

9. An electronic device, characterized in that, The electronic device includes a temperature compensation circuit as described in any one of claims 1-8.

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