A low temperature drift voltage type bandgap reference and a high sensitivity negative temperature voltage generation circuit

Abstract

The present invention relates to the field of bandgap references, and particularly to a low-temperature-drift voltage-type bandgap reference and a high-sensitivity negative-temperature-voltage generation circuit, including a curvature compensation module, a bandgap reference core module, and a high-sensitivity NTC voltage module; the bandgap reference core module includes a positive temperature coefficient voltage term generation branch and a negative temperature coefficient voltage term generation branch, the output end of the curvature compensation module is electrically connected to the input ends of the positive temperature coefficient voltage term generation branch and the negative temperature coefficient voltage term generation branch, the output ends of the positive temperature coefficient voltage term generation branch and the negative temperature coefficient voltage term generation branch are connected, and a low-temperature-drift bandgap voltage V is output bandgap ; the bandgap reference core module adopts a voltage-type CMOS bandgap reference structure, and the positive temperature coefficient voltage term generation branch generates ΔV BE , the negative temperature coefficient voltage term generation branch generates V BE , and the two are complementary to generate a low-temperature-drift bandgap voltage V bandgap .

Description

Technical Field

[0001] The present invention relates to the field of bandgap reference sources, and in particular to a low-temperature drift voltage-type bandgap reference and a high-sensitivity negative temperature voltage generating circuit. Background Art

[0002] Bandgap reference, or bandgap for short, is a circuit that provides a reference voltage or reference current and is widely used in high-precision comparators, data converters, and other analog integrated circuits. The core idea of ​​the bandgap reference is to compensate for temperature changes through circuit design. It uses the sum of a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient. By properly configuring these two voltages, their temperature coefficients cancel each other out, thereby achieving a temperature-independent voltage reference. This excellent temperature stability makes the bandgap reference an ideal choice for high-precision voltage references.

[0003] Bandgap reference sources can be divided into bipolar bandgap reference sources and CMOS bandgap reference sources. Both types of bandgap reference sources have wide adaptability in process conditions, the output voltage is less affected by temperature and power supply voltage, and the accuracy is high. Among them, the CMOS bandgap reference source has good applicability and low power consumption, and is widely used. However, the traditional first-order compensated voltage-type CMOS bandgap reference source still has a high temperature coefficient, which is difficult to meet the application requirements of high-precision chips that are sensitive to temperature changes. Summary of the invention

[0004] The purpose of the present invention is to provide a low-temperature drift voltage-type bandgap reference and a high-sensitivity negative temperature voltage generating circuit, aiming to improve the problem that the traditional voltage-type CMOS bandgap reference source after first-order compensation still has a high temperature coefficient and is difficult to meet the application requirements of high-precision chips that are sensitive to temperature changes.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A low temperature drift voltage type bandgap reference and a high sensitivity negative temperature voltage generation circuit, including a curvature compensation module, a bandgap reference core module, and a high sensitivity NTC voltage module;

[0007] The power input terminals of the curvature compensation module, the bandgap reference core module, and the high-sensitivity NTC voltage module are all electrically connected to the external power supply VDD1;

[0008] The bandgap reference core module includes a positive temperature coefficient voltage term generating branch and a negative temperature coefficient voltage term generating branch, the output end of the curvature compensation module is electrically connected to the input end of the positive temperature coefficient voltage term generating branch and the negative temperature coefficient voltage term generating branch, the output end of the positive temperature coefficient voltage term generating branch and the negative temperature coefficient voltage term generating branch are connected, and output a low temperature drift bandgap voltage Vbandgap ;

[0009] The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap To the curvature compensation module;

[0010] The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap and V BE3 The voltage is transmitted to a high-sensitivity NTC voltage module, and the high-sensitivity NTC voltage module outputs a negative temperature voltage Vout_N.

[0011] Furthermore, the positive temperature coefficient voltage term generating branch includes a trimming resistor network, a piecewise linear compensation module, a MOS tube P3 and resistors R3 and R5;

[0012] The negative temperature coefficient voltage term generating branch includes an operational amplifier OP2, a MOS tube P5, a transistor Q1, a transistor Q2, a transistor Q3 and resistors R1, R2 and R4;

[0013] The source of the MOS tube P3 is electrically connected to the external power supply VDD1; the piecewise linear compensation module outputs the bias voltage VB1 to the gate of the MOS tube P3;

[0014] The output end of the curvature compensation module is electrically connected to one end of the resistor R1, one end of the resistor R5 and the same-direction input end of the operational amplifier OP2, and the other end of the resistor R1 is electrically connected to the emitter of the transistor Q1; the reverse input end of the operational amplifier OP2 is electrically connected to one end of the resistor R2, and the other end of the resistor R2 is electrically connected to one end of the resistor R4 and the emitter of the transistor Q2; the output end of the operational amplifier OP2 is electrically connected to the gate of the MOS tube P5, and the drain of the MOS tube P5 is electrically connected to the emitter of the transistor Q3, and outputs V BE3 Voltage to high sensitivity NTC voltage module;

[0015] The other end of the resistor R5 is electrically connected to the VNL1 port of the trimming resistor network, the VNL2 port of the trimming resistor network is electrically connected to the piecewise linear compensation module and one end of the resistor R3, the other end of the resistor R3 is electrically connected to the drain of the MOS tube P3, the source of the MOS tube P5, and the other end of the resistor R4, and outputs the low temperature drift bandgap voltage V as an output end. bandgap Highest sensitivity NTC voltage module and curvature compensation module;

[0016] The collectors and bases of the transistors Q1 , Q2 and Q3 are all grounded.

[0017] Furthermore, the curvature compensation module includes an operational amplifier OP1, a MOS tube P1, a MOS tube P2, a transistor Q4, and resistors R6, R7, R11, and R12;

[0018] The source of the MOS transistor P1 and the source of the MOS transistor P2 are both electrically connected to the external power supply VDD1;

[0019] The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap to the inverting input terminal of the operational amplifier OP1; the drain of the MOS tube P1 is electrically connected to the non-inverting input terminal of the operational amplifier OP1, and the gate of the MOS tube P1 is electrically connected to the gate of the MOS tube P2 and the output terminal of the operational amplifier OP1; the resistor R6, the resistor R11 and the resistor R12 are sequentially connected in series between the drain of the MOS tube P1 and the ground;

[0020] The drain of the MOS tube P2 is electrically connected to one end of the resistor R7 and the emitter of the transistor Q4, and the other end of the resistor R7 is electrically connected as an output end to the input ends of the positive temperature coefficient voltage term generating branch and the negative temperature coefficient voltage term generating branch;

[0021] The base and collector of the transistor Q4 are both grounded.

[0022] Further, the high-sensitivity NTC voltage module includes an operational amplifier OP3, an operational amplifier OP4, a MOS transistor P4, a MOS transistor N21, a MOS transistor N22, a MOS transistor N23, a capacitor C1, and resistors R8, R9, and R10;

[0023] The source of the MOS transistor P4 and the drain of the MOS transistor N22 are both electrically connected to the external power supply VDD1; the piecewise linear compensation module outputs the bias voltage VB1 to the gate of the MOS transistor P4;

[0024] The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap to the same-direction input terminal of the operational amplifier OP3, the inverting input terminal and the output terminal of the operational amplifier OP3 are both electrically connected to one end of the resistor R8; the other end of the resistor R8 is electrically connected to one end of the resistor R9, one end of the resistor R10 and the same-direction input terminal of the operational amplifier OP4, and the bandgap reference core module outputs V BE3The voltage is supplied to the inverting input terminal of the operational amplifier OP4, the output terminal of the operational amplifier OP4 is electrically connected to the gate of the MOS tube N21, the gate of the MOS tube N23 and one end of the capacitor C1; the drain of the MOS tube N21 is electrically connected to the drain of the MOS tube P4 and the gate of the MOS tube N22, the source of the MOS tube N22 is electrically connected to the other end of the capacitor C1, the drain of the MOS tube N23 and the other end of the resistor R9, and outputs the negative temperature voltage Vout_N as the output terminal;

[0025] The source of the MOS transistor N21, the source of the MOS transistor N23 and the other end of the resistor R10 are grounded.

[0026] Furthermore, the piecewise linear compensation module includes a start-up unit, a bias unit and an I PATA Generation Unit, I CTAT Generation unit and piecewise linear compensation unit;

[0027] The startup unit, bias and I PATA Generation Unit, I CTAT The power input terminals of the generating unit and the piecewise linear compensation unit are both electrically connected to the external power supply VDD1;

[0028] The output terminal of the startup unit is connected to the bias and I PATA The signal input terminal of the generating unit is electrically connected to the bias and I PATA The output end of the generating unit outputs the bias voltage VB1 to the gate of the MOS tube P3, and outputs the bias voltage VB1 and the current I PATA To the first input terminal of the piecewise linear compensation unit; the I CTAT Generating unit output current I CTAT to a second input terminal of the piecewise linear compensation unit, the output terminal of the piecewise linear compensation unit being electrically connected to a VNL2 port of the trimming resistor network;

[0029] The current I PATA is a current that is positively proportional to absolute temperature. CTAT A current that has a complementary characteristic to absolute temperature.

[0030] Further, the startup unit includes MOS transistor P6, MOS transistor P18, MOS transistor N1 and MOS transistor N2;

[0031] The source of the MOS tube P18 is electrically connected to the external power supply VDD1;

[0032] The drain of the MOS transistor P18 is electrically connected to the source of the MOS transistor P6, and the gate of the MOS transistor P18 is electrically connected to the gate of the MOS transistor P6 and the gate of the MOS transistor N1, and serves as the first output terminal and is connected to the bias and IPATA The signal input terminal of the generating unit is electrically connected;

[0033] The drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor N1 and the gate of the MOS transistor N2. The drain of the MOS transistor N2 is used as a second output terminal and connected to the bias and I PATA The signal input terminal of the generating unit is electrically connected;

[0034] The source of the MOS transistor N1 and the source of the MOS transistor N2 are both grounded.

[0035] Furthermore, the bias and I PATA The generating unit includes MOS tube P7, MOS tube P8, MOS tube N3, MOS tube N4 and resistor R14;

[0036] The source of the MOS transistor P7 and the source of the MOS transistor P8 are both electrically connected to the external power supply VDD1;

[0037] The first output end of the startup unit is electrically connected to the gate of the MOS tube N3, the drain of the MOS tube P7 and one end of the resistor R14, the other end of the resistor R14 is electrically connected to the drain of the MOS tube N3 and the gate of the MOS tube N4, the second output end of the startup unit is electrically connected to the gate of the MOS tube P7, the gate and drain of the MOS tube P8 and the drain of the MOS tube N4, the gate of the MOS tube P7 is used as an output end to output the bias voltage VB1 to the gate of the MOS tube P3, and output the bias voltage VB1 and the current I PATA to a first input terminal of a piecewise linear compensation unit;

[0038] The source of the MOS transistor N3 and the source of the MOS transistor N4 are both grounded.

[0039] Furthermore, the I CTAT The generating unit includes an operational amplifier OP5, a MOS tube P16, a MOS tube P17, a transistor Q5 and a resistor R13;

[0040] The source of the MOS transistor P16 and the source of the MOS transistor P17 are both electrically connected to the external power supply VDD1;

[0041] The gate of the MOS transistor P16 is electrically connected to the gate of the MOS transistor P17 and the output terminal of the operational amplifier OP5, and outputs a current I CTAT to the second input terminal of the piecewise linear compensation unit; the drain of the MOS tube P16 is electrically connected to one end of the resistor R13 and the same-direction input terminal of the operational amplifier OP5, and the drain of the MOS tube P17 is electrically connected to the emitter of the transistor Q5 and the reverse input terminal of the operational amplifier OP5;

[0042] The collector and base of the transistor Q5 and the other end of the resistor R13 are grounded.

[0043] Further, the piecewise linear compensation unit includes MOS transistor P9, MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor P13, MOS transistor P14, MOS transistor P15, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10, MOS transistor N11, MOS transistor N12, MOS transistor N13, MOS transistor N14 and MOS transistor N15;

[0044] The source of the MOS transistor P9, the source of the MOS transistor P10, the source of the MOS transistor P11, the source of the MOS transistor P12, the source of the MOS transistor P13, the source of the MOS transistor P14 and the source of the MOS transistor P15 are all electrically connected to the external power supply VDD1;

[0045] The gate of the MOS transistor P9 is electrically connected to the gate and drain of the MOS transistor P10, the drain of the MOS transistor N6, the gate and drain of the MOS transistor P13, the gate of the MOS transistor N11, the gate and drain of the MOS transistor N12, and the drain of the MOS transistor N13; the drain of the MOS transistor P9 is electrically connected to the drain and gate of the MOS transistor N5 and the gate of the MOS transistor N8;

[0046] The bias and I PATA The generating unit outputs bias voltage VB1 and current I PATA To the gate of the MOS transistor P11, the drain of the MOS transistor P11 is electrically connected to the gate and drain of the MOS transistor N7 and the gate of the MOS transistor N6;

[0047] The gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P15 and the drain of the MOS transistor N15, and the drain of the MOS transistor P12 is electrically connected to the drain of the MOS transistor N8, the gate and drain of the MOS transistor N9 and the gate of the MOS transistor N10;

[0048] I CTAT Generating unit output current I CTAT to the gate of the MOS transistor P14, the drain of the MOS transistor P14 is electrically connected to the gate and drain of the MOS transistor N14, the gate of the MOS transistor N13, and the gate of the MOS transistor N15;

[0049] The drain of the MOS tube N11 is electrically connected to the drain of the MOS tube N10, and is electrically connected to the VNL2 port of the trimming resistor network as an output end;

[0050] The source of the MOS tube N5, the source of the MOS tube N6, the source of the MOS tube N7, the source of the MOS tube N8, the source of the MOS tube N9, the source of the MOS tube N10, the source of the MOS tube N11, the source of the MOS tube N12, the source of the MOS tube N13, the source of the MOS tube N14 and the source of the MOS tube N15 are all grounded.

[0051] After adopting the above technical solution, the present invention has the following advantages compared with the background technology:

[0052] The bandgap reference core module adopts a voltage-type CMOS bandgap reference structure, and the positive temperature coefficient voltage term generation branch generates ΔV BE , the negative temperature coefficient voltage term generates a branch to generate V BE , the two complement each other to generate a low temperature drift bandgap voltage V bandgap ; At the same time, the curvature compensation module further offsets the negative temperature coefficient voltage term V BE The influence of the high-order terms in the , and the low-temperature drift bandgap reference is obtained. And through the low-temperature drift bandgap voltage V bandgap and V BE3 The voltage and high-sensitivity NTC voltage module outputs a negative temperature characteristic voltage Vout_N with a specific temperature slope. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A circuit diagram of a low temperature drift voltage type bandgap reference and a high sensitivity negative temperature voltage generating circuit according to the present invention;

[0054] Figure 2 The different resistance values ​​of the resistor R9 of the low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generating circuit of the present invention, the negative temperature voltage V out_N Temperature characteristic simulation diagram;

[0055] Figure 3 The negative temperature voltage V of the low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit of the present invention is out_N With V BE3 Temperature characteristics comparison curve;

[0056] Figure 4 The low-temperature drift bandgap voltage V without any compensation under the tt process angle is the low-temperature drift voltage type bandgap reference and high-sensitivity negative temperature voltage generation circuit of the present invention. bandgap Simulation curve graph;

[0057] Figure 5 The low-temperature drift voltage-type bandgap reference and high-sensitivity negative temperature voltage generation circuit of the present invention are added with high-order curvature compensation at the tt process angle, and the low-temperature drift bandgap voltage V bandgap Simulation curve graph;

[0058] Figure 6 It is a circuit diagram of the first part of the piecewise linear compensation module of the low-temperature drift voltage-type bandgap reference and high-sensitivity negative temperature voltage generation circuit of the present invention;

[0059] Figure 7 It is a circuit diagram of the second part of the piecewise linear compensation module of the low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit of the present invention;

[0060] Figure 8 It is a compensation current simulation diagram of the piecewise linear compensation module of the low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit of the present invention;

[0061] Fig. 9 The low-temperature drift bandgap voltage V of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generation circuit of the present invention is bandgap Power-on simulation diagram;

[0062] Fig.10 The low-temperature drift voltage-type bandgap reference and high-sensitivity negative temperature voltage generation circuit of the present invention is added with a piecewise linear compensation module at the tt process angle, and the low-temperature drift bandgap voltage V bandgap Simulation curve graph;

[0063] Fig.11 The low-temperature drift bandgap voltage V of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generation circuit of the present invention is bandgap Linear regulation rate simulation curve diagram;

[0064] Fig.12 The low-temperature drift bandgap voltage V of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generation circuit of the present invention is bandgap Power supply rejection ratio simulation curve diagram;

[0065] Fig.13 A circuit diagram of a trimming resistor network of a low temperature drift voltage-type bandgap reference and a high sensitivity negative temperature voltage generating circuit according to the present invention;

[0066] Fig.14 It is a simulation diagram of bandgap voltage temperature drift at various process angles when the adjustment value of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generating circuit of the present invention is '01110';

[0067] Fig.15 It is a simulation diagram of the bandgap voltage temperature drift at each process angle when the adjustment value of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generation circuit of the present invention is '01011';

[0068] Fig.16It is a simulation diagram of the bandgap temperature drift coefficient at each process angle when the adjustment value of the low temperature drift voltage type bandgap reference and the high sensitivity negative temperature voltage generating circuit of the present invention is '01001';

[0069] Fig.17 It is a simulation diagram of the bandgap temperature drift coefficient at each process angle when the adjustment value of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generating circuit of the present invention is '10100';

[0070] Fig.18 It is a simulation diagram of the bandgap temperature drift coefficient at each process angle when the adjustment value of the low temperature drift voltage type bandgap reference and the high sensitivity negative temperature voltage generating circuit of the present invention is '10000';

[0071] Fig.19 It is a simulation diagram of the bandgap temperature drift coefficient at each process angle when the adjustment value of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generating circuit of the present invention is '11111';

[0072] Fig. 20 It is a simulation diagram of the bandgap temperature drift coefficient at each process angle when the adjustment value of the low temperature drift voltage type bandgap reference and the high sensitivity negative temperature voltage generating circuit of the present invention is '01101';

[0073] Fig.21 It is a simulation diagram of the bandgap temperature drift coefficient at each process angle when the adjustment value of the low-temperature drift voltage-type bandgap reference and the high-sensitivity negative temperature voltage generating circuit of the present invention is '00001'.

[0074] Description of reference numerals:

[0075] 1. Curvature compensation module; 2. Bandgap reference core module; 21. Adjustment resistor network; 22. Piecewise linear compensation module; 221. Startup unit; 222. Bias and I PATA Generating unit; 223, piecewise linear compensation unit; 224, I CTAT Generating unit; 3. High sensitivity NTC voltage module. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0077] In addition, it should be noted that the terms "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element of the present invention must have a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0078] When an element is referred to as being “fixed to” or “disposed on” or “provided on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0079] Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the invention can be understood according to specific circumstances. Example

[0080] Please refer to Figure 1-21 As shown, this embodiment provides a low-temperature drift voltage-type bandgap reference and a high-sensitivity negative temperature voltage generation circuit, including a curvature compensation module 1, a bandgap reference core module 2, and a high-sensitivity NTC voltage module 3. The power input terminals of the curvature compensation module 1, the bandgap reference core module 2, and the high-sensitivity NTC voltage module 3 are all electrically connected to the external power supply VDD1. The bandgap reference core module 2 includes a positive temperature coefficient voltage term generation branch and a negative temperature coefficient voltage term generation branch; the output terminal of the curvature compensation module 1 is electrically connected to the input terminal of the positive temperature coefficient voltage term generation branch and the negative temperature coefficient voltage term generation branch; the output terminals of the positive temperature coefficient voltage term generation branch and the negative temperature coefficient voltage term generation branch are connected, and output a low-temperature drift bandgap voltage V bandgap The bandgap reference core module 2 outputs a low-temperature drift bandgap voltage V bandgap To curvature compensation module 1; bandgap reference core module 2 outputs low temperature drift bandgap voltage V bandgap and V BE3 The voltage is transmitted to the high-sensitivity NTC voltage module 3, and the high-sensitivity NTC voltage module 3 outputs a negative temperature voltage Vout_N.

[0081] In this embodiment, the bandgap reference core module 2 adopts a voltage-type CMOS bandgap reference structure, and the positive temperature coefficient voltage term generating branch generates ΔV BE , the negative temperature coefficient voltage term generates a branch to generate V BE , the two complement each other to generate a low temperature drift bandgap voltage V bandgap ; At the same time, the curvature compensation module 1 further offsets the negative temperature coefficient voltage term V BE The influence of the high-order terms in the , and the low-temperature drift bandgap reference is obtained. And through the low-temperature drift bandgap voltage V bandgap and VBE3 The voltage and high-sensitivity NTC voltage module 3 outputs a negative temperature characteristic voltage Vout_N with a specific temperature slope.

[0082] Please refer to Figure 1 As shown, specifically, the positive temperature coefficient voltage term generating branch includes the trimming resistor network 21, the piecewise linear compensation module 22, the MOS tube P3 and the resistors R3 and R5; the negative temperature coefficient voltage term generating branch includes the operational amplifier OP2, the MOS tube P5, the transistor Q1, the transistor Q2, the transistor Q3 and the resistors R1, R2 and R4.

[0083] The source of the MOS transistor P3 is electrically connected to the external power source VDD1 ; the piecewise linear compensation module 22 outputs the bias voltage VB1 to the gate of the MOS transistor P3 .

[0084] The output end of the curvature compensation module 1 is electrically connected to one end of the resistor R1, one end of the resistor R5 and the same-direction input end of the operational amplifier OP2, and the other end of the resistor R1 is electrically connected to the emitter of the transistor Q1. The reverse input end of the operational amplifier OP2 is electrically connected to one end of the resistor R2, and the other end of the resistor R2 is electrically connected to one end of the resistor R4 and the emitter of the transistor Q2. The output end of the operational amplifier OP2 is electrically connected to the gate of the MOS tube P5, and the drain of the MOS tube P5 is electrically connected to the emitter of the transistor Q3, and outputs V BE3 Voltage to high sensitivity NTC voltage module3.

[0085] The other end of the resistor R5 is electrically connected to the VNL1 port of the trimming resistor network 21, the VNL2 port of the trimming resistor network 21 is electrically connected to the piecewise linear compensation module 22 and one end of the resistor R3, the other end of the resistor R3 is electrically connected to the drain of the MOS tube P3, the source of the MOS tube P5, and the other end of the resistor R4, and outputs the low temperature drift bandgap voltage V as an output end. bandgap To high sensitivity NTC voltage module 3 and curvature compensation module 1.

[0086] The collectors and bases of transistors Q1, Q2 and Q3 are all grounded.

[0087] The common negative temperature coefficient voltage term is the voltage V between the base and emitter of the transistor. BE ; From the above circuit, we can get:

[0088]

[0089] Where, ΔV BE1,2 is the voltage difference across resistor R1, I NL is the high-order compensation current, I NL2 is the piecewise linear compensation current, R trimis the equivalent resistance of the trimming resistor network 21.

[0090] According to the diode formula:

[0091]

[0092] Among them, V T is the thermal voltage; I PN1 and I PN2 are the currents flowing through transistor Q1 and transistor Q2 respectively; N is the area ratio of transistor Q1 and transistor Q2; the segmented current compensation current I NL2 and high-order compensation current I NL is small and can be approximately ignored, then:

[0093]

[0094]

[0095] Where V BE2 is the base-emitter voltage of transistor Q2, and the transformation yields:

[0096]

[0097] Substitute the low temperature drift bandgap voltage V bandgap The calculation formula is:

[0098]

[0099] Among them, I NL ·(R5+R trim +R3) is a high-order curvature compensation term, I NL2 ·R3 is a piecewise linear compensation term. It can be seen from the formula that before adding the two compensation terms, the positive temperature coefficient is similar to the thermal voltage V T About. T The relationship with T is:

[0100]

[0101] Where K is the Boltzmann constant, q is the electron charge, V T is only a first-order term for temperature T.

[0102] Specifically, the high-sensitivity NTC voltage module 3 includes an operational amplifier OP3, an operational amplifier OP4, a MOS transistor P4, a MOS transistor N21, a MOS transistor N22, a MOS transistor N23, a capacitor C1, and resistors R8, R9, and R10.

[0103] The source of the MOS transistor P4 and the drain of the MOS transistor N22 are both electrically connected to the external power source VDD1 ; the piecewise linear compensation module 22 outputs the bias voltage VB1 to the gate of the MOS transistor P4 .

[0104] Bandgap reference core module 2 outputs low temperature drift bandgap voltage V bandgap To the same-direction input terminal of the operational amplifier OP3, that is, the other end of the resistor R3 is electrically connected to the same-direction input terminal of the operational amplifier OP3. The inverting input terminal and the output terminal of the operational amplifier OP3 are both electrically connected to one end of the resistor R8. The other end of the resistor R8 is electrically connected to one end of the resistor R9, one end of the resistor R10 and the same-direction input terminal of the operational amplifier OP4. The bandgap reference core module 2 outputs V BE3 The voltage is electrically connected to the reverse input terminal of the operational amplifier OP4, that is, the drain of the MOS tube P5 is electrically connected to the reverse input terminal of the operational amplifier OP4. The output terminal of the operational amplifier OP4 is electrically connected to the gate of the MOS tube N21, the gate of the MOS tube N23 and one end of the capacitor C1; the drain of the MOS tube N21 is electrically connected to the drain of the MOS tube P4 and the gate of the MOS tube N22, and the source of the MOS tube N22 is electrically connected to the other end of the capacitor C1, the drain of the MOS tube N23 and the other end of the resistor R9, and outputs the negative temperature voltage V as the output terminal. out_N .

[0105] The source of the MOS transistor N21, the source of the MOS transistor N23 and the other end of the resistor R10 are grounded.

[0106] Specifically, the expression of the negative temperature voltage Vout_N is:

[0107]

[0108] Among them, V BE3 is the base emitter voltage of transistor Q3, which has a negative temperature characteristic and a low temperature drift bandgap voltage V bandgap The value of has nothing to do with temperature. As can be seen from the above formula, by adjusting the resistance values ​​of resistors R9 and R8, negative temperature voltages V with different temperature slopes can be obtained. out_N .

[0109] Please refer to the attached Figure 1MOS tube N21, MOS tube N22, operational amplifier OP4 and resistors R9 and R10 form a negative feedback loop of LDO. When the output fluctuates, the output voltage Vout_N can be stabilized by negative feedback. MOS tube N23 provides a feedforward path between the first-stage output of operational amplifier OP4 and the output of LDO, which helps to improve the transient response performance. Capacitor C1 is a coupling capacitor. Capacitor C1 couples the output voltage of LDO to the output of operational amplifier OP4. Through the Miller compensation effect, the output pole of operational amplifier OP4 is split from the output pole of LDO, thereby reducing the frequency of the output pole of operational amplifier OP4 and setting it as the main pole. In addition, the feedforward path can also introduce a left half plane zero, thereby improving the phase margin of the loop and improving stability.

[0110] Please refer to the attached Figure 2 , attached Figure 2 For different resistance values ​​of resistor R9, negative temperature voltage V out_N The temperature characteristics simulation diagram. Figure 2 It can be seen that the negative temperature voltage V out_N The slope of the temperature characteristic curve changes with the resistance value of resistor R9. By selecting appropriate resistance values ​​of resistors R8, R9 and R10, a negative temperature voltage V with a larger temperature variation range can be obtained. out_N .

[0111] Please refer to the attached Figure 3 , attached Figure 3 Negative temperature voltage V out_N With V BE3 Temperature characteristic comparison curve; Figure 3 It can be seen that the negative temperature voltage V out_N In the range of -40-125℃, the voltage curve shows a downward trend. The maximum voltage difference is about 1V, which is higher than the base-emitter voltage V of transistor Q3. BE3 The difference is 0.33V. When the operating temperature fluctuates, the negative temperature voltage V out_N Compared to V BE It has a wider voltage variation range to meet the use requirements of circuits such as temperature sensors.

[0112] Specifically, the curvature compensation module 1 includes an operational amplifier OP1, a MOS transistor P1, a MOS transistor P2, a transistor Q4, and resistors R6, R7, R11, and R12.

[0113] The source of the MOS transistor P1 and the source of the MOS transistor P2 are both electrically connected to the external power source VDD1.

[0114] Bandgap reference core module 2 outputs low temperature drift bandgap voltage V bandgapTo the reverse input terminal of the operational amplifier OP1, that is, the other end of the resistor R3 is electrically connected to the reverse input terminal of the operational amplifier OP1. The drain of the MOS tube P1 is electrically connected to the non-inverting input terminal of the operational amplifier OP1, and the gate of the MOS tube P1 is electrically connected to the gate of the MOS tube P2 and the output terminal of the operational amplifier OP1. The resistor R6, the resistor R11 and the resistor R12 are connected in series between the drain of the MOS tube P1 and the ground.

[0115] The drain of the MOS tube P2 is electrically connected to one end of the resistor R7 and the emitter of the transistor Q4, and the other end of the resistor R7 is electrically connected to the input ends of the positive temperature coefficient voltage term generating branch and the negative temperature coefficient voltage term generating branch as an output end; that is, the other end of the resistor R7 is electrically connected to one end of the resistor R5, one end of the resistor R1 and the non-inverting input end of the operational amplifier OP2.

[0116] The base and collector of transistor Q4 are grounded.

[0117] Transistor base emitter voltage V BE , its expression about temperature is:

[0118]

[0119] Among them, V G0 (T0) is the bandgap reference voltage at temperature T0; T is the temperature of the current circuit, T0 is the selected reference temperature; δ is a constant related to the transistor current, when the current flowing into the transistor is independent of temperature, δ is 0, when the current flowing into the transistor is linearly related to temperature, δ is 1; η is a constant of approximately 3-4 related to the bipolar transistor.

[0120] From the above formula, we can see that V BE It contains the high-order term T·lnT of T, so it needs to be temperature compensated. The basic principle is to generate a nonlinear current I containing the term T·lnT NL , to offset V BE The T·lnT term in .

[0121] Due to the existence of the first-order compensation term, the low-temperature drift bandgap voltage V bandgap It can be approximately regarded as independent of temperature, and the current generated in resistor R6 is also approximately independent of temperature. Therefore, the current flowing into transistor Q4 is independent of temperature, and the base-emitter voltage V BE4 for:

[0122]

[0123] The base-emitter voltage V on transistor Q1 BE1 for:

[0124]

[0125] Then the voltage difference across resistor R7 is:

[0126]

[0127] therefore,

[0128]

[0129] Therefore, the high-order compensation current I NL for

[0130]

[0131] Will I NL Substitute the low temperature drift bandgap voltage V bandgap In the formula, R5+R trim +R3 is recorded as R Z , after sorting, we can get:

[0132]

[0133] Therefore, when R Z When / R7 is equal to (η-1), V BE1 By selecting appropriate resistors R1, R3, R4, R5, R7 and R trim By using the voltage division of resistors R6, R11 and R12, bandgap voltages Vbg_H and Vbg_L with different voltage values ​​can be obtained. The specific voltage value can be determined by changing the resistance ratio of resistors R6, R11 and R12.

[0134] The temperature coefficient is an important indicator for evaluating the performance of a bandgap reference source, also known as temperature drift. It reflects the sensitivity of the reference source to temperature changes. The larger the temperature drift, the more sensitive the reference source is to temperature changes, and the worse its stability. The unit of temperature drift is generally ppm / ℃, and the calculation formula is as follows:

[0135]

[0136] Among them, V MAX and V MIN is the maximum and minimum output voltage, V MEAN is the average value of the output voltage, T MAX and T MIN are the maximum and minimum values ​​of the temperature variation range.

[0137] Please refer to the attached Figure 4 , attached Figure 4is the low temperature drift bandgap voltage V without any compensation under the tt process angle bandgap The simulation curve shows that the bandgap voltage fluctuates by 2.56mv in the range of -40℃ to 125℃, and its temperature drift is about 12ppm / ℃. Figure 5 , attached Figure 5 The low temperature drift bandgap voltage V after adding high-order curvature compensation at the tt process angle bandgap The simulation curve shows that the voltage fluctuation is reduced to 0.9mv, and the temperature drift is only about 4.5ppm / ℃. Figure 4 and attached Figure 5 It can be seen that the curvature compensation module 1 effectively reduces the temperature drift of the bandgap voltage.

[0138] Please refer to Figure 6 and Figure 7 As shown, Figure 6 and Figure 7 In the embodiment, the A ports are connected to each other, and the B ports are connected to each other. Specifically, the piecewise linear compensation module 22 includes a start-up unit 221, a bias unit and an I PATA Generating unit 222, I CTAT Generation unit 224 and piecewise linear compensation unit 223.

[0139] Startup unit 221, bias and I PATA Generating unit 222, I CTAT Power input terminals of the generating unit 224 and the piecewise linear compensation unit 223 are both electrically connected to the external power source VDD1 .

[0140] The output terminal of the startup unit 221 is connected to the bias terminal and I PATA The signal input terminal of the generating unit 222 is electrically connected to the bias and I PATA The output terminal of the generating unit 222 outputs the bias voltage VB1 to the gate of the MOS transistor P3 and the gate of the MOS transistor P4, and outputs the bias voltage VB1 and the current I PATA To the first input terminal of the piecewise linear compensation unit 223. CTAT The generating unit 224 outputs the current I CTAT The second input terminal of the piecewise linear compensation unit 223 is electrically connected to the VNL2 terminal of the trimming resistor network 21 .

[0141] Current I PATA The current I is positively proportional to the absolute temperature. CTAT The current with different temperature characteristics is copied through the current mirror and then fed into the VNL2 port of the trimming resistor network 21. NL2 To adjust the temperature characteristics of the bandgap reference voltage.

[0142] Please refer to Figure 6 As shown, specifically, the start-up unit 221 includes a MOS transistor P6, a MOS transistor P18, a MOS transistor N1 and a MOS transistor N2.

[0143] The source of the MOS transistor P18 is electrically connected to the external power source VDD1.

[0144] The drain of MOS transistor P18 is electrically connected to the source of MOS transistor P6, and the gate of MOS transistor P18 is electrically connected to the gate of MOS transistor P6 and the gate of MOS transistor N1, and serves as the first output terminal and the bias and I PATA The signal input terminal of the generating unit 222 is electrically connected. The drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor N1 and the gate of the MOS transistor N2. The drain of the MOS transistor N2 is used as the second output terminal and connected to the bias and I PATA The signal input terminal of the generating unit 222 is electrically connected.

[0145] The source of the MOS transistor N1 and the source of the MOS transistor N2 are both grounded.

[0146] Specifically, bias and I PATA The generating unit 222 includes a MOS transistor P7 , a MOS transistor P8 , a MOS transistor N3 , a MOS transistor N4 and a resistor R14 .

[0147] The source of the MOS transistor P7 and the source of the MOS transistor P8 are both electrically connected to the external power source VDD1.

[0148] The first output end of the start-up unit 221 is electrically connected to the gate of the MOS transistor N3, the drain of the MOS transistor P7 and one end of the resistor R14, that is, the gate of the MOS transistor P18 is electrically connected to the gate of the MOS transistor N3, the drain of the MOS transistor P7 and one end of the resistor R14. The other end of the resistor R14 is electrically connected to the drain of the MOS transistor N3 and the gate of the MOS transistor N4. The second output end of the start-up unit 221 is electrically connected to the gate of the MOS transistor P7, the gate and the drain of the MOS transistor P8 and the drain of the MOS transistor N4, that is, the drain of the MOS transistor N2 is electrically connected to the gate of the MOS transistor P7, the gate and the drain of the MOS transistor P8 and the drain of the MOS transistor N4. The gate of the MOS transistor P7 outputs the bias voltage VB1 to the gate of the MOS transistor P3 and the gate of the MOS transistor P4 as an output end, and outputs the bias voltage VB1 and the current I PATA To the first input terminal of the piecewise linear compensation unit 223.

[0149] The source of the MOS transistor N3 and the source of the MOS transistor N4 are both grounded.

[0150] Please refer to Figure 7 As shown, specifically, I CTATThe generating unit 224 includes an operational amplifier OP5, a MOS transistor P16, a MOS transistor P17, a transistor Q5 and a resistor R13.

[0151] The source of the MOS transistor P16 and the source of the MOS transistor P17 are both electrically connected to the external power source VDD1.

[0152] The gate of the MOS transistor P16 is electrically connected to the gate of the MOS transistor P17 and the output terminal of the operational amplifier OP5, and outputs a current I CTAT To the second input terminal of the piecewise linear compensation unit 223. The drain of the MOS transistor P16 is electrically connected to one end of the resistor R13 and the non-inverting input terminal of the operational amplifier OP5, and the drain of the MOS transistor P17 is electrically connected to the emitter of the transistor Q5 and the reverse input terminal of the operational amplifier OP5.

[0153] The collector and base of the transistor Q5 and the other end of the resistor R13 are grounded.

[0154] Specifically, the piecewise linear compensation unit 223 includes MOS transistor P9, MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor P13, MOS transistor P14, MOS transistor P15, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10, MOS transistor N11, MOS transistor N12, MOS transistor N13, MOS transistor N14 and MOS transistor N15.

[0155] The source of the MOS transistor P9 , the source of the MOS transistor P10 , the source of the MOS transistor P11 , the source of the MOS transistor P12 , the source of the MOS transistor P13 , the source of the MOS transistor P14 and the source of the MOS transistor P15 are all electrically connected to the external power supply VDD1 .

[0156] The gate of the MOS transistor P9 is electrically connected to the gate and drain of the MOS transistor P10, the drain of the MOS transistor N6, the gate and drain of the MOS transistor P13, the gate of the MOS transistor N11, the gate and drain of the MOS transistor N12, and the drain of the MOS transistor N13; the drain of the MOS transistor P9 is electrically connected to the drain and gate of the MOS transistor N5, and the gate of the MOS transistor N8.

[0157] Bias and I PATA The generating unit 222 outputs the bias voltage VB1 and the current I PATA To the gate of the MOS transistor P11, that is, the gate of the MOS transistor P7 is electrically connected to the gate of the MOS transistor P11; the drain of the MOS transistor P11 is electrically connected to the gate of the MOS transistor N7, the drain and the gate of the MOS transistor N6.

[0158] The gate of MOS transistor P12 is electrically connected to the gate and drain of MOS transistor P15 and the drain of MOS transistor N15. The drain of MOS transistor P12 is electrically connected to the drain of MOS transistor N8, the gate and drain of MOS transistor N9 and the gate of MOS transistor N10.

[0159] I CTAT The generating unit 224 outputs the current I CTAT To the gate of the MOS transistor P14, that is, the gate of the MOS transistor P16 is electrically connected to the gate of the MOS transistor P14; the drain of the MOS transistor P14 is electrically connected to the gate and drain of the MOS transistor N14, the gate of the MOS transistor N13 and the gate of the MOS transistor N15.

[0160] The drain of the MOS transistor N11 is electrically connected to the drain of the MOS transistor N10 , and is also electrically connected to the VNL2 port of the trimming resistor network 21 as an output terminal.

[0161] The source of the MOS tube N5, the source of the MOS tube N6, the source of the MOS tube N7, the source of the MOS tube N8, the source of the MOS tube N9, the source of the MOS tube N10, the source of the MOS tube N11, the source of the MOS tube N12, the source of the MOS tube N13, the source of the MOS tube N14 and the source of the MOS tube N15 are all grounded.

[0162] By the attached Figure 5 It can be seen that after compensation by the curvature compensation module 1, the temperature drift coefficient of the bandgap voltage is reduced, but it is still in the form of a parabola opening downward. This embodiment uses the piecewise linear compensation module 22 to reversely compensate the curves of the low temperature section and the high temperature section, and adjusts the bandgap voltage by subtracting the positive temperature characteristic current term in the low temperature section and the negative temperature characteristic current term at high temperature, thereby reducing the temperature drift.

[0163] Combined with Figure 3 It can be seen that the temperature drift between 10℃ and 90℃ is small, and the temperature change on both sides is large. Therefore, 10℃ and 90℃ are selected as temperature reference points to compensate for both sides.

[0164] Please refer to the attached Figure 6 As shown, MOS transistor P7, MOS transistor P8, MOS transistor N3 and MOS transistor N4 constitute bias and I PATA The generating unit 222 provides the bias voltage VB1 and the positive temperature coefficient current I for the bandgap reference core module 2. PTAT By setting a suitable width-to-length ratio, the MOS transistor N3 and the MOS transistor N4 are in the subthreshold region. In this embodiment, the width-to-length ratio of the MOS transistor N3 to the MOS transistor N4 is 4:5. At this time, the drain-source current of the MOS transistor can be expressed as:

[0165]

[0166] Where μ is the carrier mobility, C ox is the gate oxide capacitance per unit area, V T is the thermal voltage, V TH is the threshold voltage, V GS is the gate-source voltage, V DS is the drain-source voltage, η is the non-ideal factor, and W / L is the width-to-length ratio of the MOS tube.

[0167] When V DS >4V T When DS It can be expressed as:

[0168]

[0169] Deformed:

[0170]

[0171] The width-to-length ratio W / L of the MOS tube is recorded as K, and μC ox (η-1)V T 2 is the characteristic current of the MOS tube, which can be expressed by I0:

[0172]

[0173] Then V GS It can be expressed as:

[0174]

[0175] The gate-source voltage difference ΔV between MOS tube N3 and MOS tube N4 GS It can be expressed as:

[0176]

[0177] Substitute V GS The formula is:

[0178]

[0179] It can be seen from the formula that ΔV GS Only V T It is related to temperature and is positively correlated, so the gate-source voltage difference ΔV of the subthreshold MOS tube GS is a positive temperature coefficient, and the current flowing through the resistor R14 is I PTAT Electric current.

[0180] Because V BE is a negative temperature coefficient voltage, so the current flowing through resistor R13 is I CTATCurrent. The two currents with different temperature characteristics on resistors R13 and R14 are fed into the VNL2 port through the current mirror, and the temperature characteristics of the bandgap reference voltage are adjusted through INL2. In the low temperature range, INL2 is a negative temperature coefficient, and its value is

[0181]

[0182] In the high temperature range, INL2 is a positive temperature coefficient, and its value is

[0183]

[0184] In the above formula, k1 to k4 are the current ratios of the current mirror, and, refer to the attached Figure 8 , attached Figure 8 FIG. 2 is a simulation diagram of the compensation current of the piecewise linear compensation module 22. NL2 The low temperature section has negative temperature characteristics, and the high temperature section has positive temperature characteristics, which meets the requirements.

[0185] To prevent the degenerate state where all voltages are 0, MOS tubes P6, N1 and N2 are used to form the startup unit 221. When the drain potential of MOS tube P7 is 0, the gate of MOS tube N2 is pulled to a high level, thereby reducing the VB1 voltage, turning on MOS tube P7 and raising its drain potential, thereby breaking the degenerate state and completing the startup. Please refer to the attached Fig. 9 , attached Fig. 9 is the low temperature drift bandgap voltage V bandgap Power-on simulation diagram, as shown in the attached Fig. 9 It can be seen that a 20us rise time is given to the power supply voltage during the power-on simulation. The results show that a stable bandgap voltage can be obtained after 10us after power-on, and the startup time is about 30us.

[0186] Please refer to the attached Fig.10 , attached Fig.10 The low temperature drift bandgap voltage V after adding the piecewise linear compensation module 22 under the tt process angle is bandgap Simulation curve diagram, with attached Figure 5 In contrast, the low temperature drift bandgap voltage V bandgap The temperature characteristics in the low and high temperature ranges are effectively compensated, the voltage fluctuation amplitude is further reduced to 0.13mV, and the temperature drift is reduced to about 0.7ppm / ℃.

[0187] Please refer to the attached Fig.11 , attached Fig.11 is the low temperature drift bandgap voltage V bandgap The linear regulation rate simulation curve diagram shows the linear regulation rate, which reflects the stability of the reference source when the power supply voltage fluctuates. The unit is mv / v, and its calculation formula is:

[0188]

[0189] The low-temperature drift bandgap voltage is DC scanned in the power supply voltage range of 0 to 4V. The reference source output voltage curve is shown in the attached figure. Fig.11 As shown in the figure, it can be seen that the output of the reference source starts to build up when the power supply voltage is about 1.2V, and starts to output stably at 1.6V. In the range of power supply voltage from 2V to 3.3V, the output of the reference changes by about 0.5mV. The linear regulation rate calculation formula shows that the linear regulation rate is about 0.4mV / V, which has good stability when the voltage fluctuates.

[0190] Please refer to the attached Fig.12 , attached Fig.12 is the low temperature drift bandgap voltage V bandgap The power supply rejection ratio simulation curve is shown in Figure 1. The power supply rejection ratio (PSRR) measures the suppression effect of the reference output voltage on this power supply noise. The higher the absolute value of PSRR, the stronger the reference output voltage's ability to suppress power supply ripple, and vice versa. The unit of the power supply rejection ratio is decibel (dB), which is usually a negative value. The calculation formula is as follows:

[0191]

[0192] Among them, δV DD Represents the noise fluctuation of the power supply voltage, δV bandgap Represents the reference voltage fluctuation caused by power supply noise. Fig.12 It can be seen that the power supply rejection ratio at low frequency is about -70db, and the power supply rejection ratio at high frequency 100k is about -34db, which has good suppression capability at both low and high frequencies.

[0193] Please refer to the attached Fig.13 , attached Fig.13 In the circuit diagram of the trimming resistor network 21, Rt1, Rt2, Rt3, Rt4, Rt5 and Rt6 are all trimming resistors, and the resistance relationship is Rt1=0.5R; Rt2=1R; Rt3=2R; Rt4=4R; Rt5=8R; Rt6=6R.

[0194] The trimming resistor network 21 changes the size of the trimming resistor network 21Rtrim through the trimming signal, thereby trimming the bandgap voltage value, improving the output reference deviation caused by process error, and ensuring its low temperature drift temperature characteristics. Figure 14-21 ,in Fig.14 The bandgap voltage temperature drift simulation diagram at each process angle when the adjustment value is '01110'; Fig.15 The bandgap voltage temperature drift simulation diagram at each process angle when the adjustment value is '01011'; Fig.16 It is the simulation diagram of band gap temperature drift coefficient under each process angle when the adjustment value is '01001'; Fig.17It is the simulation diagram of bandgap temperature drift coefficient under each process angle when the adjustment value is '10100'; Fig.18 It is the simulation diagram of band gap temperature drift coefficient under each process angle when the adjustment value is '10000'; Fig.19 It is the simulation diagram of bandgap temperature drift coefficient under each process angle when the adjustment value is '11111'; Fig. 20 It is the simulation diagram of bandgap temperature drift coefficient under each process angle when the adjustment value is '01101'; Fig.21 The simulation diagram of the band gap temperature drift coefficient at each process angle when the adjustment value is '00001'.

[0195] The bandgap voltage under several common process angles is simulated. TR1 to TR5 are trimming signals, with high level being 1 and low level being 0. The trimming signals can be written into storage modules such as EEPROM through external ports. When the trimming signals from TR1 to TR5 are '01110', '01011', etc., the temperature drift under the listed process angles can be lower than 5 ppm / ℃, which can meet the low temperature drift requirements.

[0196] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A low temperature drift voltage type bandgap reference and a high sensitivity negative temperature voltage generating circuit, characterized in that: Including curvature compensation module, bandgap reference core module, high-sensitivity NTC voltage module; The power input terminals of the curvature compensation module, the bandgap reference core module, and the high-sensitivity NTC voltage module are all electrically connected to the external power supply VDD1; The bandgap reference core module includes a positive temperature coefficient voltage term generating branch and a negative temperature coefficient voltage term generating branch, the output end of the curvature compensation module is electrically connected to the input end of the positive temperature coefficient voltage term generating branch and the negative temperature coefficient voltage term generating branch, the output end of the positive temperature coefficient voltage term generating branch and the negative temperature coefficient voltage term generating branch are connected, and output a low temperature drift bandgap voltage V bandgap ; The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap To the curvature compensation module; The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap and V BE3 voltage to a high-sensitivity NTC voltage module, wherein the high-sensitivity NTC voltage module outputs a negative temperature voltage Vout_N; The high-sensitivity NTC voltage module includes an operational amplifier OP3, an operational amplifier OP4, a MOS transistor P4, a MOS transistor N21, a MOS transistor N22, a MOS transistor N23, a capacitor C1, and resistors R8, R9, and R10; The source of the MOS transistor P4 and the drain of the MOS transistor N22 are both electrically connected to the external power supply VDD1; the positive temperature coefficient voltage term generating branch includes a piecewise linear compensation module, and the piecewise linear compensation module outputs a bias voltage VB1 to the gate of the MOS transistor P4; The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap to the same-direction input terminal of the operational amplifier OP3, the inverting input terminal and the output terminal of the operational amplifier OP3 are both electrically connected to one end of the resistor R8; the other end of the resistor R8 is electrically connected to one end of the resistor R9, one end of the resistor R10 and the same-direction input terminal of the operational amplifier OP4, and the bandgap reference core module outputs V BE3 The voltage is supplied to the inverting input terminal of the operational amplifier OP4, the output terminal of the operational amplifier OP4 is electrically connected to the gate of the MOS tube N21, the gate of the MOS tube N23 and one end of the capacitor C1; the drain of the MOS tube N21 is electrically connected to the drain of the MOS tube P4 and the gate of the MOS tube N22, the source of the MOS tube N22 is electrically connected to the other end of the capacitor C1, the drain of the MOS tube N23 and the other end of the resistor R9, and outputs the negative temperature voltage Vout_N as the output terminal; The source of the MOS transistor N21, the source of the MOS transistor N23 and the other end of the resistor R10 are grounded.

2. The low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit according to claim 1, characterized in that: The positive temperature coefficient voltage term generating branch also includes a trimming resistor network, a MOS tube P3 and resistors R3 and R5; The negative temperature coefficient voltage term generating branch includes an operational amplifier OP2, a MOS tube P5, a transistor Q1, a transistor Q2, a transistor Q3 and resistors R1, R2 and R4; The source of the MOS tube P3 is electrically connected to the external power supply VDD1; the piecewise linear compensation module outputs the bias voltage VB1 to the gate of the MOS tube P3; The output end of the curvature compensation module is electrically connected to one end of the resistor R1, one end of the resistor R5 and the same-direction input end of the operational amplifier OP2, and the other end of the resistor R1 is electrically connected to the emitter of the transistor Q1; the reverse input end of the operational amplifier OP2 is electrically connected to one end of the resistor R2, and the other end of the resistor R2 is electrically connected to one end of the resistor R4 and the emitter of the transistor Q2; the output end of the operational amplifier OP2 is electrically connected to the gate of the MOS tube P5, and the drain of the MOS tube P5 is electrically connected to the emitter of the transistor Q3, and outputs V BE3 Voltage to high sensitivity NTC voltage module; The other end of the resistor R5 is electrically connected to the VNL1 port of the trimming resistor network, the VNL2 port of the trimming resistor network is electrically connected to the piecewise linear compensation module and one end of the resistor R3, the other end of the resistor R3 is electrically connected to the drain of the MOS tube P3, the source of the MOS tube P5, and the other end of the resistor R4, and outputs the low temperature drift bandgap voltage V as an output end. bandgap Highest sensitivity NTC voltage module and curvature compensation module; The collectors and bases of the transistors Q1 , Q2 and Q3 are all grounded.

3. The low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit according to claim 1, characterized in that: The curvature compensation module includes an operational amplifier OP1, a MOS tube P1, a MOS tube P2, a transistor Q4, and resistors R6, R7, R11, and R12; The source of the MOS transistor P1 and the source of the MOS transistor P2 are both electrically connected to the external power supply VDD1; The bandgap reference core module outputs a low-temperature drift bandgap voltage V bandgap to the inverting input terminal of the operational amplifier OP1; the drain of the MOS tube P1 is electrically connected to the non-inverting input terminal of the operational amplifier OP1, and the gate of the MOS tube P1 is electrically connected to the gate of the MOS tube P2 and the output terminal of the operational amplifier OP1; the resistor R6, the resistor R11 and the resistor R12 are sequentially connected in series between the drain of the MOS tube P1 and the ground; The drain of the MOS tube P2 is electrically connected to one end of the resistor R7 and the emitter of the transistor Q4, and the other end of the resistor R7 is electrically connected as an output end to the input ends of the positive temperature coefficient voltage term generating branch and the negative temperature coefficient voltage term generating branch; The base and collector of the transistor Q4 are both grounded.

4. The low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit according to claim 2, characterized in that: The piecewise linear compensation module includes a start-up unit, a bias unit and an I PATA Generation Unit, I CTAT Generation unit and piecewise linear compensation unit; The startup unit, bias and I PATA Generation Unit, I CTAT The power input terminals of the generating unit and the piecewise linear compensation unit are both electrically connected to the external power supply VDD1; The output terminal of the startup unit is connected to the bias and I PATA The signal input terminal of the generating unit is electrically connected to the bias and I PATA The output end of the generating unit outputs the bias voltage VB1 to the gate of the MOS tube P3, and outputs the bias voltage VB1 and the current I PATA To the first input terminal of the piecewise linear compensation unit; the I CTAT Generating unit output current I CTAT to a second input terminal of the piecewise linear compensation unit, the output terminal of the piecewise linear compensation unit being electrically connected to a VNL2 port of the trimming resistor network; The current I PATA is a current that is positively proportional to absolute temperature. CTAT A current that has a complementary characteristic to absolute temperature.

5. The low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit according to claim 4, characterized in that: The startup unit includes MOS transistor P6, MOS transistor P18, MOS transistor N1 and MOS transistor N2; The source of the MOS tube P18 is electrically connected to the external power supply VDD1; The drain of the MOS transistor P18 is electrically connected to the source of the MOS transistor P6, and the gate of the MOS transistor P18 is electrically connected to the gate of the MOS transistor P6 and the gate of the MOS transistor N1, and serves as the first output terminal and is connected to the bias and I PATA The signal input terminal of the generating unit is electrically connected; The drain of the MOS transistor P6 is electrically connected to the drain of the MOS transistor N1 and the gate of the MOS transistor N2. The drain of the MOS transistor N2 is used as a second output terminal and connected to the bias and I PATA The signal input terminal of the generating unit is electrically connected; The source of the MOS transistor N1 and the source of the MOS transistor N2 are both grounded.

6. The low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit according to claim 4, characterized in that: The bias and I PATA The generating unit includes MOS tube P7, MOS tube P8, MOS tube N3, MOS tube N4 and resistor R14; The source of the MOS transistor P7 and the source of the MOS transistor P8 are both electrically connected to the external power supply VDD1; The first output end of the startup unit is electrically connected to the gate of the MOS tube N3, the drain of the MOS tube P7 and one end of the resistor R14, the other end of the resistor R14 is electrically connected to the drain of the MOS tube N3 and the gate of the MOS tube N4, the second output end of the startup unit is electrically connected to the gate of the MOS tube P7, the gate and drain of the MOS tube P8 and the drain of the MOS tube N4, the gate of the MOS tube P7 is used as an output end to output the bias voltage VB1 to the gate of the MOS tube P3, and output the bias voltage VB1 and the current I PATA to a first input terminal of a piecewise linear compensation unit; The source of the MOS transistor N3 and the source of the MOS transistor N4 are both grounded.

7. The low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit according to claim 4, characterized in that: I CTAT The generating unit includes an operational amplifier OP5, a MOS tube P16, a MOS tube P17, a transistor Q5 and a resistor R13; The source of the MOS transistor P16 and the source of the MOS transistor P17 are both electrically connected to the external power supply VDD1; The gate of the MOS transistor P16 is electrically connected to the gate of the MOS transistor P17 and the output terminal of the operational amplifier OP5, and outputs a current I CTAT To the second input terminal of the piecewise linear compensation unit; the drain of the MOS tube P16 is electrically connected to one end of the resistor R13 and the same-direction input terminal of the operational amplifier OP5, and the drain of the MOS tube P17 is electrically connected to the emitter of the transistor Q5 and the reverse input terminal of the operational amplifier OP5; The collector and base of the transistor Q5 and the other end of the resistor R13 are grounded.

8. The low temperature drift voltage type bandgap reference and high sensitivity negative temperature voltage generation circuit according to claim 4, characterized in that: The piecewise linear compensation unit includes MOS transistor P9, MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor P13, MOS transistor P14, MOS transistor P15, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10, MOS transistor N11, MOS transistor N12, MOS transistor N13, MOS transistor N14 and MOS transistor N15; The source of the MOS transistor P9, the source of the MOS transistor P10, the source of the MOS transistor P11, the source of the MOS transistor P12, the source of the MOS transistor P13, the source of the MOS transistor P14 and the source of the MOS transistor P15 are all electrically connected to the external power supply VDD1; The gate of the MOS transistor P9 is electrically connected to the gate and drain of the MOS transistor P10, the drain of the MOS transistor N6, the gate and drain of the MOS transistor P13, the gate of the MOS transistor N11, the gate and drain of the MOS transistor N12, and the drain of the MOS transistor N13; the drain of the MOS transistor P9 is electrically connected to the drain and gate of the MOS transistor N5 and the gate of the MOS transistor N8; The bias and I PATA The generating unit outputs bias voltage VB1 and current I PATA To the gate of the MOS transistor P11, the drain of the MOS transistor P11 is electrically connected to the gate and drain of the MOS transistor N7 and the gate of the MOS transistor N6; The gate of the MOS transistor P12 is electrically connected to the gate and drain of the MOS transistor P15 and the drain of the MOS transistor N15, and the drain of the MOS transistor P12 is electrically connected to the drain of the MOS transistor N8, the gate and drain of the MOS transistor N9 and the gate of the MOS transistor N10; I CTAT Generating unit output current I CTAT To the gate of the MOS tube P14, the drain of the MOS tube P14 is electrically connected to the gate and drain of the MOS tube N14, the gate of the MOS tube N13 and the gate of the MOS tube N15; The drain of the MOS tube N11 is electrically connected to the drain of the MOS tube N10, and is electrically connected to the VNL2 port of the trimming resistor network as an output end; The source of the MOS tube N5, the source of the MOS tube N6, the source of the MOS tube N7, the source of the MOS tube N8, the source of the MOS tube N9, the source of the MOS tube N10, the source of the MOS tube N11, the source of the MOS tube N12, the source of the MOS tube N13, the source of the MOS tube N14 and the source of the MOS tube N15 are all grounded.

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