Circuit structure based on PC (Personal Computer) electrified CMOS (Complementary Metal Oxide Semiconductor)

Abstract

The utility model relates to the field of PC (Personal Computer) electrified clearing CMOS (Complementary Metal Oxide Semiconductor), in particular to a circuit structure based on a PC electrified clearing CMOS, which comprises an SIO circuit, an electrified clearing CMOS circuit and a PCHRTCRSTR, a signal input pin of the PCHRTCRSTR is connected to a grid electrode of Q31, a source electrode of the Q31 is connected with + 3V3RTC, a drain electrode of the Q31 is connected to a grid electrode of QS3, the grid electrode of the QS3 is indirectly controlled by a drain electrode of the Q31, a source electrode of the QS3 is connected to VBATSIO, and the source electrode and the drain electrode of the QS3 are connected to the ground through a pull-up resistor. And the grid electrode of the Q20 is directly controlled, the grid electrode of the Q20 is influenced by the level of the drain electrode of the QS3, the source electrode of the Q20 is connected to the + 3V3RTC, and the drain electrode of the Q20 is output to the VBATSIO.

Description

Technical Field

[0001] The utility model relates to the technical field of PC live CMOS cleaning, in particular to a circuit structure for PC computer live CMOS cleaning, including an SIO circuit and a live CMOS cleaning circuit. Background Art

[0002] With the development of integrated circuit technology, especially the progress of CMOS technology, it has become possible to integrate more complex logic controls on the motherboard, providing technical support for live CMOS cleaning design. Modern PC systems are more diverse and complex in configuration, posing higher requirements for the flexibility and recoverability of BIOS settings, which has promoted the development of more efficient CMOS management technology. In the trend of pursuing green computing and efficient energy utilization, live CMOS cleaning design helps to reduce unnecessary system power-off operations and meets the requirements of energy conservation and emission reduction.

[0003] The traditional VBAT circuit is directly connected to the RTC. When it is necessary to clean the CMOS, the motherboard power supply must be cut off first, and then the motherboard chassis must be removed before cleaning the CMOS. This method has the problem of cumbersome operation. And since the CMOS cleaning operation requires a complete power-off, it means that the ongoing work must be interrupted, all system states and settings will be lost, and the BIOS settings need to be reconfigured after restarting, increasing the time cost and complexity. Therefore, a circuit structure for PC computer live CMOS cleaning is proposed here. Through the live CMOS cleaning circuit, the CMOS cleaning operation can be achieved by pulling down the PCH_RTCRST_R signal when the motherboard is powered on, without cutting off the motherboard power supply or removing the motherboard chassis. Summary of the Utility Model

[0004] The purpose of the utility model is to solve the shortcoming in the prior art that when it is necessary to clean the CMOS, the motherboard power supply must be cut off first, and then the motherboard chassis must be removed before cleaning the CMOS, and a circuit structure for PC computer live CMOS cleaning is proposed, including an SIO circuit, a live CMOS cleaning circuit and PCH_RTCRST_R. The signal input pin of PCH_RTCRST_R is connected to the gate of Q31. The source of Q31 is connected to +3V3_RTC. The drain of Q31 is connected to the gate of QS3. The gate of QS3 is indirectly controlled by the drain of Q31. The source of QS3 is connected to VBAT_SIO. The source and drain of QS3 are connected to the ground through a pull-up resistor and directly control the gate of Q20. The gate of Q20 is affected by the drain level of QS3. The source of Q20 is connected to +3V3_RTC. The drain of Q20 outputs to VBAT_SIO;

[0005] When PCH_RTCRST_R is at a high level, Q31 PMOS is turned off. At this time, QS3_G is at a low level. QS3 NMOS is turned off, and Q20 PMOS is turned on. +3V3_RTC supplies power to VBAT_SIO. When PCH_RTCRST_R is at a low level, Q31 PMOS is turned on. At this time, QS3_G is at a high level, Q20 PMOS is turned off, QS3 NMOS is turned on, and VBAT_SIO is pulled down to ground to implement the powered CMOS function.

[0006] Preferably, when PCH_RTCRST_R is at a high level, Q31 is turned off, cutting off the pull-up path of the QS3 gate. When PCH_RTCRST_R is at a high level, the gate signal of Q31 is high, causing Q31 to turn off and cutting off the pull-up path of the QS3 gate.

[0007] Preferably, QS3_G is kept at a low level through a pull-up resistor to turn off QS3. Without the pull-up path, QS3_G is kept at a low level through a pull-up resistor, resulting in QS3 being turned off.

[0008] Preferably, when QS3 is turned off, the gate of Q20 remains at a high level through the off state of QS3, causing Q20 to turn on. The +3V3_RTC voltage supplies power to VBAT_SIO through Q20. Since QS3 is turned off, the gate of Q20 remains at a high level through the off state of QS3, causing Q20 to turn on, and the +3V3_RTC voltage supplies power to VBAT_SIO through Q20.

[0009] Preferably, when PCH_RTCRST_R is at a low level, Q31 is turned on. When PCH_RTCRST_R becomes low, the gate signal of Q31 becomes low, and Q31 is turned on, providing a high-level path for the gate of QS3.

[0010] Preferably, the conduction of Q31 causes QS3 to turn on. The conduction of Q31 raises the gate potential of QS3 to a high level, so QS3 is turned on, and its drain potential approaches the ground potential.

[0011] Preferably, when QS3 is turned on, Q20 is turned off. The conduction of QS3 cuts off the power supply from +3V3_RTC to VBAT_SIO. After QS3 is turned on, the gate potential of Q20 decreases due to the grounding of the QS3 drain, resulting in Q20 being turned off and cutting off the power supply from +3V3_RTC to VBAT_SIO.

[0012] Preferably, the conduction of QS3 directly connects VBAT_SIO to ground. The conduction of QS3 directly connects VBAT_SIO to ground, quickly discharging the charge on VBAT_SIO to implement the clearing or reset operation of the CMOS circuit.

[0013] Compared with the prior art, the beneficial effects of the present utility model are as follows:

[0014] The present utility model combines 2 PMOS and 1 NMOS to connect the RTC and VBAT circuits. When PCH_RTCRST_R is at a high level, Q31 PMOS is cut off, and at this time, the QS3_G is at a low level. QS3 NMOS is cut off, and Q20 PMOS is turned on, and +3V3_RTC supplies power to VBAT_SIO. When PCH_RTCRST_R is at a low level, Q31 PMOS is turned on, and at this time, the QS3_G is at a high level. Q20 PMOS is cut off, QS3 NMOS is turned on, and VBAT_SIO is pulled down to the ground, realizing the power-on CMOS function. When the main board is powered on, the CMOS operation can be cleared by pulling down the PCH_RTCRST_R signal, without cutting off the power supply of the main board or removing the main board chassis. Description of the Drawings

[0015] Figure 1 is the design block diagram of the power-on CMOS clearing circuit of the present utility model;

[0016] Figure 2 is the SIO circuit of the present utility model;

[0017] Figure 3 is the power-on CMOS clearing circuit of the present utility model. Detailed Embodiment

[0018] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0019] Embodiment 1

[0020] As Figures 1-3 shown, a circuit structure for power-on CMOS clearing of a PC computer proposed by the present utility model includes an SIO circuit, a power-on CMOS clearing circuit, and PCH_RTCRST_R. The signal input pin of PCH_RTCRST_R is connected to the gate of Q31. The source of Q31 is connected to +3V3_RTC. The drain of Q31 is connected to the gate of QS3. The gate of QS3 is indirectly controlled by the drain of Q31. The source of QS3 is connected to VBAT_SIO. The source and drain of QS3 are connected to the ground through a pull-up resistor and directly control the gate of Q20. The gate of Q20 is affected by the drain level of QS3. The source of Q20 is connected to +3V3_RTC, and the drain of Q20 outputs to VBAT_SIO.

[0021] When PCH_RTCRST_R is at a high level, Q31 is turned off, cutting off the pull-up path of the gate of QS3.

[0022] QS3_G is kept at a low level through a pull-up resistor to turn off QS3.

[0023] When QS3 is turned off, the gate of Q20 is kept at a high level through the off state of QS3, causing Q20 to conduct, and the +3V3_RTC voltage supplies power to VBAT_SIO through Q20.

[0024] In this embodiment, the workflow when PCH_RTCRST_R is at a high level is as follows:

[0025] First, when PCH_RTCRST_R is at a high level, the gate signal of Q31 is high, causing Q31 to turn off, cutting off the pull-up path of the gate of QS3. Without the pull-up path, QS3_G is kept at a low level through a pull-up resistor, resulting in QS3 being turned off. Since QS3 is turned off, the gate of Q20 is kept at a high level through the off state of QS3, causing Q20 to conduct, and the +3V3_RTC voltage supplies power to VBAT_SIO through Q20.

[0026] In actual use, PCH_RTCRST_R, as a key control signal, is generated or responded to by the PCH chipset on the motherboard. When the system software or the user issues a CMOS clear command by selecting the "Restore Default Settings" option in the BIOS setup menu through a specific interface, this signal will be actively pulled low.

[0027] Embodiment Two

[0028] As Figures 1-3 shown, based on Embodiment One, when PCH_RTCRST_R is at a low level, Q31 conducts.

[0029] The conduction of Q31 causes QS3 to conduct.

[0030] The conduction of QS3 turns off Q20, and the cutoff of Q20 cuts off the power supply from +3V3_RTC to VBAT_SIO.

[0031] The conduction of QS3 directly connects VBAT_SIO to ground.

[0032] In this embodiment, when PCH_RTCRST_R becomes low, the gate signal of Q31 becomes low accordingly, and Q31 conducts, providing a path for high level to the gate of QS3. The conduction of Q31 raises the gate potential of QS3 to high level, so QS3 conducts. The drain potential of QS3 approaches the ground potential. After QS3 conducts, the gate potential of Q20 decreases because the drain of QS3 is grounded, resulting in the cut-off of Q20, cutting off the power supply from +3V3_RTC to VBAT_SIO. The conduction of QS3 directly connects VBAT_SIO to the ground, quickly discharging the charge on VBAT_SIO, and realizing the clearing or reset operation of the CMOS circuit.

[0033] Once the PCH_RTCRST_R signal becomes low, Q31 PMOS in the circuit conducts, making the gate potential of QS3 become high level. Subsequently, QS3 NMOS conducts, forming a low-resistance path between its source and drain, connecting VBAT_SIO to the ground, and quickly discharging the charge on the part of the CMOS memory that stores BIOS setting information, realizing the data clearing. During this process, when VBAT_SIO is temporarily grounded, the RTC circuit still maintains power supply through other paths, ensuring that information such as the system time will not be lost, avoiding the inconvenience and risks brought by the motherboard power-off, and realizing that under the power-on state of the motherboard, the CMOS data can be cleared only through logical operations, greatly improving the user experience and the maintenance convenience of the system.

[0034] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A circuit structure based on PC computer live clearing CMOS, characterized by: It includes an SIO circuit, a power-clearing CMOS circuit and PCH_RTCRST_R, wherein the PCH_RTCRST_R signal input pin is connected to the gate of Q31, the source of Q31 is connected to +3V3_RTC, the drain of Q31 is connected to the gate of QS3, the gate of QS3 is indirectly controlled by the drain of Q31, the source of QS3 is connected to VBAT_SIO, the source and drain of QS3 are connected to the ground through a pull-up resistor, and directly controls the gate of Q20, the gate of Q20 is affected by the drain level of QS3, the source of Q20 is connected to +3V3_RTC, and the drain of Q20 is output to VBAT_SIO.

2. A circuit structure based on PC computer live CMOS clearing according to claim 1, characterized in that: The PCH_RTCRST_R is at a high level to turn off Q31 and cut off the pull-up path of the gate of QS3.

3. The circuit structure based on PC computer live CMOS clearing according to claim 1 is characterized in that: The QS3_G is kept at a low level through a pull-up resistor to turn off QS3.

4. The circuit structure based on PC computer live CMOS clearing according to claim 1 is characterized in that: The QS3 is turned off, and the gate of Q20 is kept at a high level by the off state of QS3, so that Q20 is turned on, and the +3V3_RTC voltage supplies power to VBAT_SIO through Q20.

5. The circuit structure based on PC computer live clearing CMOS according to claim 1, characterized in that: Q31 is turned on when the PCH_RTCRST_R is at a low level.

6. A circuit structure based on PC computer live clearing CMOS according to claim 5, characterized in that: The conduction of Q31 causes QS3 to be turned on.

7. The circuit structure based on PC computer live CMOS clearing according to claim 1 is characterized in that: The QS3 is turned on and Q20 is turned off, and the power supply from +3V3_RTC to VBAT_SIO is cut off.

8. The circuit structure based on PC computer live clearing CMOS according to claim 1, characterized in that: Turning on QS3 connects VBAT_SIO directly to ground.

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